1 san francisco july 14, 2010 itrs - ye itwg conference in san francisco (usa) july 14, 2009 l....

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San Francisco July 14, 2010

ITRS - YE ITWG

Conference in San Francisco (USA)July 14, 2009

L. Pfitzner, [email protected]

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Scope of Yield Enhancement• Aspects

– Manufacturing of integrated semiconductor devices: numerous processing steps building the 3D structure of the chip (e.g. 9 Cu and low –k interconnect layers for 32 nm)

– Yield: percentage of operating chips at the end of the manufacturing process

• Components– Determination and control of

contamination– Inspection of structures and critical

dimensions– Model to predict and calculate yield

based on historic contamination levels (particulate and metals) and defects (failures)

– Determination of kill ratios: Correlation between defects and yield

45 nm high-k metal gate transistor. Presented by Mark Bohr (Intel) 02/2009

45 nm ramp production was the fastestPresented by Mark Bohr (Intel) 02/2009

Gordon Moore: “There is no fundamental obstacle to achieving device yields of 100%.”

(Electronics, 38 (8), 1965)

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Objectives of Yield Enhancement• collect defect data

– tools for inspection and root cause analysis

– automated defect classification and filtering

– inspection strategy

• yield management– software– objective: to correlate data

and find excursions– predict yield

• defect data excursions– define specs– procedure for clarification

processmodule 1

processmodule 2

processmodule k

wafer wafer wafer1

2k

manufacturing

inspection and collection of data

review, characterization, metrology

defect densities

defect classiffication

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Defects and Failure Mechanisms

• processes: litho, etch thin film implantation, planarization, cleaning,…

• faults and problems: defects as e.g. particles, flatness, layer properties, patterns, dimensions

• challenges – yield and defect map in 2 D– root cause analysis

requires 3 D– model, predict, and forecast

yield YM&DB– requires fast and non-

destructive inspection (defect density) and metrology (root cause analysis) for 2D and 3D structures DDC

– requires preventive defect and contamination control WECC

n-well p-well

n

Via

p

crack

shortopen

contamination

p+

particle

COP

layer thickness

Metal 1

Metal 2

overlay

p

Interconnects

n+

particle

ESD Damage

Si crystal: stacking faults, contamination, stress, COP (crystal originating particles), epi defects

interfaces: roughness, state density, charges

(YM&DB: defect budget and yield modelling - DDC:

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Organization of the Chapter 2010

• Chair: Lothar Pfitzner (Fraunhofer IISB) Co-Chair: Dilip Patel (ISMI)

• Difficult Challenges• Table YE 2

• Technology Requirements and Potential Solutions- Yield Learning (YL – not active in 2010)

• Chair: N.N.; Contributors to be defined by Samsung, AMAT- Yield Model and Defect Budget (YMDB – not active in 2010)

• Chair: Sumio Kuwabara (Renesas) - Japan• Table YE 3, (2 deleted tables – defect budgets)

- Defect Detection and Characterization (DDC)• Chair: N.N. (A. Nutsch and D. Patel) – Europe and US• Table YE 4, YE 5, YE 6

- Wafer Environment Contamination Control (WECC)• Chair: Kevin Pate (Intel) – USA, Andreas Neuber (AMAT) -

Europe• Table YE 7

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2010 YE ITWG ContributorsEurope

Lothar Pfitzner ( chair, Fraunhofer IISB )Andreas Neuber (c-chair, AMAT )Dieter Rathei ( DDC, DR Yield )Francois Finck ( DDC, ST )Barry Kennedy ( DDC, Intel )Andreas Nutsch ( DDC, Fraunhofer IISB )Ines Thurner ( DDC, Smart Industry Partners )Jan Cavelaars ( DDC, NXP )Mathias Haeuser (DDC, Infineon)Delphine Gerin ( WECC, ST Crolles )Astrid Gettel ( WECC, GLOBALFOUNDRIES )Christoph Hocke ( WECC, Infineon Technologies )Michael Otto ( WECC, Fraunhofer IISB )Matthias Pfutterer ( WECC, M+W Group )Hubert Winzig ( WECC, Infineon )Francesca Illuzzi ( WECC, Numonyx )Hans Jansen ( WECC, ASML )Jost Kames ( WECC, artemis control AG )Arnaud Favre ( WECC, Adixen )

JapanSumio Kuwabara ( YMDB, Renesas )Hiroshi Nagaishi ( DDC, Renesas )Masashi Hamanaka ( DDC, Panasonic )Takahiro Tsuchiya ( DDC, Fujitsu Semiconductor )Yoshitaka Tatsumoto ( DDC, Lasertec )Masahiko Ikeno ( DDC, Hitachi High-Technologies )Mutsuhiro Amari ( WECC, Entegris )Takashi Futatsuki ( WECC, Organo )Teruyuki Hayashi ( WECC, TEL )Katsunobu Kitami ( WECC, Kurita )Kaoru Kondoh ( WECC, Rion )Yasuhiko Matsumoto ( WECC, Rohm )Fumio Mizuno ( WECC, MEISEI University )Kazuo Nishihagi ( WECC, HORIBA )Koichiro Saga ( WECC, SONY )Yoshimi Shiramizu ( co-chair, Renesas )Isamu Sugiyama ( WECC, NOMURA )Ken Tsugane ( WECC, HITACHI )Hidehiro Masuko ( WECC, ShinEtsu )

United States

Dilip Patel ( co-chair, ISMI )Barry Gotlinsky ( WECC, Pall )Biswanath Roy ( WECC, Pall )Bob Latimer ( WECC, Hach )Chris Muller ( WECC, Purafil, Inc. )Dan Fuchs ( WECC, BOCE )Dan Wilcox ( WECC, Replipoint Technologies )David Blackford ( WECC, Fluid Measurement

Technologies )David Roberts ( WECC, Nantero )Drew Sinha ( WECC, Siltronic )Dwight Beal ( WECC, PMS )James McAndrew ( WECC, Air Liquide )Jeff Chapman ( WECC, IBM )Jeff Hanson ( WECC, Texas Instruments )John DeGenova ( WECC, Texas Instruments )John Kurowski ( WECC, IBM )Keith Kerwin ( WECC, TI )Kevin Pate ( co-chair, Intel )Larry Rabellino ( WECC, SAES )Marc Camenzind ( WECC, Balazs-AirLiquide )Rich Riley ( WECC, Intel )Rick Godec ( WECC, Ionics Instruments )Sarah Schoen ( WECC, Balazs-AirLiquide )Scott Anderson ( WECC, Balazs-AirLiquide )Slava Libman ( WECC, M+W Group )Suhas Ketkar ( WECC, APCI )Terry Stange ( WECC, Hach Ultra Analytics )Tony Schleisman ( WECC, Air Liquide )Val Stradz ( WECC, Intel )Wai-Ming Choi ( WECC, Entegris )William Moore ( WECC, IBM )Milton Goldwin ( DDC, ISMI )

TaiwanVictor Liang ( , TSMC )YCHuang Huang ( , TSMC )Ray Yang ( , UMC )Mao-Hsiang Yen ( , Winbond )Cherng Guo ( , MXIX )

Korea (not confirmed)Sang Kyun Park ( Magna Chip )Jinsung Kim ( Samsung )Lim Jaewoong ( Samsung )Incheol Baek ( Dongbu HiTek )

Thank youvery much!

MalaysiaGuillaume Gallet ( WECC, Camfil)

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2010 Key Challenges The Yield Enhancement community is challenged by the following topics:

• Near Term (>16 nm)– Detection and identification of Small Yield Limiting Defects from Nuisance -

Detection of multiple killer defects and their simultaneous differentiation at high capture rates, low cost of ownership and high throughput. It is a challenge to find small but yield relevant defects under a vast amount of nuisance and false defects.

– Non-Visual Defects and Process Variations – Increasing yield loss due to non-visual defects and process variations requires new approaches in methodologies, diagnostics and control. This includes the correlation of systematic yield loss and layout attributes. The irregularity of features in logic areas makes them very sensitive to systematic yield loss mechanisms such as patterning process variations across the lithographic process window.

– 3D Inspection – For inspection tools the capability to inspect high aspect ratios but also to detect non-visuals such as voids, embedded defects, and sub-surface defects is crucial. The need for high-speed and cost-effective 3D inspection tools becomes crucial as the importance of 3D defect types increases.

– Process Stability vs. Absolute Contamination Level – Including the Correlation to Yield Test structures, methods and data are needed for correlating defects caused by wafer environment and handling with yield. This requires determination of control limits for gases, chemicals, air, precursors, ultrapure water and substrate surface cleanliness.

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2010 Key Challenges The Yield Enhancement community is challenged by the following topics:

• Long Term (<16 nm)– Next Generation Inspection - As bright field detection in the far-field loses its ability

to discriminate defects of interest, it has become necessary to explore new alternative technologies that can meet inspection requirements beyond 16 nm node. Several techniques should be given consideration as potential candidates for inspection: high speed scanning probe microscopy, near-field scanning optical microscopy, interferometry, scanning capacitance microscopy and e-beam. This pathfinding exercise needs to assess each technique’s ultimate resolution, throughput and potential interactions with samples (contamination, or degree of mechanical damage) as key success criteria.

– Inline Defect Characterization and Analysis – Alternatives to Energy Dispersive X-ray Spectroscopy systems are required for high throughput in-line characterization and analysis for defects smaller than feature sizes. The data volume to be analyzed is drastically increasing, therefore demanding for new methods for data interpretation and to ensure quality.

– Development of model-based design-manufacturing interface — Due to Optical Proximity Correction (OPC) and the high complexity of integration, the models must comprehend greater parametric sensitivities, ultra-thin film integrity, impact of circuit design, greater transistor packing, etc.

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Update 2010• Overall

– confirmation of key challenges– deleted 450 mm as a new challenge– ISMI to organize a new defect budget survey

• DDC– adjust tables to ORCT input– update colours and numbers

• DB & YL– outline for defect budget survey presented– discuss non–visible defects– Tables were deleted (not up to date)

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Update 2010 • WECC:

Focus items (Ultrapure Water, Chemicals, Gas, Airborne/Surface Molecular Contamination and Cleanroom)

– Particles: Measurement, composition, critical size, identify yield correlation, deposition models

– Organics: Measurement, speciation, identify yield correlation, deposition models

– Ionic, metallic and other molecular contamination: Deposition risk assessment methodology and model

– Gases and CVD/ALD precursor contamination control requirements: measurement, control and impact assessment

– Airborne and Surface Molecular Contamination: integrated control concept (carrier and mini-environment), metrology requirements, deposition models and impact assessments

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Activities 2010

• Setup of ITRS Forums in operation and used for communication

• Defect Budget Survey (ongoing)– outline for defect budget survey (see

https://www.surveymonkey.com/s/F9ZFTTB )– Contributors defined in Japan, Europe, and US

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YE involvement of ANNA

Input generation by ANNA (European Integrated Activity of Excellence and Networking for Nano and Micro- Electronics Analysis)

– ANNA integrates analytical infrastructures (www.anna-i3.org)• virtual distributed joint laboratory (8 laboratories accredited

according ISO 17025)• development of analytical techniques for semiconductor

manufacturing• driven by quality requirements such as comparability of techniques

and methods but also by the challenge of pushing metrology and analytical techniques to the limits

• involvement of industry, research organisations and academia

– Inputs for ITRS:• Contributions for Standardization (ISO and DIN)• Metrology Challenges• Input to be delivered by IDM and wafer manufacturers

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ANNA Contributions for Standardization

• The production of relevant reference material and standards. – References for trace analysis were produced and characterized

– Ultra-short pulsed laser deposition (PLD) of Ni was used in reference free SR-TXRF analysis

– B, As, Si implanted samples were produced at depths and concentrations for ultra shallow junctions

– To investigate nanocrystals HfO2 and HfSiO2 films were made for measurements of thickness and stoichiometry

– For strain in device processing, epitaxial wafers were used to produce standard samples for CBED analysis

– Standard samples for nanocrystals characterization were developed

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ANNA – YE/Metrology Challenges

• ANNA prepares and/or encourages standards for metrology

– Highly sensitive detection of inorganic contamination from Li to U.

– Comprehension of organic contamination of wafer surfaces

– Metrology for depth distribution of Ultra Shallow Junctions

– Nanofilms Characterization

– Crystal defects and strain in device processing

– Nanocrystal Characterization:

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ITRS-SEMI Alignment on Ultrapure Water Spec

• UPW ITRS group identified limitations of use of ITRS tables for design UPW facilities – ITRS enables future technologies

• Collaboration between UPW ITRS group and SEMI resulted in development of new UPW quality guide (SEMI F063)

– F063 is a guide providing advanced Semiconductor Fabs with information required for setting internal specifications

– F063 is based on ITRS risk assessment– F063 considers UPW treatment technology and metrology

feasibility– F063 takes into account economical viability – The agreement is that F063 be updated every two year,

maintaining ITRS pace– The SEMI TF is attempting to align the F063 with ASTM standard

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Summary July 2010

Development / Improvement of the Yield Enhancement Chapter

– Addition of new key challenges • integrated AMC concept (together with Factory Integration), • next generation inspection

– ISMI / SEMATECH outlined a defect budget survey:• request to get support from IDMs (Asia, US, Europe) and TWG as

FEP, Interconnect, Litho,….• presentation survey outline available

(contact: [email protected])– European IDMs committed to work on IDM contribution to the

survey and chairing DDC - Defect Detection and

Characterization

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Outlook

Development/ Improvement of the Yield Enhancement chapter

– Reflection of current status and future requirements needs subsequent adjustment of outline and content of the chapter

– Request to IDMs, ESIA, JEITA, KSIA, SIA, TSIA, ISMI, academia contributing to ITRS:

• assure that sufficient contributors and resources are available

• surveys required for future updates e.g. DB&YM

1 san francisco july 14, 2010 itrs - ye itwg conference in san francisco (usa) july 14, 2009 l....

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