1 lecture 1: computer system structures we go over the aspects of computer architecture relevant to...

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1 Lecture 1: Computer System Structures We go over the aspects of computer architecture relevant to OS design overview input and output (I/O) organization cache and storage structure multiple processors

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Page 1: 1 Lecture 1: Computer System Structures We go over the aspects of computer architecture relevant to OS design  overview  input and output (I/O) organization

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Lecture 1: Computer System Structures

We go over the aspects of computer architecture relevant to OS design

overview input and output (I/O) organization cache and storage structure multiple processors

Page 2: 1 Lecture 1: Computer System Structures We go over the aspects of computer architecture relevant to OS design  overview  input and output (I/O) organization

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Computer System Operation

controllers and CPU can execute concurrently memory is a critical resource - memory controller synchronizes access to

memory device controller contains registers for communication with that device

• input register, output register — for data

• control register — to tell it what to do

• status register — to see what it’s done

all devices are attached to controllers which are joined by system bus

adapter – separate board controller

Page 3: 1 Lecture 1: Computer System Structures We go over the aspects of computer architecture relevant to OS design  overview  input and output (I/O) organization

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Input/Output

Synchronous I/O — CPU waits while I/O proceeds Asynchronous I/O — I/O proceeds concurrently with

CPU execution• Software-polling (programmed) I/O:

CPU starts an I/O operation, and continuously polls (checks) that device until the I/O operation finishes

• Interrupt-driven I/O: Device controller has its own processor, and executes asynchronously

with CPU• Device controller puts an interrupt signal on the bus when it

needs CPU’s attention When CPU receives an interrupt:

1. It saves the CPU state and invokes the appropriate interrupt handler using the interrupt vector (addresses of OS routines to handle various events)

2. Handler must save and restore software state (e.g., registers it will modify)

3. CPU restores CPU state

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Direct Memory Access, Memory-Mapped I/O

some devices (like character terminals) are slow compared to CPU-speed (say, each character typed can be serviced as separate interrupt)

others (disk controllers) are close to CPU-speed

DMA

• I/O controller can transfer block of data to/from memory without going through CPU

• OS allocates buffer in memory, tells I/O device to use that buffer

• I/O device operates asynchronously with CPU, interrupts CPU when finished

• note, that DMA controller competes with CPU for memory access memory-mapped I/O - convenient way of addressing I/O devices,

no specific I/O instructions are needed (used for video cards, ports)

• device registers are mapped to memory addresses, when accessed the data moves directly to registers

CPU

memory

I/O commands

data data

I/O controllerinterrupts

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Secondary Storage Provide secondary storage for system

(after main memory) Technology

• Covered with magnetic material

• Read / write head “floats” just above surface of disk

• Hierarchically organized as platters, tracks, sectors (blocks) Devices

• Hard (moving-head) disk — one or more platters, head moves across tracks

• Floppy disk — disk covered with hard surface, read / write head sits on disk, slower, smaller, removable, rugged

• CDROM — uses laser, read-only or read/write, high-density

• solid state - flash

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Storage-Device Hierarchy Storage systems organized

in hierarchy.

• Speed

• Cost

• Volatility Caching – copying

information into faster storage system; main memory can be viewed as a last cache for secondary storage.

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Multiple Processors

for reasons of economy, speed and reliability multipleprocessors are jointed into single system

• note: specialized micro-processors (in disk controller, graphics adapter keyboard) with no OS access are present in single-processor architectures

types

• multiple core processors – processors are on a single chip

• multiprocessors – several CPUs share bus and have access to common memory

asymmetric – processors have different capabilities, usually speed of access to various parts of memory differs

symmetric (SMP) – speed is the same

• blade – each processor is also equipped separate I/O, networking, each processor may boot independently and runs its own OS

• clusters – multiple independent computers jointed by either LAN or a high-speed network

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Lecture Review

to parallelize execution each device is connectedto a controller; all controllers are joined by commonbus; communication between controllers and CPU is interrupt based

the storage is hierarchical - fastest types of storage are accessed first; to exploit locality of reference caching mechanism is used; faster types of storage tend to be more expensive and less reliable

several processors may be connected together to create a multiprocessor system