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History of 64-bit Computing: AMD64 and

Intel Itanium Processors

Brett Casbeer, Adam Kenny, Chris Kopek, Nick Snead

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64-bit History

• “640K ought to be enough for anybody” – Bill Gates

• 64-bit twice as fast as 32-bits?• Benefits of 64-bit technology• Applications of 64-bit technology

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AMD64 Outline

• AMD Athlon 64 Specifications• Operating Modes• Register overview• DDR controller and Hypertransport

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AMD Athlon 64 Specifications

Infrastructure Socket 754Number of Transistors 105.9 million64-bit Instruction Set YES32-bit Instruction Set YESSystem Bus Technology HypertransportIntegrated DDR Controller YESOn-Chip Cache L1: 128KB

L2: 512KB-1024KBClock-Speed 1.8Ghz-2.4Ghz

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AMD64 Operating Modes

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AMD64 Register Overview

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Reduce Bottlenecks

• DDR Memory Controller– Built into CPU– Saves Time

• Hypertransport– Transport Speeds– Data packets

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Intel Itanium Outline

• Itanium Processor Specifications• Itanium Features• Itanium Epic Architecture• IA-64 Instruction Set• IA-64 vs. IA-32

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The Itanium Processor

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The Itanium Processor

• Designed for 1-4000 processor workstations and servers.

• Level 3 bus designed for communication between processors

• Level 2 cache reduces traffic• Page sizes from 4KB-256MB

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Itanium: EPIC Architecture

• Explicitly Parallel Instruction Computing

• Allows processor to run instructions parallel to other instructions

• Instructions “bundled” during the compiler stage

• No size limit for the groups of “bundled” instructions

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IA-64 Instruction Set

Source Code:

if (x == 4){

z = 9;}else z = 0;

• Using the IA-32 bit architecture the instruction follow this scheme:

1. Compare x to 4 2. If not equal goto line 5 3. z = 9 4. goto line 6 5. z = 0 6. // Program continues

from here

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IA 64 vs IA 32 architecture

• IA-32 bit architecture instruction flow:

1. Compare x to 4 2. If not equal goto line

5 3. z = 9 4. goto line 6 5. z = 0 6. // Program continues

from here

IA-64 bit architecture instruction flow:

1. Compare x to 4 and store result in a predicate bit (we'll call it P)

2. If P==1; z = 9 3. If P==0; z = 0

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Conclusion

• AMD64– Operating Modes

• Long Mode, Legacy Mode

– Registers• GPRs, XMM, RIP

– Reduce Bottlenecks• DDR Controller, Hypertransport

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Conclusion

• Intel Specifications and Features• EPIC Architecture

– Parallel Computing, Bundled Instructions

• IA-64 Instruction Set• IA-64 vs. IA-32