1 c.h. ho © rapid prototyping of fpga based floating point dsp systems c.h. ho department of...

1 C.H. Ho©

Rapid Prototyping of FPGA based Floating Point DSP Systems

C.H. Ho

Department of Computer Science and Engineering

The Chinese University of Hong Kong

30JUN2002

2 C.H. Ho©

Overview

Introduction Objective Float Design Flow Floating Point Number Representation Float Class Optimization Digital Sine-Cosine Generator Results Conclusion

3 C.H. Ho©

Introduction

FPGA based DSP systems prototyping methodology Using standard programming language for simulation and

verification Using floating point arithmetic on simulation Using fixed point operation on implementing hardware

FPGA systems could adapt Floating Point arithmetic Less overhead in developing DSP systems FPGA density has improved for using floating point operation

Float – A tools for porting floating point algorithm into hardware

Simulation/Optimization/Implementation can be completed using a single description

Optimize the floating point operation to balance the quantization error and the circuit size

Translate of a high level algorithmic description to an FPGA implementation (under development)

4 C.H. Ho©

Objective

The tools have the following features Designer need not have expertise in the implementation of

floating point arithmetic The size of exponent and fraction of the floating point number

can be different for each signal The optimizer uses a user-specified set of input vectors and a

cost function which takes into account the tradeoff between quantization error and the size of circuit

Reduced the design time• Simulation is done in high level

• Hardware implementation is correct by automatic construction

5 C.H. Ho©

Float Design Flow Algorithm is described

in Perl Language using the class Float

Cost function suggests the circuit size and quantization error required

Optimizer will minimizes the cost function by varying the precision of Float object

Simulate the algorithm by executing the program

VHDL code produced by compiler

Optimizer

Floating-PointAlgorithm

SynthesizableVHDL code

Cost Function

Float Class

Compiler

Use Float Class toimplement the algorithm Suggest the required size

and accuracy constraints

Float ToolsSimulator

6 C.H. Ho©

Floating Point Number Representation

Based on the IEEE 754 Floating Point Number Format e – biased exponent f – fraction ebits – size of exponent bias = 2ebits-1 –1 Numbers = 1.f x 2(e-bias)

IEEE double precision is used as reference signal for computation of quantization error

7 C.H. Ho©

Float Class Simulation of arbitrary precision floating point

arithmetic Core method

add()/multiply()• Return a new Float object representing the sum/product of the

argument• Calculate the IEEE 754 double precision as a reference value for

computing quantization error• Store the maximum and minimum range of this value for finding

minimum exponent setExponentSize()/setFractionSize()

• Adjust the size of the floating point number getValue()/setValue()

• Retrieve/write the value represented by Float object getQERR()

• Return the quantization error between the arbitrary size floating point number and IEEE double precision reference value

8 C.H. Ho©

Optimization

Two factors: Quantization Error/Circuit Size Quantization Error (QERR), in decibels

Area of the floating point adder, in Virtex slices

Area of the floating point multiplier, in Virtex slices

Cost Function (a and b are non-negative weightings):

i i

ii

ref

refoutQERR log20

sizeexponent 6size fraction12_ areaadd

2

15

size fraction106size exp8230_

areamul

QERRbareamulareaaddafj

ji

it

__cos

9 C.H. Ho©

Optimization

Uses Nelder-Mead method to minimize the cost function

Designer can adjust a, b to weight the relative importance of area and QERR

Optimization procedure Change the precision of Float variable Simulation the algorithm function at the specified precision Compare the result with the reference result and compute the

cost function Repeat until the optimization terminates

10 C.H. Ho©

Digital Sine-Cosine Generator

Let s1 and s2 denote the two outputs of a digital sine-cosine generator

We will use cos() = 0.9 in this paper

ns

ns

ns

ns

2

1

2

1

cos1cos

1coscos

1

1

11 C.H. Ho©


$cos_theta = new Float(23, 8, 0.9); $cos_theta_p1 = new Float(23, 8, 1.9); $cos_theta_m1 = new Float(23, 8, -0.1);

$s1[0] = new Float(23, 8, 0); $s2[0] = new Float(23, 8, 1);

for ($i = 0 ; $i < 50 ; $i ++) {

$s1[i+1] = $s1[$i] * $cos_theta + $s2[$i] * $cos_theta_p1;

$s2[i+1] = $s1[$i] * $cos_theta_m1 + $s2[$i] * $cos_theta; }

12 C.H. Ho©


This algorithm can be passed to different component for processing

Simulation• By executing the program, the correctness of the algorithm can

be verified Optimization

• Determine the suitable precision format for each of the five Float objects in the algorithm function

Implementation• Parsing the inner loop to produce an expression tree

• Generating the VHDL for implementation of reconfigurable computing platform

13 C.H. Ho©

Results

Different Configuration of Floating Point operator Implemented

Fraction Size Circuit Size (Virtex slices)

Frequency (MHz) Latency (cylces)

Multiplication

7 178 103 8

15 375 102 8

23 598 100 8

31 694 100 8

Addition

7 120 58 7

15 225 46 7

23 336 41 7

31 455 40 7

14 C.H. Ho©

Results

Simulation of Algorithm

-5

-4

-3

-2

-1

0

1

2

3

4

5

0 5 10 15 20 25 30 35 40 45 50

Ampl

itude

i

Waveform of Digital Sine-Cosine Generator

15 C.H. Ho©

Results

Quantization Error

1e-12

1e-11

1e-10

1e-09

1e-08

1e-07

1e-06

1e-05

0.0001

0.001

0.01

0.1

0 5 10 15 20 25 30 35 40 45 50

Noi

se fo

r diff

eren

t fra

ctio

n siz

e

i

Fraction size = 12Fraction size = 20Fraction size = 28Fraction size = 36

16 C.H. Ho©

Results

Optimization Result

0

50000

100000

150000

200000

250000

300000

12 16 20 24 28 32 36 40

Circ

uit S

ize E

stim

atio

n

Size of Fraction

Fixed Fraction SizeOptimized Fraction Size

17 C.H. Ho©

Conclusions

The Float Environment Enable designers to concentrate on higher level algorithmic

issue Increasing the productivity

The digital sine-cosine generator was implemented Using Float Environment Simulation and Optimization involved Achieve 2% - 5% reduction in area

1 c.h. ho © rapid prototyping of fpga based floating point dsp systems c.h. ho department of...

Documents