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Design of a 5GHz Phase-Locked LoopZainab Mohamad Ashari, Anis Nurashikin Nordin, and Muhamad Ibn Ibrahimy

Electrical and Computer Engineering Department

International Islamic University Malaysia

53100 Kuala Lumpur, Malaysia

zainab_ashari@yahoo.com

AbstractNoise or jitter performance is a major concern in the

design of phase-locked loop (PLL). Linearity and speed issues are of

relevance when receiving data at gigahertz speed. The main function

of a PLL circuit is to generate stable higher frequencies (GHz)

output from a lower input frequency signal. PLLs are often used in

communication technology to implement a variety of functions such

as clock recovery, frequency multiplication, and clock

synchronization. This paper presents the design and simulation

results of PLL with low jitter performance. The key goal is to design

and develop an analog PLL circuit for 5 GHz clock data recovery

circuit. The PLL comprises of a phase frequency detector (PFD),

low pass filter, voltage controlled oscillator (VCO), and feedback

divider. In this work, analog mixed-signal architecture of PLL is

simulated using hardware discipline modeling language, Verilog-

AMS HDL. Multilingual and Mixed-Signal simulator SMASH

software has been used for the Verilog-AMS design. A 5 GHz PLL

with less jitter was successfully designed in this work.

Keywords: Phase-locked loop (PLL), jitter, Verilog-AMS, PhaseFrequency Detector, Low-pass Filter, and Voltage-controlled Oscillator

I. INTRODUCTION

Phase-locked loop (PLL) is one of the techniques to generatehigh frequencies for receivers and transmitters. PLL wasintroduced in the communication technology and electronicdevices since early 1930 by De Bellescize, a French Engineer [1,2]. It started to be popular in industrial applications when itbecame an integrated circuit. Different types of PLLs were

developed for different applications and technologies in recentyears. New applications of PLL are in instrumentation,communication, and electronics devices such as memories, harddisk drives, and wireless transceivers.

Modern communication demands high speed performance indata transmission with low power consumption, low jitter, lowcost, and small size. A high speed transceiver is required innumerous applications and areas such as backplane routing, chip-to-chip interconnect integrated circuits and optical devices incommunication systems. The demands of high bandwidth andhigh speed input/output (I/O) performance especially in the chip-to-chip interconnect applications is extremely increased from timeto time [2, 3].

Another application of the PLL is in the clock data recovery

circuit (CDR). CDR is a major component of the transceiverwhich determines its performance [4]. A signal transmissionprocess is easily distorted for high bandwidth data. The resultingdata and clock signals will be noisy, jittery and difficult to extract.

Due to this reason, CDR circuit has become a crucial componentfor high speed performance to receive gigahertz data.

In this work, a mixed-signal (PLL) of 5 GHz CDR receivercircuit was designed. PLL clocks are required to be aligned to thetransitions of the input data stream [4].This paper presents thedesign and simulation results of high performance 5GHz PLLwith low jitter performance. The PLL circuit was designed usinghardware modeling language, Verilog-AMS HDL using SMASHsoftware.

This paper first describes basic architecture of phase locked-loop (PLL). Modeling and simulation of proposed PLL isdiscussed next in section III. Finally, the simulation results withimproved jitter performance and conclusion are analyzed.

II. BASIC ARCHITECTURE OF PHASE LOCKED LOOP (PLL)

The phase-locked loop is generally known as a negative-feedback system with forward gain term and feedback term.Various PLL architectures have been developed as its popularitygrew in communication systems. Programmable PLL, single andmulti-phase PLL, digital PLL, PLL with lock detector, PLLfrequency synthesizer, PLL FM/AM, single RF/ multi RF PLLand super PLL have been reported [5, 6].

The basic design of PLL usually consists of three functionalblocks which are phase detector (PD), loop filter, and voltagecontrolled oscillator (VCO) as shown in Fig. 1. This simpledesign of PLL is capable to supress noise from the input signal.For high frequency operations, a PLL should be capable ofoperating in both locked and unlocked conditions. The simplePLL circuit shown in Fig.1 can only operate in the lockedcondition .

The PLL technique is capable of generating high frequencieseven from a low-frequency reference. It is really suitable for anysystem which requires stable high frequency performance. Fig. 2demonstrates a basic frequency multiplication architecture whichis typically used for CDR circuits. It consists of PFD, charge-pump, low pass filter, VCO and divider. This architecture is quite

Fig. 1. Simple PLL circuit .

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Fig. 2. Multiplication architecture for PLL [5].

Fig. 3. Basic PLL architecture for CDR circuits [7].

popular for PLL design. However, the output signal suffers fromsubtantial skew with respect to input data [6] . Most of the clockdrives a large number of transistors and logic interconnectswhich causes delay.

Fig. 3 shows the basic architecture of PLL for CDR circuitswhich consists of five main blocks; phase detector, charge pump,low pass filter, voltage controlled oscillator, and decision circuit[7]. What makes the second PLL different with the first PLLarcitecture is the divider.

According to [6], the skew effect suffered using the PLLarchitecture of Fig.2 and Fig.3 can be reduced by adding a buffer

and a capacitor between the VCO and feedback divider. Thedesign of proposed PLL in Fig.4 is the advancement from Fig.2and Fig.3 with additional components and coding using Verilog-AMS HDL.

III.

MODELING AND SIMULATION

Many different simulator tools are available for designing andmodeling integrated circuits such as SPICE and analog hardwaredescription language (HDL). Conventionally, SPICE is one ofthe popular tools that support modeling and designing of analogcircuit. However, SPICE is not applicable for analog mixed-signal integrated circuit design [8]. An analog hardwaredescription language (HDL) allows the modeling of analog anddigital signals simultaneously. One of the advantages of Verilog-

AMS is that the electrical components are described based on themathematical description or behavioral expression. Thedescription and simulation of analog mixed-signal systems isobtained from the behavioral to the circuit level [8, 9].

Fig. 4. Architecture of proposed PLL model.

Fig. 5. PLL circuit design.

It is important to note that the Verilog-AMS is easy to usesince it needs simple expression to make a circuit work. Insteadof using complicated resistor, conductor, and transistor SPICEmodels, Verilog-AMS of SMASH software is chosen to designthe PLL circuit.

The proposed PLL architecture is composed of analog mixed-signal blocks. PFD, low pass filter, VCO, feedback divider, andresistor. The phase frequency detector is a digital block. The lowpass filter and the VCO are categorized as analog block. Fig.4illustrates the proposed modeling PLL architecture. Fig. 5illustrates the detailed connection of 5 GHz PLL circuit. ThisPLL compares the input signal at PFD with the output signal at

the VCO. Each block was simulated separately before connectedas an overall PLL system.

A.

Phase Frequency Detector (PFD)

The phase frequency detector (PFD) is a key component inPLL system. It compares the phase and frequency differentbetween the reference signal and internal feedback signal [1011]. The performance of a CDR circuit is determined by thephase frequency detector [11, 12]. The best phase detector shouldaccomplish three essential functions namely data transitiondetection, phase and frequency difference detection and lownoise. Fig. 6 shows the implementation of PFD in a PLL system.

Fig. 5. PFD block.

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The output of PFD is proportional to the injected input phaseand frequency signal with low noise. The output voltage of PFDis dictated by the verilog equation and verilog AMS code. Fig.6illustrates the verilog AMS code used to design the PFD. Fig.7illustrates the input signal of the PFD which contains jitter andFig.8 shows the clean output signal of PFD. The second input ofthe PFD, b is obtained from the feedback divider output and isshown in Fig.15.

( ) ( ) ( )( )inVsrcVoutV *0.20tanh**0.2+< (1)

Fig. 6. Verilog AMS code for PFD.

Fig. 7. Input signal of 50 MHz, (a).

Fig. 8. Output signal of 50 MHz, (c).

Fig. 9. RLC low-pass filter [13].

B. Loop FilterBased on Fig.4, the second block in the PLL after a phase

detector is a loop filter. The low pass filter with one pole and onezero is frequently used in designing CDR circuit based on thePLL approach [11, 14]. The transient response of the loop filterdepends on the magnitude of the pole and zero is slightlyimportant in designing stable low-pass filter. The circuit designof RLC low-pass filter is shown in Fig.9.The following formulasand coding in Fig.10 is used to verify the numerical values of the

RLC low-pass filter. The simulation result shown in Fig.11 isconstantly zero because the loop filter is used to diminish jitterfrom the input.

( )

LCLR

s

LCsGs 1

1

2++

= (2)

fLjXL 2= (3)

CjXc 2

1= (4)

( ) 22 RXXZ CL ++= (5)

The voltage and current of RLC low-pass filter is based onthree equations below.

( ) ( )1*Re1 bIsbV +< (6)

( ) ( )( )1*1 bVddtCapbI +< (7)

( ) ( )( )1*1 bIddtIndbV +< (8)

`include "../packages/disciplines.vams"`include "../packages/constants.vams"

module pfd(in, src, out);

inout in, src, out;electrical in, src, out;

parameter real gain = 0.40;analog

V(out)

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Fig. 10. Verilog AMS code for LPF.

Fig. 11. Waveform signal of RLC low-pass filter, (e).

C. VCO

Fig. 12. Verilog AMS code for VCO.

Fig. 13. Output waveform of VCO, (out).

VCO is another part of PLL system shown in between nodes eand out in Fig.5. It is frequency-controlled device which controlvoltage input and creates a frequency proportional to the controlvoltage [9]. It will generate high or low output frequency basedon the requirement value. Center frequency and VCO gain aretwo important parameters must be determined to design PLLsystem. In this work, the VCO is responsible to generate highoutput frequency signal compares to its input frequency. TheVCO was programmed using Verilog AMS code as shown inFig.12. Fig.13 illustrates the simulation results of the VCOoutput at 5 GHz frequency.

D. DividerThe frequency divider is also known as frequency down

scalers was also implemented in the PLL. The additionalfeedback divider between out and b in the PLL system is to forcethe VCOs frequency to be equal to the reference frequencysignal. The feedback loop indirectly makes the referencefrequency identical with the output frequency of the VCO over Ntimes. The following equation determines the value of feedbackdivider, N. The Verilog AMS code for divider shows in Fig.14The output frequency, fout is equal to the N times of referencefrequency, fref.The output waveform shows in Fig. 15 which isequal with the input frequency of PFD, 50 MHz.

refout Nff = (9)

Fig. 14. Verilog AMS code for divider.

`include "../packages/disciplines.vams"`include "../packages/constants.vams"module rlc(N1, N2);

parameter real res=3e3;

parameter real ind=68e-6parameter real cap=0.149e-12;

inout N1, N2;

electrical N1, N2;

analog beginV(N1,N2)

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Fig. 15. Feedback waveform of proposed PLL 50 MHz, (b).

Fig. 16. Output waveform of proposed PLL 5 GHz, (out).

IV.

DISCUSSION

With reference to the PFD simulation results in Fig.7 andFig.8, the output signal of 50 MHz was less noise compares tothe input PFD. This means that the proposed PFD circuit iscapable of handling GHz data and removing jitter. The output ofthe PFD circuit is an uncorrupted square wave which is ideal forclock-handling circuits. RLC low-pass filter is used to ensure theCDRs stability. The transient response of the RLC low-pass

filter depends on the magnitude of the pole/zero as shown inFig.11. The VCO generates a stable high frequency sinusoidalsignal based on the DC voltage output from the RLC. The highfrequency output of the VCO can be utilized. The divider blockdivides the output frequency produced by the VCO by a factor ofN in order to be equal to the input frequency signal, 50 MHz.This is proven in Fig.15. The divider provides a clean lowfrequency sinusoidal output which can be compared with theinput reference signal using the PFD. Fig. 16 demonstrates thatthe proposed PLL model can generate a clean high frequencyoutput a hundred times larger than the input frequency.

V.

CONCLUSION

This paper presented the design of 5GHz analog mixed signalPLL using Verilog-AMS SMASH Dolphin Integration softwareThe proposed design composed of PFD, RLC lowpass filter,VCO, feedback divider, and resistor. A 50 MHz input wassuccessfully applied in this PLL design to generate 5 GHzfrequency signal with less jitter performance.

ACKNOWLEDGMENT

This work is funded by the Ministry of Science and Technologys(MOSTI) Techno Fund Grant TF0409D100.

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