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Low-Power Switched-Capacitor Integrator for
Delta-Sigma ADCs
Tao Wang and Gabor C. Temes
School of Electrical Engineering and Computer Science
Oregon State University
Corvallis, Oregon, USA
Abstract A new low-power switched-capacitor integrator is
proposed for high-resolution ADCs. Compared to the
conventional switched-capacitor integrator, it achieves much
lower power dissipation for the same noise specifications. To
verify the effectiveness of the new integrator, and to compare it
with the conventional one, a third-order delta-sigma modulator
was simulated. A detailed comparison between the conventional
SC integrator and the proposed SC integrator is also presented.
I.
INTRODUCTION
Switched-capacitor (SC) ADCs are widely used inhigh-resolution applications for their insensitiveness toparasitics and relaxed accuracy requirements. However, theSC circuit introduces kT/C noise due to the thermal noisegenerated by the on-resistance of the sampling switches. Theoversampling ratio (OSR) in high-resolution low-to-mediumbandwidth ADCs may be large, and the quantization noisein such applications is easy to suppress by increasing the looporder, internal quantizer resolution and OSR.
CI=CS/2k
Cs1=CS/2
Cs2=CS/2
Vin
2Vdac
Vout
Vin
Cs1=Cs
Vout
Vdac
CI=CS/k
(b)
(a)
O1
O1
O2
O2
O1 O1
O1 O1
O2
O2 O2
Fig. 1. (a) Conventional SC integrator. (b) Nilchi-Johns integrator.
However, the kT/C noise depends only on the OSR,sampling capacitor size and input topology. For the same kT/Cnoise specification and the same input topology, the powerdissipation of the first integrator remains almost unchangedfor different OSRs. This is because the sampling capacitor sizecan be halved for every doubling of the OSR. The powerdissipation of the input integrator with halved load anddoubled speed is roughly unchanged, neglecting the parasiticsand the load capacitance. The power consumption of thequantizer and the digital decimation filter is proportional to theoperating speed. Therefore, the overall dissipation can bereduced by using a low OSR, while at the same time ensuringenough quantization noise suppression. However, the OSRcannot be too low. One reason is quantization noisesuppression concern mentioned above; another reason is thatthe chip area would be very big for large sampling capacitorsize.
Recently, Nilchi and Johns proposed a new SC integratorwhich has a lower kT/C noise for the same power dissipation(or lower power dissipation for the same kT/C noise)compared to conventional SC integrator [1]. It uses a voltagedoubling input branch. Fig. 1 compares the Nilchi-Johns
integrator with a conventional one. The new integrator hassmaller load capacitor and higher feedback factor than theconventional one, and therefore for the same clock frequencyand noise, the required OTA transconductance is muchsmaller (by a factor of 4) than in the conventional integrator.Unfortunately, due to the doubled voltages in the input branch,the maximum allowable input voltage is halved in the newcircuit. Hence, it is best suited for applications at the front endof a system, where the signal is very small.
In this paper, we propose a modified structure which has thesame beneficial features as the Nilchi-Johns integrator, butwithout the restrictions on the maximum input signal. Thepaper is organized as follows: Section II introduces the newSC input integrator for ADCs. Section III analyzes the new
integrator, and compares its properties with those of aconventional SC integrator. In Section IV, ADCs with thenew SC integrator and the conventional one are simulated andcompared. Section V summarizes the paper.
This research was supported in part by the NSF Center of Analog/DigitalIntegrated Circuits and by the National Semiconductor Corporation.
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Cs/Ns
Vin
Vdac
Vcm
Vcm
Vout
CI
Cs/Ns Cs/Ns Cs/Ns
O1 O1 O1
O1 O1 O1O2
O2 O2
O2
Fig. 2. The general structure of the low-power SC integrator.
II. LOW-POWER SCINTEGRATOR
Fig. 2 shows the general structure of the new SC integrator.1and 2here are non-overlapping clock phases. During 1,all the Nssampling capacitors are connected in parallel. Theeffective sampling capacitor is Cs during 1. The voltagedifference Vin-Vdacis stored on the sampling capacitors. Here,Vinis the input signal and Vdacis the feedback DAC output ofthe ADC. The difference of Vinand Vdacbecomes smallerfor a higher resolution feedback DAC and a more slowlymoving input, which means a higher resolution internalquantizer and a higher OSR. This is true for high-resolutionlow-to-medium bandwidth ADCs.
Cs
Vin
Vdac
Vcm
CI
Vout
Vcm
O1
O1O2
O2
Fig. 3. Noise analysis model in the sampling phase.
Fig. 4. Noise analysis model in the integration phase.
Fig. 3 shows an equivalent kT/C noise analysis modelduring sampling phase 1. The power of the sampling noisevoltage during 1 is kT/(OSRCs) [2]. Here, k is theBoltzmann constant, and T is the absolute temperature indegrees Kelvin. During 2, all the Nssampling capacitors areconnected in series and the effective capacitance is (Cs/Ns)/Ns.The voltage difference across this equivalent capacitance isNs(Vin-Vdac). Therefore, this sampling scheme amplifies the
difference between Vinand Vdacby a factor Ns. The power ofthe thermal noise charge delivered into the integrationcapacitor CI using the switches closed during 2 iskT(NsNs)/Cs. This value is very large for large N s values.However, as mentioned above, the sampling capacitors inseries realize a signal gain of Ns from the input Vin-Vdac.Therefore, the input-referred voltage noise power is still kT/Cs.Fig. 4 shows the noise analysis model during integration phase.
III. COMPARISON WITH THE CONVENTIONAL SC
INTEGRATOR
For comparison purpose, Figs. 5 and 6 show theconventional SC integrator and the low-power SC integrator inintegration phase. Here, k is the gain of the integrator. The
feedback factors Cand Lfor the two circuits are
kCkC
kC
ss
sC
+
=
+
=
1
1
/
/ (1)
kN
N
NCkNC
kNC
s
s
ssss
ssL
+
=
+
=2/)/(
)/( (2)
Neglecting the parasitics and the load from the next stage,the load capacitances of the integrators in the integration phaseare given by
Fig. 5. Conventional SC integrator in the integration phase.
Fig. 6. Low-power SC integrator in the integration phase.
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Fig. 7. A modified third-order low-distortion modulator with a multi-bit internal quantizer.
k
C
CkC
kCC s
ss
sCL
+
=
+
=
1/
/2
, (3)
kN
NC
NCkNC
kNCC
s
ss
ssss
ssLL
+
=
+
=/
/)/(
)/(2
32
, (4)
The power of the amplifiers is proportional to the requiredgm [1]. Hence, it is given by
sdB
C
CLdB
CmC CkCk
gkP 30,30
,0
===
(5)
2
30,30
,0
s
sdB
L
LLdB
LmLN
CkCkgkP
===
(6)
Here, k0 is the proportionality constant between the powerrequired and the transconductance of the amplifier, while -3dBis the closed-loop 3-dB bandwidth. Therefore, for the same
kT/C noise specification, the proposed low-power SCintegrator saves a significant amount of power. The saving isthe same as for the Nilchi-Johns integrator. Table I comparesthe performances of the conventional SC integrator and thelow-power SC integrator.
TABLE I. COMPARISON BETWEEN THE CONVENTIONAL SCINTEGRATOR AND LOW-POWER SCINTEGRATOR
Conventional
SC integrator
Low-power
SC integrator
Gain k k
Sampling capacitance Cs CsIntegration capacitance Cs/k Cs/(kNs)
kT/C noise 2kT/(OSRCs) 2kT/(OSRCs)
Feedback factor (1+k)- s(Ns+k)-
Capacitance load Cs(1+k)- (Cs/Ns)( s+k)
-
Power dissipation k0-3dBCs k0-3dBCs s-
C1/N
Vin
VrefpDi C
2
/N
Vcm
Vrefn
Di
DACs N
O2
O2
O2
O1 O1
O1O1
O1
Fig. 8. SC feedback DAC implementation.
IV. ADCUSING LOW-POWER INTEGRATOR
To verify the effectiveness of the new scheme, a modifiedthird-order low-distortion feed-forward modulator [3] with
a 15-level internal quantizer was simulated. For simplicity, N sin Fig. 2 was chosen to be 2. This structure was used toincorporate the low-power SC integrator. By removing thedelay in the feed-forward signal path, the structure becomes thestandard low-distortion feed-forward modulator (SLD) [4]and was used to incorporate the conventional SC integrator forsimulation.
For the modified structure, the adder operates during 2. Thequantization is done during the non-overlapping time. TheDAC output is already available before the next phase 1. Forthe low-distortion feed-forward structure [4], the adderperforms the addition in 1. The quantization is also done thenon-overlapping time. The DAC output is available before thenext phase 2.
Fig. 8 shows the implementation of the feedback DAC in
Fig. 7. N=14 and C1=C2=0.5Cswere used here. iD and iD_
are
the complementary digital thermometer-code outputs from thequantizer. At the beginning of the phase 1, some of thecapacitor DAC unit elements are connected to Vrefp, and therest to Vrefn, depending on the quantizer output.
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Fig. 9. The output PSDs of the third-order modulators.
Fig. 10. The output PSDs of the third-order modulators (kT/C noise included).
Fig. 11. Voltage swing across the sampling capacitor.
Fig. 12. The achievable Nsvalue versus the number of comparators in theinternal quantizer of the modulator.
Fig. 9 shows the power spectrum densities (PSDs) of themodulator outputs Voutin Fig. 7 and SLD withoutkT/C noise.Fig. 10 shows the output PSDs of the two modulators withkT/C noise. The simulated SNR was 86 dB for both cases forthe same input signal (-4.2dBFS). However, the powerdissipation of the first integrator with the low-power realizationis only one-fourth of the conventional one.
The effective voltage swing across the sampling capacitors
of the first stage integrator in Fig. 7 is shown in Fig. 11(normalized to the reference voltage). Fig. 12 shows theallowable Ns value versus the number of comparators in theinternal quantizer of the modulator. Nscan be made as high as4 for a 31-level internal quantizer without the voltage swing ofthe sampling capacitors exceeding the reference voltage of themodulator. However, the nonideal effects introduced by thefloating switches may limit Ns to lower values.
A dc analysis of the low-power stage [5] reveals that theinput bias voltage of the opamp, provided by the SC inputbranch, is Vcm + Ns(Vin,aVdac,a), where the subscript a denotesthe average value. Since the dc averages Vin,a and Vdac,a arekept equal by the loop, the input bias is forced to be Vcm . Theequivalent resistance connected between the opamp common
mode input and the bias voltage Vcm is12
ss TCN , where T is
the cycle of the non-overlapping clocks.
I. CONCLUSION
A low-power integrator was described which uses voltagemultiplication as the Nilchi-Johns integrator [1] but does notlimit the input signal swing. The performance of the newintegrator was analyzed and compared with that of theconventional integrator. The usefulness of the proposedstructure was verified by simulating third-order modulatorswith a 15-level internal quantizer using either the conventionalinput integrator or the proposed low-power one.
ACKNOWLEDGMENT
The authors are grateful to Prof. David Johns for informingthem about ref. [1], and for useful discussions.
REFERENCES
[1] A. Nilchi, D.A. Johns, Charge-pump based switched-capacitorintegrator for modulators, Electron. Lett. , 2010, 46, (6), pp. 400401.
[2] R. Schreier and G. C. Temes, Understanding Delta-Sigma DataConverters, IEEE Press/Wiley, 2005.
[3] H. Park, K. Nam, D.K. Su, K. Vleugels and B.A. Wooley, A 0.7-V870-W Digital-Audio CMOS Sigma-Delta Modulator, IEEE J. Solid-State Circuits, vol. 44, no. 4, pp.10781088, March 2009.
[4] J. Silva, U. Moon, J. Steengard, and G. Temes, Wideband low
distortion delta-sigma ADC topology, Electron. Lett., 2001, 37, (12),pp. 737738.
[5] M. Keskin, N. Keskin and G. C. Temes, An efficient and accurate dcanalysis technique for switched-capacitor circuits, Analog IntegratedCircuits and Signal Processing, vol. 30, pp. 239-241, March 2002.
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