04_i2c_rtc
TRANSCRIPT
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Real Time Clock and LCD Display
Task:
Using UP3 Education Kit board implement a stop-watch timer. Initialize Real Time Clock
(RTC) device and read seconds value afterwards. Minutes may either be read from RCT as
well, or computed based on seconds value. Output seconds and minutes on LCD display.
Also incorporate a Reset mechanism, so the stop-watch may be halted and started over.
Refer to UP3 manual for pin numbers.
I2C Bus
I2C is a two-line, bi-directional serial bus most suitable for short distance communication.
It was developed by Phillips in the 1980s, but still remains a widely used mean for data
exchange between many devices.
Devices on the I2C bus are organized as Masters and Slaves. To begin communication
Master device issues a start sequence. To end transmission Master device sends a stop
sequence. Slave devices just respond to these requests. Slave device is selected using a 7-bit
address, which is unique for every device connected to the same I2C bus.
Data exchange is made using two wires SCL (clock line) and SDA (serial data and
address line). Master device drives the SCL line to clock each new bit on the SDA line in
either direction. Slave device can force a wait by driving the SCL line Low. Before each
new clock cycle Master device must ensure the wait condition is not present.
Both SCL and SDA lines are open-drain pulled up with resistors. It means that any device
attached to the bus can drive the line Low, but it cannot drive it High. The device releases
the line instead to let it float. To implement a bi-directional transmission on SDA line an
open-drain buffer must be used. It can be instantiated using the following VHDL code:
with data_in select data_out
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Real Time Clock
UP3 Education Kit board has a Real Time Clock circuit with a built-in 32.768 kHz
oscillator (external crystal controlled). Eight bytes of internal RAM are used for holding
clock/calendar information, which is stored in binary coded decimal (BCD) format. Data is
transferred serially via a two-line, bi-directional I2C bus. After each Read or Write
operation the Address Register increments automatically. Voltage Sense and Switch
Circuitry detects power failures and turns to the battery supply when the main power source
is disconnected. Typical data retention time for the 50 mA/h 3 V lithium cell (included with
UP3 board) is approximately 5 years.
RTC operates as a slave device. Access to the internal RAM (Table 1) is granted if a start
sequence is followed by the correct slave address (D0h). Note that some bytes hold control
bits along with clock/calendar information. Bits DB7 and DB6 of the Hours byte contain
the century enable bit (CEB) and the century bit (CB). When CEB is set to High, the CB
will toggle at the turn of the century. Setting CEB to Low disables CB toggle feature. Bit
DB7 of the Seconds byte contains the stop bit (ST). When ST is set to High, the internal
oscillator is stopped (which reduces the current drain). Setting ST to Low restarts the
oscillator within one second.
Table 1: Real Time Clock internal RAM map
AddressData
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0Range
0 ST 10 Seconds Seconds 00-59
1 --- * 10 Minutes Minutes 00-59
2 CEB CB 10 Hours Hours 00-23
3 --- --- --- --- --- Day 01-07
4 --- --- 10 Date Date 01-31
5 --- --- --- 10 M. Month 01-12
6 10 Years Years 00-99
7 OUT FT S Calibration Control
*) --- denotes dont care value
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The seventh byte is used for calibration control. The oscillation rate of any crystal changes
with temperature. Real Time Clock circuit, provided on UP3 board, utilizes periodic
counter correction method. The calibration circuit adds (splits) or subtracts (blanks) counts
from the normal frequency of 32.768 kHz. Bit DB5 of the control byte contains the sign bit
(S). Setting S to High indicates positive calibration, while resetting it to Low indicates
negative calibration. Correction is made within a 64 minute cycle. Once per minute one
second is either shortened by 128 or lengthened by 256 oscillator cycles. Five lower bits
(DB4-DB0) of the control byte determine the rate, at which modification is made. If a
binary one (00001) is placed into the Calibration field of the control byte, only the first
two minutes in the 64 minute cycle will be adjusted. Placing binary two (00010) will
affect the first four minutes, and so on.
In order to test the correctness of the calibration settings, FT/OUT pin output (header
JP13.1 on the UP3 board) can be measured. When the frequency test bit (FT) is set to High,
the FT/OUT pin output should normally toggle at 512 Hz. The degree and direction of
oscillator frequency shift can be calculated based on deviation from the default value.
When FT is set to Low, the FT/OUT pin reflects the content of DB7 bit (OUT) of the
control byte.
RTC circuit exchanges data and address information with the FPGA device using two-line
I2C serial bus. One bi-directional line is used to transfer data signals (SDA), the second line
is for clock signal (SCL). The following bus conditions are defined:
Bus not busy -both data and clock lines remain High
Start data transfer - data line changes from High to Low, while the clock is High.
Stop data transfer - data line changes from Low to High, while the clock is High
Data valid - after the start condition the data line presents valid data during the
High period of the clock signal, data may be changed during the Low period of the
clock signal
Acknowledge after the reception of each byte the receiver device pulls data line
Low for one clock cycle, master receiver signals end of transmission by not sending
an acknowledge bit and slave transmitter leaves data line High
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To write data to the internal RAM master transmitter signals start data transfer condition
followed by slave receiver address and mode control bit. Master transmitter specifies slave
device address (1101000 in case of RTC) and Low mode control bit, which indicates
write operation. After RTC acknowledges this byte, master transmitter continues with the
eight bits of word address, which are placed to the address pointer. When address word is
acknowledged, master transmitter may begin sending data bytes one by one. RTC
acknowledges every data byte and automatically increments address pointer. When there is
no more data to send, master transmitter signals stop data transfer condition.
Reading from internal RAM starts out exactly the same as write operation. Master receiver
issues a start data transfer condition followed by slave device address and Low mode
control bit, RTC acknowledges first byte. Master receiver continues with word address,
which is also acknowledged by slave transmitter. Next, the start data transfer condition and
slave address are repeated, but this time mode control bit is High, which indicates read
operation. RTC sends an acknowledge bit and begins transferring the data bytes one by one.
Master receiver acknowledges every data byte, while slave transmitter automatically
increments address pointer. After the last byte of data master receiver does not issue an
acknowledge bit and generates stop data transfer condition.
LCD Display
LCD display is a very handy tool for showing information, debugging, etc. And it is no
wonder that many of todays FPGA boards are equipped with them. As a rule, LCDs require
fewer connections than LED displays and use less power, but they are controlled in a much
more complex way. While putting a few volts on the right pin would light a LED segment,
most of the LCDs have to be programmed.
Typically, LCD is equipped with a controller, which internally does all the functions.
Display data RAM (DDRAM), character generator ROM and RAM (CGROM and
CGRAM), liquid crystal display driver are also provided. Usually LCD display format
ranges from 8 to 80 characters. LCD modules have 14 or 16 (provided on UP3 board) pin
connections.
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There are two models of character generator: A00 (used in LCD provided with UP3 board)
and A02. Both have the standard ASCII character set, but the rest differs. The A00 model
has Japanese characters, plus a number of graphic, Greek and math symbols. The A02
model has the European characters plus a number of graphic, Greek and Cyrillic characters.
U1 (as LCD is marked on UP3 board) is a 16x2 character Liquid Crystal Display. Here
16x2 stands for two 16 character long lines. LCD can be configured to show only one
character line, though. Figure 1 shows LCD connected to the UP3 board. Note that LCD
module is connected facing away from the board, placing it otherwise would be illegal.
Figure 1: LCD display
The LCDs interface is standard. Connection is made through 16 pins. Eight pins form data
bus (DB7-DB0). Enable pin (E), register select pin (RS), read/write select pin (R/W) are
used for control. Finally, there are pins for power (Vss), ground (Vdo), for voltage to
control the contrast (Vo) and two more pins for the backlight (LED+ and LED-). Note that
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LCD shares data lines (DB7-DB0) with SRAM, SDRAM and FLASH. But controller
ignores incoming data while enable input signal (E) is set Low.
LCD module incorporates a controller, which performs all the functions using commands
sent by the user designed Finite State Machine or processor. It has two externally controlled
8-bit registers instruction register (IR) and data register (DR). IR stores instructions and
address information, DR data to be written or read. Write and read operation is selected
via R/W input signal, register is selected using RS input signal. Table 2 lists all available IR
and DR operations.
Table 2: IR and DR operations
RS R/W Operation
0 0 Instruction is written to IR
0 1 Busy flag (DB7) and address counter (AC) value (DB6-DB0) are read
1 0 Write data from DR to DDRAM or CGRAM
1 1 Read data from DDRAM or CGRAM to DR
Note that IR register can only be written. When IR is selected and R/W input is High
(indicating read operation) busy flag and address counter value are read instead.
Busy flag is set High while internal operation is being performed, so the next instruction
will not be accepted. Thus, new instruction must be sent only after busy flag is cleared (set
to Low). Many prefer to use appropriate delays instead of polling, though.
Address counter (AC) holds addresses to both DDRAM and CGRAM. Memory selection is
determined by the instruction. Note that after writing to (reading from) DDRAM or
CGRAM, AC is automatically incremented or decremented by one (direction is selected
using appropriate instruction).
The abbreviations DDRAM and CGRAM refer to the two types of memory used by LCD
module controller. DDRAM stands for display data RAM. It stores eighty 8-bit character
codes (although only 16 or 32 characters can be displayed at once). With shift instruction
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the viewable part of DDRAM can be altered. Figure 2 and Figure 3 illustrate relationships
between DDRAM addresses and the visible area of the LCD module for different display
modes.
Home position
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
After shift left
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
After shift right
4F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
Figure 2: 16x1 display visible DDRAM area (addresses are presented in HEX format)
Home position
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F
After shift left
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50
After shift right
27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E
Figure 3: 16x2 display visible DDRAM area (addresses are presented in HEX format)
Note that when in 16x2 mode the first line is represented by DDRAM address range
starting from 00h down to 27h (forty characters in total), but the second line starts from 40h
and ends with address 67h (also forty characters in total).
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Values stored in DDRAM are actually addresses for the character generator, which stores
5x7 dot and 5x10 dot character patterns. It consists of CGRAM and CGROM. CGROM
holds predefined character patterns, while CGRAM can be programmed to store custom
ones (either eight 5x7 dot or four 5x10 dot characters for LCD module provided with UP3
board). Figure 4 illustrates A00 model character generator patterns.
Figure 4: A00 model character generator patterns
The leftmost column on Figure 4 represents CGRAM. CGRAM custom character pattern is
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programmed line by line. Note that only five least significant bits would be represented in
character pattern. It is recommended to write empty lines as well as on power-up CGRAM
may not be totally empty. Note that custom characters get duplicated. For example, codes
00h and 08h represent one and the same custom character pattern.
Two rightmost columns on Figure 4 show 5x10 dot character patterns. Note that LCD
module provided with UP3 board is not best suited to display them. 5x10 dot font can be
activated only in 16x1 display mode, but three lower rows get separated as they are
displayed on the second line. Regardless of the mode, upper seven rows of the 5x10 dot
pattern will always be displayed.
LCD module uses eight 8-bit wide instructions. These commands are differentiated by the
leftmost non-zero bit. Bits to the right of the instruction bit represent additional parameters.
Table 3 lists all available instructions.
Table 3. LCD module instructions
Instruction D7 D6 D5 D4 D3 D2 D1 D0
Clear display 0 0 0 0 0 0 0 1
Cursor at home 0 0 0 0 0 0 1 ---*
Entry mode set 0 0 0 0 0 1 I/D S
Display control 0 0 0 0 1 D C B
Cursor or display shift 0 0 0 1 S/C R/L --- ---
Function set 0 0 1 DL N F --- ---
CGRAM address set 0 1 ADDRESS
DDRAM address set 1 ADDRESS
*) --- denotes dont care value
Clear display instruction writes 20h (space character code) to all DDRAM addresses and
writes 00h to AC, cursor is returned to home position and entry mode direction is set to
increment. Cursor at home instruction basically does the same, but DDRAM content and
entry mode direction are left unchanged.
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Entry mode instruction sets the way characters are written and read. I/D parameter defines
whether AC value would increment (when set to High) or decrement (when set to Low)
after data is written to or read from either DDRAM or CGRAM. With S bit enabled (set to
High) writing data to DDRAM will shift visible memory area right or left, visually leaving
cursor at the same position. I/D bit defines shift direction (left when High, right when
Low). When S bit is disabled (set to Low) visible memory area position is not changed,
thus cursor would visually move to the next position.
Display control instruction is used to manage LCD visual appearance. D bit turns display
ON/OFF (DDRAM content remains unchanged), C bit makes cursor visible or hides it and
B bit defines whether the character at the cursor position will blink or not. Setting
parameter High enables corresponding feature, Low value disables it. Note that cursor or
blinking position is determined by the address stored in AC. If AC stores CGRAM address,
then cursor or blinking would occur at the wrong place.
Cursor or display shift instruction either moves cursor one position or shifts entire display
left or right. S/C bit selects cursor (Low value) or display shift (High value), R/L
determines direction (left when Low, right when High). Note that in two-line mode cursor
jumps to the second line after the 40th character of the first line.
Function set instruction defines some hardware aspects of display. DL bit selects either
8-bit (High value) or 4-bit (Low value) interface. When using 4-bit interface only four data
bus lines are active (DB7-DB4), the rest is disabled. Firstly, four high order bits of data are
transferred, then four remaining low order bits. N bit sets the number of display lines (one
line when Low, two lines when High). Note that LCD supplied with UP3 board supports
both modes. F bit defines character size (5x10 dots when High, 5x7 dots when Low).
CGRAM address set instruction loads AC with the value specified in the address field and
causes subsequent data to be stored in the character generator RAM. DDRAM address set
instruction does exactly the same, but this time the display data RAM is selected.
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On power up LCD module performs internal reset itself. However, if power supply
problems occur, internal reset circuit would not function correctly. It may be necessary to
provide initialization by instruction. The initialization sequence is as follows:
POWER ON
15 ms delay
Function Set
4.1 ms delay
Function Set
100 s delay
Function Set
5 ms delay
Function Set
Display OFF
Display ON
Entry Mode Set