IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 4, APRIL 2009 1147Bridgeless SEPIC Rectier With Unity Power Factorand Reduced Conduction LossesEsam H. Ismail, Senior Member, IEEEAbstractInthispaper, anewbridgelesssingle-phaseacdcconverterwithanautomaticpowerfactorcorrection(PFC) isproposed. The proposedrectier is basedonthe single-endedprimary inductance converter (SEPIC) topology and it utilizes abidirectional switch and two fast diodes. The absence of an inputdiodebridgeandthepresenceofonlyonediodeintheowing-current path during each switching cycle result in less conductionloss and improved thermal management compared to existing PFCrectiers. Otheradvantagesincludesimplecontrolcircuitry, re-duced switch voltage stress, and low electromagnetic-interferencenoise. PerformancecomparisonbetweentheproposedandtheconventionalSEPICPFCrectierisperformed. Simulationandexperimental results are presented to demonstrate the feasibilityof the proposed technique.Index TermsBridgeless rectier, discontinuous current mode(DCM), power factor correction (PFC), rectier, single-ended pri-maryinductanceconverter(SEPIC), total harmonicdistortion(THD).I. INTRODUCTIONIN RECENT years, the demand for improving power qualityof theacsystemhasbecomeagreat concernduetotherapidly increased numbers of electronic equipment. To reduceharmonic contamination in power lines and improve the trans-mission efciency, power factor correction (PFC) research be-came an active topic in power electronics, and signicant effortshavebeenmadeonthedevelopmentsofthePFCconverters[1][4]. Asamatter of fact, thePFCcircuitsarebecomingmandatoryonsingle-phasepowersuppliesasmorestringentpower quality regulations and strict limits on the total harmonicdistortion (THD) of input current are imposed [5].Thepreferabletypeof PFCisactivePFCsinceit makesthe load behave like a pure resistor, leading to near-unity loadpower factor and generating negligible harmonics in the inputline current [6]. Most active PFC circuits as well as switched-mode power supplies in the market today comprise a front-endbridge rectier, followed by a high-frequency dcdc convertersuch as a boost, a buckboost, a Cuk, a single-ended primaryinductanceconverter (SEPIC), andaybackconverter. Thisapproach is suitable for a low-to-medium power range. As thepower level increases, the high conduction loss caused by thehigh forward voltage drop of the diode bridge begins to degradetheoverall systemefciency, andtheheat generatedwithinManuscript received April 2, 2008; revised September 18, 2009. Firstpublished October 31, 2008; current version published April 1, 2009.Theauthor iswiththeDepartment of Electrical Engineering, CollegeofTechnological Studies, Al-Shaab 36051, Kuwait (e-mail: eismail@ieee.org).Digital Object Identier 10.1109/TIE.2008.2007552Fig. 1. Conventional bridgeless boost rectier [7].the bridge rectier may destroy the individual diodes. Hence,it becomesnecessarytoutilizeabridgerectierwithhighercurrent-handlingcapabilityorheat-dissipatingcharacteristics.This increases the size and cost of the power supply, which isunacceptableforanefcientdesign.Anotherreasonforhighconduction losses in conventional active PFC circuits is due tothe fact that during each switching cycle, there are always threepowersemiconductorsintheowing-currentpath(twoslow-recovery diodes plus an active switch or a fast-recovery diode).In an effort to improve the power supply efciency, a num-berofbridgelessPFCcircuit topologieshavebeenproposed[7][24]. All thepresentedbridgeless topologies sofar im-plement a boost-type circuit conguration (also referred to asdual-boost PFC rectiers) because of its low cost and its highperformance in terms of efciency, power factor, and simplic-ity. In[25], asystematicreviewofthebridgelessPFCboostrectier implementations that have received the most attentionis presented along with their performance comparison with theconventional PFC boost rectier. A simplied schematic of theconventional bridgeless PFC boost rectier is shown in Fig. 1.The switching conduction sequences for the rectier of Fig. 1areas follows: 1) duringpositiveaclinecycle, Q1Dq2,D1Dq2, and2) duringnegativeaclinecycle, Q2Dq1,D2Dq1. Thus, during each switching cycle, the current pathgoes through only two semiconductor devices instead of three.As a result, the total conduction losses on the semiconductor de-vices will be considerably lower compared to the conventionalPFC boost rectier. These features have led power supply com-panies to start looking for bridgeless PFC circuit topologies.Althoughthebridgelessboost rectierisverysimpleandpopular, it has the same major practical drawbacks as theconventional boost converter. These drawbacks are that thedcoutput voltageisalwayshigherthanthepeakinput volt-age, inputoutput isolation cannot be easily implemented, highstartupinrushcurrent, as well as alackof current limitingduringoverloadconditions. Moreover, it iswell knownthat0278-0046/$25.00 2009 IEEE1148 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 4, APRIL 2009Fig. 2. (a) Proposed bridgeless SEPICrectier. (b) Circuit diagramforpositive half-line cycle. (c) Circuit diagram for negative half-line cycle.theboost converter operatingindiscontinuouscurrent mode(DCM) canoffer anumber of advantages, suchasinherentPFCfunction, verysimplecontrol, soft turn-onof themainswitch, and reduced diode reversed-recovery losses. However,the DCM operation requires a high-quality boost inductor sinceit must switch extremely high peak ripple currents and voltages.Asaresult, amorerobust input lter must beemployedtosuppress the high-frequency components of the pulsating inputcurrent, whichincreases theoverall weight andcost of therectier.In order to overcome these problems, a new bridgeless PFCcircuit based on the SEPIC topology is introduced in this paper.Unlike the boost converter, the SEPIC and Cuk converters offerseveral advantages in PFCapplications, such as easy implemen-tationoftransformerisolation,inherentinrushcurrentlimita-tion during startup and overload conditions, lower input currentripple, and less electromagnetic interference (EMI) associatedwiththeDCMtopology[26][30]. TheproposedbridgelessSEPIC rectier is shown in Fig. 2(a). This circuit is formed byconnecting two SEPICs, one with a positive input source andthe other having an inverted input source. The proposed rectierutilizesabidirectional switchandtwofast diodes. However,thetwopower switches, namely, Q1andQ2, canbedrivenwith the same PWM signal, which signicantly simplies theimplementation of the control circuit. The operational circuitsduringapositiveandanegativehalf-linecycleareshowninFig. 2(b) and (c), respectively. Note that during each switchingcycle, there is either one or two semiconductors in the owing-current path; hence, the conduction losses as well as the thermalstresses on the semiconductor devices are further reduced,and the circuit efciency is improved compared with thatof the bridgeless boost rectier. Another advantage of the pro-posed rectier is a reduction in the semiconductor voltage stressas compared with that of the conventional SEPIC PFC rectier.Thevoltagestress is reducedtoalevel that is comparablewith that of the PFC boost rectier. On the other hand, compo-nents current stresses are comparablewith their counterpartsin the conventional SEPIC. The proposed rectier structure uti-lizes three inductors, which are often described as a disadvan-tage. However, the three inductors can be coupled on the samemagnetic core [31], allowing considerable size and cost reduc-tion, and additionally, the near-zero-ripple-current conditionat the input port of the rectier can be achieved without com-promising performance. This condition is very desirable, partic-ularly for the DCM operation, because the generated EMI noiseisminimized, reducinginput lteringrequirementsdramati-cally. Moreover, both the conventional SEPIC PFC rectier andthe proposed rectier of Fig. 2(a) have the same count of totalcomponents whenthecoupledinductor techniqueis imple-mented. The major drawback of the proposed bridgeless SEPICPFC rectier in Fig. 2(a) is that it requires an additional gate-drive transformer.Theremainderofthispaperisorganizedasfollows. Prin-ciple of operationandtheoretical analysis are presentedinSectionII. Detailedanalysis, modeling, andcomparisonsarepresented in Section III. A simplied design procedure exampleandsimulationresultsareincludedinSectionIV. SectionVprovides adetailedanalysis of theproposedconverter withcoupled inductors. Finally, results from a laboratory prototypeand conclusion are given in Sections VI and VII, respectively.II. OPERATIONOFTHE PROPOSED BRIDGELESS PFCSEPIC RECTIFIERTheoperationoftheconverterwillbeexplainedassumingthat thethreeinductorsareworkinginDCM. OperatingtheSEPICinDCMoffers advantages over continuous-current-mode (CCM) operation, suchas a near-unitypower factorcanbeachievednaturallyandwithout sensingtheinput linecurrent [26]. Also, inDCM, bothQ1andQ2areturnedonat zerocurrent, whilediodesDo1andDo2areturnedoffatzero current. Thus, the loss due to the switching losses and thereverse recovery of the rectier are considerably reduced.The theoretical analysis of the proposed rectier is performedduringoneswitchingperiodinapositivehalf-periodof theinput voltage [Fig. 2(b)]. Similar to the conventional SEPIC andCuk converters, the DCMfor the proposed rectier occurs whenthe current through diode Do1drops to zero before the end ofthe switch-off time. Thus, the circuit operation in one switchingcycle, Ts, can be divided into three stages, as shown in Fig. 3. Tosimplify the analysis, it is assumed that the rectier of Fig. 2(a)ISMAIL: BRIDGELESS SEPIC RECTIFIER WITH UNITY POWER FACTOR AND REDUCED CONDUCTION LOSSES 1149Fig.3. TopologicalstagesfortheproposedrectierduringswitchingcycleTs. (a) Switch-on topology. (b) Switch-off topology. (c) DCM topology.is operating in steady state, and the following assumptions aremade during one switching cycle:1) The input voltage vac is considered to be an ideal rectiedsine wave, i.e., vac = Vm sin(t), where Vmis the peakamplitude and is the line angular frequency.2) All components are ideal; thus, the efciency is 100%.3) Theswitchingfrequency(fs)ismuchhigherthantheac line frequency (fL), so that the input voltage can beconsidered constant during one switching period (Ts).4) All the capacitors are big enough such that their switchingvoltage ripples are negligible during the switching periodTs. Moreover, the capacitor voltages vC1 and vC2 followthe input voltage vac, while the output voltage Voisequally divided between Co1 and Co2, i.e., Vo1 = Vo2 =Vo/2. Note that the assumption of vC1 and vC2 followingvac can be justied by considering the two loops contain-ing(vac, L1, C1, L2) and(vac, L1, C2, L3) [Fig. 2(a)].These two loops are independent of the converter topol-ogy. Since the net change in the inductor current is zeroduring one switching cycle Ts, it follows that the steady-state average voltage across all inductors must be equaltozeroduringeachswitchingperiodTs(voltsecondbalance). Thus, during eachTs, the steady-state averagevoltage across C1 (vc1-avg) and C2 (vc2-avg) must equaltheinputvoltagevac.InapracticalSEPICrectier, C1andC2have a small capacitance (0.52F), sothatbothvc1-avgandvc2-avgtracktheaclinevoltage, i.e.,vac = vc1 = vc2.Asmallhigh-frequencyripplevoltagealso appears across C1 and C2.Withtheseassumptions, themaintheoretical waveforms ofthe rectier in DCM during one switching cycle are shown inFig. 4. The circuit operation during a switching period Ts in apositive half-line cycle will be briey discussed next.Stage1[t0, t1], Fig. 3(a): WhentheswitchQ1isturnedon,Q2is conducting through its antiparallel body diodeDq2.Therefore, turningonoroff Q2hasnoeffect onthecircuitoperation. Thus, both of the switches Q1 and Q2 can be drivenbythesamecontrolsignal, whichhelpsinreducingthecostand complexity of the system. In this stage, the three-inductorcurrentsincreaselinearlyat aratethat isproportional totheinput voltagevac. Therateofincreaseofthethreeinductorcurrents are given bydiLndt=vacLn, n = 1, 2, 3. (1)ReferringtoFig.3(a),theswitchcurrentisequaltothesumof the three inductors currents. Thus, the peak switch currentIQ1-pk is given byIQ1,pk =VmLeD1Ts(2)where1Le=1L1+1L2+1L3(3)and D1 is the switch duty cycle. This interval ends when Q1 isturned off, initiating the next subinterval.Stage2[t1, t2], Fig. 3(b): At theinstant tl, switchQ1isturnedoff, diodeDo1isturnedon, simultaneouslyprovidingapathforthethreeinductorcurrents.Inthisstage,thethreeinductor currents decrease linearly at a rate that is proportionaltotheoutput voltageVo1. Thethreeinductors currentsaregiven bydiLndt= Vo1Ln, n = 1, 2, 3. (4)This interval ends whenthediodecurrent iDo1reaches theground level. The normalized length of this interval is given byD2 =2vacD1VoD2 =2D1Msin t (5)where M= Vo/Vm is the voltage conversion ratio.Stage 3 [t2, Ts], Fig. 3(c): In this stage, all the semiconduc-torsareintheir OFFstate, asshowninFig. 3(c). Thethreeinductorsbehaveascurrentsources, whichkeepthecurrentsconstant. The capacitors C1and C2are being charged ordischargedbythecurrentsiL2andiL3, respectively. Inthisstage, the voltage across the three inductors is zero.1150 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 4, APRIL 2009Fig. 4. Theoretical waveforms in DCM of the proposed rectier.Fig. 4 shows the blocking voltage of diodeDo2during theswitching cycle. For Do2 to be off during the entire positive acline cycle, the following condition must be satised:Vo2vac 0 M 2. (6)Equation(6)showsthatthestep-downpropertyislost(com-pared to the conventional SEPIC), which may be considered asadisadvantageinsomeapplications. However, theconstraintin (6) can be removed by implementing inputoutput galvanicisolation. On the other hand, similar to the conventional SEPIC,galvanicisolationcanbeobtainedeasilybyemployingtwowindinginductorsfor bothL2andL3insteadof twosepa-rate ones.III. ANALYSIS, MODELING,AND COMPARISONA. Voltage Conversion Ratio MThe voltage conversion ratio M= Vo/Vm in terms of circuitparameters can be found by evaluating the average diodeDo1current IDo1 during one line cycle of the ac input voltage, i.e.,IDo1 =1TLTL

0iDo1dt (7)whereTListheperiodofthelinevoltage. Thesymbol denotes the average value during one switching cycle Ts. FromFig. 4, theaverageoutput diodecurrent over oneswitchingperiod is given byiDo1 =1TsTs

0iDo1(t)dt iDo1 =D21Tsv2acLevo. (8)Substituting (8) into (7) and evaluating (7) giveIDo1 =V2m2ReVo=V2ac,rmsReVo(9)where Re is the emulated input resistance of the converter andequalsRe =2LeD21Ts. (10)On the other hand, the average output current during one linecycle is simply equal toIo =VoRL. (11)Sincetheintegralofthesteady-statecapacitorCo1currentover one line-cycle integration period is zero, the average valueof the diodeDo1current during one line cycle is equal to theaverage current through the load RL. Thus, by equating (9) and(11), the desired voltage conversion ratio MisM=

RL2Re=D12Ke(12)where the dimensionless parameter Ke is dened asKe =2LeRLTs. (13)The voltage conversion ratioMin (12) is the same expres-sion obtained for the conventional SEPIC PFC rectier in DCM[28], except for the denition of Le.ISMAIL: BRIDGELESS SEPIC RECTIFIER WITH UNITY POWER FACTOR AND REDUCED CONDUCTION LOSSES 1151Fig. 5. Large-signal circuit model of the proposed rectier.B. Boundaries Between CCM and DCMReferring to the diodeDo1current waveform in Fig. 4, theDCM operation mode requires that the sum of the duty cycleand the normalized switch-off time length be less than one, i.e.,D2< 1 D1. (14)Substituting (5) into (14) and using (12), the following condi-tion for DCM is obtained:Ke< Ke-crit =12(M + 2)2. (15)For values of Ke> Ke-crit, the converter operates in CCM;otherwise, the converter operates in DCM.C. Input Line CurrentAssuming that the efciency is close to unity, the averagedinput current over one switching period can be obtained fromthe instantaneous power balancing between the input and outputports of the rectier; thus,vaciL1 = vo1iDo1 =voiDo12(16)whereiL1 represents the input inductor current averaged duringone switching cycle. Substituting (8) into (16), we obtainiL1 =vacRe. (17)Similar to the conventional SEPIC PFC rectier, (17) showsthattheinputportoftheproposedrectierobeysOhmslawsothat theinput current issinusoidal andinphasewiththeinput voltage. At thispoint, alargesignal circuit model canbe developed by using (16) and (17), as shown in Fig. 5. Thismodel can greatly reduce the long computation time when it isimplemented in simulation software to predict the steady-stateand large-signal dynamic characteristics of the real circuit.D. Semiconductor StressesThe semiconductors voltage andcurrent stresses for theproposedandtheconventional SEPICtopologyarelistedinTable I. Referring to Table I, the ratio between the peak switch(or diode) voltages for the two topologies is given byV(Q-pk)BLV(Q-pk)Conv.=M + 22(M + 1)(18)TABLE ICOMPARISON BETWEENTHE CONVENTIONAL PFC SEPIC ANDTHEPROPOSED BRIDGELESS SEPIC TOPOLOGYIN DCMwhere the subscripts BL and Conv. refer to bridgeless andconventional, respectively. Moreover, TableI showsthat thesemiconductors current stresses are expressed in terms ofMand Ke. However, the value of Ke-crit for the proposed topol-ogyisalwayslessthantheoneobtainedbytheconventionalSEPIC [28], provided that both topologies are operating at thesame voltage conversion ratio M. The expression of Ke-crit forthe conventional SEPIC is given byK(e-crit)Conv. =12(M + 1)2. (19)Therefore, toensure a fair comparisonbetweenthe twotopologies, the semiconductors current stresses needtobecompared for the same ratio value ofKe/Ke-crit. When bothconverters are operating at the same ratio ofKe/Ke-crit, thentheratiobetweentheswitchanddiodermscurrentsfor theproposed topology and the conventional SEPIC becomesI(Q-rms)BLI(Q-rms)Conv.=I(Do-rms)BLI(Do-rms)Conv.=

M + 2M + 1. (20)Similarly, the ratio between the peak switch (or diode) cur-rents for the two topologies becomesI(Q-pk)BLI(Q-pk)Conv.=M + 2M + 1. (21)The graphical representation of (18), (20), and (21) is shownin Fig. 6, where the gure shows that the switch and diode in thebridgeless SEPIC topology are subjected to lower voltage stresscomparedtotheconventionalSEPICPFCrectier. Whereas,the switch and diode current stresses in the proposed topologyareslightlyhigherthantheircounterpartsintheconventionalSEPIC. This increase, however, is compensated by fewer semi-conductor components needed in the bridgeless topology. Also,1152 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 4, APRIL 2009Fig. 6. Switch-and-output-diode voltage and current stress ratio between theproposed bridgeless and conventional SEPIC rectiers as a function of M.the increase in the semiconductor current stress becomes lesspronounced as Mincreases.E. Input Current and Output Voltage RipplesThepeak-to-peakinput inductorcurrent rippleinboththeconventional SEPIC and proposed converters is proportional tothe operating duty cycle. When both converters are operating atthe same ratio of Ke/Ke-crit, then the ratio between the inputcurrent ripples is given byiL1,BLiL1,Conv.=L1,Conv.L1,BL 1 +M2 +M. (22)From(22),itisclearthatifbothrectiersaredesignedtohavethesameinputcurrentripple, thentheamountofinputinductance required by the bridgeless SEPIC is always less thanthat of the conventional SEPIC. The low-frequency peakpeakoutput voltage ripple is given byvo =1Co3TL/8

TL/8[iDo1Io] dt= TLVo2Co

1ReM2

1 + 12

1RL

(23)where Co1 = Co2 = Co. The output voltage ripple in theproposedtopologyistwicethat of theconventional SEPIC.However, connectinganadditional capacitor acrosstheloadterminals withacapacitanceof (CL = Co/2) produces thesame output voltage ripple as that of the conventional SEPIC.IV. DESIGN PROCEDUREAND SIMULATIONAsimplieddesignprocedureispresentedinthissectiontodeterminethecomponent valuesoftheproposedrectier.Supposethat wewant todesignthePFCrectier withthefollowing power stage specications:1) input voltage vac = 120 Vrms at 50 Hz;2) output voltage Vo = 400 Vdc;3) output power Pout = 200 W;4) switching frequency fs = 50 kHz;5) maximuminput current rippleiL1 = 20%of funda-mental current;6) output voltage ripple vo = 1% of Vo.From the aforementioned data, and assuming that the efciencyis 100%, the values of the circuit components are calculated asfollows.1) The voltage conversion ratio MisM=4002 120= 2.36. (24)2) The value of Ke-crit can now be evaluated from (15) asKe-crit = 26.34 103. (25)To ensure DCM operation, the following value ofKeisselected:Ke = 0.85 Ke-crit = 22.4 103. (26)Thus, evaluating (13) gives an equivalent inductanceLevalue ofLe =KeRL2fs= 179.1 H. (27)3) From (12), the required switch duty ratio D1 is found asD1 = 2KeM= 0.5. (28)4) From the given specications, the required input currentripple isiL1 = 20%VmRe= 0.47 A (29)where Re is evaluated from (10) byRe =2LeD21Ts= 72 . (30)Toachievethisrequirement,theinputinductancevalueL1 must beL1 =VmD1fsiL1= 3.6 mH. (31)If we choose the value of L2to be equal to the value ofL3, thenL2 = L3 =2L1LeL1Le= 377 H. (32)5) Therequiredoutputcapacitancetomaintainpeakpeakoutput voltage ripple of 2% of Vo can be calculated from(23) asCo1 = Co2 = 400 F. (33)6) Thecouplingcapacitor C1isanimportant element inthe SEPIC topology since its value greatly inuences thequalityofinputlinecurrent.ThecapacitorC1mustbechosen such that its voltage follows the shape of the inputac line voltage waveform with the lowest voltage rippleas possible. Also, C1shouldnot causelow-frequencyISMAIL: BRIDGELESS SEPIC RECTIFIER WITH UNITY POWER FACTOR AND REDUCED CONDUCTION LOSSES 1153Fig. 7. Simulated waveforms for the converter of Fig. 2(a) in DCM.oscillations withinductors L1, L2, andL3. Basedonthese constraints, the value of C1 = C2 = 1 F is chosenfor this particular design.7) Fordesignpurposes,itisimportanttohavetheclosed-formexpressions for the inductor currents duringtheDCM stage (i.e., ix and iy). These expressions are impor-tant for evaluating the rms currents in the three inductorsandthe couplingcapacitors C1and C2. ReferringtoFig. 4, theaveragecurrentsinL1andC1duringoneswitching cycle can be expressed asiL1 = D21Tsvac2L1

1 + 2vacVo

+ix(34)iC1 = D21Tsvac2

2vacVo

1Le1L2

1L2

iy(35)respectively. The current ixcan be simply found byequating (34) and (17) which givesix =vacRe

1 LeL1

1 + 2vacVo

. (36)Onthe other hand, since the average capacitor C1voltageduringoneswitchingcycleis equal totheinput voltage, itfollows that the low-frequency component (average value overone switching period) of iC1 can be represented byiC1 = C1Vm cos(t). (37)Hence, iy can found by equating (35) and (37).To verify the aforementioned design values, the proposed cir-cuit of Fig. 2(a) is simulated by using PSpice circuit simulator.1154 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 4, APRIL 2009Fig.8. SimulatedlinecurrentfortheconverterofFig.2(a)inDCMunderdistorted input voltage.TABLE IIPERFORMANCE COMPARISONOFTHE RECTIFIERSFig. 9. Bridgeless SEPIC rectier with coupled inductors.For the simulation, all switching devices and componentsareassumedideal withnolosses. Fig. 7(a)showsthat theinputlinecurrentfollowstheinputlinevoltage.Thepercentageofthe THD in the input line current is 0.03%. The waveforms ofthethreeinductorscurrentsatpeakinputvoltageareshownin Fig. 7(b) for several switching periods. Fig. 7(c) shows thatthepeakpeakoutput voltagerippleis8Vwithanaveragedc value close to400V. Fig. 7(d) shows the intermediatecapacitor voltage VC1 and the inverted input line voltage vac fora complete ac cycle. It is clear from Fig. 7(d) that VC1 followsthe input voltage vac. Fig. 7(e) shows the switch Q1 as well asthe output diodes (Do1andDo2) currents over a complete accycle. The simulated results conrm the operating principles ofthe proposed bridgeless PFC SEPIC rectier.The simulated results in Fig. 7 are obtained when the inputvoltage is a pure sinusoid. However, (17) predicts that theproposed rectier operates as a voltage follower, meaning thattheinput current naturallyfollowstheinput voltageprole.Fig. 10. Simulated waveforms for the converter of Fig. 9.TABLE IIIEXPERIMENTAL CONVERTER PARAMETERSTo demonstrate this behavior, the circuit of Fig. 2(a) has beensimulated with a distorted input voltage. In this case, the inputvoltage contains third, fth, and seventh harmonic components,with their magnitude being equal to 2.5% of the fundamentalcomponent, Vm. Thus, the THD in the input voltage is 4.33%.Fig. 8 shows the simulated input current waveform under a dis-torted input voltage condition. It is evident from Fig. 8 that volt-agedistortionsarereectedalmostperfectlyintheinputlinecurrent. Inotherwords, thesingleharmonicdistortionintheinput voltage is almost identical to the single harmonic distor-tion in the input line current. However, this does not mean anypractical restriction if the PFCcircuit is targeted to meet the IEC61000-3-2 limits, since the compliance with harmonic limits isalways checked with an ideal sinusoidal line voltage waveform.The performance of the proposed rectier is compared withtheconventional SEPICrectier throughPSpicesimulation.ISMAIL: BRIDGELESS SEPIC RECTIFIER WITH UNITY POWER FACTOR AND REDUCED CONDUCTION LOSSES 1155Fig. 11. Experimental waveforms for the converter of Fig. 2.The rectiers were simulated for the following input and outputdata specications: vac = 120 Vrms, Vo = 400 Vdc, Pout =200W, andfs = 50kHz. Toensureafair comparison, theinductance values in each topology are selected such that K =0.9 Kcrit. Moreover, anequivalent series resistor of 50and100misplacedinserieswithalltheinductorsandcapac-itors, respectively. Furthermore, actualPSpicesemiconductormodels have been used to simulate the switches: STY60NM60(600V, 60A, RDS-ON = 50m) for theactiveswitchandMUR460 ultrafast rectier (600 V, 4 A, VF = 1.05 Vat3A)forthediode. TableIIshowsthesimulationresults. Itis evident from Table II that the proposed rectier leads to animprovement of 1.5% in the conversion efciency compared tothe conventional SEPIC rectier. Note that although the switchanddiodesintheproposedschemearesubjectedtoahighercurrent stress than the conventional SEPIC, it has a better con-version efciency. This is because, during each switching cycle,therearefewer numbers of semiconductors intheowing-current path.V. BRIDGELESS SEPIC RECTIFIER WITHCOUPLED INDUCTORSIn the proposed circuit of Fig. 2(a), the three inductors haveidentical voltage waveforms; hence, they can be magneticallycoupled into a single magnetic core, as shown in Fig. 9. Notethat Fig. 9 shows that the inductors L1 and L2 are magneticallycoupled together by a mutual inductance M12, whereas L1 andL3are magnetically coupled together by a mutual inductanceM13. There is no magnetic coupling between L2 and L3. In thiscase, a standard EI magnetic core can be used for the practicalimplementation of the magnetic circuit [31].1156 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 4, APRIL 2009Thetopological stagesfor thecoupledinductor circuit ofFig. 9 are similar to the three topological stages for the uncou-pled case (Fig. 3). Referring to Fig. 9, k12 and k13 represent thecoupling coefcient betweenL1L2andL1L3, respectively.By proper coupling between the three windings, it is possible toobtain an input current having very low high-frequency content(near-zero current ripples). This can be demonstrated by writingthecharacteristicequationsofthecoupledinductorsL1, L2,and L3 during switch-on time which is given byddtiL1iL2iL3=1L2L3M12L3L2M13M12L3L1L3M213M12M13L2M13M12M13L1L2M212vacvC1vC2(38)where =L1L2L3L2M213L3M212> 0 (39)M12 =k12

L1L2, (0 < k12< 1) (40)M13 =k13

L1L3, (0 < K13< 1). (41)Notethat (39)must bepositivesincethetotal inductancematrixis symmetric positive denite, i.e., it has a positivedeterminant. At steady state, vC1 = vC2 = vac, and then from(38), the following condition must be satised for zero currentripples in the input current:diL1dt= 0 L2L3L3M12L2M13 = 0. (42)During switch-off time, one can show that the condition forzero current ripples in the input current is similar to (42).It shouldbementionedherethat thesteady-stateanalysispresentedinSectionsII andIII for theuncoupledinductorsis also valid for the coupled-inductor extension, except for thedenitionoftheeffectiveinductanceLe(3). Thisisbecauseonly the inductorsL2andL3determine the switching currentripple. Thus, for the coupled-inductor case, the denition of LebecomesLe =L2L3L2 +L3. (43)In the proposed topology, it is preferred that inductors L2andL3 have equal values so that they carry the same ripple current.In this case, the condition in (39) and (42) reduces tok212 +k213