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IEEE POWER ELECTRONICS LETTERS, VOL. 2, NO. 4, DECEMBER 2004 121

A Low-Cost Digital Controller for a Switching DCConverter With Improved Voltage Regulation

M. Murshidul Islam, David R. Allee, Siva Konasani, and Armando A. Rodriguez

AbstractA new control algorithm with improved regulationis presented for a switching dc buck converter. The controller isrealized with hardware description language (HDL) and can beimplemented in any process. The controller uses four decisionlevels, combines pulse frequency modulation (PFM), pulse widthmodulation (PWM), and uses dithering for improved regulation.The controller is prototyped on a field programmable gate array(FPGA) and experimental results show good performance overinput and load disturbances. Importantly, the controller does notrequire high resolution analog-to-digital conversion for signalprocessing, and also does not require fast digital clocking. Thiscontroller has significant potential to be widely used in industrialapplications where cost and design time are of great concern.

Index TermsDc-dc, digital controls, dithering, duty, fieldprogrammable gate array (FPGA), pulse frequency modula-tion (PFM), pulse width modulation (PWM), rapid prototype,regulation.

I. INTRODUCTION

THE OUTPUT voltage regulation for a dc-dc converter

has traditionally been accomplished using analog circuits

that are custom-designed for particular applications [1]. While

this approach has been commercially successful over many

years, it does lead to relatively long design, layout, and testing

times. However, a digital controller can be quickly designedwith high-level language, and automatically laid out using

appropriate software. This automated process dramatically

decreases the length of the design cycle. Moreover, digital

controllers are flexible and allow the implementation of more

functional control schemes [2][5]. Digital circuits are poten-

tially less susceptible to noise and parameter variations. The

disadvantage with digital control is generally inferior voltage

regulation. Other issues hampering the applications of digital

controllers are cost/performance, availability, and/or ease of

use [3]. Available digital signal processing (DSP) systems or

micro-controllers require a high-resolution analog-to-digital

converter (a/d), which in turn increases the word length for

DSP calculation, area and cost. In [3], the conventional flasha/d has been replaced with a time delay a/d and the digital

pulse-width modulator (DPWM) has been designed with a

hybrid delay-line/counter [3], [6]. The design is a significant

advance but still requires an a/d that depends on process param-

eters to get the expected delay and the a/d demands a redesign

for a new process. However, it is preferable to design a digital

Manuscript received June 16, 2004; revised November 4, 2004. Recom-mended by Associate Editor J. Sun.

The authors are with the Department of Electrical Engineering, Arizona StateUniversity, Tempe, AZ 85287-5706 USA (e-mail: allee@asu.edu).

Digital Object Identifier 10.1109/LPEL.2004.840256

Fig. 1. Buck converter with digital controller.

Fig. 2. Window definition for a four-level controller.

controller that works with few decision levels for simplicity

and can be realized in HDL for rapid transformation from one

process to another without any changes in the algorithm. The

design also needs to be small in area to be cost-competitive

with traditional analog controllers.

In this letter, a digital controller is presented that uses only

four decision levels to achieve improved regulation and better

performance. A block diagram of a buck converter with its com-

parators and controller is shown in Fig. 1. The basic algorithm

is presented in Section II and is realized with verilog-HDL.

The experimental results for various disturbances are presented

in Section III. The results show good performance considering

complexity, area, and output regulation. The controller is en-

tirely digital, making it less sensitive to process variation. It can

also be implemented on any process.

II. BACKGROUNDTHEORY

Due to flexibility and short design times, digital controllers

are becoming popular in power management. Recently, a

few companies have introduced dc-dc converters with digital

controllers [7]. In [8], a digital controller has been proposed

that uses two decision levels and takes the advantages of two

different types of control schemespulse width modulation

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122 IEEE POWER ELECTRONICS LETTERS, VOL. 2, NO. 4, DECEMBER 2004

Fig. 3. State diagram for a four-level controller.

(PWM) and pulse frequency modulation (PFM) control. The

algorithm attempts to maintain the output voltage between the

two decision levels. Better regulation is achieved by reducing

the voltage separation between the two levels. However, if the

separation is too small, instability arises. A good compromise is

to take at least of output voltage spreading on both sides

of the expected output voltage level [7]. Another disadvantage

of two-level control is that the regulation is poor, as the con-

troller lacks information while the output voltage is between

the two voltage levels.

To take advantage of the window concept and also improve

the regulation problem, a four-level controller is proposed here.

This controller has two internal levels ( high, low) that

are used for improved regulation and two external levels ( high,

low) that are used for fast recovery (Fig. 2). The state diagram

for the four-level digital controller is shown in Fig. 3. Two com-

parators with decision levels above and below the output

voltage determine the states for fast recovery. These states are

discontinuous state and ramp-up state. The two-internal levels

are set from the effective series resistance (ESR) of output ca-

pacitor or the maximum possible ripple voltage. These two in-

ternal levels create three more states realized here as dither-up,

dither-down, and continuous states.

If the output voltage decreases below low, thefinite state

machine moves into ramp-up mode. This usually is the result ofa sudden increase in the required load current. The quickest way

Fig. 4. Output regulation (around 35 mV) for two-level controller with load

disturbances from 200600 mA at a rate of 200 Hz.

to return to the desired output voltage range is to hold the power

switch (Sw1 in Fig. 1) on. The current through the inductor lin-

early rises providing more current to the load and raising the

output voltage. At the end of each digital clock period, the output

is monitored to determine if the output has risen to the desired

range. When it does, thefinite state machine returns to the con-tinuous state, but with a slightly larger duty cycle. If the duty

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ISLAM et al.: LOW-COST DIGITAL CONTROLLER FOR A SWITCHING DC CONVERTER 123

cycle is still too low, the output voltage will again fall below

low and the cycle repeats further increasing the duty cycle.

Since the controller is digital, the duty cycle can only be

set at time increments corresponding to the digital clock. For

example, with a 10-MHz digital clock (100-ns period) and

a 100-KHz switching clock (10- period), the duty cycle

can only be set at increments of 0.01(100 ns/10 ). Thisresults in a coarse setting of the output voltage. A simple

way to achieve high duty resolution is to increase the digital

clock frequency. A digital clock frequency of 1 GHz with

a switching frequency of 100 KHz allows the duty cycle to

be set to 1 part in 10 000. That is, there are 10 000 digital

clock periods in 1 switching cycle. However, this would lead

to excessive power consumption in the digital circuitry and

require an expensive deep submicron process. An alternative

approach to achieve high resolution using a slow digital clock

is known as dithering. The idea behind the digital dither is to

vary the duty cycle by a least significant bit (LSB) over a few

switching periods, so that the average duty cycle has a value

between two adjacent duty cycle levels. The output LCfilterperforms the averaging action required for dithering [9]. As

an example, a duty cycle of 0.3633 could be achieved with a

dithering over four-cycles with subsequent duty cycles of 0.36,

0.36, 0.37, and 0.36. To achieve this high resolution in duty

cycle, dithering was done in our controller as long as the output

stays in dither-up or dither-down states. In dither-up state the

duty is increased by one step after subsequent wait cycles

to drive the output voltage into the desired internal voltage

window. Similarly, in dither-down state the duty is decreased

by one step after subsequent period to achieve the desired

regulation. If the output voltage is in the internal window,

the controller works in continuous state without any changesinto the duty cycle. If the output voltage exceeds high, the

finite state machine moves into the discontinuous state. This

usually is the result of a sudden decrease in the required load

current. The quickest way to return to the desired output voltage

range without wasting energy stored on the output capacitor

is to simply allow the load to draw all its current from the

output capacitor. The power switch (Sw1 in Fig. 1) is kept off,

preventing any additional current flowing through the inductor

to the load. At the end of each digital clock period, the output

is monitored to determine if the output has fallen back into the

desired range. When it does, thefinite state machine returns to

the continuous state but with a slightly decreased duty cycle.

If the duty cycle is still too high providing too much load

current, the load voltage will again rise above high and the

cycle repeats further decreasing the duty cycle.

From the previous discussion, it is obvious that the discontin-

uous and ramp-up operation ensures fast response in case any

disturbance occurs and the dithering ensures better regulation

when the load is constant or the change is small.

III. EXPERIMENTAL RESULTS

Two-level and four-level control schemes have been imple-

mented on a Virtex1 XCV300-6PQ240C field programmable

gate array (FPGA). The two-level controller designed here1 Virtex is a registered trademark of Xilinx Incorporated, San Jose, CA.

Fig. 5. Output regulation (around 10 mV) for four-level controller with loaddisturbances from 200600 mA at a rate of 200 Hz.

Fig. 6. Output regulation (around 40 mV) for two-level controller with inputdisturbances from 35 V at a rate of 200 Hz.

has only three states: continuous, discontinuous, and ramp-up.

The window definition and the state diagram for this two-level

control scheme can be easily realized from thefigures (Figs. 2

and 3) presented for the four-level controller by just ignoringthe dither-up and dither-down states. The buck converter as

well as the comparator schemes is implemented on a printed

circuit board (PCB) with standard components. Thefilter com-

ponents are and . The rated input

voltage is 35 V and the output voltage is 1.8 V with a load

current of 200600 mA. The digital clock runs at 50 MHz

and the switching clock is at 100 KHz. As can be seen in

Figs. 4 and 6, the output regulation for the two-level controller

is very poor for load and input disturbances. The regulation

with two-level control for a load disturbance of 200600 mA

at a rate of 200 Hz is around 35 mV. Whereas, the regulation

with four-level control is around 10 mV for the same load

disturbances (Fig. 5). For input disturbances from 3 V to 5 Vat a rate of 200 Hz, the regulation in two-level control is about

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124 IEEE POWER ELECTRONICS LETTERS, VOL. 2, NO. 4, DECEMBER 2004

Fig. 7. Output regulation (around 5 mV) for four-level controller with inputdisturbances from 35 V at a rate of 200 Hz.

40 mV, and in four-level control it is 5 mV (Fig. 7). In brief,

a four-level controller gives much better regulation than its

two-level counterpart in low-frequency disturbances. It should

be noted that the improvement in regulation in four-level con-

trol comes with only two additional comparators. However, at

high-frequency disturbances (beyond 10 kHz) the four-level

controller provides regulations similar to the two-level con-

troller. So, a four-level controller is preferable if the load/input

disturbances are at low frequency. The numbers of gates used

in the FPGA for implementing the two-level and four-level

controller are 1.3 k and 1.7 k, respectively, which represents

about 2% and 3% of resources on a XCV300 device. During

the experiment, it was observed that both the two-level and

the four-level control become unstable if the external window

separation is below (40 mv) of output voltage level.

More research needs to be done to determine the exact min-

imum window separation needed for stability. To compare the

window-based design with a standard redesign technique, a

DSP implementation of the Type-3 analog compensator was

also performed using Xilinx System Generator. This implemen-

tation uses 16 16 multipliers to realize the digital filter and

requires about 30% of the chip area on the same FPGA device.

So, the four-level controller is a good choice for improvedregulation considering simplicity, area, and performance.

IV. CONCLUSION

A four-level controller is presented with state-diagram and

experimental results. The controller shows good performance

for input and load disturbances over its two-level counter-

part. Replacing the high-resolution a/d, required for most DSP

calculations, with comparators is a significant improvement

considering area, costand complexity. Also, the pulse-frequencyoperation described in ramp-up and discontinuous mode pro-

vides fast recovery for any disturbances. The extra window

allows the controller to work in dithering state, which eventually

improves the regulation. Moreover, the algorithm is realized

in verilog-HDL and implemented on a Xilinx Virtex FPGA

device. The controller uses logical comparison to make any

decision and avoids any complexity related to multiplication,

addition etc. to implement the algorithm. Thus, this control

technique is appealing for commercial applications due to its

simplicity, performance and rapid transformation from process

to process.

ACKNOWLEDGMENT

The authors wish to thank D. Gervasio and F. Zenhausern

of the Center for Applied NanoBioScience for the support and

fruitful discussions.

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