8/4/2019 00869810

1/6

VHDL-BASED DIGITAL CIRCUIT SYNT HESIS: A CASE STUDYFsibio Luiz Viana, Furio DamianiDepartment of Semiconductors, Instruments and Photonics

Faculty of Electrical and Computing EngineeringUniversity of CampinasAV.Albert Einstein, 400, 13081-970 Campinas, SP, Brazil{FabioV, Furio) @dsif.fee.unicamp.br

Abstract - Present day computer-aided design of VLSIcircuits calls for specifying the design at a sufficientlyhigh level of abstraction. This approach allows thedesigners to describe systems in terms of a set ofinteracting components, which facilitates the reuse ofsubsystems in a complex design and reduces the designcycle. This paper describes a case study of theDescription-and-Synthesis methodology for digitalcircuit design. Distinct digital addition algorithms werecoded in VHDL and automatically synthesized usingtwo different commercial Electronic DesignAutomation (EDA) environments. The resulting circuitswere simulated and the overall results are shown anddiscussed.

I. INTRODUCTIONTodays highly competitive electronics market andincreasing complexity ICs, due to manufacturetechnology evolution, fostered a high degree ofautomation in the design methodologies, usingcomputer-aided design tools in EDA environments [6].The combined forces of shrinking design cycles andever-more-complex circuits have favored the use of

higher levels of abstraction, with hardware descriptionlanguages (HDLs) [1,7] and methods for automaticgeneration (synthesis) of circuits [3,6].Digital circuit design methodologies are trans-formation sequences applied to circuit specification(and/or description). Their purpose is to generatevalidated descriptions, eventually used for themanufacture process [5,6,7,17].There are two approaches to design: top-down andbottom-up. In top-down design, transformationsequences start from a higher level of abstraction toarrive to a lower one. In bottom-up design,transformation sequences start from a lower level ofabstraction to arrive to a higher one.Usually, circuit design uses a combination of both.Top-down approach is used initially, refining thestarting circuit description to a detailed level, where theprimitive circuit components (cells) for the physicalcircuit implementation are known. The cells areretrieved from an existing library. These cells weredesigned with a bottom-up approach.

Until recently, digital circuit designs used theCapture-and-simulation methodology, that starts froman initial specification, involving a group ofrequirements. An initial block diagram is generated,containing functional structures, that are refined to alogical circuit. This logical circuit is captured byschematic capture tools for functionality verification oftiming and fault occurrence 171.Due to circuit complexity increase and new circuitmanufacture technologies, the Description-and-syn-thesis methodology is having better acceptance than theCapture-and-simulation [6]. This methodology reducesdevelopment time, allowing the manipulation of morecomplex structures and portability. The designer workswith the high level solution of the problem, without theneed of IC manufacture technology details knowledge~ 7 1 .

11. DESIGN SPECIFICATIONAND SYNTHESISDigital circuit design can be classified in threedomains: structural, physical and behavioral [3,6,7].Each domain can be further divided in abstractionlevels: architecture, RTL (Register Transfer Level),

logical and device.Each abstraction level in the structural domain ischaracterized by the primitive elements used for circuitrepresentation. In the physical domain by the geometriccells. And in the behavioral domain by the formalismsused in functional representation [3,6].In architecture level descriptions, large circuits canbe set up without the need to specify details of theunderlying hardware. In RTL evel, basic digital circuitcomponents are described in operational mode. Inlogical level, logical gate interconnections represent thecircuit. And in device level, circuit behavior isdescribed with the maximum of details. Fig. 1 shows adiagram with the primitive elements for eachabstraction level in each domain. The diagram alsodepicts the transformations involved in logic synthesis.The synthesis is an automatic process. It usesalgorithms that execute transformations between digitalcircuit specification levels, arriving at a physicalimplementation of the circuit. Each transformationintroduces structural or geometric details, maintainingthe circuit functionality [3,5,7,14].

0-7803-5766-3/00/!%1nnb m n n IFFF

8/4/2019 00869810

2/6

..+.PhysicalDomain

Fig. 1. Digital circuit design representation.The first commercial synthesis tools worked at the

lowest abstraction level. Eventually, they haveincorporated logical level tools, both structural andbehavioral, thus reaching higher abstraction levels. Thisinterest is justified for the following reasons [4,7]:Shorter design cycle, due to design automation. Asmost of circuit cost is associated to the developmentphase, automation reduces costs.Fewer errors, through the use of simulation orinternal verification rules.Exploration of design alternatives. The synthesisprocess allows variations in the design, maintainingspecifications. The designer can investigate para-meters as speed, area, energy consumption.Design process documentation. Being automated, thesynthesis tool stores information on changes in theinitial descriptions and the ensuing results.Evolution of the IC technologies. Technologyevolution has pushed the synthesis toolsdevelopment.In logic synthesis, functional units can be describedby Boolean equations and then synthesized in twophases. In the first phase, called logic minimization, thenumber of and, or and other operators in the Booleanequations are factored (minimized) to satisfy time andcost constraints. In the second phase, called technologymapping, these minimized Boolean equations areimplemented (mapped) using the logic gates from thegiven gate library in a selected technology [2,7,14].The control units (sequential logic) can be definedby finite state machines (FSM) nd synthesized in two

phases. In the first phase, called state minimization, thenumber of states is minimized and a binary encoding isattributed to each state. In the second phase, theequations obtained are submitted to the logicminimization and the technology mapping [7,14].In high-level synthesis (HLS), the complex circuitbehavioral description is transformed to a structural

representation by the application of allocation,scheduling and binding procediures [3,5,6,7].The allocation procedure determines the number ofcomponents and resources, at ithe register level, that willbe used in the implementation. Specifically, it executesthe following functions:It determines the number of functional units, theoperations executed by each unit, the number ofpipeline stages, the operation delays, as well as thesize of each unit.It determines the number of storage units (forexample, registers and memories), the read and writeaccess time for each unit, as well as their size.It determines the number, size, protocol and delayfor each system bus, as well as the connectionoptions of the functional and storage units.The scheduling procedure partitions and orders thebehavioral descriptions in time intervals, or controlsteps. During each step, usuallly a clock cycle, data aretransferred from a register to another and, if necessary,transformed by functional units during the transfer. Thescheduling procedure determines all the ope-rations thatmust be executed at each control step.The binding procedure assigns variables to storageunits and operations to functional units, as well as itspecifies the intercommunication busses.111. VHDL MODELING AND SYNTHESIS

The choice of an HDL involves the analysis of itscharacteristics: the hardware platform independence,the schematic capture tools integration, the simulation,the logical synthesis, the models diversity, thestandardization and the accessible cost [13.The VHDL language is a standard in the integratedcircuits modeling area, being supported by differenthardware platforms for the compilation, debugging,synthesis and simulation [9,10,13].A digital circuit can be modeled in VHDL in threedescription styles: structural, data-flow and behavioral[12,13,17]. Structural descriptions present a largerdetail, and are hierarchical arrangements of componentsand their interconnections.In the data-flow descriptions, the digital circuitcontrol and data flows are represented. The relationshipbetween the input and the output is determined byinstructions and concurrent signal assignments.Behavioral descriptions have less detail. They areused for digital circuit verification and functionalsimulation of its operations. Output to input relationshipis usually specified by VHDL, processes.In the case of synthesis, it is not easy to identifywhich VHDL description style will give better results.Although not optimized, structural models already havecircuit form. This form reduces optimization toolsefficiency. Behavioral models are more flexible,however undesirable hard ware structures can be

8/4/2019 00869810

3/6

generated, depending on the commands used and oftheir position in the description [17].The tools to synthesize VHDL descriptions performoptimizations seeking for area andor timing goals.Area optimization minimizes IC area. Timingoptimization seeks to fulfill operation frequencyspecifications [11,13,15].Thus, it is necessary to set design constraints forsynthesis tools. They set the optimization goals for achosen manufacture technology. The constraints set theminimum and maximum bounds or acceptable valueranges. An example is minimum and maximum delaytime for the signals.IV. ADDER CIRCUITS VHDL IMPLEMENTATIONAND SYNTHESIS- A CASE

The knowledge of cost and delay functions of thefundamental building blocks enables designers tooptimize costs and propagation delays of the largerunits built from them, A fundamental building block ofan arithmetic logic unit (ALU) is the binary adder.Therefore, the Dwcriptian-and-synthesis me-thodology was applied in the implementation of fixed-point adders. Some VHDL description styles foraddition algorithms were modeled. These descriptionswere synthesized, with area optimization, using thesame constraints, in two commercial EDA en-vironments.Considering a possible design space exploration,ripple-carry and carry-lookahead adders were modeledin VHDL. The 8 bit fixed point arithmetic sum wasperformed using two complement representation of thearguments [8,16].n the two EDA environments, botharchitecture types can be found as macrocells, stored ina cell library. These macrocells were used forcomparison purposes.Ripple-carry adders are structures composed by fulladders. The quantity of full adders is dependent on thenumber of bits used. Ripple-carry adders performaddition by summing the nth order bit of the arguments,generating a partial sum result and a carry. The cany issummed together with the (n+Z)th order bit of thearguments. This process is repeated until the addition ofall the bits is completed [8,16,17]. ipple-carry addersmodeled were [171:H rc l model: 8 bit ripple-carry adder with behavioraldescription.rc 2 model: 8 bit ripple-carry adder with structuraldescription. Data-flow description of full adders.

rc3 model: 8 bit ripple-carry adder with structuraldescription. Structural description of full adders.Carry-lookahead adders accelerate the additionoperation using the carry properties. Complementary

logic structures are implemented to eliminate theinterdependence between carry signals and theiroccurrence order. These structures produce thepropagate and generate signals [8,16,17]. Carry-lookahead adders modeled were [171:la1 model: 8 bit carry-lookahead adder withstructural description. Unit-lookahead-addersinstantiations(4 bit carry-lookahead adders).la2 model: 8 bit carry-lookahead adder withstructural description. Unit-lookahead-adderssinstantiations (4 bit cany-lookahead adders, thatmanipulate the group propagation and groupgeneration additional signals).The synthesis results were compared using area andtiming reports. Validation and performance wereevaluated using simulations, with timing informationfrom the manufacture technology.The design followed the sequence below:The adder circuits were described in VHDL, usingthe IEEE-1164 tandard package [9];The VHDL descriptions were compiled andsimulated to verify the functionality (validation);The VHDL compiled descriptions were synthesizedat the gate-level, using an independent technology(generic);These representations were optimized for area andmapped to the logical gates library of a manufacturetechnology (AMs CMOS 1.2pm);Simulation of the optimized circuits was used toverify their performance and functionality.Area optimization does redundant logic elimina-tion, thus reducing the number of gates used. This stepmaps the circuit in the manufacture technology, usingits specific macrocell library. The macrocell library issupplied by the manufacturing foundry and containscells with optimized layout [11,13,15].Area reports supply information on used cells. Italso gives an area estimate. The area unit in our case

was mils2 1 mil = 25,4 pm).Timing reports give circuit delay times in functionof a clock (virtual or specific). The synthesis toolsperform static timing analysis [11,13,15]. he outputsignal determination depends on the input signal timedelay and on the time delays of the gates in the criticalpath.All synthesis were carried with the sameoptimization constraints.For area constraints, no restrictions were made.Thus, area optimizations were executed in differenteffort levels: low, medium and high. The effort level isthe demand optimization degree of the circuit areareduction.

8/4/2019 00869810

4/6

V. RESULTS Fig. 5 show the simulation waveforms for the rclmodel and macrocell models.Table 3 shows the output stabilization time values.Input changes every 20 ns, and the pattern sequence(pa(7:O) and pb(7:0) values), s]nown n Fig. 3 and Fig. 5 ,are the same for all models.

Values obtained from the area and timing reportsare st"arized in Table 1 and Table 2. The values arenormalized in function of the smallest Value obtainedfor each implementation.Fig. 2 and Fig. 4 show the schematics for the rclmodel and macrocell synthesis, respectively. Fig. 3 and

rc l modelII Imdementation I Effort level I V e n d o r A I Vend,orB Ilo w 101 158medium, high 100 156rc2 modelrc3 modella1 model

low, medium, high 100 173low, medium, high 100 177low, medium, high 100 159~~~ ~~ ~

la2 model lo wmedium, high

macrocell low, medium, high

rcl model

rc3 model low. medium. hieh

~~ ~ ~~ ::q05100100 133

79 ( m e t ) 66 (met:)

107 (violated)

la1 model low, medium, highla2 model lo w

medium, highmacrocell low, medium, high

~ ~ ~ ~~115 (violated) 101(violated)94 (met ) 80 (met)

Table 2:Timing values. Values are normalized in function of the required time for all implementations.Met means that the outputcorrect values generation happened before required time. Violated means that in certain situations, depending to theinput signal values, the output correct values generation cannot happen before required time. Required time for allmodels was 15ns = 100%.

8/4/2019 00869810

5/6

-0 ".

Fig. 2. Synthesized rclmodel schematic.

O l O l O f l + X l I l l M 1 1 .+ x10101010 - x 1 w 0 0 0 0 0 + X i l l l l l l f + X1 01 01 1f ll + xooowooo t t1 I0.00 18. 00 36 . 00 54 . 00 7 2 . 0 0 9 0 .0 0 1 0 8 . 0 0 1 2 6 . 0 0 14 4

T i m e h S )~ ~~Fig. 3. Synthesized rc l model simulation waveforms.

Fig. 4. Synthesiz ed macrocell schematic.

/pa (7 :0)/& (7 :01

ISLnnR 01I0.00 1 8 . 0 0 3 6 . 0 0 5 4 . 0 0 7 2 . 0 0 9 0 . 0 0 108.00 1 2 6 . 0 0TimehS)

Fig. 5. Synthesiz ed macrocell simulation waveforms.

Table 3:Output sta bilization times. As can be seen in Fig. 3and Fig. 5, foreach 20 ns period the adder operands change and so theoutput stab ilization time varies.

8/4/2019 00869810

6/6

VI. CONCLUSIONSIn this paper, the basic notions of the methodologyand of the automated synthesis process involved werediscussed.The Description-and-synthesis methodology hasmany advantages: it is efficient, it allows an initialvalidation of the design and it grants the exploration ofdesign alternatives.The synthesis results were reported and theiranalysis show that for a given implementation andmanufacture technology, area and timing differenceswere always observed, depending on the synthesissoftware used.The difference is due to the mapping tool of thesynthesis software. It can be seen that the vendor Bsynthesis algorithms are tuned to timing optimization,whereas vendor A synthesis algorithms are tuned toarea optimization.Designs synthesized with vendor B softwareshowed about 50% area increase. Because of theaforementioned algorithms tuning, the vendor Bdesigns showed about 15%static timing improvement.The adder circuit design synthesis, performed on thedifferent VHDL descriptions, provides decisionparameters for complex designs. That will allow toevaluate the quality of the proposed specification andguide th e synthesis towards optimal circuits.These parameters are the circuit descriptionabstraction level, synthesis and simulation toolsefficiency, and design cycle time.Finally, Description-and-synthesis methodologyensues the design reuse, through the establishment ofcomponents library and facilitates the design migration

between different implementation technologies, withoutthe need for a complete change of design steps.

* This work was supported by grants from Brazilianagency CNPq.

REFERENCESBRAGE, Jens P. Language Models for DesignAutomation, Technical report, Department ofComputer Science, Technical University ofDenmark, July 1993.BRAYTON, Robert K., HACHTEL, Gary D.,SANGIOVANNI-VINCENTELLI,Albert0 Mul-tilevel Logic Synthesis, Proceedings of the IEEE,v.78, n.2, p.264-300, February 1990.CAMPOSANO, Raul High-Level Synthesis. In: I 1Brazilian Microeletronics School, p.93- 128,Gramado-RS, Brazil, March 1992.CAMPOSANO, Raul, ROSENSTIEL, WolfgangSynthesizing Circuits From Behavioral

Descriptions, IEEE Transactions on Computer-Aided Design, v.8, n.2, p.171-180, February 1989.[5] EDWARDS, Stephen, et al. Design of EmbeddedSystems: Formal Models, Validation, andSynthesis, Proceedings of the IEEE, v.85, n.3,

[6] GAJSKI, Daniel D., et al. System DesignMethodologies: Aiming at the lOOh Design Cycle,IEEE Transactions on Very Large ScaleIntegration (VLSI) Systems, v.4, n.1, p.70-82,March 1996.[7] GAJSKI, Daniel D., VAIIID, Frank, NARAYAN,Sanjiv, GONG, Jie Specification and Design ofEmbedded Systems, Prentice Hall Inc., 1994.181 HWANG, Kai Computer Arithmetic: Principles,Architecture, and Design.,John Wiley & Sons Inc.,1979.[9] IEEE Standard Multivalue Logic System forVHDL Model Interoperability. IEEE Standard1164-1993. The Institute of Electrical and Elec-tronics Engineers Inc., 1993.

[lo] IEEE Standard VHDL Language Reference Ma-nual, IEEE Standard 1076-1987. The Institute ofElectrical and Electro nks E ngineers Inc., 1987.[111 MENTOR GRAPHICS CORPORATION. Intro-duction to Autologic and Design Synthesis. MentorGraphics Corporation, 1994.[12] NAGASAMY, V., BER.RY, N., DANGELO, C.Specification, Planning and Synthesis, IEEEDesign & Test of Computers, v.9, n.2, p.58-68,June 1992.[131 PERRY, Douglas L. VHIIL, 2nd ed., McGraw-HillInc., 1994.[I41 RUDELL, Richard Tutorial: Design of a LogicSynthesis System, In: Proceedings of 33rd DesignAutomation Conference, Las Vegas, Nevada, USA,June 1996.[15] SYNOPSYS INC. CHIP Synthesis and Simula-tion. Synopsys Inc., 19961.[161 TAUB, Herbert Digital Circuits and Micropro-cessors, McGraw-Hill Inc., 1982.[17] VIANA, Fi5bio L. A Study on the Arithmetic-Digital Circuit Design Using VHDL DescriptionSynthesis. Master Thesis - Faculty of Electrical andComputing Engineering, University of Campinas,1997 (in Portuguese).

p.366-390, March 1997.