数字系统设计 1 spring 2015 zdmc – lec. #7 触发器 flip-flops march 31, 2015 刘鹏...
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数字系统设计 1Spring 2015 ZDMC – Lec. #7
触发器 触发器 Flip-FlopsFlip-Flops
March 31, 2015
刘鹏
浙江大学信息与通信工程研究所
数字系统设计 2Spring 2015 ZDMC – Lec. #7
复习复习
时序电路的基本概念 触发器
本节内容本节内容
组合电路和 Verilog 语言 测试
数字系统设计 3Spring 2015 ZDMC – Lec. #7
测试(补充)测试(补充)
测试是一个专门用来给电路的 HDL 模型施加的一个激励的 HDL 程序,目的是测试和观察其在激励下的响应。
典型的测试模块没有输入和输出,加到设计模块用于模拟的输入信号在激励模块中定义为局部 reg 型数据。显示设计模块的测试输出在激励模块中定义为局部 wire 型数据。用局部的标识来例化测试的模块。
测试模块的 HDL 格式: module test_module_name;
//Declare local reg and wire identifiers.
//Instantiate the design module under test.
//Specify a stopwatch, using $finish to terminate the simulation
//Generate stimulus, using initial and always statements.
//Display the output response (text or graphics (or both)).
endmodule
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Sequential Logic Sequential Logic 时序逻辑时序逻辑
Sequential Circuits 时序电路 Simple circuits with feedback Latches (level sensitive)
– Storage elements that operate with signal levels (rather than signal transitions) are referred to as latches.
Flip-flops (edge sensitive) (abbreviated FF)– A flip-flop is a binary storage device capable of storing one bit
of information.
Timing Methodologies 定时 Cascading 级联 flip-flops for proper operation Clock skew 时钟偏移
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C1 C2 C3
comparator
value
equal
multiplexer
reset
open/closed
new equal
mux control
clock
comb. logic
state
Sequential CircuitsSequential Circuits Circuits with Feedback
Outputs = f(inputs, past inputs, past outputs) Basis for building "memory" into logic circuits Door combination lock is an example of a sequential circuit
– State is memory– State is an "output" and an "input" to combinational logic– Combination storage elements are also memory
数字系统设计 6Spring 2015 ZDMC – Lec. #7
X1X2•••
Xn
switchingnetwork
Z1Z2•••
Zn
Circuits with FeedbackCircuits with Feedback
How to control feedback? What stops values from cycling around endlessly
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"remember"
"load""data" "stored value"
"0"
"1"
"stored value"
Simplest Circuits with FeedbackSimplest Circuits with Feedback
Two inverters form a static memory cell Will hold value as long as it has power applied
How to get a new value into the memory cell? Selectively break feedback path Load new value into cell
数字系统设计 8Spring 2015 ZDMC – Lec. #7
R
S
Q
Q'
R
S
Q
R'
S'Q
Q
Q'
S'
R'
Memory with Cross-coupled GatesMemory with Cross-coupled Gates
Cross-coupled NOR gates Similar to inverter pair, with capability to force output to 0 (reset=1) or 1
(set=1)
Cross-coupled NAND gates Similar to inverter pair, with capability to force output to 0 (reset=0) or 1
(set=0)
数字系统设计
Setting the Latch (FF)Setting the Latch (FF)
Pulsing the SET input to the 0 state when (a) Q = 0 prior to SET pulse; (b) Q = 1 prior to SET pulse. Note that, in both cases, Q ends up HIGH.
9Spring 2015 ZDMC – Lec. #7
数字系统设计
Resetting the Latch (FF)Resetting the Latch (FF)
Pulsing the RESET input to the LOW state when (a) Q = 0 prior to RESET pulse; (b) Q = 1 prior to RESET pulse. In each case, Q ends up low.
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数字系统设计 11Spring 2015 ZDMC – Lec. #7
Reset Hold Set SetReset Race
R
S
Q
\Q
100
Timing BehaviorTiming Behavior
R
S
Q
Q'
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S R Q0 0 hold0 1 01 0 11 1 unstable
State Behavior of R-S latchState Behavior of R-S latch
Truth table of R-S latch behavior
Q Q'0 1
Q Q'1 0
Q Q'0 0
Q Q'1 1
数字系统设计 13Spring 2015 ZDMC – Lec. #7
Theoretical R-S Latch BehaviorTheoretical R-S Latch Behavior
State Diagram States: possible values Transitions: changes
based on inputs
Q Q'0 1
Q Q'1 0
Q Q'0 0
Q Q'1 1
SR=00SR=11SR=00
SR=10
SR=01
SR=00SR=10
SR=00SR=01
SR=11 SR=11
SR=10SR=01
SR=01 SR=10
SR=11
possible oscillationbetween states 00 and 11
数字系统设计 14Spring 2015 ZDMC – Lec. #7
Observed R-S Latch BehaviorObserved R-S Latch Behavior
Very difficult to observe R-S latch in the 1-1 state One of R or S usually changes first
Ambiguously returns to state 0-1 or 1-0 A so-called "race condition" Or non-deterministic transition
SR=00SR=00
Q Q'0 1
Q Q'1 0
Q Q'0 0
SR=10
SR=01
SR=00SR=10
SR=00SR=01
SR=11 SR=11
SR=01 SR=10
SR=11
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R
S
Q
Q'
Q(t+)
R
S
Q(t)
S R Q(t) Q(t+)0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 X1 1 1 X
hold
reset
set
not allowed characteristic equationQ(t+) = S + R’ Q(t)
R-S Latch AnalysisR-S Latch Analysis
Break feedback path
0 0
1 0
X 1
X 1Q(t)
R
S
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enable'
S'Q'
QR' R
S
Gated R-S LatchGated R-S Latch
Control when R and S inputs matter Otherwise, the
slightest glitch on R or S while enable is low could cause change in value stored
Set Reset
S'
R'
enable'
Q
Q'
100
数字系统设计 17Spring 2015 ZDMC – Lec. #7
period
duty cycle (in this case, 50%)
ClocksClocks
Used to keep time Wait long enough for inputs (R' and S') to settle Then allow to have effect on value stored
Clocks are regular periodic signals Period (time between ticks) Duty-cycle (time clock is high between ticks - expressed as
% of period)
数字系统设计 18Spring 2015 ZDMC – Lec. #7
clock
R' and S'
changing stable changing stablestable
Clocks (contClocks (cont’’d)d)
Controlling an R-S latch with a clock Can't let R and S change while clock is active (allowing R
and S to pass) Only have half of clock period for signal changes to
propagate Signals must be stable for the other half of clock period
clock'
S'Q'
QR' R
S
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clock
R
S Q
Q' R
S Q
Q'R
S
Cascading LatchesCascading Latches
Connect output of one latch to input of another How to stop changes from racing through chain?
Need to control flow of data from one latch to the next Advance from one latch per clock period Worry about logic between latches (arrows) that is too fast
数字系统设计 20Spring 2015 ZDMC – Lec. #7
Master-Slave StructureMaster-Slave Structure
Break flow by alternating clocks (like an air-lock) Use positive clock to latch inputs into one R-S latch Use negative clock to change outputs with another R-S latch
View pair as one basic unit master-slave flip-flop twice as much logic output changes a few gate delays after the falling edge of
clock but does not affect any cascaded flip-flops
master stage slave stage
P
P'
CLK
R
S Q
Q' R
S Q
Q'R
S
数字系统设计 21Spring 2015 ZDMC – Lec. #7
Set1s
catch
SR
CLKPP'QQ'
Reset
MasterOutputs
SlaveOutputs
The 1s Catching ProblemThe 1s Catching Problem
In first R-S stage of master-slave FF 0-1-0 glitch on R or S while clock is high "caught" by master
stage Leads to constraints on logic to be hazard-free
master stage slave stage
P
P'
CLK
R
S Q
Q' R
S Q
Q'R
S
数字系统设计 22Spring 2015 ZDMC – Lec. #7
10 gates
D Flip-FlopD Flip-Flop
Make S and R complements of each other Eliminates 1s catching problem Can't just hold previous value (must have new value ready
every clock period) Value of D just before clock goes low is what is stored in flip-
flop Can make R-S flip-flop by adding logic to make D = S + R' Q
D Q
Q'
master stage slave stage
P
P'
CLK
R
S Q
Q' R
S Q
Q'
数字系统设计 I 23Spring 2015 ZDMC – Lec. #7
课后作业课后作业
习题: /P248 5.2, 5.3, 5.4,5.6,5.9, 5.12,5.13,5.14 ;
Verilog HDL 语言 自学