8/13/2019 Zili_Yu

1/28

Bits&Chips Hardware Conference 2012

Low-Power Receive-Electronics for a Miniature 3D Ultrasound ProbeZil i Yu

Electronic Instrumentation Laboratory

Delft University of Technology

Imaging the Heart with Ultrasound

8/13/2019 Zili_Yu

2/28

2

Introduction

Heart Diseases

No.1 cause of death globally.(World Health Organization 2011)

In 2008, about 17.3 million people

died from heart diseases, representing 30% ofthe global death.

Accurate diagnosis is of vital importance!!

Echocardiography

use ultrasound to visualize theinner structure of the heart.

Safe, low cost and good quality.

8/13/2019 Zili_Yu

3/28

3

Echocardiography Basics

Trans-Thoracic

Echocardiography

(TTE)

Trans-Esophageal

Echocardiography

(TEE)

(Available by http://en.wikipedia.org)

Two Types of Echocardiography:

outside the body

attenuation due to the

ribs and lungs, etc.

inside the body

less attenuation

http://en.wikipedia.org/http://en.wikipedia.org/

8/13/2019 Zili_Yu

4/28

4

Imaging Principle

energy MechanicalDomain

Electrical

Domain

Piezoelectric transducer

symbol

Tx

Rx

Control

&

Signal

processing Display

8/13/2019 Zili_Yu

5/28

5

From 2D to 3D

1D array

2D array

(matrix)

2D plane

slow

small element count

3D volume

fast

large element count

8/13/2019 Zili_Yu

6/28

6

3D Trans-Esophageal Echocardiography (TEE)

Limited space (L: 2 cm, W: 1 cm, H: 1 cm)

Large number of elements (> 2000 elements)

1 eurocentHierachical design:

(1) A proper system

partitioning.

(2) An optimal signal

processing algorithm.

(3) Simple and low-power

circuit implementation.

Challenges:

Size

Temperature

Interconnection

8/13/2019 Zili_Yu

7/28

7

Both Tx and Rx transducers can be optimized for their specific roles.

Protection circuitry is no longer needed.

TxRx

High voltage pulses

(>100V)

Low voltage echo signal( < 1Vrms )

Separation of Transmit (Tx) and Receive (Rx) transducers

System Partitioning

8/13/2019 Zili_Yu

8/28

8

System Block Diagram

8/13/2019 Zili_Yu

9/28

9

Receive-Signal Features

Typical signal level: 10V ~ 100mV

Frequency: several MHz.

Dynamic range: 80dB, time-gain-compensation (TGC) is needed.

Time delay: signals should be aligned in time-domain.

Dynamic Range

A

I

D

CB

F

G H

E

Time Delay

8/13/2019 Zili_Yu

10/28

10

Rx Signal Processing Architecture

To reduce the

design complexity,

simplifications aremade in the time-

gain-compensation

(TGC) scheme and

micro-beamforming

methodology.

8/13/2019 Zili_Yu

11/28

11

The Time-Gain-Compensation Scheme

Ideal compensat ion:

Very fine gain steps

Complicated electronics.

Four-step

compensat ion:

Discrete gain settings

(0dB/12dB/26dB/40dB).

Timing is determined

by an external controlsignal (2-bit control).

Very simple

electronics!

8/13/2019 Zili_Yu

12/28

12

Micro-beamforming Scheme

Delay division: a coarse

delay, common for all elements

of a group, and a fine delayfor

each individual element within a

group.

Pre-steering is applied in

such a way that all groups get

the same delay pattern, which

has the advantage that the

delay-control c ircui t can be

sharedamong all groups.

Example: Delay profile for a 99 matrix transducer.

8/13/2019 Zili_Yu

13/28

13

LNA and TGC Amplifier

TGC amplifier

LNA Single transistorimplementation

Differential pair with

source degeneration

8/13/2019 Zili_Yu

14/28

14

TGC Amplifier

V/Iconverter

I/Vconverter

Source follower

Gain=2RL/RS 0dB/12dB/26dB/40dB

8/13/2019 Zili_Yu

15/28

15

TGC Amplifier: Simple V/IConverter

Vin

i=GmVin =Vin[gm/(1+gmRS)]

Vin/RS

when RS>> 1/gm

RS

Conventional

transconductance

stage with source

degeneration

Accurate V/I conversion

requires either a high

value for Rsor gm.

8/13/2019 Zili_Yu

16/28

16

TGC Amplifier: Accurate V/I Conversion

Vbias

Trans-conductance stage

with CASFVF structure [1]

Vin M1

M3

IS1

IS2CC

Vout

M2iout

Vcm

Feedback loop boosts gm1by a

factor of gm2ro2

Minimize the parasitic

capacitance by careful layout.

[1] J.Ramirez-Angulo, S.G. Ivan Padilla, et al., Comparison of Conventional

and New Flipped Voltage Structure With Increased Input/Output Swing and

Current Sourcing/Sinking Capabilities, IEEE International Midwest

Symposium on Circuits and Systems, pp.1276-1291, 2005.

CASFVF: CAScoded-Flipped-Voltage-Follower

8/13/2019 Zili_Yu

17/28

17

TGC Amplifier: Kelvin Switches

Eliminate the errors due to the ON-resistance of the MOS switches.

8/13/2019 Zili_Yu

18/28

18

TGC Amplifier: I/VConversion

Cascoded current mirrors are used to reduce gain errors due to channel length modulation.

Gain=2RL/RS

8/13/2019 Zili_Yu

19/28

19

TGC Amplifier: Measurement Results

Die micrograph and layout of the prototype Gain measurement for 4 gain settings (4.5 MHz ~ 7.5 MHz)Gain error less than 1 dB for all settings.

Input referred noise voltage < 50 Vrms(4.5 MHz ~ 7.5 MHz, 40 dB gain setting).

Power consumption: 130 W when driving a 250 fF load.

8/13/2019 Zili_Yu

20/28

20

Micro-Beamformer: Design Choices

Analog beamforming vs. Digital beamforming

Digital beamformer requires an ADC for every transducer elementpower

hungry! In our design, analog beamforming is employed.

Digital Beamformer Analog Beamformer

8/13/2019 Zili_Yu

21/28

21

Types of analog delay lines:

CCD principle difficult to implement in a standard CMOS process.

Cascaded filter cells with constant group delays Gain errors with the filter

cells accumulate and result in different gains for different delay settings.

Our design choice: an analog delay line using the pipel ine-operated

sample-and-hold principle[1].

[1] T.K. Song, J.F. Greenleaf, Ultrasonic dynamic focusing using an analog FIFO and asynchronous sampling, IEEE Transaction s on Ultrasonics, Ferroelectrics and

Frequency Control, vol. 41, no. 3, pp.326-332, 1994.

Analog Delay Line

8/13/2019 Zili_Yu

22/28

22

Pipeline-Operated S/H Delay Line

Nyquist law

Settling time

Maximum delay

Parallel processing

8/13/2019 Zili_Yu

23/28

23

Analog -beamformer with current domain summation

A beamforming cell with V/I converter Die micrograph

Measured delay function Measured beamforming function

480 W per delay line

8/13/2019 Zili_Yu

24/28

24

Analog -beamformer with charge-domain summation

A 9-channel beamformer with charge domain summation Die micrograph

Measured delay function Measured summation function

2.4 mW for 9 channels

270 W per delay line

8/13/2019 Zili_Yu

25/28

25

Ultrasound Receiver Realization: 9-channel Receiver

Block diagram of the 9-channel Receiver IC Die Micrograph

500 W per channel

8/13/2019 Zili_Yu

26/28

26

Transducer-to-ASIC Interconnection Method

Electricalconductive glue

Piezo-electrictransducer Ground foil

Silicon chip with matrixpattern pads

Buffer layer

Impedance measurement

Illustration of the interconnection scheme

Matrix transducer built

on a test chipComplete transducer-to-ASIC

interconnection structure

Good yield has been achieved!

8/13/2019 Zili_Yu

27/28

27

Conclusions

Solutions Evaluations Outlook

system level design

signal processing

methodology

circuit implementation

Interconnection design

Simulations

Measurement of

prototypes

optimization

integration

simple & flexible! Proof of concept

Goal: a fullyfunctional 3D

TEE probe!

8/13/2019 Zili_Yu

28/28

28

Acknowledgements

Oldelft Ultrasound B.V.

Biomedical Engineering Department, Erasmus MC

Research group Acoustical Imaging, TU Delft

Electronic Instrumentation Lab, TU Delft