ZHAO(176/MAPLD2004)1 FFT Mapping on Mathstars FPOA FilterBuilder Platform MathStar, Inc. Sept 2004 ZHAO (176/MAPLD2004)2 Agenda MathStar FPOA Architecture Program Development Model 1024 Complex FFT Implementation ZHAO (176/MAPLD2004)3 Architecture Summary Heterogeneous Array of 16-bit Silicon Objects MAC, ALU, Truth Tables, Register File, CRC, CAM, Block RAM Single Clock Cycle Execution for All Objects Homogeneous 2-Layer Interconnect Mesh Tightly Integrated Data and Control Flow Integrated DDR DRAM & SRAM Controllers High Speed I/O at Device Boundaries: SerDes, LVDS, HSTL, LVCMOS ZHAO (176/MAPLD2004)4 Silicon Objects ALU-Truth Table-Data Router 8 instructions/ALU 4 4-term Boolean Function 16-bit Single Cycle MAC with 40-bit ACC bit word Register File Dual-Port/FIFO/Sequencing Content Addressable Memory State Machine/Lookup Table Internal SRAM Block External DDRII/RLDRAM Controller 800MHz DDR LVDS/250MHz HSTL RapidIO,HyperTransport,SPI4 1 to 4.25GHz 1x 2x or 4x SerDes PCI-Express,RapidIO,XAUI,Fibre Channel, GigE 8B/10B 64/66 codec ZHAO (176/MAPLD2004)5 Communication Architecture Each 21-Bit Link consists of: 16 data bits, 1 valid bit, 4 control bits Nearest Neighbor Links Range of 1 Object (N/E/S/W, diagonals) No Latency Dataflow to Nearest Neighbors or Intra-Object Party Line Links Extend 3 Objects in One More Clock Cycle (25-Object Neighborhood) Add Clock Cycles for Data Alignment Add Clock Cycles to Send Data Across Chip ZHAO (176/MAPLD2004)6 Conceptual FPOA Layout Matrix of Silicon Objects ALU RF MAC LVDS iRAM ZHAO (176/MAPLD2004)7 MathStar OHDL NoGates TM FPOA Design Flow Summit Visual Elite Capture Design - Objects, Connections, Behavior Functional Simulation with Timing Cosimulate with Verilog, VHDL, C Models and/or Processor ISS with Firmware MathStar COAST TM Floorplan and Assign SO Cells Connect SO Cells MathStar Object Compiler TM Generate FPOA Load Image MathStar BugSpray TM In-Circuit Verification & Debug FPOA Device or Proto Board Back Annotation MAP File Hardware Accurate Silicon Object Models Timing Accurate Connection Models for Nearest Neighbor and Party Line Links No RTL Synthesis No Physical Timing Closure JTAG Bitstream via Parallel or JTAG ZHAO (176/MAPLD2004)8 Summit Visual Elite SystemC, C/C++, VHDL, Verilog, Cosimulation FastC SystemC Simulator Multiple Abstraction Levels Matlab, SPW C Models Behavioral Models Detailed RTL Models Interactive Debug with Cause and Effect Tracking Integration with Data Management Integration with All Leading HDL Simulators Unlimited Hierarchy Block Diagrams, State Machines, Flow Diagrams, Truth Tables ZHAO (176/MAPLD2004)9 Mathstar COAST TM Drag-n-drop design objects to physical array object sites Connect objects, memories, I/O cells Resolve any cycle timing violations Export MAP file with layout data ZHAO (176/MAPLD2004)10 Radix-2 Butterfly BF0BF1BF2BF3 BF16BF17BF18BF19 BF4BF5BF6BF7 BF20BF21BF22BF23 BF8BF9BF10BF11 BF24BF25BF26BF27 BF12BF13BF14BF15 BF28BF29BF30BF31 ZHAO (176/MAPLD2004)11 Silicon Object Mapping