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www.xjtag.comXJTAG Layout Viewer

XJTAG-LAYV-22D-03

OverviewThe Layout Viewer allows you to quickly find the physical location ofcomponents, nets and pins on a board. It provides the capability to viewlayout design data extracted from ODB++ jobs in XJDeveloper,XJInvestigator and XJRunner.

You can use the Layout Viewer to visualise any faults that are found whenrunning tests. The Connection Test output includes clickable links todirectly display all of the relevant circuit elements.

It is easy to see where devices are on the board

Layout Viewer shown by XJDeveloper

Key Benefit

Improve productivity by visualising the exactlocation of faults to be repaired

Features

• Aids identifying likely points of failure

• Measures distance between objects

• Control over which layers are visible

• Advanced layer and zoom controls

• Exports graphics to the clipboard, a file or printer

• Import pictures for clearer display

Free with XJDeveloper,XJInvestigator and XJRunner

The Layout Viewer is integrated intoXJDeveloper, XJInvestigator andXJRunner to help engineers quicklyidentify faults.

Visualise circuit elements

The advanced graphical displayhighlights the physical location ofselected components and nets.Individual layers can be turned on oroff as required to make it easy to seespecific circuit elements.

www.xjtag.comXJTAG-LAYV-22D-03

XJTAG Layout Viewerwww.xjtag.com

By showing the routing of nets, theLayout Viewer helps to locate the faulton the physical board by showing thepotential problem areas.

In the example below, XJRunner reportsthat Connection Test has failed, andhas identified two nets that are shortedtogether. By looking at the layout, it is

easy to determine that the four mostlikely locations are the pads on thememory devices. It is unlikely that thefault is under the BGA device as thepins are not next to each other.

By examining the four locations on theboard, it was quickly identified that theproblem was a soldering fault on IC31.

Distributor / Technology Partner

The Layout Viewer can be used toquickly locate where faults are on theboard under test.

XJRunner’s textual output providesdetails about the types of fault andwhich nets are involved. There are alsoclickable links that allow the fault to beeasily visualised in the Layout Viewer.

Import board pictures

For even more help in identifyingwhere on a board the faults arelocated, pictures of the front and theback of the board can be imported.

These images can then be displayedbehind the CAD data with itshighlighted components and nets.

Determine the location of faults within seconds

Most likely short locations

Checking the integrity of the JTAG chain.

CheckChain passedGenerating Connection test data...Performing standard Connection Test...Performing Logic Tests (phase 1)...Performing Logic Tests (phase 2)...Analysing Connection Test results...Analysing Logic Tests (phase 1)...Checking analysis: DoneAnalysing Logic Tests (phase 2)...

Error: Short found between nets: DDRSIG13,DDRA0.

Net DetailError Detail

View all faults in the layout viewer

CONNTEST failed>>>> FAILED <<<<

NAME RESULT TOTAL TIMECheck Chain Passed 0.631Connnection Test Failed 0.858

Zoomed in view

Identified short