xilinx tutorial for testbench

8/22/2019 Xilinx Tutorial for Testbench

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IIITB

2012

XILINX SHORT TUTORIAL

Pooja MG


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Let's learn making simple verilog simulation.

Let's design a simple logic gates :

Steps:

1. Create a new project.File -> NewProject.

New Project Wizard opens as below

2. Enter the name of the project (say logic_gate) and choose Top-level source for the project as 'HDL', as shown in above fig .Next you will be asked to make project settings as below. Don't bother much about it as of now, just check the simulator

and preferred language as shown below.


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3. After clicking next you'll see the project summary, like below.

4. Click finish, your project is created successfully.5. Next, create a new source file (verilog).

For this, right click on the device, as below figure, and follow the screen shots.


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6. Choose Verilog Module and enter filename, and check add to project box

7. Now define the inputs and outputs to the logic gates.See the below and enter the same.


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8. Press next and this generates Summary of the file, check the generated port definitions.

9. Press Finish to generate the verilog module.Complete the verilog code for logic_gates.v as below :

module logic_gate

(input a, input b,output out_not, output out_and, output out_or);

assign out_not = ~a;

assign out_and = a&b;assign out_or = a|b;

endmodule


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10.Next save and synthesize the verilog code, by selecting the .v file in Hierarchy, and clicking on Synthesis in Design box asabove figure.

Now you are done with your verilog code, Now to make test bench for verilog code follow the below procedure :

1. Right click on the device, to open New source Wizard, now choose Verilog Test Fixture, as below,Enter the name of testbench (say logic_gates_testbench) and check the add to project box.

2. Now click next and Associate your testbench file to the logic_gate project as below.


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3. click next and view the summary as below.

4. Finish to create the testbench file.Now in the template, edit verilog code to look like below .v code :

logic_gates_testbench.v


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module logic_test;

// Inputs

reg a;

reg b;

// Outputs

wire out_not;

wire out_and;

wire out_or;

wire out_nand;

wire out_nor;

wire out_xor;

wire out_xnor;

// Instantiate the Unit Under Test (UUT)

logic_gate uut (

.a(a),

.b(b),

.out_not(out_not),

.out_and(out_and),

.out_or(out_or),

.out_nand(out_nand),

.out_nor(out_nor),

.out_xor(out_xor),

.out_xnor(out_xnor)

);

initial begin

// Initialize Inputs

#100

a = 1'b0;

b = 1'b0;

// Wait 100 ns for global reset to finish

#100;// Add stimulus here

b = 1'b1;

#100;

a = 1'b1;

b = 1'b0;

#100;

b = 1'b1;

end

endmodule


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5. Save the code and enter to simulation mode as below.6. now select your verilog code7. And run the Isim simulator as below. ( first run Behavioural Check syntax , on success simulate Behavioural Model).


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8. on success Isim opens as below, with the required output,

9. Zoom in/out and set the time scale to 100ns to view better and click run as below.


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That's it

xilinx tutorial for testbench

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