xilinx hdlc

IJRREST: International Journal of Research Review in Engineering Science and Technology (ISSN 2278- 6643) | Volume-2 Issue-1, March 2013

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Xilinx HDLC Bit Stuffed Algorithm for Insertion and Deletion and

Checking 32bit CRC for 16 bit Address *Neeraj Kumar Mishra

*Asst. Professor, R.D. Foundation Group of Institutions, Modinagar, Ghaziabad, U.P., India

Abstract— HDLC operates at the data link layer

of the OSI Model main focus of the is to

understand the data link layer and develop a

protocol which can offer its services to the layer

above it i.e. is the network layer and the layer

below it i.e. the physical layer. The function of this

protocol controller is to perform a number of

separate activities like to check for errors,

physical addressing, flow control Xilinx design of

HDLC Controller and simulation design and

implement a high performance. This will then be

coded in a VHSIC hardware description language

(VHDL). The functioning of the coded design is to

be simulated on simulation software (e.g. Model

Sim.). After proper simulation, the design is to be

synthesized and then translated to a structural

architecture in terms of the components on the

target FPGA,CPLD and ASIC’s device (Spartan

3) and the perform the post-translate simulation

in order to proof the proper checking the

functionality of Xilinx HDLC of the design after

translation. After the well functioning simulation

of the post-translate model the design of HDLC is

mapped to the existing slices of the FPGA, CPLD

and ASIC’s etc. and the post-map model

simulated. The post-map model doesn’t include

the delay and optimization of channel length.

After then l completion of the post-map

simulation, the design of coded is then routed and

a post-route simulation model with the

appropriate routing delays is generated to be

simulated on the Xilinx HDL simulator. After this

a programming file is generated to program the

FPGA device. And checking redundancy bit CRC

in both transmitter and receiver side.

Keywords: Xilinx, HDLC, CRC.

1. INTRODUCTION

HDLC [High-level Data Link Control] is a group of

protocols for transmitting [synchronous] data

[Packets] between [Point-to-Point] nodes. In HDLC,

data is organized into a frame. HDLC protocol

resides with Layer 2 of the OSI model, data link

control protocol, falls within layer 2, the Data Link

Layer, of the Open Systems Interface (OSI) model.

Xilinx HDLC Features are Automatic frame check

sequence generation and checking, full duplex and

half duplex modes of operation, Minimum CPU

overhead, Single +5V Supply and Capable of

working in various modes like Normal response

mode, Asynchronous Balance Mode and

Asynchronous Response Mode etc.

2. LITERATURE SURVEY

The layered concept of networking was developed to

accommodate changes in technology. Synchronous

Data Link Control (SDLC) from IBM supported the

computer structure of the 70s with provisions for host

systems. The ISO termed it as High level Data Link

Control (HDLC). HDLC uses a 32-bit CRC and is

very similar to SDLC As a close cousin; its functions

are virtually identical to SDLC with the exception of

a few minor differences.

Figure.1: Network Layer Interaction


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The Xilinx HDLC survey is to understand the data

link layer and develop a protocol which can offer its

services to the layer above it i.e. is the network layer

and the layer below it i.e. the physical layer. The

main function of this protocol controller is to perform

a number of separate activities like physical

addressing, to check errors, and flow control etc.

Network layer interaction as shown in figure 1. The

Data Link layer of OSI performs a number of

separate activities, including:

• Physical addressing

• Network topology

• Error notification

• Access to the physical medium

• Flow control

3. TECHNICAL OVERVIEW OF HDLC

HDLC [High-level Data Link Control] is a group of

protocols for transmitting [synchronous] data

[Packets] between [Point-to-Point] nodes. HDLC

Controllers are devices, which execute the HDLC

protocol. It includes transmitting and receiving the

packaging data serially, while providing the data

transparency through zero insertion and deletion.

These controllers generate and detect flags that

indicate the HDLC status. They provide 32-bit CRC

on data packets using defined polynomial, and

recognize the single byte address in the received

frame.

Figure.2: Block Diagram of HDLC Controller

3.1 Features of Xilinx HDLC are:

1. Flag insertion and detection.

2. Zero bit stuffing and deletion.

3. 32-bit CRC generation and checking.

4. CRC can be separately enabled and disabled for

transmit.

5. Automatic insertion of 1 to 255 IDLE characters

between frames.

6. Channel status indicators.

7. Optionally compresses Address, Control fields

and Protocol field.

8. Generates discard packet signal for the packet

with FCS error or invalid packet on packet

Interface.

9. Programmable interface space.

10. NRZ or NRZI data encoding.

11. Enable and data valid signals for flow control.

12. Address filtering allowing multicast and broadcast

addresses

13. Buffering at the network interface not required.

14. Full or half duplex operation.

4. SCOPE OF XILINX HDLC CONTRO-

LLER

1. Internet/edge routers, bridges and switches – for

high bandwidth WAN links.

2. Error-correction in modems.

3. Frame relay switches – high-density access.

4. Protocol converter.

5. Distributed packet-based communications system.

6. Data link controllers and protocol generators.

7. Inter-processor communication.

8. Frame Relay networks.

9. Logic Consolidation.

10. Cellular base station switch controller.

In HDLC, data is organized into a frame. HDLC uses

zero insertion/deletion process [bit stuffing] to ensure

that the bit pattern of the delimiter flag does not

occur in the fields between flags. The HDLC frame is

synchronous and therefore relies on the physical layer

to provide method of clocking and synchronizing the

transmission and reception of frames.

Figure.3: General HDLC Frame

5. RELATED WORK FOR DESIGN AND

IMPLEMENTATION OF XILINX HDLC

This paper is organized as follows: first describes

briefly block diagram and frame format of Xilinx

Opening Flag, 8 bits [01111110]

Address, 8 bits/16 bits

Control, 8 bits, or 16 bits

Data [Payload], Variable, not used in some

frames, or may be padded to complete the fill

CRC, 16 bits, or 32 bits

Closing Flag, 8 bits [01111110]


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HDLC (In introduction part). Second discusses the

CRC 32bit generation and calculation method and

last discuss the bit stuffing algorithm in Xilinx

HDLC. Simulation result for 32bit CRC is verifying

properly 99.9984 % of other error patterns will be

detected and removed correctly that verifying by

simulation result.

The Xilinx HDLC was designed and implemented

using VHDL codes. The codes were simulated by

ModelSim 10.0a and successfully implemented in

Xilinx VirtexII FPGA using Xilinx ISE 8.2i tool. The

reason for using Virtex FPGA is its various built-in

features that help the designer throughout the process

of design.

5.1 Xilinx HDLC CRC Checking Field

HDLC Controller is to interface with data link layer

and Data Link layer is to error detection and

correction. Error detection is the process of detecting

whether errors occurred during the transmission of

the bits across the wire. The Data Link layer uses a

calculated value called the CRC (Cyclic Redundancy

Check) that's placed into the Data Link trailer that's

added to the message frame before it's sent to the

Physical layer. The receiving computer recalculates

the CRC and compares it to the one sent with the

data. If the two values are equal, it's assumed that the

data arrived without errors. Otherwise, the message

frame may need to be retransmitted under control of

an upper layer. Although the Data Link layer

implements error detection, it does not include a

function to perform error recovery. This is left for the

upper layers to deal with, primarily on the Transport

layer.

In CRC generation Method CRC is calculated by

performing a Modulo 2 division of the data by a

generator polynomial and recording the remainder

after division:

1. A string of 0s is appended to the data unit. The no.

n is less than the no. of data of bits in the

predetermined divisor, which is n+ 1 bit.

2. The newly elongated is divided is divided by the

divisor. The remainder is the CRC.

3. CRC replaces n 0 bits derived in step 2 at the end

of data unit.

4. Data unit arrives at the receiver data first, followed

by CRC. The receiver treats the whole string as a

data unit and divides by the same divisor.

5. If remainder comes out to be 0 the string is error

free.

Figure.4: CRC Generation Method

CRC-32 = x32 + x26 + x23 + x22 + x16 + x12 + x11

+ x10+ x8 + x7 + x5 + x4 + x2 + x + 1

Although this division may be performed in software,

it usually performed using a shift register and X-OR

gates. The hardware solution for implementing a

CRC is much simpler than a software approach. One

example for a CRC-32 is:

Figure.5: Basic Block Diagram of CRC32

Basic Encoder/Decoder for a 32-bit CRC:

1. Change the polynomial to a divisor of size N+1.

2. Make a shift register of size N.

3. Align the shift register cells with the divisor so that

the cells are located between the bits.

4. Put a XOR gate where there is a 1 in the divisor

except for the leftmost bit.

5. Make a feedback connection from the leftmost bit

to the XORs.

In CRC Calculation Method receiver side reverse

function of the CRC generator. The whole packet is

again divided by the same polynomial that was used

at the transmitter end. If after the packet with the

polynomial the remainder comes out to be zero that

means the transmission and reception are error free

and in case the remainder is not zero that means an

error has occurred during the process and hence the

packet is discarded and the whole packet is

retransmitted as shown in Figure 6.


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Figure.6: CRC Calculation

1. Data unit arrives at the receiver data first, followed

by CRC. The receiver treats the whole string as a data

unit and divides by the same divisor.

2. If remainder comes out to be 0 the string is error

free and is accepted but if the remainder comes out to

be other than 0, it is assumed that it contains an error

and the whole frame is discarded and is retransmitted.

The CRC-32 is able to detect all single errors, all

double errors, all odd numbers of errors and all errors

with burst less than 32 bits in length. In addition

99.9984 % of other error patterns will be detected.

Protocols at the network layer and higher (e.g. IP,

UDP, TCP) usually use a simpler checksum to verify

that the data being transported has not been corrupted

by the processing performed by the nodes in the

network.

5.2 BIT Stuffing Algorithm

In HDLC Block diagram to guarantee that a flag does

not appear in advertently anywhere else in the frame,

HDLC uses a process called bit stuffing. Every time

the user wants to send a bit sequence having more

than 5 consecutive 1s, it inserts (stuffs) one redundant

0after the fifth 1. For example the sequence

01111111111000 becomes 011111101111000. This

extra zero is inserted regardless of whether the sixth

bit is another one or not. Its presence tells the

receiver that the current sequence is not a flag. Once

the receiver has seen the stuffed 0, it is dropped from

the data and the original stream is retorted .The bit

stuffing at the sender’s end and bit removal at the

receiver. As shown in Figure 7,

Figure.7: Bit Stuffing and Removal

Figure.8: Stuffed and Unstuffed Bits

When it finds five consecutive 1s after a zero, it

checks the seventh bit. If the seventh bit is a 0, the

receiver recognizes it as a stuffed bit and discards it,

and resets the counter. If the seventh bit is a 1, the

receiver checks the eighth bit. If the eighth bit is

another 1, the receiver continues counting. A total of

7 to 14 consecutive 1s indicates an abort. A total of

15 or more 1s indicates an idle channel. As shown in

Figure 9.

Figure.9: Xilinx HDLC Flow Chart for Discarding

Stuffed Bit

6. CHALLENGES INVOLVED IN XILINX

HDLC

In designing of HDLC some more features can be

added to increase its utility. Now for obtaining our


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result better, there are several modifications, which

can improve its performance listed - Enhanced to 256

Independent, Bi-directional HDLC Channels, Large

16kB FIFO in Both Receive and Transmit Directions,

Transmit Packet Priority Setting, Independent

watchdog timer and Facility to disable protocol

functions

7. SIMULATION AND SYNTHESIS RESULT

After the design and implementation of the HDLC

Controller, the results obtained are as follows:

Simulation result for 8-bit data, 16 bit address and

crc-32,

For the data<=11110000 and 16bitaddress i.e.

txaddressinlo<=11110000,

txaddressinhi<=11110000,

txadrressout<=1111000011110000 we make

clock=1,reset=0, wrtaddresshi=1 and wrtaddresslo=1.

After the address and the data are attached together,

we divide them with a constant polynomial of 32 bits

and append the remainder of the division along the

data and address. The simulation result for the

generation of crc1 is highlighted below:

Figure.10: Simulation result for CRC-32 of 16-bit

address and 8 bit data

The highlighted simulation results shown below

shows the result of the CRC check at the O/P which

is crc32<=0000000000000000000000000000000

which indicates an error free transmission. The

resultant address, data at the O/P which is same as

that of transmitter is. Rxdatout<=11110000 and

rxaddressout<=1111000011110000. As shown in

figure 11 below:

Figure.11: Simulation result for O/P at the

receiver for 16-bit address and 8 bit data and 32

bit CRC

8. CONCLUSION AND FUTURE SCOPE

The coding written in VHDL language was checked

using XilinxISE8.2 i and Modelsim10.0a Simulator.

HDLC Controller is automatically check frame

sequence generation using cyclic redundancy check

of CRC-32Bit. The result of Post Synthesis is an

Optimized Gate Level net list form which a net list

code is extracted and it is simulated using Simulator

and it is verified that design is working properly.

Coding written for this paper is tested along with


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random stimulator values and the results obtained

were up to the designer’s expectation 99.9984 % of

other error patterns will be detected. HDLC

controller can also support ISDN frame format and

thus the flexibility of this controller is very high. It

support most WAN cards can be adapted to any

HDLC derived protocol. HDLC is the basis for a

wide variety of data link layer protocols. Regardless

of the data link protocol, most HDLC framing, bit

stuffing, and CRC generation is performed by the

serial controller chips with the specific protocol stack

software supplying the rest of the necessary fields

The future enhancement in this paper is to implement

this controller in real time application and also to

accommodate more number of channels in the same

design. more functions like facility to disable

protocol function, watch dog timers, interrupt

controllers, increased data capacity in frame and

transmit packet priority setting.

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