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x86 Assembly Language Reference Manual
Part No: E28388–01October 2012
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Contents
Preface .....................................................................................................................................................9
1 Overview of the Oracle Solaris x86 Assembler ............................................................................... 13Assembler Overview ........................................................................................................................... 13Syntax Differences Between x86 Assemblers ................................................................................... 13
2 Oracle Solaris x86 Assembly Language Syntax .............................................................................. 15Lexical Conventions ............................................................................................................................ 15
Statements ..................................................................................................................................... 15Tokens ........................................................................................................................................... 17
Instructions, Operands, and Addressing .......................................................................................... 19Instructions ................................................................................................................................... 19Operands ....................................................................................................................................... 20
Assembler Directives .......................................................................................................................... 21
3 Instruction Set Mapping ....................................................................................................................27Instruction Overview .......................................................................................................................... 27General-Purpose Instructions ........................................................................................................... 28
Data Transfer Instructions .......................................................................................................... 28Binary Arithmetic Instructions .................................................................................................. 31Decimal Arithmetic Instructions ............................................................................................... 32Logical Instructions ..................................................................................................................... 33Shift and Rotate Instructions ...................................................................................................... 33Bit and Byte Instructions ............................................................................................................. 34Control Transfer Instructions .................................................................................................... 36String Instructions ....................................................................................................................... 38I/O Instructions ............................................................................................................................ 39
3
Flag Control (EFLAG) Instructions ........................................................................................... 40Segment Register Instructions .................................................................................................... 41Miscellaneous Instructions ......................................................................................................... 41
Floating-Point Instructions ................................................................................................................ 42Data Transfer Instructions (Floating Point) ............................................................................. 42Basic Arithmetic Instructions (Floating-Point) ....................................................................... 43Comparison Instructions (Floating-Point) .............................................................................. 44Transcendental Instructions (Floating-Point) ......................................................................... 45Load Constants (Floating-Point) Instructions ......................................................................... 46Control Instructions (Floating-Point) ...................................................................................... 46
SIMD State Management Instructions ............................................................................................. 48MMX Instructions ............................................................................................................................... 48
Data Transfer Instructions (MMX) ........................................................................................... 49Conversion Instructions (MMX) ............................................................................................... 49Packed Arithmetic Instructions (MMX) ................................................................................... 49Comparison Instructions (MMX) ............................................................................................. 51Logical Instructions (MMX) ....................................................................................................... 51Shift and Rotate Instructions (MMX) ....................................................................................... 52State Management Instructions (MMX) ................................................................................... 52
SSE Instructions ................................................................................................................................... 53SIMD Single-Precision Floating-Point Instructions (SSE) ..................................................... 53MXCSR State Management Instructions (SSE) ........................................................................ 5964–Bit SIMD Integer Instructions (SSE) ................................................................................... 59Miscellaneous Instructions (SSE) .............................................................................................. 60
SSE2 Instructions ................................................................................................................................. 61SSE2 Packed and Scalar Double-Precision Floating-Point Instructions ............................... 61SSE2 Packed Single-Precision Floating-Point Instructions .................................................... 67SSE2 128–Bit SIMD Integer Instructions .................................................................................. 68SSE2 Miscellaneous Instructions ............................................................................................... 69
Operating System Support Instructions ........................................................................................... 7064–Bit AMD Opteron Considerations ............................................................................................. 72
A Using the Assembler Command Line ............................................................................................... 75Assembler Command Line ................................................................................................................. 75Assembler Command Line Options ................................................................................................. 76
Contents
x86 Assembly Language Reference Manual • October 20124
Disassembling Object Code ............................................................................................................... 78
Index ......................................................................................................................................................79
Contents
5
6
Tables
TABLE 3–1 Data Transfer Instructions ....................................................................................... 28TABLE 3–2 Binary Arithmetic Instructions ................................................................................ 32TABLE 3–3 Decimal Arithmetic Instructions ............................................................................ 32TABLE 3–4 Logical Instructions ................................................................................................... 33TABLE 3–5 Shift and Rotate Instructions ................................................................................... 33TABLE 3–6 Bit and Byte Instructions .......................................................................................... 34TABLE 3–7 Control Transfer Instructions .................................................................................. 36TABLE 3–8 String Instructions ..................................................................................................... 38TABLE 3–9 I/O Instructions ......................................................................................................... 40TABLE 3–10 Flag Control Instructions ......................................................................................... 40TABLE 3–11 Segment Register Instructions ................................................................................. 41TABLE 3–12 Miscellaneous Instructions ...................................................................................... 41TABLE 3–13 Data Transfer Instructions (Floating-Point) .......................................................... 42TABLE 3–14 Basic Arithmetic Instructions (Floating-Point) ..................................................... 43TABLE 3–15 Comparison Instructions (Floating-Point) ............................................................ 44TABLE 3–16 Transcendental Instructions (Floating-Point) ....................................................... 45TABLE 3–17 Load Constants Instructions (Floating-Point) ...................................................... 46TABLE 3–18 Control Instructions (Floating-Point) .................................................................... 46TABLE 3–19 SIMD State Management Instructions ................................................................... 48TABLE 3–20 Data Transfer Instructions (MMX) ......................................................................... 49TABLE 3–21 Conversion Instructions (MMX) ............................................................................ 49TABLE 3–22 Packed Arithmetic Instructions (MMX) ................................................................ 50TABLE 3–23 Comparison Instructions (MMX) ........................................................................... 51TABLE 3–24 Logical Instructions (MMX) .................................................................................... 52TABLE 3–25 Shift and Rotate Instructions (MMX) ..................................................................... 52TABLE 3–26 State Management Instructions (MMX) ................................................................ 53TABLE 3–27 Data Transfer Instructions (SSE) ............................................................................. 53TABLE 3–28 Packed Arithmetic Instructions (SSE) .................................................................... 55
7
TABLE 3–29 Comparison Instructions (SSE) ............................................................................... 56TABLE 3–30 Logical Instructions (SSE) ........................................................................................ 57TABLE 3–31 Shuffle and Unpack Instructions (SSE) ................................................................... 58TABLE 3–32 Conversion Instructions (SSE) ................................................................................ 58TABLE 3–33 MXCSR State Management Instructions (SSE) ..................................................... 59TABLE 3–34 64–Bit SIMD Integer Instructions (SSE) ................................................................ 59TABLE 3–35 Miscellaneous Instructions (SSE) ............................................................................ 60TABLE 3–36 SSE2 Data Movement Instructions ......................................................................... 62TABLE 3–37 SSE2 Packed Arithmetic Instructions ..................................................................... 63TABLE 3–38 SSE2 Logical Instructions ......................................................................................... 64TABLE 3–39 SSE2 Compare Instructions ..................................................................................... 65TABLE 3–40 SSE2 Shuffle and Unpack Instructions .................................................................... 65TABLE 3–41 SSE2 Conversion Instructions ................................................................................. 66TABLE 3–42 SSE2 Packed Single-Precision Floating-Point Instructions ................................. 68TABLE 3–43 SSE2 128–Bit SIMD Integer Instructions ............................................................... 68TABLE 3–44 SSE2 Miscellaneous Instructions ............................................................................. 69TABLE 3–45 Operating System Support Instructions ................................................................. 70
Tables
x86 Assembly Language Reference Manual • October 20128
Preface
The Oracle Solaris x86 Assembly Language Reference Manual documents the syntax of theOracle Solaris x86 assembly language. This manual is provided to help experiencedprogrammers understand the assembly language output of Oracle Solaris compilers. Thismanual is neither an introductory book about assembly language programming nor a referencemanual for the x86 architecture.
Note – This Oracle Solaris release supports systems that use the SPARC and x86 families ofprocessor architectures. The supported systems appear in the Oracle Solaris OS: HardwareCompatibility Lists. This document cites any implementation differences between the platformtypes.
In this document, these x86 related terms mean the following:
■ x86 refers to the larger family of 64-bit and 32-bit x86 compatible products.■ x64 relates specifically to 64-bit x86 compatible CPUs.■ "32-bit x86" points out specific 32-bit information about x86 based systems.
For supported systems, see the Oracle Solaris OS: Hardware Compatibility Lists.
Who Should Use This BookThis manual is intended for experienced x86 assembly language programmers who are familiarwith the x86 architecture.
Before You Read This BookYou should have a thorough knowledge of assembly language programming in general and befamiliar with the x86 architecture in specific. You should be familiar with the ELF object fileformat. This manual assumes that you have the following documentation available forreference:
■ Intel 64 and IA-32 Architectures Software Developer Manuals.
9
■ AMD64 Architecture Programmer's Manual (Advanced Micro Devices, 2003). Volume 1:Application Programming. Volume 2: System Programming. Volume 3: General-Purpose andSystem Instructions. Volume 4: 128-Bit Media Instructions. Volume 5: 64-Bit Media and x87Floating-Point Instructions.
■ Oracle Solaris 11.1 Linkers and Libraries Guide■ Oracle Solaris Studio 12.3: C User’s Guide■ Man pages for the as(1), ld(1), and dis(1) utilities.
How This Book Is OrganizedChapter 1, “Overview of the Oracle Solaris x86 Assembler,” provides an overview of the x86functionality supported by the Oracle Solaris x86 assembler.
Chapter 2, “Oracle Solaris x86 Assembly Language Syntax,” documents the syntax of the Solarisx86 assembly language.
Chapter 3, “Instruction Set Mapping,” maps Oracle Solaris x86 assembly language instructionmnemonics to the native x86 instruction set.
Access to Oracle SupportOracle customers have access to electronic support through My Oracle Support. Forinformation, visit http://www.oracle.com/pls/topic/lookup?ctx=acc&id=info or visithttp://www.oracle.com/pls/topic/lookup?ctx=acc&id=trs if you are hearing impaired.
Typographic ConventionsThe following table describes the typographic conventions that are used in this book.
TABLE P–1 Typographic Conventions
Typeface Description Example
AaBbCc123 The names of commands, files, and directories,and onscreen computer output
Edit your .login file.
Use ls -a to list all files.
machine_name% you have mail.
AaBbCc123 What you type, contrasted with onscreencomputer output
machine_name% su
Password:
aabbcc123 Placeholder: replace with a real name or value The command to remove a file is rmfilename.
Preface
x86 Assembly Language Reference Manual • October 201210
TABLE P–1 Typographic Conventions (Continued)Typeface Description Example
AaBbCc123 Book titles, new terms, and terms to beemphasized
Read Chapter 6 in the User's Guide.
A cache is a copy that is storedlocally.
Do not save the file.
Note: Some emphasized itemsappear bold online.
Shell Prompts in Command ExamplesThe following table shows UNIX system prompts and superuser prompts for shells that areincluded in the Oracle Solaris OS. In command examples, the shell prompt indicates whetherthe command should be executed by a regular user or a user with privileges.
TABLE P–2 Shell Prompts
Shell Prompt
Bash shell, Korn shell, and Bourne shell $
Bash shell, Korn shell, and Bourne shell for superuser #
C shell machine_name%
C shell for superuser machine_name#
Preface
11
12
Overview of the Oracle Solaris x86 Assembler
This chapter provides a brief overview of the Oracle Solaris x86 assembler as. This chapterdiscusses the following topics:■ “Assembler Overview” on page 13■ “Syntax Differences Between x86 Assemblers” on page 13
Assembler OverviewThe Oracle Solaris x86 assembler as translates Oracle Solaris x86 assembly language intoExecutable and Linking Format (ELF) relocatable object files that can be linked with otherobject files to create an executable file or a shared object file. (See Chapter 12, “Object FileFormat,” in Oracle Solaris 11.1 Linkers and Libraries Guide for a complete discussion of ELFobject file format.) The assembler supports macro processing by the C preprocessor (cpp) or them4 macro processor.
Syntax Differences Between x86 AssemblersThere is no standard assembly language for the x86 architecture. Vendor implementations ofassemblers for the x86 architecture instruction sets differ in syntax and functionality. Thesyntax of the Oracle Solaris x86 assembler is compatible with the syntax of the assemblerdistributed with earlier releases of the UNIX operating system (this syntax is sometimes termed“AT&T syntax”). Developers familiar with other assemblers derived from the original UNIXassemblers, such as the Free Software Foundation's gas, will find the syntax of the Oracle Solarisx86 assembler very straightforward.
However, the syntax of x86 assemblers distributed by Intel and Microsoft (sometimes termed“Intel syntax”) differs significantly from the syntax of the Oracle Solaris x86 assembler. Thesedifferences are most pronounced in the handling of instruction operands:■ The Oracle Solaris and Intel assemblers use the opposite order for source and destination
operands.
1C H A P T E R 1
13
■ The Oracle Solaris assembler specifies the size of memory operands by adding a suffix to theinstruction mnemonic, while the Intel assembler prefixes the memory operands.
■ The Oracle Solaris assembler prefixes immediate operands with a dollar sign ($) (ASCII0x24), while the Intel assembler does not delimit immediate operands.
See Chapter 2, “Oracle Solaris x86 Assembly Language Syntax,” for additional differencesbetween x86 assemblers.
Syntax Differences Between x86 Assemblers
x86 Assembly Language Reference Manual • October 201214
Oracle Solaris x86 Assembly Language Syntax
This chapter documents the syntax of the Oracle Solaris x86 assembly language.
■ “Lexical Conventions” on page 15■ “Instructions, Operands, and Addressing” on page 19■ “Assembler Directives” on page 21
Lexical ConventionsThis section discusses the lexical conventions of the Oracle Solaris x86 assembly language.
StatementsAn x86 assembly language program consists of one or more files containing statements. Astatement consists of tokens separated by whitespace and terminated by either a newlinecharacter (ASCII 0x0A) or a semicolon (;) (ASCII 0x3B). Whitespace consists of spaces (ASCII0x20), tabs (ASCII 0x09), and formfeeds (ASCII 0x0B) that are not contained in a string orcomment. More than one statement can be placed on a single input line provided that eachstatement is terminated by a semicolon. A statement can consist of a comment. Emptystatements, consisting only of whitespace, are allowed.
CommentsA comment can be appended to a statement. The comment consists of the slash character (/)(ASCII 0x2F) followed by the text of the comment. The comment is terminated by the newlinethat terminates the statement.
2C H A P T E R 2
15
LabelsA label can be placed at the beginning of a statement. During assembly, the label is assigned thecurrent value of the active location counter and serves as an instruction operand. There are twotypes of lables: symbolic and numeric.
Symbolic Labels
A symbolic label consists of an identifier (or symbol) followed by a colon (:) (ASCII 0x3A).Symbolic labels must be defined only once. Symbolic labels have global scope and appear in theobject file's symbol table.
Symbolic labels with identifiers beginning with a period (.) (ASCII 0x2E) are considered to havelocal scope and are not included in the object file's symbol table.
Numeric Labels
A numeric label consists of a unsigned decimal int32 value followed by a colon (:). Numericlabels are used only for local reference and are not included in the object file's symbol table.Numeric labels have limited scope and can be redefined repeatedly.
When a numeric label is used as a reference (as an instruction operand, for example), thesuffixes b (“backward”) or f (“forward”) should be added to the numeric label. For numericlabel N, the reference Nb refers to the nearest label N defined before the reference, and thereference Nf refers to the nearest label N defined after the reference. The following exampleillustrates the use of numeric labels:
1: / define numeric label "1"one: / define symbolic label "one"
/ ... assembler code ...
jmp 1f / jump to first numeric label "1" defined
/ after this instruction
/ (this reference is equivalent to label "two")
jmp 1b / jump to last numeric label "1" defined
/ before this instruction
/ (this reference is equivalent to label "one")
1: / redefine label "1"two: / define symbolic label "two"
jmp 1b / jump to last numeric label "1" defined
/ before this instruction
/ (this reference is equivalent to label "two")
Lexical Conventions
x86 Assembly Language Reference Manual • October 201216
TokensThere are five classes of tokens:
■ Identifiers (symbols)■ Keywords■ Numerical constants■ String Constants■ Operators
IdentifiersAn identifier is an arbitrarily-long sequence of letters and digits. The first character must be aletter; the underscore (_) (ASCII 0x5F) and the period (.) (ASCII 0x2E) are considered to beletters. Case is significant: uppercase and lowercase letters are different.
KeywordsKeywords such as x86 instruction mnemonics (“opcodes”) and assembler directives are reservedfor the assembler and should not be used as identifiers. See Chapter 3, “Instruction SetMapping,” for a list of the Oracle Solaris x86 mnemonics. See “Assembler Directives” onpage 21 for the list of as assembler directives.
Numerical ConstantsNumbers in the x86 architecture can be integers or floating point. Integers can be signed orunsigned, with signed integers represented in two's complement representation. Floating-pointnumbers can be: single-precision floating-point; double-precision floating-point; anddouble-extended precision floating-point.
Integer Constants
Integers can be expressed in several bases:
■ Decimal. Decimal integers begin with a non-zero digit followed by zero or more decimaldigits (0–9).
■ Binary. Binary integers begin with “0b” or “0B” followed by zero or more binary digits (0, 1).■ Octal. Octal integers begin with zero (0) followed by zero or more octal digits (0–7).■ Hexadecimal. Hexadecimal integers begin with “0x” or “0X” followed by one or more
hexadecimal digits (0–9, A–F). Hexadecimal digits can be either uppercase or lowercase.
Lexical Conventions
Chapter 2 • Oracle Solaris x86 Assembly Language Syntax 17
Floating Point Constants
Floating point constants have the following format:■ Sign (optional) – either plus (+) or minus (–)■ Integer (optional) – zero or more decimal digits (0–9)■ Fraction (optional) – decimal point (.) followed by zero or more decimal digits■ Exponent (optional) – the letter “e” or “E”, followed by an optional sign (plus or minus),
followed by one or more decimal digits (0–9)
A valid floating point constant must have either an integer part or a fractional part.
String ConstantsA string constant consists of a sequence of characters enclosed in double quotes ( ") (ASCII0x22). To include a double-quote character ("), single-quote character (’), or backslashcharacter (\) within a string, precede the character with a backslash (\) (ASCII 0x5C). Acharacter can be expressed in a string as its ASCII value in octal preceded by a backslash (forexample, the letter “J” could be expressed as “\112”). The assembler accepts the following escapesequences in strings:
Escape Sequence Character Name ASCII Value (hex)
\n newline 0A
\r carriage return 0D
\b backspace 08
\t horizontal tab 09
\f form feed 0C
\v vertical tab 0B
OperatorsThe assembler supports the following operators for use in expressions. Operators have noassigned precedence. Expressions can be grouped in square brackets ([]) to establishprecedence.
+ Addition
- Subtraction
\* Multiplication
\/ Division
& Bitwise logical AND
Lexical Conventions
x86 Assembly Language Reference Manual • October 201218
| Bitwise logical OR
>> Shift right
<< Shift left
\% Remainder
! Bitwise logical AND NOT
^ Bitwise logical XOR
Note – The asterisk (*), slash (/), and percent sign (%) characters are overloaded. When used asoperators in an expression, these characters must be preceded by the backslash character (\).
Instructions, Operands, and AddressingInstructions are operations performed by the CPU. Operands are entities operated upon by theinstruction. Addresses are the locations in memory of specified data.
InstructionsAn instruction is a statement that is executed at runtime. An x86 instruction statement canconsist of four parts:
■ Label (optional)■ Instruction (required)■ Operands (instruction specific)■ Comment (optional)
See “Statements” on page 15 for the description of labels and comments.
The terms instruction and mnemonic are used interchangeably in this document to refer to thenames of x86 instructions. Although the term opcode is sometimes used as a synonym forinstruction, this document reserves the term opcode for the hexadecimal representation of theinstruction value.
For most instructions, the Oracle Solaris x86 assembler mnemonics are the same as the Intel orAMD mnemonics. However, the Oracle Solaris x86 mnemonics might appear to be differentbecause the Oracle Solaris mnemonics are suffixed with a one-character modifier that specifiesthe size of the instruction operands. That is, the Oracle Solaris assembler derives its operandtype information from the instruction name and the suffix. If a mnemonic is specified with notype suffix, the operand type defaults to long. Possible operand types and their instructionsuffixes are:
Instructions, Operands, and Addressing
Chapter 2 • Oracle Solaris x86 Assembly Language Syntax 19
b Byte (8–bit)
w Word (16–bit)
l Long (32–bit) (default)
q Quadword (64–bit)
The assembler recognizes the following suffixes for x87 floating-point instructions:
[no suffix] Instruction operands are registers only
l (“long”) Instruction operands are 64–bit
s (“short”) Instruction operands are 32–bit
See Chapter 3, “Instruction Set Mapping,” for a mapping between Oracle Solaris x86 assemblylanguage mnemonics and the equivalent Intel or AMD mnemonics.
OperandsAn x86 instruction can have zero to three operands. Operands are separated by commas (,)(ASCII 0x2C). For instructions with two operands, the first (lefthand) operand is the sourceoperand, and the second (righthand) operand is the destination operand (that is,source→destination).
Note – The Intel assembler uses the opposite order (destination←source) for operands.
Operands can be immediate (that is, constant expressions that evaluate to an inline value),register (a value in the processor number registers), or memory (a value stored in memory). Anindirect operand contains the address of the actual operand value. Indirect operands arespecified by prefixing the operand with an asterisk (*) (ASCII 0x2A). Only jump and callinstructions can use indirect operands.
■ Immediate operands are prefixed with a dollar sign ($) (ASCII 0x24)■ Register names are prefixed with a percent sign (%) (ASCII 0x25)■ Memory operands are specified either by the name of a variable or by a register that contains
the address of a variable. A variable name implies the address of a variable and instructs thecomputer to reference the contents of memory at that address. Memory references have thefollowing syntax:segment:offset(base, index, scale).■ Segment is any of the x86 architecture segment registers. Segment is optional: if specified,
it must be separated from offset by a colon (:). If segment is omitted, the value of %ds (thedefault segment register) is assumed.
Instructions, Operands, and Addressing
x86 Assembly Language Reference Manual • October 201220
■ Offset is the displacement from segment of the desired memory value. Offset is optional.■ Base and index can be any of the general 32–bit number registers.■ Scale is a factor by which index is to be multipled before being added to base to specify
the address of the operand. Scale can have the value of 1, 2, 4, or 8. If scale is not specified,the default value is 1.
Some examples of memory addresses are:
movl var, %eax Move the contents of memory location var
into number register %eax.
movl %cs:var, %eax Move the contents of memory location var
in the code segment (register %cs) intonumber register %eax.
movl $var, %eax Move the address of var into numberregister %eax.
movl array_base(%esi), %eax Add the address of memory locationarray_base to the contents of numberregister %esi to determine an address inmemory. Move the contents of this addressinto number register %eax.
movl (%ebx, %esi, 4), %eax Multiply the contents of number register%esi by 4 and add the result to the contentsof number register %ebx to produce amemory reference. Move the contents ofthis memory location into number register%eax.
movl struct_base(%ebx, %esi, 4), %eax Multiply the contents of number register%esi by 4, add the result to the contents ofnumber register %ebx, and add the result tothe address of struct_base to produce anaddress. Move the contents of this addressinto number register %eax.
Assembler DirectivesDirectives are commands that are part of the assembler syntax but are not related to the x86processor instruction set. All assembler directives begin with a period (.) (ASCII 0x2E).
Assembler Directives
Chapter 2 • Oracle Solaris x86 Assembly Language Syntax 21
.align integer, padThe .align directive causes the next data generated to be aligned modulo integer bytes.Integer must be a positive integer expression and must be a power of 2. If specified, pad is aninteger byte value used for padding. The default value of pad for the text section is 0x90(nop); for other sections, the default value of pad is zero (0).
.ascii "string"The .ascii directive places the characters in string into the object module at the currentlocation but does not terminate the string with a null byte (\0). String must be enclosed indouble quotes (") (ASCII 0x22). The .ascii directive is not valid for the .bss section.
.bcd integerThe .bcd directive generates a packed decimal (80-bit) value into the current section. The.bcd directive is not valid for the .bss section.
.bss
The .bss directive changes the current section to .bss.
.bss symbol, integerDefine symbol in the .bss section and add integer bytes to the value of the location counterfor .bss. When issued with arguments, the .bss directive does not change the currentsection to .bss. Integer must be positive.
.byte byte1,byte2,...,byteNThe .byte directive generates initialized bytes into the current section. The .byte directiveis not valid for the .bss section. Each byte must be an 8-bit value.
.2byte expression1, expression2, ..., expressionNRefer to the description of the .value directive.
.4byte expression1, expression2, ..., expressionNRefer to the description of the .long directive.
.8byte expression1, expression2, ..., expressionNRefer to the description of the .quad directive.
.comm name, size,alignmentThe .comm directive allocates storage in the data section. The storage is referenced by theidentifier name. Size is measured in bytes and must be a positive integer. Name cannot bepredefined. Alignment is optional. If alignment is specified, the address of name is aligned toa multiple of alignment.
.data
The .data directive changes the current section to .data.
.double floatThe .double directive generates a double-precision floating-point constant into the currentsection. The .double directive is not valid for the .bss section.
.even
The .even directive aligns the current program counter (.) to an even boundary.
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x86 Assembly Language Reference Manual • October 201222
.ext expression1, expression2, ..., expressionNThe .ext directive generates an 80387 80–bit floating point constant for each expression intothe current section. The .ext directive is not valid for the .bss section.
.file "string"The .file directive creates a symbol table entry where string is the symbol name andSTT_FILE is the symbol table type. String specifies the name of the source file associated withthe object file.
.float floatThe .float directive generates a single-precision floating-point constant into the currentsection. The .float directive is not valid in the .bss section.
.globl symbol1, symbol2, ..., symbolNThe .globl directive declares each symbol in the list to be global. Each symbol is eitherdefined externally or defined in the input file and accessible in other files. Default bindingsfor the symbol are overridden. A global symbol definition in one file satisfies an undefinedreference to the same global symbol in another file. Multiple definitions of a defined globalsymbol are not allowed. If a defined global symbol has more than one definition, an erroroccurs. The .globl directive only declares the symbol to be global in scope, it does not definethe symbol.
.group group, section, #comdatThe .group directive adds section to a COMDAT group. Refer to “COMDAT Section” inOracle Solaris 11.1 Linkers and Libraries Guide for additional information about COMDAT.
.hidden symbol1, symbol2, ..., symbolNThe .hidden directive declares each symbol in the list to have hidden linker scoping. Allreferences to symbol within a dynamic module bind to the definition within that module.Symbol is not visible outside of the module.
.ident "string"The .ident directive creates an entry in the .comment section containing string. String is anysequence of characters, not including the double quote ("). To include the double quotecharacter within a string, precede the double quote character with a backslash (\) (ASCII0x5C).
.lcomm name, size, alignmentThe .lcomm directive allocates storage in the .bss section. The storage is referenced by thesymbol name, and has a size of size bytes. Name cannot be predefined, and size must be apositive integer. If alignment is specified, the address of name is aligned to a multiple ofalignment bytes. If alignment is not specified, the default alignment is 4 bytes.
.local symbol1, symbol2, ..., symbolNThe .local directive declares each symbol in the list to be local. Each symbol is defined in theinput file and not accessible to other files. Default bindings for the symbols are overridden.Symbols declared with the .local directive take precedence over weak and global symbols.(See“Symbol Table Section” in Oracle Solaris 11.1 Linkers and Libraries Guide for a
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Chapter 2 • Oracle Solaris x86 Assembly Language Syntax 23
description of global and weak symbols.) Because local symbols are not accessible to otherfiles, local symbols of the same name may exist in multiple files. The .local directive onlydeclares the symbol to be local in scope, it does not define the symbol.
.long expression1, expression2, ..., expressionNThe .long directive generates a long integer (32-bit, two's complement value) for eachexpression into the current section. Each expression must be a 32–bit value and must evaluateto an integer value. The .long directive is not valid for the .bss section.
.popsection
The .popsection directive pops the top of the section stack and continues processing of thepopped section.
.previous
The .previous directive continues processing of the previous section.
.pushsection sectionThe .pushsection directive pushes the specified section onto the section stack and switchesto another section.
.quad expression1, expression2, ..., expressionNThe .quad directive generates an initialized word (64-bit, two's complement value) for eachexpression into the current section. Each expression must be a 64-bit value, and must evaluateto an integer value. The .quad directive is not valid for the .bss section.
.rel symbol@ typeThe .rel directive generates the specified relocation entry type for the specified symbol. The.lit directive supports TLS (thread-local storage). Refer to Chapter 14, “Thread-LocalStorage,” in Oracle Solaris 11.1 Linkers and Libraries Guide for additional information aboutTLS.
.section section, attributesThe .section directive makes section the current section. If section does not exist, a newsection with the specified name and attributes is created. If section is a non-reserved section,attributes must be included the first time section is specified by the .section directive.
.set symbol, expressionThe .set directive assigns the value of expression to symbol. Expression can be any legalexpression that evaluates to a numerical value.
.size symbol, exprDeclares the symbol size to be expr. expr must be an absolute expression.
.skip integer, valueWhile generating values for any data section, the .skip directive causes integer bytes to beskipped over, or, optionally, filled with the specified value.
.sleb128 expressionThe .sleb128 directive generates a signed, little-endian, base 128 number from expression.
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x86 Assembly Language Reference Manual • October 201224
.string "string"The .string directive places the characters in string into the object module at the currentlocation and terminates the string with a null byte (\0). String must be enclosed in doublequotes (") (ASCII 0x22). The .string directive is not valid for the .bss section.
.symbolic symbol1, symbol2, ..., symbolNThe .symbolic directive declares each symbol in the list to havesymbolic linker scoping. Allreferences to symbol within a dynamic module bind to the definition within that module.Outside of the module, symbol is treated as global.
.tbss
The .tbss directive changes the current section to .tbss. The .tbss section containsuninitialized TLS data objects that will be initialized to zero by the runtime linker.
.tcomm
The .tcomm directive defines a TLS common block.
.tdata
The .tdata directive changes the current section to .tdata. The .tdata section contains theinitialization image for initialized TLS data objects.
.text
The .text directive defines the current section as .text.
.type symbol[, symbol, ..., symbol], type[, visibility]Declares the type of symbol, where type can be:
#object #tls_object #function #no_type
and where visibility can be one of:
#hidden #protected #eliminate #singleton #exported #internal
.uleb128 expressionThe .uleb128 directive generates an unsigned, little-endian, base 128 number fromexpression.
.value expression1, expression2, ..., expressionNThe .value directive generates an initialized word (16-bit, two's complement value) for eachexpression into the current section. Each expression must be a 16-bit integer value. The.value directive is not valid for the .bss section.
.weak symbol1, symbol2, ..., symbolNThe .weak directive declares each symbol in the argument list to be defined either externallyor in the input file and accessible to other files. Default bindings of the symbol are overriddenby the .weak directive. A weak symbol definition in one file satisfies an undefined referenceto a global symbol of the same name in another file. Unresolved weak symbols have a defaultvalue of zero. The link editor does not resolve these symbols. If a weak symbol has the samename as a defined global symbol, the weak symbol is ignored and no error results. The .weakdirective does not define the symbol.
Assembler Directives
Chapter 2 • Oracle Solaris x86 Assembly Language Syntax 25
.zero expressionWhile filling a data section, the .zero directive fills the number of bytes specified byexpression with zero (0).
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Instruction Set Mapping
This chapter provides a general mapping between the Oracle Solaris x86 assembly languagemnemonics and the Intel or Advanced Micro Devices (AMD) mnemonics. Refer to Intel 64 andIA-32 Architectures Software Developer Manuals for details on individual processorinstructions.
■ “Instruction Overview” on page 27■ “General-Purpose Instructions” on page 28■ “Floating-Point Instructions” on page 42■ “SIMD State Management Instructions” on page 48■ “MMX Instructions” on page 48■ “SSE Instructions” on page 53■ “SSE2 Instructions” on page 61■ “Operating System Support Instructions” on page 70■ “64–Bit AMD Opteron Considerations” on page 72
Instruction OverviewIt is beyond the scope of this manual to document the x86 architecture instruction set. Thischapter provides a general mapping between the Oracle Solaris x86 assembly languagemnemonics and the Intel or AMD mnemonics to enable you to refer to your vendor'sdocumentation for detailed information about a specific instruction. Instructions are groupedby functionality in tables with the following sections:
■ Oracle Solaris mnemonic■ Intel/AMD mnemonic■ Description (short)■ Notes
For certain Oracle Solaris mnemonics, the allowed data type suffixes for that mnemonic areindicated in braces ({}) following the mnemonic. For example, bswap{lq} indicates that the
3C H A P T E R 3
27
following mnemonics are valid: bswap, bswapl (which is the default and equivalent to bswap),and bswapq. See “Instructions” on page 19 for information on data type suffixes.
To locate a specific Oracle Solaris x86 mnemonic, look up the mnemonic in the index.
General-Purpose InstructionsThe general-purpose instructions perform basic data movement, memory addressing,arithmetic and logical operations, program flow control, input/output, and string operations oninteger, pointer, and BCD data types.
Data Transfer InstructionsThe data transfer instructions move data between memory and the general-purpose andsegment registers, and perform operations such as conditional moves, stack access, and dataconversion.
TABLE 3–1 Data Transfer Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
bswap{lq} BSWAP byte swap bswapq valid only under-m64
cbtw CBW convert byte to word
cltd CDQ convert doubleword toquadword
%eax → %edx:%eax
cltq CDQE convert doubleword toquadword
%eax → %rax
cltq valid only under-m64
cmova{wlq},cmov{wlq}.a
CMOVA conditional move if above cmovaq valid only under-m64
cmovae{wlq},cmov{wlq}.ae
CMOVAE conditional move if aboveor equal
cmovaeq valid only under-m64
cmovb{wlq},cmov{wlq}.b
CMOVB conditional move if below cmovbq valid only under-m64
cmovbe{wlq},cmov{wlq}.be
CMOVBE conditional move if belowor equal
cmovbeq valid only under-m64
cmovc{wlq},cmov{wlq}.c
CMOVC conditional move if carry cmovcq valid only under-m64
General-Purpose Instructions
x86 Assembly Language Reference Manual • October 201228
TABLE 3–1 Data Transfer Instructions (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
cmove{wlq},cmov{wlq}.e
CMOVE conditional move if equal cmoveq valid only under-m64
cmovg{wlq},cmov{wlq}.g
CMOVG conditional move ifgreater
cmovgq valid only under-m64
cmovge{wlq},cmov{wlq}.ge
CMOVGE conditional move ifgreater or equal
cmovgeq valid only under-m64
cmovl{wlq},cmov{wlq}.l
CMOVL conditional move if less cmovlq valid only under-m64
cmovle{wlq},cmov{wlq}.le
COMVLE conditional move if less orequal
cmovleq valid only under-m64
cmovna{wlq},cmov{wlq}.na
CMOVNA conditional move if notabove
cmovnaq valid only under-m64
cmovnae{wlq},cmov{wlq}.nae
CMOVNAE conditional move if notabove or equal
cmovnaeq valid onlyunder -m64
cmovnb{wlq},cmov{wlq}.nb
CMOVNB conditional move if notbelow
cmovnbq valid only under-m64
cmovnbe{wlq},cmov{wlq}.nbe
CMOVNBE conditional move if notbelow or equal
cmovnbeq valid onlyunder -m64
cmovnc{wlq},cmov{wlq}.nc
CMOVNC conditional move if notcarry
cmovncq valid only under-m64
cmovne{wlq},cmov{wlq}.ne
CMOVNE conditional move if notequal
cmovneq valid only under-m64
cmovng{wlq},cmov{wlq}.ng
CMOVNG conditional move ifgreater
cmovngq valid only under-m64
cmovnge{wlq},cmov{wlq}.nge
CMOVNGE conditional move if notgreater or equal
cmovngeq valid onlyunder -m64
cmovnl{wlq},cmov{wlq}.nl
CMOVNL conditional move if notless
cmovnlq valid only under-m64
cmovnle{wlq},cmov{wlq}.nle
CMOVNLE conditional move if notabove or equal
cmovnleq valid onlyunder -m64
cmovno{wlq},cmov{wlq}.no
CMOVNO conditional move if notoverflow
cmovnoq valid only under-m64
cmovnp{wlq},cmov{wlq}.np
CMOVNP conditional move if notparity
cmovnpq valid only under-m64
General-Purpose Instructions
Chapter 3 • Instruction Set Mapping 29
TABLE 3–1 Data Transfer Instructions (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
cmovns{wlq},cmov{wlq}.ns
CMOVNS conditional move if notsign (non-negative)
cmovnsq valid only under-m64
cmovnz{wlq},cmov{wlq}.nz
CMOVNZ conditional move if notzero
cmovnzq valid only under-m64
cmovo{wlq},cmov{wlq}.o
CMOVO conditional move ifoverflow
cmovoq valid only under-m64
cmovp{wlq},cmov{wlq}.p
CMOVP conditional move if parity cmovpq valid only under-m64
cmovpe{wlq},cmov{wlq}.pe
CMOVPE conditional move if parityeven
cmovpeq valid only under-m64
cmovpo{wlq},cmov{wlq}.po
CMOVPO conditional move if parityodd
cmovpoq valid only under-m64
cmovs{wlq},cmov{wlq}.s
CMOVS conditional move if sign(negative)
cmovsq valid only under-m64
cmovz{wlq},cmov{wlq}.z
CMOVZ conditional move if zero cmovzq valid only under-m64
cmpxchg{bwlq} CMPXCHG compare and exchange cmpxchgq valid onlyunder -m64
cmpxchg8b CMPXCHG8B compare and exchange 8bytes
cqtd CQO convert quadword tooctword
%rax → %rdx:%rax
cqtd valid only under-m64
cqto CQO convert quadword tooctword
%rax → %rdx:%rax
cqto valid only under-m64
cwtd CWD convert word todoubleword
%ax → %dx:%ax
cwtl CWDE convert word todoubleword in %eax
register
%ax → %eax
General-Purpose Instructions
x86 Assembly Language Reference Manual • October 201230
TABLE 3–1 Data Transfer Instructions (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
mov{bwlq} MOV move data betweenimmediate values, generalpurpose registers,segment registers, andmemory
movq valid only under-m64
movabs{bwlq} MOVABS move immediate value toregister
movabs valid only under-m64
movabs{bwlq}A MOVABS move immediate value toregister {AL, AX, GAX, RAX}
movabs valid only under-m64
movsb{wlq}, movsw{lq} MOVSX move and sign extend movsbq and movswq validonly under -m64
movzb{wlq}, movzw{lq} MOVZX move and zero extend movzbq and movzwq validonly under -m64
pop{wlq} POP pop stack popq valid only under-m64
popaw POPA pop general-purposeregisters from stack
popaw invalid under -m64
popal, popa POPAD pop general-purposeregisters from stack
invalid under -m64
push{wlq} PUSH push onto stack pushq valid only under-m64
pushaw PUSHA push general-purposeregisters onto stack
pushaw invalid under-m64
pushal, pusha PUSHAD push general-purposeregisters onto stack
invalid under -m64
xadd{bwlq} XADD exchange and add xaddq valid only under-m64
xchg{bwlq} XCHG exchange xchgq valid only under-m64
xchg{bwlq}A XCHG exchange xchgqA valid only under-m64
Binary Arithmetic InstructionsThe binary arithmetic instructions perform basic integer computions on operands in memoryor the general-purpose registers.
General-Purpose Instructions
Chapter 3 • Instruction Set Mapping 31
TABLE 3–2 Binary Arithmetic Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
adc{bwlq} ADC add with carry adcq valid only under-m64
add{bwlq} ADD integer add addq valid only under-m64
cmp{bwlq} CMP compare cmpq valid only under-m64
dec{bwlq} DEC decrement decq valid only under-m64
div{bwlq} DIV divide (unsigned) divq valid only under-m64
idiv{bwlq} IDIV divide (signed) idivq valid only under-m64
imul{bwlq} IMUL multiply (signed) imulq valid only under-m64
inc{bwlq} INC increment incq valid only under-m64
mul{bwlq} MUL multiply (unsigned) mulq valid only under-m64
neg{bwlq} NEG negate negq valid only under-m64
sbb{bwlq} SBB subtract with borrow sbbq valid only under-m64
sub{bwlq} SUB subtract subq valid only under-m64
Decimal Arithmetic InstructionsThe decimal arithmetic instructions perform decimal arithmetic on binary coded decimal(BCD) data.
TABLE 3–3 Decimal Arithmetic Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
aaa AAA ASCII adjust afteraddition
invalid under -m64
General-Purpose Instructions
x86 Assembly Language Reference Manual • October 201232
TABLE 3–3 Decimal Arithmetic Instructions (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
aad AAD ASCII adjust beforedivision
invalid under -m64
aam AAM ASCII adjust aftermultiplication
invalid under -m64
aas AAS ASCII adjust aftersubtraction
invalid under -m64
daa DAA decimal adjust afteraddition
invalid under -m64
das DAS decimal adjust aftersubtraction
invalid under -m64
Logical InstructionsThe logical instructions perform basic logical operations on their operands.
TABLE 3–4 Logical Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
and{bwlq} AND bitwise logical AND andq valid only under-m64
not{bwlq} NOT bitwise logical NOT notq valid only under-m64
or{bwlq} OR bitwise logical OR orq valid only under -m64
xor{bwlq} XOR bitwise logical exclusiveOR
xorq valid only under-m64
Shift and Rotate InstructionsThe shift and rotate instructions shift and rotate the bits in their operands.
TABLE 3–5 Shift and Rotate Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
rcl{bwlq} RCL rotate through carry left rclq valid only under-m64
General-Purpose Instructions
Chapter 3 • Instruction Set Mapping 33
TABLE 3–5 Shift and Rotate Instructions (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
rcr{bwlq} RCR rotate through carry right rcrq valid only under-m64
rol{bwlq} ROL rotate left rolq valid only under-m64
ror{bwlq} ROR rotate right rorq valid only under-m64
sal{bwlq} SAL shift arithmetic left salq valid only under-m64
sar{bwlq} SAR shift arithmetic right sarq valid only under-m64
shl{bwlq} SHL shift logical left shlq valid only under-m64
shld{bwlq} SHLD shift left double shldq valid only under-m64
shr{bwlq} SHR shift logical right shrq valid only under-m64
shrd{bwlq} SHRD shift right double shrdq valid only under-m64
Bit and Byte InstructionsThe bit instructions test and modify individual bits in operands. The byte instructions set thevalue of a byte operand to indicate the status of flags in the %eflags register.
TABLE 3–6 Bit and Byte Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
bsf{wlq} BSF bit scan forward bsfq valid only under-m64
bsr{wlq} BSR bit scan reverse bsrq valid only under-m64
bt{wlq} BT bit test btq valid only under -m64
btc{wlq} BTC bit test and complement btcq valid only under-m64
btr{wlq} BTR bit test and reset btrq valid only under-m64
General-Purpose Instructions
x86 Assembly Language Reference Manual • October 201234
TABLE 3–6 Bit and Byte Instructions (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
bts{wlq} BTS bit test and set btsq valid only under-m64
seta SETA set byte if above
setae SETAE set byte if above or equal
setb SETB set byte if below
setbe SETBE set byte if below or equal
setc SETC set byte if carry
sete SETE set byte if equal
setg SETG set byte if greater
setge SETGE set byte if greater or equal
setl SETL set byte if less
setle SETLE set byte if less or equal
setna SETNA set byte if not above
setnae SETNAE set byte if not above orequal
setnb SETNB set byte if not below
setnbe SETNBE set byte if not below orequal
setnc SETNC set byte if not carry
setne SETNE set byte if not equal
setng SETNG set byte if not greater
setnge SETNGE set byte if not greater orequal
setnl SETNL set byte if not less
setnle SETNLE set byte if not less or equal
setno SETNO set byte if not overflow
setnp SETNP set byte if not parity
setns SETNS set byte if not sign(non-negative)
setnz SETNZ set byte if not zero
General-Purpose Instructions
Chapter 3 • Instruction Set Mapping 35
TABLE 3–6 Bit and Byte Instructions (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
seto SETO set byte if overflow
setp SETP set byte if parity
setpe SETPE set byte if parity even
setpo SETPO set byte if parity odd
sets SETS set byte if sign (negative)
setz SETZ set byte if zero
test{bwlq} TEST logical compare testq valid only under-m64
Control Transfer InstructionsThe control transfer instructions control the flow of program execution.
TABLE 3–7 Control Transfer Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
bound{wl} BOUND detect value out of range boundw invalid under-m64
call CALL call procedure
enter ENTER high-level procedureentry
int INT software interrupt
into INTO interrupt on overflow invalid under -m64
iret IRET return from interrupt
ja JA jump if above
jae JAE jump if above or equal
jb JB jump if below
jbe JBE jump if below or equal
jc JC jump if carry
jcxz JCXZ jump register %cx zero
je JE jump if equal
General-Purpose Instructions
x86 Assembly Language Reference Manual • October 201236
TABLE 3–7 Control Transfer Instructions (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
jecxz JECXZ jump register %ecx zero invalid under -m64
jg JG jump if greater
jge JGE jump if greater or equal
jl JL jump if less
jle JLE jump if less or equal
jmp JMP jump
jnae JNAE jump if not above or equal
jnb JNB jump if not below
jnbe JNBE jump if not below or equal
jnc JNC jump if not carry
jne JNE jump if not equal
jng JNG jump if not greater
jnge JNGE jump if not greater orequal
jnl JNL jump if not less
jnle JNLE jump if not less or equal
jno JNO jump if not overflow
jnp JNP jump if not parity
jns JNS jump if not sign(non-negative)
jnz JNZ jump if not zero
jo JO jump if overflow
jp JP jump if parity
jpe JPE jump if parity even
jpo JPO jump if parity odd
js JS jump if sign (negative)
jz JZ jump if zero
lcall CALL call far procedure valid as indirect only for-m64
General-Purpose Instructions
Chapter 3 • Instruction Set Mapping 37
TABLE 3–7 Control Transfer Instructions (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
leave LEAVE high-level procedure exit
loop LOOP loop with %ecx counter
loope LOOPE loop with %ecx and equal
loopne LOOPNE loop with %ecx and notequal
loopnz LOOPNZ loop with %ecx and notzero
loopz LOOPZ loop with %ecx and zero
lret RET return from far procedure valid as indirect only form64
ret RET return
String InstructionsThe string instructions operate on strings of bytes. Operations include storing strings inmemory, loading strings from memory, comparing strings, and scanning strings for substrings.
Note – The Oracle Solaris mnemonics for certain instructions differ slightly from the Intel/AMDmnemonics. Alphabetization of the table below is by the Oracle Solaris mnemonic. All stringoperations default to long (doubleword).
TABLE 3–8 String Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
cmps{q} CMPS compare string cmpsq valid only under-m64
cmpsb CMPSB compare byte string
cmpsl CMPSD compare doublewordstring
cmpsw CMPSW compare word string
lods{q} LODS load string lodsq valid only under-m64
lodsb LODSB load byte string
lodsl LODSD load doubleword string
General-Purpose Instructions
x86 Assembly Language Reference Manual • October 201238
TABLE 3–8 String Instructions (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
lodsw LODSW load word string
movs{q} MOVS move string movsq valid only under-m64
movsb MOVSB move byte string movsb is not movsb{wlq}.See Table 3–1
movsl, smovl MOVSD move doubleword string
movsw, smovw MOVSW move word string movsw is not movsw{lq}.See Table 3–1
rep REP repeat while %ecx not zero
repnz REPNE repeat while not equal
repnz REPNZ repeat while not zero
repz REPE repeat while equal
repz REPZ repeat while zero
scas{q} SCAS scan string scasq valid only under-m64
scasb SCASB scan byte string
scasl SCASD scan doubleword string
scasw SCASW scan word string
stos{q} STOS store string stosq valid only under-m64
stosb STOSB store byte string
stosl STOSD store doubleword string
stosw STOSW store word string
I/O InstructionsThe input/output instructions transfer data between the processor's I/O ports, registers, andmemory.
General-Purpose Instructions
Chapter 3 • Instruction Set Mapping 39
TABLE 3–9 I/O Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
in IN read from a port
ins INS input string from a port
insb INSB input byte string fromport
insl INSD input doubleword stringfrom port
insw INSW input word string fromport
out OUT write to a port
outs OUTS output string to port
outsb OUTSB output byte string to port
outsl OUTSD output doubleword stringto port
outsw OUTSW output word string to port
Flag Control (EFLAG) InstructionsThe status flag control instructions operate on the bits in the %eflags register.
TABLE 3–10 Flag Control Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
clc CLC clear carry flag
cld CLD clear direction flag
cli CLI clear interrupt flag
cmc CMC complement carry flag
lahf LAHF load flags into %ah register
popfw POPF pop %eflags from stack
popf{lq} POPFL pop %eflags from stack popfq valid only under-m64
pushfw PUSHF push %eflags onto stack
General-Purpose Instructions
x86 Assembly Language Reference Manual • October 201240
TABLE 3–10 Flag Control Instructions (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
pushf{lq} PUSHFL push %eflags onto stack pushfq valid only under-m64
sahf SAHF store %ah register intoflags
stc STC set carry flag
std STD set direction flag
sti STI set interrupt flag
Segment Register InstructionsThe segment register instructions load far pointers (segment addresses) into the segmentregisters.
TABLE 3–11 Segment Register Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
lds{wl} LDS load far pointer using %ds ldsl and ldsw invalidunder -m64
les{wl} LES load far pointer using %es lesl and lesw invalidunder -m64
lfs{wl} LFS load far pointer using %fs
lgs{wl} LGS load far pointer using %gs
lss{wl} LSS load far pointer using %ss
Miscellaneous InstructionsThe instructions documented in this section provide a number of useful functions.
TABLE 3–12 Miscellaneous Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
cpuid CPUID processor identification
lea{wlq} LEA load effective address leaq valid only under-m64
nop NOP no operation
General-Purpose Instructions
Chapter 3 • Instruction Set Mapping 41
TABLE 3–12 Miscellaneous Instructions (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
ud2 UD2 undefined instruction
xlat XLAT table lookup translation
xlatb XLATB table lookup translation
Floating-Point InstructionsThe floating point instructions operate on floating-point, integer, and binary coded decimal(BCD) operands.
Data Transfer Instructions (Floating Point)The data transfer instructions move floating-point, integer, and BCD values between memoryand the floating point registers.
TABLE 3–13 Data Transfer Instructions (Floating-Point)
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
fbld FBLD load BCD
fbstp FBSTP store BCD and pop
fcmovb FCMOVB floating-point conditionalmove if below
fcmovbe FCMOVBE floating-point conditionalmove if below or equal
fcmove FCMOVE floating-point conditionalmove if equal
fcmovnb FCMOVNB floating-point conditionalmove if not below
fcmovnbe FCMOVNBE floating-point conditionalmove if not below orequal
fcmovne FCMOVNE floating-point conditionalmove if not equal
fcmovnu FCMOVNU floating-point conditionalmove if unordered
Floating-Point Instructions
x86 Assembly Language Reference Manual • October 201242
TABLE 3–13 Data Transfer Instructions (Floating-Point) (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
fcmovu FCMOVU floating-point conditionalmove if unordered
fild FILD load integer
fist FIST store integer
fistp FISTP store integer and pop
fld FLD load floating-point value
fst FST store floating-point value
fstp FSTP store floating-point valueand pop
fxch FXCH exchange registers
Basic Arithmetic Instructions (Floating-Point)The basic arithmetic instructions perform basic arithmetic operations on floating-point andinteger operands.
TABLE 3–14 Basic Arithmetic Instructions (Floating-Point)
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
fabs FABS absolute value
fadd FADD add floating-point
faddp FADDP add floating-point andpop
fchs FCHS change sign
fdiv FDIV divide floating-point
fdivp FDIVP divide floating-point andpop
fdivr FDIVR divide floating-pointreverse
fdivrp FDIVRP divide floating-pointreverse and pop
fiadd FIADD add integer
fidiv FIDIV divide integer
Floating-Point Instructions
Chapter 3 • Instruction Set Mapping 43
TABLE 3–14 Basic Arithmetic Instructions (Floating-Point) (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
fidivr FIDIVR divide integer reverse
fimul FIMUL multiply integer
fisub FISUB subtract integer
fisubr FISUBR subtract integer reverse
fmul FMUL multiply floating-point
fmulp FMULP multiply floating-pointand pop
fprem FPREM partial remainder
fprem1 FPREM1 IEEE partial remainder
frndint FRNDINT round to integer
fscale FSCALE scale by power of two
fsqrt FSQRT square root
fsub FSUB subtract floating-point
fsubp FSUBP subtract floating-pointand pop
fsubr FSUBR subtract floating-pointreverse
fsubrp FSUBRP subtract floating-pointreverse and pop
fxtract FXTRACT extract exponent andsignificand
Comparison Instructions (Floating-Point)The floating-point comparison instructions operate on floating-point or integer operands.
TABLE 3–15 Comparison Instructions (Floating-Point)
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
fcom FCOM compare floating-point
fcomi FCOMI compare floating-pointand set %eflags
Floating-Point Instructions
x86 Assembly Language Reference Manual • October 201244
TABLE 3–15 Comparison Instructions (Floating-Point) (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
fcomip FCOMIP compare floating-point,set %eflags, and pop
fcomp FCOMP compare floating-pointand pop
fcompp FCOMPP compare floating-pointand pop twice
ficom FICOM compare integer
ficomp FICOMP compare integer and pop
ftst FTST test floating-point(compare with 0.0)
fucom FUCOM unordered comparefloating-point
fucomi FUCOMI unordered comparefloating-point and set%eflags
fucomip FUCOMIP unordered comparefloating-point, set%eflags, and pop
fucomp FUCOMP unordered comparefloating-point and pop
fucompp FUCOMPP compare floating-pointand pop twice
fxam FXAM examine floating-point
Transcendental Instructions (Floating-Point)The transcendental instructions perform trigonometric and logarithmic operations onfloating-point operands.
TABLE 3–16 Transcendental Instructions (Floating-Point)
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
f2xm1 F2XM1 computes 2x−1
fcos FCOS cosine
fpatan FPATAN partial arctangent
Floating-Point Instructions
Chapter 3 • Instruction Set Mapping 45
TABLE 3–16 Transcendental Instructions (Floating-Point) (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
fptan FPTAN partial tangent
fsin FSIN sine
fsincos FSINCOS sine and cosine
fyl2x FYL2X computes y * log2x
fyl2xp1 FYL2XP1 computes y * log2(x+1)
Load Constants (Floating-Point) InstructionsThe load constants instructions load common constants, such as π, into the floating-pointregisters.
TABLE 3–17 Load Constants Instructions (Floating-Point)
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
fld1 FLD1 load +1.0
fldl2e FLDL2E load log2e
fldl2t FLDL2T load log210
fldlg2 FLDLG2 load log102
fldln2 FLDLN2 load loge2
fldpi FLDPI load π
fldz FLDZ load +0.0
Control Instructions (Floating-Point)The floating-point control instructions operate on the floating-point register stack and save andrestore the floating-point state.
TABLE 3–18 Control Instructions (Floating-Point)
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
fclex FCLEX clear floating-pointexception flags afterchecking for errorconditions
Floating-Point Instructions
x86 Assembly Language Reference Manual • October 201246
TABLE 3–18 Control Instructions (Floating-Point) (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
fdecstp FDECSTP decrement floating-pointregister stack pointer
ffree FFREE free floating-pointregister
fincstp FINCSTP increment floating-pointregister stack pointer
finit FINIT initialize floating-pointunit after checking errorconditions
fldcw FLDCW load floating-point unitcontrol word
fldenv FLDENV load floating-point unitenvironment
fnclex FNCLEX clear floating-pointexception flags withoutchecking for errorconditions
fninit FNINIT initialize floating-pointunit without checkingerror conditions
fnop FNOP floating-point nooperation
fnsave FNSAVE save floating-point unitstate without checkingerror conditions
fnstcw FNSTCW store floating-point unitcontrol word withoutchecking error conditions
fnstenv FNSTENV store floating-point unitenvironment withoutchecking error conditions
fnstsw FNSTSW store floating-point unitstatus word withoutchecking error conditions
frstor FRSTOR restore floating-point unitstate
Floating-Point Instructions
Chapter 3 • Instruction Set Mapping 47
TABLE 3–18 Control Instructions (Floating-Point) (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
fsave FSAVE save floating-point unitstate after checking errorconditions
fstcw FSTCW store floating-point unitcontrol word afterchecking error conditions
fstenv FSTENV store floating-point unitenvironment afterchecking error conditions
fstsw FSTSW store floating-point unitstatus word after checkingerror conditions
fwait FWAIT wait for floating-pointunit
wait WAIT wait for floating-pointunit
SIMD State Management InstructionsThe fxsave and fxrstor instructions save and restore the state of the floating-point unit andthe MMX, XMM, and MXCSR registers.
TABLE 3–19 SIMD State Management Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
fxrstor FXRSTOR restore floating-point unitand SIMD state
fxsave FXSAVE save floating-point unitand SIMD state
MMX InstructionsThe MMX instructions enable x86 processors to perform single-instruction,multiple-data(SIMD) operations on packed byte, word, doubleword, or quadword integeroperands contained in memory, in MMX registers, or in general-purpose registers.
SIMD State Management Instructions
x86 Assembly Language Reference Manual • October 201248
Data Transfer Instructions (MMX)The data transfer instructions move doubleword and quadword operands between MMXregisters and between MMX registers and memory.
TABLE 3–20 Data Transfer Instructions (MMX)
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
movd MOVD move doubleword movdq valid only under-m64
movq MOVQ move quadword valid only under -m64
Conversion Instructions (MMX)The conversion instructions pack and unpack bytes, words, and doublewords.
TABLE 3–21 Conversion Instructions (MMX)
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
packssdw PACKSSDW pack doublewords intowords with signedsaturation
packsswb PACKSSWB pack words into byteswith signed saturation
packuswb PACKUSWB pack words into byteswith unsigned saturation
punpckhbw PUNPCKHBW unpack high-order bytes
punpckhdq PUNPCKHDQ unpack high-orderdoublewords
punpckhwd PUNPCKHWD unpack high-order words
punpcklbw PUNPCKLBW unpack low-order bytes
punpckldq PUNPCKLDQ unpack low-orderdoublewords
punpcklwd PUNPCKLWD unpack low-order words
Packed Arithmetic Instructions (MMX)The packed arithmetic instructions perform packed integer arithmetic on packed byte, word,and doubleword integers.
MMX Instructions
Chapter 3 • Instruction Set Mapping 49
TABLE 3–22 Packed Arithmetic Instructions (MMX)
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
paddb PADDB add packed byte integers
paddd PADDD add packed doublewordintegers
paddsb PADDSB add packed signed byteintegers with signedsaturation
paddsw PADDSW add packed signed wordintegers with signedsaturation
paddusb PADDUSB add packed unsigned byteintegers with unsignedsaturation
paddusw PADDUSW add packed unsignedword integers withunsigned saturation
paddw PADDW add packed word integers
pmaddwd PMADDWD multiply and add packedword integers
pmulhw PMULHW multiply packed signedword integers and storehigh result
pmullw PMULLW multiply packed signedword integers and storelow result
psubb PSUBB subtract packed byteintegers
psubd PSUBD subtract packeddoubleword integers
psubsb PSUBSB subtract packed signedbyte integers with signedsaturation
psubsw PSUBSW subtract packed signedword integers with signedsaturation
MMX Instructions
x86 Assembly Language Reference Manual • October 201250
TABLE 3–22 Packed Arithmetic Instructions (MMX) (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
psubusb PSUBUSB subtract packed unsignedbyte integers withunsigned saturation
psubusw PSUBUSW subtract packed unsignedword integers withunsigned saturation
psubw PSUBW subtract packed wordintegers
Comparison Instructions (MMX)The compare instructions compare packed bytes, words, or doublewords.
TABLE 3–23 Comparison Instructions (MMX)
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
pcmpeqb PCMPEQB compare packed bytes forequal
pcmpeqd PCMPEQD compare packeddoublewords for equal
pcmpeqw PCMPEQW compare packed wordsfor equal
pcmpgtb PCMPGTB compare packed signedbyte integers for greaterthan
pcmpgtd PCMPGTD compare packed signeddoubleword integers forgreater than
pcmpgtw PCMPGTW compare packed signedword integers for greaterthan
Logical Instructions (MMX)The logical instructions perform logical operations on quadword operands.
MMX Instructions
Chapter 3 • Instruction Set Mapping 51
TABLE 3–24 Logical Instructions (MMX)
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
pand PAND bitwise logical AND
pandn PANDN bitwise logical AND NOT
por POR bitwise logical OR
pxor PXOR bitwise logical XOR
Shift and Rotate Instructions (MMX)The shift and rotate instructions operate on packed bytes, words, doublewords, or quadwordsin 64–bit operands.
TABLE 3–25 Shift and Rotate Instructions (MMX)
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
pslld PSLLD shift packed doublewordsleft logical
psllq PSLLQ shift packed quadwordleft logical
psllw PSLLW shift packed words leftlogical
psrad PSRAD shift packed doublewordsright arithmetic
psraw PSRAW shift packed words rightarithmetic
psrld PSRLD shift packed doublewordsright logical
psrlq PSRLQ shift packed quadwordright logical
psrlw PSRLW shift packed words rightlogical
State Management Instructions (MMX)The emms (EMMS) instruction clears the MMX state from the MMX registers.
MMX Instructions
x86 Assembly Language Reference Manual • October 201252
TABLE 3–26 State Management Instructions (MMX)
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
emms EMMS empty MMX state
SSE InstructionsSSE instructions are an extension of the SIMD execution model introduced with the MMXtechnology. SSE instructions are divided into four subgroups:
■ SIMD single-precision floating-point instructions that operate on the XMM registers■ MXSCR state management instructions■ 64–bit SIMD integer instructions that operate on the MMX registers■ Instructions that provide cache control, prefetch, and instruction ordering functionality
SIMD Single-Precision Floating-Point Instructions(SSE)The SSE SIMD instructions operate on packed and scalar single-precision floating-point valueslocated in the XMM registers or memory.
Data Transfer Instructions (SSE)The SSE data transfer instructions move packed and scalar single-precision floating-pointoperands between XMM registers and between XMM registers and memory.
TABLE 3–27 Data Transfer Instructions (SSE)
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
movaps MOVAPS move four aligned packedsingle-precisionfloating-point valuesbetween XMM registersor memory
movhlps MOVHLPS move two packedsingle-precisionfloating-point valuesfrom the high quadwordof an XMM register to thelow quadword of anotherXMM register
SSE Instructions
Chapter 3 • Instruction Set Mapping 53
TABLE 3–27 Data Transfer Instructions (SSE) (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
movhps MOVHPS move two packedsingle-precisionfloating-point values to orfrom the high quadwordof an XMM register ormemory
movlhps MOVLHPS move two packedsingle-precisionfloating-point valuesfrom the low quadword ofan XMM register to thehigh quadword of anotherXMM register
movlps MOVLPS move two packedsingle-precisionfloating-point values to orfrom the low quadword ofan XMM register ormemory
movmskps MOVMSKPS extract sign mask fromfour packedsingle-precisionfloating-point values
movss MOVSS move scalarsingle-precisionfloating-point valuebetween XMM registersor memory
movups MOVUPS move four unalignedpacked single-precisionfloating-point valuesbetween XMM registersor memory
Packed Arithmetic Instructions (SSE)SSE packed arithmetic instructions perform packed and scalar arithmetic operations on packedand scalar single-precision floating-point operands.
SSE Instructions
x86 Assembly Language Reference Manual • October 201254
TABLE 3–28 Packed Arithmetic Instructions (SSE)
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
addps ADDPS add packedsingle-precisionfloating-point values
addss ADDSS add scalarsingle-precisionfloating-point values
divps DIVPS divide packedsingle-precisionfloating-point values
divss DIVSS divide scalarsingle-precisionfloating-point values
maxps MAXPS return maximum packedsingle-precisionfloating-point values
maxss MAXSS return maximum scalarsingle-precisionfloating-point values
minps MINPS return minimum packedsingle-precisionfloating-point values
minss MINSS return minimum scalarsingle-precisionfloating-point values.
mulps MULPS multiply packedsingle-precisionfloating-point values
mulss MULSS multiply scalarsingle-precisionfloating-point values
rcpps RCPPS compute reciprocals ofpacked single-precisionfloating-point values
rcpss RCPSS compute reciprocal ofscalar single-precisionfloating-point values
SSE Instructions
Chapter 3 • Instruction Set Mapping 55
TABLE 3–28 Packed Arithmetic Instructions (SSE) (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
rsqrtps RSQRTPS compute reciprocals ofsquare roots of packedsingle-precisionfloating-point values
rsqrtss RSQRTSS compute reciprocal ofsquare root of scalarsingle-precisionfloating-point values
sqrtps SQRTPS compute square roots ofpacked single-precisionfloating-point values
sqrtss SQRTSS compute square root ofscalar single-precisionfloating-point values
subps SUBPS subtract packedsingle-precisionfloating-point values
subss SUBSS subtract scalarsingle-precisionfloating-point values
Comparison Instructions (SSE)The SEE compare instructions compare packed and scalar single-precision floating-pointoperands.
TABLE 3–29 Comparison Instructions (SSE)
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
cmpps CMPPS compare packedsingle-precisionfloating-point values
cmpss CMPSS compare scalarsingle-precisionfloating-point values
SSE Instructions
x86 Assembly Language Reference Manual • October 201256
TABLE 3–29 Comparison Instructions (SSE) (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
comiss COMISS perform orderedcomparison of scalarsingle-precisionfloating-point values andset flags in EFLAGSregister
ucomiss UCOMISS perform unorderedcomparison of scalarsingle-precisionfloating-point values andset flags in EFLAGSregister
Logical Instructions (SSE)The SSE logical instructions perform bitwise AND, AND NOT, OR, and XOR operations onpacked single-precision floating-point operands.
TABLE 3–30 Logical Instructions (SSE)
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
andnps ANDNPS perform bitwise logicalAND NOT of packedsingle-precisionfloating-point values
andps ANDPS perform bitwise logicalAND of packedsingle-precisionfloating-point values
orps ORPS perform bitwise logicalOR of packedsingle-precisionfloating-point values
xorps XORPS perform bitwise logicalXOR of packedsingle-precisionfloating-point values
Shuffle and Unpack Instructions (SSE)The SSE shuffle and unpack instructions shuffle or interleave single-precision floating-pointvalues in packed single-precision floating-point operands.
SSE Instructions
Chapter 3 • Instruction Set Mapping 57
TABLE 3–31 Shuffle and Unpack Instructions (SSE)
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
shufps SHUFPS shuffles values in packedsingle-precisionfloating-point operands
unpckhps UNPCKHPS unpacks and interleavesthe two high-order valuesfrom two single-precisionfloating-point operands
unpcklps UNPCKLPS unpacks and interleavesthe two low-order valuesfrom two single-precisionfloating-point operands
Conversion Instructions (SSE)The SSE conversion instructions convert packed and individual doubleword integers intopacked and scalar single-precision floating-point values.
TABLE 3–32 Conversion Instructions (SSE)
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
cvtpi2ps CVTPI2PS convert packeddoubleword integers topacked single-precisionfloating-point values
cvtps2pi CVTPS2PI convert packedsingle-precisionfloating-point values topacked doublewordintegers
cvtsi2ss CVTSI2SS convert doublewordinteger to scalarsingle-precisionfloating-point value
cvtss2si CVTSS2SI convert scalarsingle-precisionfloating-point value to adoubleword integer
SSE Instructions
x86 Assembly Language Reference Manual • October 201258
TABLE 3–32 Conversion Instructions (SSE) (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
cvttps2pi CVTTPS2PI convert with truncationpacked single-precisionfloating-point values topacked doublewordintegers
cvttss2si CVTTSS2SI convert with truncationscalar single-precisionfloating-point value toscalar doubleword integer
MXCSR State Management Instructions (SSE)The MXCSR state management instructions save and restore the state of the MXCSR controland status register.
TABLE 3–33 MXCSR State Management Instructions (SSE)
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
ldmxcsr LDMXCSR load %mxcsr register
stmxcsr STMXCSR save %mxcsr register state
64–Bit SIMD Integer Instructions (SSE)The SSE 64–bit SIMD integer instructions perform operations on packed bytes, words, ordoublewords in MMX registers.
TABLE 3–34 64–Bit SIMD Integer Instructions (SSE)
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
pavgb PAVGB compute average ofpacked unsigned byteintegers
pavgw PAVGW compute average ofpacked unsigned byteintegers
pextrw PEXTRW extract word
pinsrw PINSRW insert word
SSE Instructions
Chapter 3 • Instruction Set Mapping 59
TABLE 3–34 64–Bit SIMD Integer Instructions (SSE) (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
pmaxsw PMAXSW maximum of packedsigned word integers
pmaxub PMAXUB maximum of packedunsigned byte integers
pminsw PMINSW minimum of packedsigned word integers
pminub PMINUB minimum of packedunsigned byte integers
pmovmskb PMOVMSKB move byte mask
pmulhuw PMULHUW multiply packed unsignedintegers and store highresult
psadbw PSADBW compute sum of absolutedifferences
pshufw PSHUFW shuffle packed integerword in MMX register
Miscellaneous Instructions (SSE)The following instructions control caching, prefetching, and instruction ordering.
TABLE 3–35 Miscellaneous Instructions (SSE)
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
maskmovq MASKMOVQ non-temporal store ofselected bytes from anMMX register intomemory
movntps MOVNTPS non-temporal store offour packedsingle-precisionfloating-point valuesfrom an XMM registerinto memory
movntq MOVNTQ non-temporal store ofquadword from an MMXregister into memory
SSE Instructions
x86 Assembly Language Reference Manual • October 201260
TABLE 3–35 Miscellaneous Instructions (SSE) (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
prefetchnta PREFETCHNTA prefetch data intonon-temporal cachestructure and into alocation close to theprocessor
prefetcht0 PREFETCHT0 prefetch data into alllevels of the cachehierarchy
prefetcht1 PREFETCHT1 prefetch data into level 2cache and higher
prefetcht2 PREFETCHT2 prefetch data into level 2cache and higher
sfence SFENCE serialize store operations
SSE2 InstructionsSSE2 instructions are an extension of the SIMD execution model introduced with the MMXtechnology and the SSE extensions. SSE2 instructions are divided into four subgroups:
■ Packed and scalar double-precision floating-point instructions■ Packed single-precision floating-point conversion instructions■ 128–bit SIMD integer instructions■ Instructions that provide cache control and instruction ordering functionality
SSE2 Packed and Scalar Double-PrecisionFloating-Point InstructionsThe SSE2 packed and scalar double-precision floating-point instructions operate ondouble-precision floating-point operands.
SSE2 Data Movement InstructionsThe SSE2 data movement instructions move double-precision floating-point data betweenXMM registers and memory.
SSE2 Instructions
Chapter 3 • Instruction Set Mapping 61
TABLE 3–36 SSE2 Data Movement Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
movapd MOVAPD move two aligned packeddouble-precisionfloating-point valuesbetween XMM registersand memory
movhpd MOVHPD move high packeddouble-precisionfloating-point value to orfrom the high quadwordof an XMM register andmemory
movlpd MOVLPD move low packedsingle-precisionfloating-point value to orfrom the low quadword ofan XMM register andmemory
movmskpd MOVMSKPD extract sign mask fromtwo packeddouble-precisionfloating-point values
movsd MOVSD move scalardouble-precisionfloating-point valuebetween XMM registersand memory.
movupd MOVUPD move two unalignedpacked double-precisionfloating-point valuesbetween XMM registersand memory
SSE2 Packed Arithmetic InstructionsThe SSE2 arithmetic instructions operate on packed and scalar double-precision floating-pointoperands.
SSE2 Instructions
x86 Assembly Language Reference Manual • October 201262
TABLE 3–37 SSE2 Packed Arithmetic Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
addpd ADDPD add packeddouble-precisionfloating-point values
addsd ADDSD add scalardouble-precisionfloating-point values
divpd DIVPD divide packeddouble-precisionfloating-point values
divsd DIVSD divide scalardouble-precisionfloating-point values
maxpd MAXPD return maximum packeddouble-precisionfloating-point values
maxsd MAXSD return maximum scalardouble-precisionfloating-point value
minpd MINPD return minimum packeddouble-precisionfloating-point values
minsd MINSD return minimum scalardouble-precisionfloating-point value
mulpd MULPD multiply packeddouble-precisionfloating-point values
mulsd MULSD multiply scalardouble-precisionfloating-point values
sqrtpd SQRTPD compute packed squareroots of packeddouble-precisionfloating-point values
sqrtsd SQRTSD compute scalar squareroot of scalardouble-precisionfloating-point value
SSE2 Instructions
Chapter 3 • Instruction Set Mapping 63
TABLE 3–37 SSE2 Packed Arithmetic Instructions (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
subpd SUBPD subtract packeddouble-precisionfloating-point values
subsd SUBSD subtract scalardouble-precisionfloating-point values
SSE2 Logical InstructionsThe SSE2 logical instructions operate on packed double-precision floating-point values.
TABLE 3–38 SSE2 Logical Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
andnpd ANDNPD perform bitwise logicalAND NOT of packeddouble-precisionfloating-point values
andpd ANDPD perform bitwise logicalAND of packeddouble-precisionfloating-point values
orpd ORPD perform bitwise logicalOR of packeddouble-precisionfloating-point values
xorpd XORPD perform bitwise logicalXOR of packeddouble-precisionfloating-point values
SSE2 Compare InstructionsThe SSE2 compare instructions compare packed and scalar double-precision floating-pointvalues and return the results of the comparison to either the destination operand or to theEFLAGS register.
SSE2 Instructions
x86 Assembly Language Reference Manual • October 201264
TABLE 3–39 SSE2 Compare Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
cmppd CMPPD compare packeddouble-precisionfloating-point values
cmpsd CMPSD compare scalardouble-precisionfloating-point values
comisd COMISD perform orderedcomparison of scalardouble-precisionfloating-point values andset flags in EFLAGSregister
ucomisd UCOMISD perform unorderedcomparison of scalardouble-precisionfloating-point values andset flags in EFLAGSregister
SSE2 Shuffle and Unpack InstructionsThe SSE2 shuffle and unpack instructions operate on packed double-precision floating-pointoperands.
TABLE 3–40 SSE2 Shuffle and Unpack Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
shufpd SHUFPD shuffle values in packeddouble-precisionfloating-point operands
unpckhpd UNPCKHPD unpack and interleave thehigh values from twopacked double-precisionfloating-point operands
unpcklpd UNPCKLPD unpack and interleave thelow values from twopacked double-precisionfloating-point operands
SSE2 Instructions
Chapter 3 • Instruction Set Mapping 65
SSE2 Conversion InstructionsThe SSE2 conversion instructions convert packed and individual doubleword integers intopacked and scalar double-precision floating-point values (and vice versa). These instructionsalso convert between packed and scalar single-precision and double-precision floating-pointvalues.
TABLE 3–41 SSE2 Conversion Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
cvtdq2pd CVTDQ2PD convert packeddoubleword integers topacked double-precisionfloating-point values
cvtpd2dq CVTPD2DQ convert packeddouble-precisionfloating-point values topacked doublewordintegers
cvtpd2pi CVTPD2PI convert packeddouble-precisionfloating-point values topacked doublewordintegers
cvtpd2ps CVTPD2PS convert packeddouble-precisionfloating-point values topacked single-precisionfloating-point values
cvtpi2pd CVTPI2PD convert packeddoubleword integers topacked double-precisionfloating-point values
cvtps2pd CVTPS2PD convert packedsingle-precisionfloating-point values topacked double-precisionfloating-point values
cvtsd2si CVTSD2SI convert scalardouble-precisionfloating-point values to adoubleword integer
SSE2 Instructions
x86 Assembly Language Reference Manual • October 201266
TABLE 3–41 SSE2 Conversion Instructions (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
cvtsd2ss CVTSD2SS convert scalardouble-precisionfloating-point values toscalar single-precisionfloating-point values
cvtsi2sd CVTSI2SD convert doublewordinteger to scalardouble-precisionfloating-point value
cvtss2sd CVTSS2SD convert scalarsingle-precisionfloating-point values toscalar double-precisionfloating-point values
cvttpd2dq CVTTPD2DQ convert with truncationpacked double-precisionfloating-point values topacked doublewordintegers
cvttpd2pi CVTTPD2PI convert with truncationpacked double-precisionfloating-point values topacked doublewordintegers
cvttsd2si CVTTSD2SI convert with truncationscalar double-precisionfloating-point values toscalar doublewordintegers
SSE2 Packed Single-Precision Floating-PointInstructionsThe SSE2 packed single-precision floating-point instructions operate on single-precisionfloating-point and integer operands.
SSE2 Instructions
Chapter 3 • Instruction Set Mapping 67
TABLE 3–42 SSE2 Packed Single-Precision Floating-Point Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
cvtdq2ps CVTDQ2PS convert packeddoubleword integers topacked single-precisionfloating-point values
cvtps2dq CVTPS2DQ convert packedsingle-precisionfloating-point values topacked doublewordintegers
cvttps2dq CVTTPS2DQ convert with truncationpacked single-precisionfloating-point values topacked doublewordintegers
SSE2 128–Bit SIMD Integer InstructionsThe SSE2 SIMD integer instructions operate on packed words, doublewords, and quadwordscontained in XMM and MMX registers.
TABLE 3–43 SSE2 128–Bit SIMD Integer Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
movdq2q MOVDQ2Q move quadword integerfrom XMM to MMXregisters
movdqa MOVDQA move aligned doublequadword
movdqu MOVDQU move unaligned doublequadword
movq2dq MOVQ2DQ move quadword integerfrom MMX to XMMregisters
paddq PADDQ add packed quadwordintegers
pmuludq PMULUDQ multiply packed unsigneddoubleword integers
SSE2 Instructions
x86 Assembly Language Reference Manual • October 201268
TABLE 3–43 SSE2 128–Bit SIMD Integer Instructions (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
pshufd PSHUFD shuffle packeddoublewords
pshufhw PSHUFHW shuffle packed high words
pshuflw PSHUFLW shuffle packed low words
pslldq PSLLDQ shift double quadwordleft logical
psrldq PSRLDQ shift double quadwordright logical
psubq PSUBQ subtract packedquadword integers
punpckhqdq PUNPCKHQDQ unpack high quadwords
punpcklqdq PUNPCKLQDQ unpack low quadwords
SSE2 Miscellaneous InstructionsThe SSE2 instructions described below provide additional functionality for cachingnon-temporal data when storing data from XMM registers to memory, and provide additionalcontrol of instruction ordering on store operations.
TABLE 3–44 SSE2 Miscellaneous Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
clflush CLFLUSH flushes and invalidates amemory operand and itsassociated cache line fromall levels of the processor'scache hierarchy
lfence LFENCE serializes load operations
maskmovdqu MASKMOVDQU non-temporal store ofselected bytes from anXMM register intomemory
mfence MFENCE serializes load and storeoperations
SSE2 Instructions
Chapter 3 • Instruction Set Mapping 69
TABLE 3–44 SSE2 Miscellaneous Instructions (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
movntdq MOVNTDQ non-temporal store ofdouble quadword from anXMM register intomemory
movnti MOVNTI non-temporal store of adoubleword from ageneral-purpose registerinto memory
movntiq valid only under-m64
movntpd MOVNTPD non-temporal store oftwo packeddouble-precisionfloating-point valuesfrom an XMM registerinto memory
pause PAUSE improves theperformance of spin-waitloops
Operating System Support InstructionsThe operating system support instructions provide functionality for process management,performance monitoring, debugging, and other systems tasks.
TABLE 3–45 Operating System Support Instructions
Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
arpl ARPL adjust requested privilegelevel
clts CLTS clear the task-switchedflag
hlt HLT halt processor
invd INVD invalidate cache, nowriteback
invlpg INVLPG invalidate TLB entry
lar LAR load access rights larq valid only under-m64
lgdt LGDT load global descriptortable (GDT) register
Operating System Support Instructions
x86 Assembly Language Reference Manual • October 201270
TABLE 3–45 Operating System Support Instructions (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
lidt LIDT load interrupt descriptortable (IDT) register
lldt LLDT load local descriptor table(LDT) register
lmsw LMSW load machine status word
lock LOCK lock bus
lsl LSL load segment limit lslq valid only under-m64
ltr LTR load task register
rdmsr RDMSR read model-specificregister
rdpmc RDPMC read performancemonitoring counters
rdtsc RDTSC read time stamp counter
rsm RSM return from systemmanagement mode(SMM)
sgdt SGDT store global descriptortable (GDT) register
sidt SIDT store interrupt descriptortable (IDT) register
sldt SLDT store local descriptortable (LDT) register
sldtq valid only under-m64
smsw SMSW store machine status word smswq valid only under-m64
str STR store task register strq valid only under-m64
sysenter SYSENTER fast system call, transfersto a flat protected modelkernel at CPL=0
sysexit SYSEXIT fast system call, transfersto a flat protected modekernal at CPL=3
verr VERR verify segment for reading
Operating System Support Instructions
Chapter 3 • Instruction Set Mapping 71
TABLE 3–45 Operating System Support Instructions (Continued)Oracle Solaris Mnemonic Intel/AMD Mnemonic Description Notes
verw VERW verify segment for writing
wbinvd WBINVD invalidate cache, withwriteback
wrmsr WRMSR write model-specificregister
64–Bit AMD Opteron ConsiderationsTo assemble code for the AMD Opteron CPU, invoke the assembler with the -m64 commandline option. See the as(1) man page for additional information.
The following Oracle Solaris mnemonics are only valid when the -m64 command line option isspecified:
adcq
addq
andq
bsfq
bsrq
bswapq
btcq
btq
btrq
btsq
cltq
cmovaeq
cmovaq
cmovbeq
cmovbq
cmovcq
cmoveq
cmovgeq
cmovgq
cmovleq
cmovlq
cmovnaeq
cmovnaq
cmovnbeq
cmovnbq
cmovncq
cmovneq
cmovngeq
cmovngq
cmovnleq
cmovnlq
cmovnoq
cmovnpq
cmovnsq
cmovnzq
cmovoq
cmovpeq
cmovpoq
cmovpq
cmovsq
cmovzq
cmpq
cmpsq
cmpxchgq
cqtd
cqto
decq
divq
idivq
imulq
incq
larq
leaq
lodsq
lslq
movabs
movdq
movntiq
movq
movsq
movswq
movzwq
mulq
negq
notq
orq
popfq
popq
pushfq
pushq
rclq
rcrq
rolq
rorq
salq
sarq
sbbq
scasq
64–Bit AMD Opteron Considerations
x86 Assembly Language Reference Manual • October 201272
shldq
shlq
shrdq
shrq
sldtq
smswq
stosq
strq
subq
testq
xaddq
xchgq
xchgqA
xorq
The following Oracle Solaris mnemonics are not valid when the -m64 command line option isspecified:
aaa
aad
aam
aas
boundw
daa
das
into
jecxz
ldsw
lesw
popa
popaw
pusha
pushaw
64–Bit AMD Opteron Considerations
Chapter 3 • Instruction Set Mapping 73
74
Using the Assembler Command Line
This appendix describes how to invoke the assembler from the command line, and details thecommand-line options.
Assembler Command LineYou invoke the assembler command line as follows:
as [options] [inputfile] ...
Note – The Oracle Solaris Studio C, C++, and Fortran compilers (cc(1), CC(1), and f95(1))invoke the assembler with the fbe command. You can use either the as or fbe command on aOracle Solaris platform to invoke the assembler. On an Oracle Solaris x86 platform, the as orfbe command will invoke the x86 assembler. On an Oracle Solaris SPARC platform, thecommand invokes the SPARC assembler.
The as command translates the assembly language source files, inputfile, into an executableobject file, objfile. The assembler recognizes the filename argument hyphen (-) as the standardinput. It accepts more than one file name on the command line. The input file is theconcatenation of all the specified files. If an invalid option is given or the command linecontains a syntax error, the assembler prints the error (including a synopsis of the commandline syntax and options) to standard error output, and then terminates.
The assembler supports macros, #include files, and symbolic substitution through use of the Cpreprocessor cpp(1). The assembler invokes the preprocessor before assembly begins if it hasbeen specified from the command line as an option. (See the -P option.)
AA P P E N D I X A
75
Assembler Command Line Options-a32
Allow 32–bit addresses in 64–bit mode.
-Dname -Dname=defWhen the -P option is in effect, these options are passed to the cpp preprocessor withoutinterpretation by the as command; otherwise, they are ignored.
-{n}H
Enable (-H) or suppress (-nH) generation of the Hardware Capabilities section.
-IpathWhen the -P option is in effect, this option is passed to the cpp preprocessor withoutinterpretation by the as command; otherwise, it is ignored.
-i
Ignore line number information from the preprocessor.
-KPIC
Check for address referencing with absolute relocation and issue warning.
-m
This option runs m4 macro preprocessing on input. The m4 preprocessor is more useful forcomplex preprocessing than the C preprocessor invoked by the -P option. See the m4(1)man page for more information about the m4 macro-processor.
-m64|-m32
Select the 64–bit (-m64) or 32–bit (-m32) memory model. With –m64, the resulting .o objectfiles are in 64-bit ELF format and can only be linked with other object files in the sameformat. The resulting executable can only be run on a 64-bit x86 processor running 64-bitOracle Solaris OS. –m32 is the default.
-n
Suppress all warnings while assembling.
-o outfileWrite the output of the assember to outfile. By default, if –o is not specified, the output filename is the same as the input file name with .s replaced with .o.
-P
Run cpp(1), the C preprocessor, on the files being assembled. The preprocessor is runseparately on each input file, not on their concatenation. The preprocessor output is passedto the assembler.
Assembler Command Line Options
x86 Assembly Language Reference Manual • October 201276
-Q{y|n}
This option produces the “assembler version” information in the comment section of theoutput object file if the y option is specified; if the n option is specified, the information issuppressed.
-S[a|b|c|l|A|B|C|L]
Produces a disassembly of the emitted code to the standard output. Adding each of thefollowing characters to the -S option produces:
■ a - disassembling with address■ b - disassembling with ".bof"■ c - disassembling with comments■ l - disassembling with line numbers
Capital letters turn the switch off for the corresponding option.
-s
This option places all stabs in the ".stabs" section. By default, stabs are placed in"stabs.excl" sections, which are stripped out by the static linker ld during final execution.When the -s option is used, stabs remain in the final executable because ".stab" sections arenot stripped out by the static linker ld.
-UnameWhen the -P option is in effect, this option is passed to the cpp preprocessor withoutinterpretation by the as command; otherwise, it is ignored.
-V
This option writes the version information on the standard error output.
-xchip=processorprocessor specifies the target architecture processor. When there is a choice between severalpossible encodings, choose the one that is appropriate for the stated chip. In particular, usethe appropriate no-op byte sequence to fill code alignment padding, and warn wheninstructions not defined for the stated chip are used.
The assembler accepts the instruction sets for the following recognized -xchip processorvalues:
processor value Target Processor
generic Generic x86
native This host processor.
core2 Intel Core2
Assembler Command Line Options
Appendix A • Using the Assembler Command Line 77
processor value Target Processor
nehalem Intel Nehalem
opteron AMD Opteron
penryn Intel Penryn
pentium Intel Pentium
pentium_pro Intel Pentium Pro
pentium3 Intel Pentium 3.
pentium4 Intel Pentium 4
sandybridge Intel Sandy Bridge
westmere Intel Westmere
amdfam10 AMD FAM10
ivybridge Intel Ivy Bridge
haswell Intel Hawell
-xmodel=[small | medium | kernel]
For -m64 only, generate R_X86_64_32S relocatable type for data access under kernel.Otherwise, generate R_X86_64_32 under small. SHN_AMD64_LCOMMON and .lbcomm supportadded under medium. The default is small.
-Y{d|m},pathSpecify the path to locate the version of cm4defs (-Yd,path) or m4 (-Ym,path) to use.
-YI,pathIndicate path to search for #include header files.
Disassembling Object CodeThe dis program is the object code disassembler for ELF. It produces an assembly languagelisting of the object file. For detailed information about this function, see the dis(1) man page.
Disassembling Object Code
x86 Assembly Language Reference Manual • October 201278
Index
A–a32 option, 76aaa, 32aad, 33aam, 33aas, 33adc, 32add, 32addpd, 63addps, 55addressing, 20addsd, 63addss, 55.align, 22and, 33andnpd, 64andnps, 57andpd, 64andps, 57arpl, 70as, syntax, UNIX versus Intel, 13–14as command, 75.ascii, 22assembler command line, 75assembler command line options, 76–78
B.bcd, 22binary arithmetic instructions, 31bit instructions, 34
bound, 36bsf, 34bsr, 34.bss, 22bswap, 28bt, 34btc, 34btr, 34bts, 35.2byte, 22.4byte, 22.8byte, 22.byte, 22byte instructions, 34
Ccall, 36cbtw, 28clc, 40cld, 40clflush, 69cli, 40cltd, 28cltq, 28clts, 70cmc, 40cmov.a, 28cmova, 28cmov.ae, 28cmovae, 28
79
cmov.b, 28cmovb, 28cmov.be, 28cmovbe, 28cmov.c, 28cmovc, 28cmov.e, 29cmove, 29cmov.g, 29cmovg, 29cmov.ge, 29cmovge, 29cmov.l, 29cmovl, 29cmov.le, 29cmovle, 29cmov.na, 29cmovna, 29cmov.nae, 29cmovnae, 29cmov.nb, 29cmovnb, 29cmov.nbe, 29cmovnbe, 29cmov.nc, 29cmovnc, 29cmov.ne, 29cmovne, 29cmov.ng, 29cmovng, 29cmov.nge, 29cmovnge, 29cmov.nl, 29cmovnl, 29cmov.nle, 29cmovnle, 29cmov.no, 29cmovno, 29cmov.np, 29cmovnp, 29cmov.ns, 30cmovns, 30cmov.nz, 30cmovnz, 30
cmov.o, 30cmovo, 30cmov.p, 30cmovp, 30cmovpe, 30cmovpo, 30cmovs, 30cmovz, 30cmp, 32cmppd, 65cmpps, 56cmps, 38cmpsb, 38cmpsd, 65cmpsl, 38cmpss, 56cmpsw, 38cmpxchg, 30cmpxchg8b, 30comisd, 65comiss, 57.comm, 22command-line options, 76–78comment, 15compiler drivers, 75control transfer instructions, 36cpuid, 41cqtd, 30cqto, 30cvtdq2pd, 66cvtdq2ps, 68cvtpd2dq, 66cvtpd2pi, 66cvtpd2ps, 66cvtpi2pd, 66cvtpi2ps, 58cvtps2dq, 68cvtps2pd, 66cvtps2pi, 58cvtsd2si, 66cvtsd2ss, 67cvtsi2sd, 67cvtsi2ss, 58cvtss2sd, 67
Index
x86 Assembly Language Reference Manual • October 201280
cvtss2si, 58cvttpd2dq, 67cvttpd2pi, 67cvttps2dq, 68cvttps2pi, 59cvttsd2si, 67cvttss2si, 59cwtd, 30cwtl, 30
D-D option, 76daa, 33das, 33.data, 22data transfer instructions, 28dec, 32decimal arithmetic instructions, 32directives, 21dis program, 78disassembling object code, 78div, 32divpd, 63divps, 55divsd, 63divss, 55.double, 22
Eemms, 52enter, 36.even, 22.ext, 22
Ff2xm1, 45fabs, 43fadd, 43faddp, 43
fbe command, 75fbld, 42fbstp, 42fchs, 43fclex, 46fcmovb, 42fcmovbe, 42fcmove, 42fcmovnb, 42fcmovnbe, 42fcmovne, 42fcmovnu, 42fcmovu, 43fcom, 44fcomi, 44fcomip, 45fcomp, 45fcompp, 45fcos, 45fdecstp, 47fdiv, 43fdivp, 43fdivr, 43fdivrp, 43ffree, 47fiadd, 43ficom, 45ficomp, 45fidiv, 43fidivr, 44fild, 43.file, 23fimul, 44fincstp, 47finit, 47fist, 43fistp, 43fisub, 44fisubr, 44flag control instructions, 40fld, 43fld1, 46fldcw, 47fldenv, 47
Index
81
fldl2e, 46fldl2t, 46fldlg2, 46fldln2, 46fldpi, 46fldz, 46.float, 23floating-point instructions
basic arithmetic, 43comparison, 44control, 46data transfer, 42load constants, 46logarithmic
See transcendentaltranscendental, 45trigonometric
See transcendentalfmul, 44fmulp, 44fnclex, 47fninit, 47fnop, 47fnsave, 47fnstcw, 47fnstenv, 47fnstsw, 47fpatan, 45fprem, 44fprem1, 44fptan, 46frndint, 44frstor, 47fsave, 48fscale, 44fsin, 46fsincos, 46fsqrt, 44fst, 43fstcw, 48fstenv, 48fstp, 43fstsw, 48fsub, 44
fsubp, 44fsubr, 44fsubrp, 44ftst, 45fucom, 45fucomi, 45fucomip, 45fucomp, 45fucompp, 45fwait, 48fxam, 45fxch, 43fxrstor, 48fxsave, 48fxtract, 44fyl2x, 46fyl2xp1, 46
Ggas, 13–14.globl, 23.group, 23
H-{n}H option, 76.hidden, 23hlt, 70hyphen (-), 75
I-I option, 76-i option, 76I/O (input/output) instructions, 39.ident, 23identifier, 17idiv, 32imul, 32in, 40inc, 32
Index
x86 Assembly Language Reference Manual • October 201282
ins, 40insb, 40insl, 40instruction, 19
format, 19suffixes, 19
instructionsbinary arithmetic, 31bit, 34byte, 34control transfer, 36data transfer, 28decimal arithmetic, 32flag control, 40floating-point, 42–48I/O (input/output), 39logical, 33miscellaneous, 41MMX, 48–53operating system support, 70–72Opteron, 72rotate, 33segment register, 41shift, 33SIMD state management, 48SSE, 53–61SSE2, 61–70string, 38
insw, 40int, 36into, 36invd, 70invlpg, 70invoking, as command, 75iret, 36
Jja, 36jae, 36jb, 36jbe, 36jc, 36jcxz, 36
je, 36jecxz, 37jg, 37jge, 37jl, 37jle, 37jmp, 37jnae, 37jnb, 37jnbe, 37jnc, 37jne, 37jng, 37jnge, 37jnl, 37jnle, 37jno, 37jnp, 37jns, 37jnz, 37jo, 37jp, 37jpe, 37jpo, 37js, 37jz, 37
Kkeyword, 17–KPIC option, 76
Llabel, 16
numeric, 16symbolic, 16
lahf, 40lar, 70lcall, 37.lcomm, 23ldmxcsr, 59lds, 41
Index
83
lea, 41leave, 38les, 41lfence, 69lfs, 41lgdt, 70lgs, 41lidt, 71lldt, 71lmsw, 71.local, 23lock, 71lods, 38lodsb, 38lodsl, 38lodsw, 39logical instructions, 33.long, 24loop, 38loope, 38loopne, 38loopnz, 38loopz, 38lret, 38lsl, 71lss, 41ltr, 71
M-m option, 76–m64 and –m32 options, 76maskmovdqu, 69maskmovq, 60maxpd, 63maxps, 55maxsd, 63maxss, 55mfence, 69minpd, 63minps, 55minsd, 63minss, 55miscellaneous instructions, 41
MMX instructionscomparison, 51conversion, 49data transfer, 49logical, 51packed arithmetic, 49rotate, 52shift, 52state management, 52
mov, 31movabs, 31movabsA, 31movapd, 62movaps, 53movd, 49movdq2q, 68movdqa, 68movdqu, 68movhlps, 53movhpd, 62movhps, 54movlhps, 54movlpd, 62movlps, 54movmskpd, 62movmskps, 54movntdq, 70movnti, 70movntpd, 70movntps, 60movntq, 60movq, 49movq2dq, 68movs, 39movsb, 31, 39movsd, 62movsl, 39movss, 54movsw, 31, 39movupd, 62movups, 54movzb, 31movzw, 31mul, 32
Index
x86 Assembly Language Reference Manual • October 201284
mulpd, 63mulps, 55mulsd, 63mulss, 55multiple files, on, 75
N–n option, 76neg, 32nop, 41not, 33numbers, 17
floating point, 18integers, 17
binary, 17decimal, 17hexadecimal, 17octal, 17
O-o option, 76operands, 20
immediate, 20indirect, 20memory
addressing, 20ordering (source, destination), 20register, 20
operating system support instructions, 70Opteron instructions, 72options, command-line, 76–78or, 33orpd, 64orps, 57out, 40outs, 40outsb, 40outsl, 40outsw, 40
P-P option, 76packssdw, 49packsswb, 49packuswb, 49paddb, 50paddd, 50paddq, 68paddsb, 50paddsw, 50paddusb, 50paddusw, 50paddw, 50pand, 52pandn, 52pause, 70pavgb, 59pavgw, 59pcmpeqb, 51pcmpeqd, 51pcmpeqw, 51pcmpgtb, 51pcmpgtd, 51pcmpgtw, 51pextrw, 59pinsrw, 59pmaddwd, 50pmaxsw, 60pmaxub, 60pminsw, 60pminub, 60pmovmskb, 60pmulhuw, 60pmulhw, 50pmullw, 50pmuludq, 68pop, 31popa, 31popal, 31popaw, 31popf, 40popfw, 40.popsection, 24por, 52
Index
85
prefetchnta, 61prefetcht0, 61prefetcht1, 61prefetcht2, 61.previous, 24psadbw, 60pshufd, 69pshufhw, 69pshuflw, 69pshufw, 60pslld, 52pslldq, 69psllq, 52psllw, 52psrad, 52psraw, 52psrld, 52psrldq, 69psrlq, 52psrlw, 52psubb, 50psubd, 50psubq, 69psubsb, 50psubsw, 50psubusb, 51psubusw, 51psubw, 51punpckhbw, 49punpckhdq, 49punpckhqdq, 69punpckhwd, 49punpcklbw, 49punpckldq, 49punpcklqdq, 69punpcklwd, 49push, 31pusha, 31pushal, 31pushaw, 31pushf, 41pushfw, 40.pushsection, 24pxor, 52
Q-Q option, 77.quad, 24
Rrcl, 33rcpps, 55rcpss, 55rcr, 34rdmsr, 71rdpmc, 71rdtsc, 71.rel, 24rep, 39repnz, 39repz, 39ret, 38rol, 34ror, 34rotate instructions, 33rsm, 71rsqrtps, 56rsqrtss, 56
S-S option, 77-s option, 77sahf, 41sal, 34sar, 34sbb, 32scas, 39scasb, 39scasl, 39scasw, 39.section, 24segment register instructions, 41.set, 24seta, 35setae, 35setb, 35
Index
x86 Assembly Language Reference Manual • October 201286
setbe, 35setc, 35sete, 35setg, 35setge, 35setl, 35setle, 35setna, 35setnae, 35setnb, 35setnbe, 35setnc, 35setne, 35setng, 35setnge, 35setnl, 35setnle, 35setno, 35setnp, 35setns, 35setnz, 35seto, 36setp, 36setpe, 36setpo, 36sets, 36setz, 36sfence, 61sgdt, 71shift instructions, 33shl, 34shld, 34shr, 34shrd, 34shufpd, 65shufps, 58sidt, 71SIMD state management instructions, 48.size, 24.skip, 24sldt, 71.sleb128, 24smovl, 39smsw, 71
sqrtpd, 63sqrtps, 56sqrtsd, 63sqrtss, 56SSE instructions
compare, 56conversion, 58data transfer, 53integer (64–bit SIMD), 59logical, 57miscellaneous, 60MXCSR state management, 59packed arithmetic, 54shuffle, 57unpack, 57
SSE2 instructionscompare, 64conversion, 66data movement, 61logical, 64miscellaneous, 69packed arithmetic, 62packed single-precision floating-point, 67shuffle, 65SIMD integer instructions (128–bit), 68unpack, 65
statement, 15empty, 15
stc, 41std, 41sti, 41stmxcsr, 59stos, 39stosb, 39stosl, 39stosw, 39str, 71.string, 24string, 18string instructions, 38sub, 32subpd, 64subps, 56subsd, 64
Index
87
subss, 56.symbolic, 25sysenter, 71sysexit, 71
T.tbss, 25.tcomm, 25.tdata, 25test, 36.text, 25.type, 25
U-U option, 77ucomisd, 65ucomiss, 57ud2, 41.uleb128, 25unpckhpd, 65unpckhps, 58unpcklpd, 65unpcklps, 58
V-V option, 77.value, 25verr, 71verw, 72
Wwait, 48wbinvd, 72.weak, 25whitespace, 15wrmsr, 72
Xxadd, 31xchg, 31xchgA, 31-xchip option, 77xlat, 41xlatb, 41-xmodel option, 78xor, 33xorpd, 64xorps, 57
Y–Y{d|m} option, 78-YI option, 78
Z.zero, 25
Index
x86 Assembly Language Reference Manual • October 201288