Workshop on Instruction Enhancement Programme (IEP)

Radio Frequency Lab Manual

by

Indrajit Das

&

Kamlesh Badiyari

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Experiment 1: Oscillator Design

Objective – Design a 2.4 GHz LC Oscillator with the architecture shown in the

figure below.

Figure: LC Oscillator circuit topology

Design Constraints –

1. Lp = 1 nH

2. Oscillation frequency = 2.4 GHz

3. Supply Voltage = 1.2 V

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Design Procedure –

Step1- Calculating Cp:

From the equation,

√

For this design, Cp comes out to be 4.4 pF (as, Lp = 1 nH)

Step2- Estimating Q and Rp of the inductor:

Quality factor (Q) of the inductor depends on the

on the value of inductance and also on the

technology being used.

For a parallel resonator, quality factor is

represented by: Q =

For the inductor that was selected, a Q of 10.76 was obtained and so, Rp = 162Ω.

Step3- Estimating of the transistors:

For sustained Oscillations following condition needs

to be fulfilled:

or,

Concept of Negative resistence:

Two MOSFETs connected in a cross-coupled manner

gives input impedance of -2/gm.

Figure: Inductor and its equivalent loss resistance

Figure: cross coupled transistor pair gives a

negative resistance

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Simulation setup in Cadence Virtuoso

1. DC Analysis – DC analysis is done to check the operating condition of transistors

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Operating condition of all the components can be checked by annotating them on

schematic.

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2. Transient analysis – Transient anlysis setup is as shown in the figure below.

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3. PSS – Periodic Steady State Analysis

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4. Pnoise analysis – to obtain phase noise of the oscillator. For pnoise analysis to

run, PSS must be run simultaneously.

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5. Result – to view the result of any simulation

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OUTPUT WAVEFORMS

1. Transient waveform:

2. Phase noise

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Experiment 2: LNA Design

Objective – Design a wideband resistive shunt feedback LNA. Circuit architecture is

shown in the figure.

Figure: Resistive shunt feedback LNA

The input impedance of this resistive shunt feedback LNA is

LNA Design parameters:

1. Input match (S11)

2. Voltage gain

3. Noise Figure

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Design steps:

step1: choose feedback Resistor (Rf)

The voltage gain of this architecture is approximately equal to Rf/Rs

Rs = 50 Ω for RF source.

To get a linear gain of ~10, Rf is chosen to be 500 Ω.

step2: choosing proper W/L for the MOS

The input impedance Zin depends mostly on the gm values of the MOS

Set the W/L values such that,

Ensure that both the MOS are in saturation.

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Simulation setup in Cadence Virtuoso

1. sp analysis: to obtain port parameters

After doing sp analysis, check S11 to see how much matching is there.

Input port impedance can also be checked. Port impedance can be measured by plotting real part

of Zm from the direct plot window.

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If real part of Zm is much deviated from 50 Ω, then resize the MOSFETs accordingly get better

S11

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2. ac analysis: to obtain voltage gain over the operating frequency range

For doing ac analysis, ensure to give ac signal in the input voltage source, otherwise this

analysis will not work.

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OUTPUT WAVEFORMS

1. input matching: (S11 plot)

2. Voltage gain:

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3. Noise Figure: