Working Inside and Outside of the Processor Inside of the Processor

We are familiar with various addressing schemes Let’s quickly review basic methods

To alter the flow of control through program Altering flow of control involves context switch Context

Information that characterizes Current executing environment of program Includes items such as

Program counter Auto variables Register contents State of globals

Context Switch Change from current context to new one May involve

Saving current one Retrieving old one

Depending upon tasks to be performed Takes varying amounts of time

Can be critical in real time system Let’s look at alternatives at high level first We have 4 basic ways we can proceed through program Sequential

Each instruction executed in sequence

Branch Select one of several branches based upon condition Graphically Type of construct seen in

if else switch or case

Loop

Repeatedly execute set of instructions

DecisionPoint

Forever Until some condition met

Can make decision Before

Code may not be executed After loop

Code executed at least once Type of construct seen in

do or repeat while for

Procedure Leave current context Execute set of instructions Return to context Type of construct seen for

Procedure or subroutine call Interrupt handler Co-routine

Let’s now look at assembly language level Sequential

Code

DecisionPoint

DecisionPoint

ProcedureProcedure Call

code i

code i+1

a = 10;

b = 20;

c = a + b;

clr R0;

addi R0, 10 // puts 10 into R0

clr R1;

addi R1, 20; // puts 20 into R1

add R0, R1; // computes R0 + R1 and puts result into R0

Branch if - else construct

Assume a .. e in registers R1..R5

Loop

Assume a in R2 and i in R3

if (a == b)

c = d + e;

else

c = d - e;

cmp R1, R2 // test if contents of R1 and R2 equal

beq $1 // if equal branch to $1

// $1 is a label created by compiler

sub R4, R5 // compute d - e and put results in d

movea R3, R4 // move results to c

jmp $2 // $2 is label created by compiler

$1: add R1, R2 // compute d + e and put results in d

movea R3, R1 // move results to c $2: ...

while (a < 10)

{

i = i + 2;

a++;

}

br $2 // jump around code

$1: add i, 2 // compute i + 2 put result in i

inc c // auto increment c

cmp c, #0AH // compare c with 10

blt $1 // continue looping

$2: ....

Procedure Call Most complex of flow of control constructs Not more difficult

More involved Will include

Procedures Subroutines Co-routines

Process

We’ll consider from high level Program loaded at address 3000 Code executed until address 3053 Procedure encountered

1. Save return address Several important things to note

Address saved is 3054 Stack gets

Return address Parameters

2. Address of procedure 5000 put into PC 3. Instruction at 5000 begins executing 4. Execution continues until 5053 5. Return encountered

Action similar to call Stack gets

Return values Stack looses

Return address 6. Return Address put into PC 7. Execution continues at 3057 Had procedure call been encountered in procedure F!

Identical process repeated Can be repeated multiple times

Must be aware that stack can overflow If too much pushed on

Begin to loose information Particularly return address

3000 Code

3053 Procedure Call F1

3054 More Code

5000 F1

Procedure Code

5053 Return

CoRoutine Special kind of procedure call Mutual call exchange between

Co-operating procedures Exclusive procedures

Sharing time Mechanics are the same as procedure call

Major difference Conventional procedure executes until end

Unless leaves under extraordinary circumstances Co-routines

Exit and return Throughout body of procedure

Usually under direction Third process or procedure

Graphically process appears as shown Control procedure starts process Context switch determined by

Control procedure External event

Timing signal Internal event

Data value Process continues until procedures completed With each switch

Appropriate information from current context Must be saved

Interfacing to the Outside World

Introduction There are variety of ways and reasons to talk to outside world Consider first kinds of devices we may want to interface to

For embedded systems tasks include • Measuring • Controlling • Interacting with other subsystems • Computing

Accelerators

Procedure 0 Procedure 1

ControlProcedure

Graphics • Communications

Collectively such devices called I/O system Devices we may interact with include

• File systems and storage devices Read and write data

• Network Send and receive data Execute remote procedures

• Keyboard and mouse Interact with computer

• Scanning devices Bring in information

• Display and printing devices Display variety of data

The procedure serves as basis for look at

Interacting with outside world signals Controlling such devices

As we’ve noted embedded systems Designed to perform some task

Performing such a task means interfacing with world outside processor Such tasks may include

Making measurements Controlling motor Running telecommunication system

We are dealing with portions of von Neumann machine Designated

Input and Output Memory

When consider memory mapped I/O

When studying processor input and output We must look at several things

• Data source or destination I/O ports Memory address space

• Nature of the exchange Three types possible

Event Shared variable Message

Note Such exchange also occurs between / among

Tasks within same processor • How I/O procedure invoked

Associated restrictions • Where procedure resides • Protocol for the data exchange • Timing requirements • The physical medium of the exchange

Let’s look at each of these

We’ll begin with the physical medium We call such a medium a bus

Busses

Comprised of Address Control Data

Serial Bit and character Character

Parallel Character Character and Word

Timing

Our exchange with outside world Synchronous

Based upon some timing element

Asynchronous Start of and subsequent transactions temporally independent

Asynchronous Transfer independent of sender / receiver timing

Synchronous Transfer dependent upon sender / receiver timing

Busses a Deeper Look

To understand input and output We must have some understanding of

How we communicate with such devices Three general configurations

Star Ring Bus

Each has certain advantages and disadvantages For all configurations

Two kinds of messages Addressed to single device Multicast

Star Master slave kind of arrangement Device to device communication must go through master Transmit

Device at center directs activities and message exchange With all other devices

Receive Master transmits to desired destinations Failure

If one device or link fails Communication with others continues

Ring Variants are common in communication networks Basis for token ring networks

Embedded processors in an automobile There is typically no bus master Device accepts all messages circulating in ring

If device receiving message ADDRESSED device Message accepted

Else Message passed on o next device

Transmit

Some protocol used to decide who is able to transmit messages To use the bus

Receive All devices can listen for message

Failure Ring usually implemented as two concentric rings

If device fails or ring severed Can repair itself by reconfiguring

Traditional Bus Variation on the star architecture

May or may not be a bus master Simple bus probably one of more common architectures Device interconnection several ways

All can transmit or receive Some transmit or receive only Control bus to all or request / grant configuration

Transmit If bus master

It addresses device Sends information Permits another device to transmit

Else Some protocol used to decide who is able to transmit messages To use the bus

Messages may be • Broadcast • Multicast • Polled

Receive

All devices can listen for message and act on message Failure

Individual device failure will not compromise net

Severed net can prevent communication beyond severed point Elements of a Bus

Whichever scheme we choose Generally must provide three basic functions

• Data • Address • Control

Address

An important question How do we define and establish an address

Initial address for a device Subsequent addresses as device added to system

Current schemes Geographic addressing

Addresses are dynamically assigned during initial configuration Sometimes called enumeration

As new device attached to system and detected Forward capabilities

Serial System Address sent down same path as data Appears first to select receiver

Typically address and data

Have some means to distinguish Bit pattern

Parallel System Address may be handled in two main ways

Transmit over same bus as data Precedes data

Works like serial method only faster Tagged to distinguish from data

Address Data

Either as part of transmission or with control lines

Transmit each over separate bus

Bus may be same size as data Depending upon architecture

May be larger if also used to access memory Smaller is special bus

Transmitted simultaneously with data

Now gain greater throughput

Address and data simultaneously sent In either case

Strobes are essential Identifies when signals on a bus are

Stable and valid Without strobe

No way to tell

Control Number and structure depend upon nature of system Typical signals may include

Read / Write Address / Data present or stable

Address / DataBus

Address Data

Address Strobe

Data Strobe

Address BusAddress i

Data i

Data Strobe

Address i+1

Data i +1

Data Bus

Address Strobe

Clock Where does the clock come from

Separate line Encoded in the data

Transmission Direction Ready or Active Synchronize Reset Power

May or may not be counted as control signal

Data Whether serial or parallel

Data lines carry information we wish to transmit or receive When in parallel

Will typically carry one word For system with 32 bit words

Bus would be 32 bits wide Carry DB0 - DB31

Important to determine which is the MSB and which the LSB

Data Source or Destination Data may be exchanged with external world

Two ways I/O ports Memory address space

I/O Ports Input / Output Ports

Number of lines on processor dedicated Bringing data into processor Sending data out of processor

Direction Lines may be

Input Output Input and Output

Unidirectional lines tend to be static Direction established

Hardware During initialization

Bi-directional lines are dynamic

CPU

I/O Ports

MemoryAddress Space

Direction selected Based upon nature of transaction

Usually grouped in sets of 4 or 8 Direction for entire group set

Memory Address Space

Read from or written to Locations within the processors

Primary memory address space Will elaborate shortly

When discuss memory mapped I/O

Where is the Procedure Although state of embedded systems art changing Presently embedded system limited to

Microcontroller ROM RAM Assorted support chips

Generally do not have luxury peripheral processor Consequently I/O routine resides within

Address space of embedded processor As driver or set of drivers

Associated with the I/O ports

Several primary ways procedure implemented With and without help from processor

• Memory Mapped I/O • Program Controlled I/O • Peripheral Processor

Memory Mapped I/O Basic idea is to for memory and I/O to share the same address space

That is map I/O space into an memory address I/O reads and writes are done to memory addresses

Traditional scheme used in PC Such a scheme places the responsibility of external communication

Onto CPU Simple to implement Adds extra task

Implementation Assign address to each input or output device Some devices may have multiple addresses

Read Write

Such addresses are typically hard coded Using switches or jumpers

Early PCs used such a scheme Expansion led to

Address conflicts IRQ conflicts Limited expansion

Advantage Easy to implement Low cost

Disadvantage Extra burden on CPU Potentially slow

Let’s see how this works Device connected to system

Address bus 80196 Address lines

A0 - A15 Shared with Ports 3 and 4

Appear during address portion of external bus cycle A0 - A15 Muxed with Data in 16 bit mode A0 - A7 Muxed with Data in 8 bit mode

Data Bus

80196 Data lines D0 - D7

Appear on P3 D0 - D16

Appear on P3 and P4

Control Bus 80196

ALE - Address Latch Enable High Going

Printer

Serial Comm

F000

F010

F100Display

I/O Space

F000F010F100

FFFF

Trailing Edge identifies valid address RD - Low Going

Trailing Edge identifies data read WR - Low Going Trailing Edge identifies data read

Decode its address

Respond as appropriate for control signals Address lines usually stored in buffer

As seen in accompanying figure Data lines usually buffered

Prevent interfering with other data signals Accompanying figure illustrates

Bi-directional bus Higher speed systems

Hard constraints Have two unidirectional buses Don’t want cost of turning bus around

Data transfer may be Single word Block of words

For 80196 Must set EA to logic 0 level

EA input to select external memory access Generally hardwired

Recognized during chip reset Must partition address space

Code Data I/O Devices

Code fragments

ALE

Address Out Data In

Address Out Data Out

RD

WR

Address Latch

A0

An-1

Address Strobe

74ls374typ

A0

An-1

D0 D0

Dn-1 Dn-1

direction

C *anAddress = aValue; aValue = *anAddress;

Assembler

LD aReg, anAddress ;Register <- data ST anAddress, aReg ;Register -> an address

Program Controlled I/O

Instructions exist in the CPU instruction set Execute the transfer of data

IN type instruction used to transfer data From

Specified memory location or I/O Port To

Specified memory location or Register

OUT type instruction used to transfer data From

Specified memory location or Register To

Specified memory location or I/O Port

For 80196 These instructions are

LDB breg, baop Code fragments

C ioport1 = aValue;

aValue = ioport1; return (ioport1); Assembler

LDB ioport1, aReg; LDB aReg, ioport1;

Peripheral Processor

As noted with memory mapped I/O CPU must be involved in all transactions

Including detailed timing Can place significant burden on CPU

Peripheral processor scheme Dedicates processor to handle all I/O tasks

Basic architecture appears as Peripheral processor

May or may not be connected to memory Several interface schemes utilized

Various levels of involvement of System Bus CPU Non peripheral devices

Alternative protocols Based upon level of CPU involvement

• CPU send / receive from peripheral processor PP

Manages all I/O Uses bus in bursts during exchange Signals CPU when data available

• CPU tells peripheral processor where to find / put data in memory

PP Exchanges data with memory Manages all I/O Signals CPU when data available Uses bus

In bursts during exchange For duration of exchange

DMA Using address passing and shared buffer

• CPU enables non-peripheral device and peripheral processor to communicate

PP

Printer

DisplayPeripheralProcessor

CPU

Memory

Serial Comm

A03

879

D5E

Exchanges data with device Manages all I/O Signals Device when data available May signal CPU when complete Uses bus

In bursts during exchange For duration of exchange

Advantage

I/O speed independent of CPU Unburdens CPU

Disadvantage Higher cost Complex

Nature of the Exchange Three types possible

Event Shared Variable Message Observe these are abstractions

Within each type Variety of related signals

Exchange may be used Outside world Between tasks within processor

Exchange types Event

Event is change in state signal Usually assumed to be single signal Generally asynchronous to executing process Every occurrence of event

Simultaneously activates Functions procedures to tasks

Linked to it Occurrence of event

May or may not be stored in some way Becomes important issue in real time systems

Acquired in several ways Sampled

One example called polling Arrives in form of asynchronous input

One example called interrupt Processor may or may not respond

Generated Under software control of

I/ O port or line Write to data line accompanied by control signal

Shared Variable Variable may be read or written by multiple

Processors I/O devices

Used to exchange data between asynchronous functions Because no inter process timing constraints

Integrity of data must be respected Such shared data

Represent critical section Protect with

Semaphore Monitor

As we learned earlier with shared data Among tasks and threads

Shared variable(s) may be

• Global Normally discouraged in traditional programming We use such schemes in real time embedded systems

Eliminate cost of passing parameters via stack Here we may designate

A global buffer area into which to store data Pointer to buffer area

• Passed Usually done as pointer to buffer area Passed by task or thread

Wishing to do I/O

Direction

Unidirectional Bi-directional

Modification Read Read/Write

Nature may be Complete word

If in memory space 1 to several bits if in I/O port space Complex data type

Pointer exchanged Message

May be exchanged via Proprietary network One of several standards

Which ever approach used Typically implemented as hierarchy virtual networks

Above the hardware Varying number of software layers or levels

At each level A different language is spoken

Referred to as a protocol The function is to provide services for the level above Relationship

Service provider Service consumer

Entire collection called A network architecture

Set of protocols used by a machine called A protocol stack

Information sent on each level called A message or messages It is possible that message on higher level

Composed of several lower level messages Two major protocol schemes or stacks used

OSI Open Systems Interconnection model Proposed and developed by

Physical Layer

Layer 1 Layer 1Layer 1 Protocol

Layer 2 Layer 2Layer 1 Protocol

Layer n-1 Layer n-1Layer n-1Protocol

Layer n Layer nLayer n Protocol

The International Standards Organization Comprises 7 layer virtual machine TCP /IP

Transmission Control Protocol / Internet Protocol Comprises 5 layer virtual machine Physical and data link layers of OSI

Combined into Host to network layer

When we elect to communicate via either standard We generally integrate a

Commercially available protocol stack

Messages comprise Several complete words

Simple 1 - 2 words transferred

Complex Several blocks of data

Message exchange

Can be viewed as producer - consumer relationship Usually follows some protocol

Start of message Header information Body Error management End of message

Message may be transmitted

Serial / Parallel

Serial Data transferred into out of processor 1 - 2 lines

1 Line May be

Unidirectional Input or output only Half duplex

OSI TCP/IP Physical Host to Network Data Link Network Internet Transport Transport Session Not Present Presentation Not Present Application Application

Bi-directional One direction at a time Controlled by protocol Duplex

2 Lines Data transferred in both directions

Simultaneously Full duplex

Perhaps some control lines

Parallel Usually width of word Transmission

Unidirectional Input or output only

Bi-directional One direction at a time

Timing and Data Exchange Interface can be designed to be synchronous or asynchronous Let’s look first at the asynchronous Asynchronous

No clock Exchanges co-ordinated using some form of handshaking protocol Such protocols can be simple or complex Typical examples

Strobe associated with each data word No acknowledgment of acceptance

Observe Strobe can be of either polarity

Strobe associated with each data word Each data word acknowledged

With return strobe Full handshake

Ready for data Here’s data

Data

Strobe

!Strobe

Data

Strobe

Ack

I’ve got it OK Exchange looks like this

Time from bit transition

Often used in serial protocols Agreed upon

Change in state on data line signals Start of transmission End of transmission

Potential problems Difficult to test Clock noise more difficult to filter out Potentially complex protocol

To identify start / end of transmission

Potential advantages Devices may run at different / differing speed No clock skew on long busses

Synchronous There are several drawbacks of the asynchronous transmission schemes

Extra overhead of control bits Bit clock synchronization scheme less reliable at higher data rates

Problems can be alleviated with synchronous transmission Still must achieve

Bit, character, frame synchronization Frame synchronization usually derived from the former Generally includes clock in control lines Exchanges between sender and receiver

Synchronized to the clock • Directly • Signals derived from the clock

Manchester phase encoding Serial Exchange

Clock either separate or encoded in data Parallel Exchange

Sample Points

Clock one of control lines

Bit Synchronization

Two schemes typically used Encode the clock in the data Re-derive the clock from the data

Encoded Clock

Three different methods generally used

Bipolar Encoding

Binary 0’s and 1’s are represented by Different polarity signals

Each bit cell contains clocking information Observe

Signal returns to zero level after each encoded bit Referred to as return-to-zero RZ signal

Scheme requires 3 distinct signal levels

Manchester Phase Encoding

Binary 0 - high to low signal transition Binary 1 - low to high signal transition Transition in the center of each bit cell

0 → 1 1 → 0 Provides the clock information

Observe Signal does not return to zero level after each encoded bit Referred to as non-return-to-zero NRZ signal

Manchester Differential Encoding

Transition in the center of each bit cell

0 → 1 1 → 0 Provides the clock information

Transition at the start of each bit cell Only if next bit to be encoded is a binary 0

Re-derive the Clock

Use a preamble including sync sequence Done using phase lock loop- PLL Based upon very stable receiver clock PLL used to keep sample clock locked

Signal transitions of incoming signal Data encoded to ensure a sufficient number of signal transitions At each transition sample timing adjusted to ensure

Sampling in center of bit Scheme will tolerate intervals without transitions

Based upon stability of the clock

Bit / Character / Frame Synchronization

Once individual bits are identified

Potential problems All devices must run at same speed Clock skew on long busses

Because of different loading Have propagation delay along bus Clock arriving at different times with respect to data

Along bus Clock noise in system

Potential advantages Easier to test Simpler protocol Easier to stay in sync with data

Interrupts and Polling Once we have decided upon a the physical configuration

Outside world connection Several aspects of exchange remain Will often be interacting with several devices

Must determine How best to share resources

Cannot afford to continually watch device To determine if it

Has some information Is ready to receive (more) information

Data

Clock

Clock

Data

t0

t0

module 0

module n-1

Exactly like we do inside the processor

Several methods by which the is done Polling Interrupts

Let’s examine each Polling

With polling scheme We need a control device

Controller can be either CPU Peripheral Processor

Execution proceeds as follows In the polling loop

Interrogate each external device That may be serviced

Such service may be necessary on several occasions During power up On demand As part of normal flow of

control 1. Send device address 2. Receives response

Response may consist of Single signal Word

State Status

a. If goal to transmit or receive data to device

When device ready received Transfer to appropriate routine Execute transfer Return to polling loop

b. If goal is to collect status Can do so and continue polling other devices Status may include

Self test results Ready condition after power up Availability for additional transfer Data available

Start

Address 1

Address 2

Response 2

Response 1

Service orGet Information

Alternate path

Alternate path

In such loop Control device knows with whom it is communicating

This is important

Problem with polling Control device can do nothing else while polling

Advantage however Process deterministic Time to complete predictable

Interrupt

Goal of interrupt scheme same as that of polled scheme Difference

Control device not dedicated to monitoring external devices External interrupts are going to be hardware based

I/O system may have from 1 to many interrupt lines Each line may be connected to 1 or several devices

Let’s look at the interrupt hierarchy

Single Interrupt Line with Single Device Let’s first examine how single interrupt might work As name suggests

Interrupt signal interrupts foreground activity

Identifying the interrupting device easy Only single device

When interrupt occurs several actions possible Ignore Respond

Ignore Will discuss shortly

Respond Responding to interrupt much like subroutine call Procedure

1. Suspend current process 2. Branch to ISR appropriate to interrupting device 3. Execute routine

4. Resume former process

Single Interrupt Line with Multiple Devices Dealing with multiple devices on single interrupt

Only slightly more complicated

One method of connecting to the interrupt line Illustrated in figure below

Each source uses open collector driver to connect to the interrupt line

Interrupt connected to controller as shown Controller responds with ack

Indicates acknowledge of interrupt Ack is chained through the peripheral devices

If devicei has not generated Passes ack to devicei+1

Else Proceeds with task associated with interrupt

Observe priority determined by Physical proximity to controller

Closest device has highest priority Identifying the Interrupt Source

With multiple sources on single interrupt Dilemma of course

Identifying which device is requesting service Several alternatives available to identify source of interrupt

Polling Vector

Vcc

Device 0

Device 1

Device n-1

Open Collector

ack

interrupt

Device 0 Device 1 Device n-1

Polling

Straight forward Sequence

Interrupt occurs Suspend current task Branch to high level handler

Poll devices to identify Branch to appropriate handler routine

Handle Return

Resume suspended task

Vector With vector scheme Device requesting service

Interrupts When acknowledged

Returns identifier of some sort Can be

Device name Address of service routine

Sequence then proceeds as with polled alternative

Multiple Simultaneous Interrupts With several devices on the same line Must now address question

How to accommodate multiple Simultaneous interrupts Sequential interrupts

Simultaneous Interrupts Must have priority scheme Can be

Physical proximity Assigned

Higher priority device gets serviced first

Sequential Interrupts If second interrupt occurs while handling first

Ignore until finished with first

Assign each device priority If interrupting device has higher priority

Handle in same way Similar to calling subroutine from subroutine

Multiple Interrupt Lines with Single Device on Each

For each line Same as single line with single device

With multiple lines

Must assign priority to each Same as single line with multiple devices

Can manage priority in several ways External hardware Internal hardware Internal software External Hardware

Can use device called priority encoder

For such a device

We assume int0 is the highest priority If Int0 is asserted

Out0 will be asserted If Int0 is not asserted and any other interrupt input, Inti is asserted

Corresponding output Outiwill be asserted If subsequently Int0 is asserted

Out0 will be asserted Processing of Inti is suspended

Int0 processing commences Internal Hardware

Same scheme as described above Implemented in hardware

Priority Encoder

Int 0Int 1

Int n-1

Out 0Out 1

Out n-1

Inside controller chip Internal Software

Same scheme as described above Implemented in software

Inside controller chip

Multiple Interrupt Lines with Multiple Devices on Each For each line

Same as single line with multiple devices

With multiple lines Must assign priority to each Same as single line with multiple devices

Masking Interrupts Masking is process of ignoring interrupt

By preventing propagation of occurrence To interrupt management

Hardware Software

As with other concepts we’ve looked at Can be implemented in

Software or hardware Let’s look at a hardware implementation

Software would implement same idea

An interrupt is Enabled

By placing a logical one on the enable input Disabled

By placing a logical zero on the enable input

Int 0

Int 1

Int n-1

Enab 0

Enab 1

Enab n-1

Interrupt

Observe The interrupt can still happen

Blocked from affecting signal - Interrupt

We could incorporate a priority scheme General term is of the form

ei * ii * !ii+1 * !ii+2 *…. Higher priority interrupts are

Those to the right

How I/O Procedure Invoked

I/O procedure resides in primary memory space As collection of functions

Written to perform some task Invocation can occur in several ways

Observe these are event type signals Polled Loop

If timing on event critical Sit in loop waiting for change in state of some variable

When state change occurs Invoke procedure by giving its name

This is a foreground task

Interrupt Change in state on interrupt line Invokes interrupt process

Generally causes context change to location in memory Contains addresses of all interrupt procedures

Interrupt identified Appropriate procedure selected Procedure invoked by giving its name Return to original context

This is a background task