wilk et al., "high-k gate dielectrics" - stanford university

JOURNAL OF APPLIED PHYSICS VOLUME 89, NUMBER 10 15 MAY 2001

APPLIED PHYSICS REVIEW

High- k gate dielectrics: Current status and materials propertiesconsiderations

G. D. Wilka)

Agere Systems, Electronic Device Research Laboratory, Murray Hill, New Jersey 07974

R. M. Wallaceb)

University of North Texas, Department of Materials Science, Denton, Texas 76203

J. M. AnthonyUniversity of South Florida, Center for Microelectronics Research, Tampa, Florida 33620

~Received 9 November 2000; accepted for publication 19 January 2001!

Many materials systems are currently under consideration as potential replacements for SiO2 as thegate dielectric material for sub-0.1mm complementary metal–oxide–semiconductor~CMOS!technology. A systematic consideration of the required properties of gate dielectrics indicates thatthe key guidelines for selecting an alternative gate dielectric are~a! permittivity, band gap, and bandalignment to silicon,~b! thermodynamic stability,~c! film morphology,~d! interface quality,~e!compatibility with the current or expected materials to be used in processing for CMOS devices,~f!process compatibility, and~g! reliability. Many dielectrics appear favorable in some of these areas,but very few materials are promising with respect to all of these guidelines. A review of currentwork and literature in the area of alternate gate dielectrics is given. Based on reported results andfundamental considerations, the pseudobinary materials systems offer large flexibility and show themost promise toward successful integration into the expected processing conditions for futureCMOS technologies, especially due to their tendency to form at interfaces with Si~e.g. silicates!.These pseudobinary systems also thereby enable the use of other high-k materials by serving as aninterfacial high-k layer. While work is ongoing, much research is still required, as it is clear that anymaterial which is to replace SiO2 as the gate dielectric faces a formidable challenge. Therequirements for process integration compatibility are remarkably demanding, and any seriouscandidates will emerge only through continued, intensive investigation. ©2001 American Instituteof Physics. @DOI: 10.1063/1.1361065#

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I. INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . .5243II. SCALING AND IMPROVED

PERFORMANCE. . . . . . . . . . . . . . . . . . . . . . . . . . .5244III. METAL-INSULATOR-SEMICONDUCTOR

~MIS! GATE STACK STRUCTURES. .. . . . . . . . 5245IV. SCALING LIMITS FOR CURRENT GATE

DIELECTRICS. . . . . . . . . . . . . . . . . . . . . . . . . . . .5247A. Ultrathin SiO2 properties.. . . . . . . . . . . . . . . . . . 5247B. Ultrathin SiO2 reliability. . . . . . . . . . . . . . . . . . . 5248C. Boron penetration and surface preparation.. . . . 5249D. SiOxNy and Si–N/SiO2 dielectrics. . . . . . . . . . . . 5249E. Fundamental limitations. . . . . . . . . . . . . . . . . . . . 5249F. Device structures. .. . . . . . . . . . . . . . . . . . . . . . .5250

V. ALTERNATIVE HIGH-k GATE DIELECTRICS.. 5250A. High-k candidates from memory applications. . 52B. Issues for interface engineering. .. . . . . . . . . . . . 5252C. Recent high-k results. . . . . . . . . . . . . . . . . . . . . .5253

a!G. D. Wilk is formerly of Bell Laboratories, Lucent Technologies; eletronic mail: [email protected]

b!Electronic mail: [email protected]

5240021-8979/2001/89(10)/5243/33/$18.00

Downloaded 11 Apr 2003 to 171.64.106.216. Redistribution subject to A

1. Group IIIA and IIIB metal oxides. . . . . . . . . 52542. Group IVB metal oxides.. . . . . . . . . . . . . . . 52563. Pseudobinary alloys. . . . . . . . . . . . . . . . . . . . 52624. High-k device modeling and transport. . . . . 5265

VI. MATERIALS PROPERTIESCONSIDERATIONS.. . . . . . . . . . . . . . . . . . . . . . .5266

A. Permittivity and barrier height. . . . . . . . . . . . . . . 5266B. Thermodynamic stability on Si.. . . . . . . . . . . . . 5268C. Interface quality. . . . . . . . . . . . . . . . . . . . . . . . . .5269D. Film morphology. . . . . . . . . . . . . . . . . . . . . . . . .5270E. Gate compatibility. . . . . . . . . . . . . . . . . . . . . . . .5271F. Process compatibility. . . . . . . . . . . . . . . . . . . . . .5272G. Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5272

VII. CONCLUSIONS. . . . . . . . . . . . . . . . . . . . . . . . . . .5273

I. INTRODUCTION

The rapid progress of complementary metal–oxidsemiconductor~CMOS! integrated circuit technology sincthe late 1980’s has enabled the Si-based microelectroindustry to simultaneously meet several technologicalquirements to fuel market expansion. These requirements

3 © 2001 American Institute of Physics

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5244 J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony

clude performance~speed!, low static~off-state! power, anda wide range of power supply and output voltages.1 This hasbeen accomplished by developing the ability to performcalculated reduction of the dimensions of the fundameactive device in the circuit: the field effect transist~FET!—a practice termed ‘‘scaling.’’2–4 The result has beena dramatic expansion in technology and communicatimarkets including the market associated with higperformance microprocessors as well as low static-powerplications, such as wireless systems.5

It can be argued that the key element enabling the sing of the Si-based metal–oxide–semiconductor field efftransistor~MOSFET! is the materials~and resultant electri-cal! properties associated with the dielectric employed to ilate the transistor gate from the Si channel in CMOS devifor decades: silicon dioxide. The use of amorphous, thmally grown SiO2 as a gate dielectric offers several key avantages in CMOS processing including a stable~thermody-namically and electrically!, high-quality Si–SiO2 interface aswell as superior electrical isolation properties. In modeCMOS processing, defect charge densities are on the ord1010/cm2, midgap interface state densities are;1010/cm2 eV, and hard breakdown fields of 15 MV/cm are rotinely obtained and are therefore expected regardless odevice dimensions. These outstanding electrical propeclearly present a significant challenge for any alternative gdielectric candidate.

II. SCALING AND IMPROVED PERFORMANCE

The industry’s demand for greater integrated circfunctionality and performance at lower cost requires ancreased circuit density, which has translated into a higdensity of transistors on a wafer.3 This rapid shrinking of thetransistor feature size has forced the channel length anddielectric thickness to also decrease rapidly. As will be dcussed in the next few sections, the current CMOS gateelectric SiO2 thickness can scale to at least 13 Å, but theare several critical device parameters that must be baladuring this process.

The improved performance associated with the scaof logic device dimensions can be seen by considerinsimple model for the drive current associated with a FE1

The drive current can be written~using the gradual channeapproximation! as

I D5W

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whereW is the width of the transistor channel,L is the chan-nel length,m is the channel carrier mobility~assumed con-stant here!, Cinv is the capacitance density associated wthe gate dielectric when the underlying channel is in theverted state,VG andVD are the voltages applied to the trasistor gate and drain, respectively, and the threshold volis given byVT . It can be seen that in this approximation tdrain current is proportional to the average charge acrosschannel~with a potentialVD/2! and the average electric fiel


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(VD /L) along the channel direction. Initially,I D increaseslinearly with VD and then eventually saturates to a maximuwhenVD,sat5VG2VT to yield

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The term (VG2VT) is limited in range due to reliabilityand room temperature operation constraints, since too larVG would create an undesirable, high electric field acrossoxide. Furthermore,VT cannot easily be reduced beloabout 200 mV, becausekT;25 mV at room temperatureTypical specification temperatures~<100 °C! could there-fore cause statistical fluctuations in thermal energy, whwould adversely affect the desired theVT value. Thus, evenin this simplified approximation, a reduction in the channlength or an increase in the gate dielectric capacitanceresult in an increasedI D,sat.

In the case of increasing the gate capacitance, considparallel plate capacitor~ignoring quantum mechanical andepletion effects from a Si substrate and gate!6

C5ke0A

t, ~3!

where k is the dielectric constant~also referred to as therelative permittivity in this article! of the material,7 e0 is thepermittivity of free space (58.8531023 fF/mm), A is thearea of the capacitor, andt is the thickness of the dielectricThis expression forC can be rewritten in terms ofteq ~i.e.,equivalent oxide thickness! and kox ~53.9, dielectric con-stant of SiO2! of the capacitor. The termteq represents thetheoretical thickness of SiO2 that would be required toachieve the same capacitance density as the dielectric~ignor-ing issues such as leakage current and reliability!. For ex-ample, if the capacitor dielectric is SiO2, teq53.9e0(A/C),and a capacitance density ofC/A534.5 fF/mm2 correspondsto teq510 Å. Thus, the physical thickness of an alternatidielectric employed to achieve the equivalent capacitadensity ofteq510 Å can be obtained from the expression

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A dielectric with a relative permittivity of 16 therefore affords a physical thickness of;40 Å to obtainteq510 Å. ~Asnoted above, actual performance of a CMOS gate stack dnot scale directly with the dielectric due to possible quantmechanical and depletion effects.!6

From a CMOS circuit performance point of view, a peformance metric considers the dynamic response~i.e., charg-ing and discharging! of the transistors, associated with a spcific circuit element, and the supply voltage provided to telement at a representative~clock! frequency. A commonelement employed to examine such switching time effecta CMOS inverter.1 This circuit element is shown in Fig. 1where the input signal is attached to the gates and the ousignal is connected to both then-type MOS ~nMOS! andp-type MOS~pMOS! transistors associated with the CMO


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5245J. Appl. Phys., Vol. 89, No. 10, 15 May 2001 Appl. Phys. Rev.: Wilk, Wallace, and Anthony

stage. The switching time is limited by both the fall timrequired to discharge the load capacitance by then-FETdrive current and the rise time required to charge the lcapacitance by thep-FET drive current. That is, the switching response times are given by1

t5CLOADVDD

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and Cj and Ci are parasitic junction and local interconnetion capacitances, respectively. The ‘‘fan out’’ for interconected devices is given by the factor ‘‘F.’’ Ignoring delay ingate electrode response, astGATE!tn,p , the average switching time is therefore

t5tp1tn

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The load capacitance in the case of a single CMOS inveis simply the gate capacitance if one ignores parasitic conbutions such as junction and interconnect capacitanHence, an increase inI D is desirable to reduce switchinspeeds. For more realistic estimates of microprocessorformance, the load capacitance is connected~‘‘fanned out’’!to other inverter elements in a predetermined fashion. Wcoupled with other NMOS/PMOS transistor pairs in the cofiguration shown in Fig. 1, one can create a logic ‘‘NANDgate which can be used to investigate the dynamic respof the transistors and thus examine their performance unsuch configurations. For example, in microprocessor emates, a fan out ofF53 is often employed, as shown iFig. 1.1

One can then characterize the performance of a cir~based on a particular transistor structure! through thisswitching time. To do this, various ‘‘figures of merit’~FOM! have been proposed which incorporate parasiticpacitance as well as the influence of gate sheet resistancthe switching time.8 For example, a common FOM employeis related to Eq.~6! simply by

FOM>1

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In the case where parasitics are ignored, it is easily sthen that an increase in the device drive currentI D results ina decrease in the switching time and an increase in the Fvalue ~performance!. Even in this simple model, howevethe incorporation of parasitic effects, results in the ‘‘claming’’ of FOM improvement, despite an increase in the ga

FIG. 1. Components used to test a CMOS FET technology.VDD and VS

serve as the source and drain voltages, respectively, and are commonNAND gates shown. Each NAND gate is connected to three others resuin a fanout of 3.


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dielectric capacitance. This can be seen in Fig. 2 where vous FOM calculations are plotted as a function of‘‘equivalent oxide thickness,’’teq, as described earlier.

Each FOM calculation shown in Fig. 2 correspondsspecific assumptions on the values of parasitic capacitaand gate sheet resistance, as indicated~gate length is keptconstant in this analysis!. Important aspects such as gate iduced drain leakage and reliability are ignored in this simmodel.1 Nevertheless, the result of the FOM calculatioshown in Fig. 1 indicates that tradeoffs on all aspects oftransistor design and scaling, including parasitics, mustcarefully considered in order to increase the circperformance.8

III. METAL–INSULATOR–SEMICONDUCTOR „MIS…GATE STACK STRUCTURES

Figure 3 provides the reader a schematic overview ofvarious regions associated with the gate stack of a CMFET ~regions are separated simply to clarify the followindiscussion!. The gate dielectric insulates the gate electro~gate! from the Si substrate. Gate electrodes in modCMOS technology are composed of polycrystalline Si~poly-Si! which can be highly doped~e.g. by ion implantation! andsubsequently annealed in order to substantially increaseductivity. The selection of the dopant species and concen

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FIG. 2. FOM as a function of equivalent oxide thickness,teq. Parasiticcapacitances and resistances result in transistor design tradeoffs to optperformance.

FIG. 3. Schematic of important regions of a field effect transistor gate st


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FIG. 4. Energy-band diagrams and associated hifrequencyC–V curves for ideal MIS diodes for~a!n-type and ~b! p-type semiconductor substrates. Fthese ideal diodes,V50 corresponds to a flatband condition. For dielectrics with positive (1Qf) or negative(2Qf) fixed charge, an applied voltage (VFB) is re-quired to obtain a flatband condition and the corrspondingC–V curve shifts in proportion to the fixedcharge.~after Refs. 9 and 10!.

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tion permits the adjustment of the poly-Si Fermi level feithernMOS orpMOS FETs. Metals can also be used asgate electrode, and, in fact, are commonly used for evation of capacitor structures. Work is underway to find suable metal gates for CMOS~see Sec. VI E!.

The interfaces with either the gate or the Si channelgion are particularly important in regard to device perfomance. These regions,;5 Å thick, serve as a transition between the atoms associated with the materials in theelectrode, gate dielectric and Si channel. As will be dcussed, these interface regions can alter the overall captance of the gate stack, particularly if they have a thicknwhich is substantial relative to the gate dielectric. Additioally, these interfacial regions can be exploited to obtainsirable properties. The upper interface, for example, canengineered in order to block boron outdiffusion from thep1

poly-Si gate. The lower interface, which is in direct contawith the CMOS channel region, must be engineered to pmit low interface trap densities~e.g. dangling bonds! andminimize carrier scattering~maximize mobility! in order toobtain reliable, high performance.

It is instructive to consider the band diagrams for tMIS structures discussed in this review. Figure 4 showsenergy-band diagrams for ideal MIS diode structures us~a! n-type and~b! p-type semiconductor substrates.9,10 Forthese ideal structures, atV50 applied voltage on the metagate, the work function difference between the metal asemiconductor,FMS, is zero

FMS5FM2S x1Eg

2q2CBD50; n-type


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FMS5FM2S x1Eg

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whereFM is the metal work function,x is the semiconductorelectron affinity,Eg is the semiconductor band gap,FB is thepotential barrier between the metal and dielectric, andcB isthe potential difference between the Fermi levelEF and theintrinsic Fermi level,EI . Under these conditions, the energbands are flat across the structure as shown in Fig. 4 anV5VFB50, whereVFB is the flat band voltage~i.e., the volt-age required to bring the Fermi levels into alignment!. Amore typical case is that the Fermi levels of the electrodesubstrate are misaligned by an energy difference, and a vage (VFBÞ0) must be applied to bring the Fermi levels inalignment.

Many dielectrics exhibit a fixed charge (Qf), however,resulting in a required applied voltageV5VFBÞ0 to achievea flat band condition. The amount of fixed charge canrelated to the measuredVFB value by the expression9

VFB5FMS6Qf /Cacc, ~9!

where Cacc is the measured capacitance in accumulatiThus, a value for fixed charge densityQf can be determinedfrom measured values ofVFB , FMS and Cacc. The sign ofthe fixed charge is also important, as negative fixed chacorrelates with the plus sign in Eq.~9!, and positive fixedcharge correlates with the minus sign. These expressionsbe discussed further in Sec. V C 2.

The source of such fixed charge, often thoughnot alwayspositive, is thought to originate from the detailed bondingthe atoms associated with the dielectric near the dielec


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semiconductor interface. Several proposed explanationsthe cause of the observed fixed charge will be discusseSec. V C 2. Figure 4 shows that for positiveQf , a negativeshift in the VFB from ideal conditions~whereV50! is re-quired for bothn-type andp-type MIS structures. Similarlya positiveVFB is required for negativeQf .

Most of the alternate dielectric candidates examineddate appear to have a substantial amount of fixed chawhich could present significant issues for CMOS applitions. Given the scaling limitations on applied voltages dto power consumption, shifts in theVFB value are undesir-able and must be minimized. In some applications, biasthe substrate to compensate for the fixed charge hasproposed.5 Moreover, a reproducibleVFB ~correspondinglyVT for transistors! value is also required for stable, reliabtransistor operation. Thus, hysteretic changes in theVFB fromvoltage cycling of less than 20 mV are often required.

Some dielectrics which incorporate aluminum, howevthus far suggest that a negative fixed charge is present. Ibeen recently proposed to combine Al ions with some alnate dielectric candidates in order to compensate posand negative fixed charges to achieve a neutral state oleast, minimize such fixed charge effects.11 If fixed charge isdetermined to be large and difficult to minimize and contin high-k dielectrics, it will be a significant issue for obtaining the desired device performance on bothnMOS andpMOS transistors. The magnitude of measuredVFB shifts formany alternate dielectrics will be discussed later.

IV. SCALING LIMITS FOR CURRENT GATEDIELECTRICS

The previous sections outlined the need to scale oxthicknesses to improve performance. The next two sectdescribe the present understanding in the field regardinglimits of scaling current gate dielectric materials, SiO2 andSi-oxide-nitride variations, for CMOS. Issues include baoffset, interfacial structure, boron penetration and reliabilBeyond this scaling limit, another material will be requireas the gate dielectric to allow further CMOS scaling.

A. Ultrathin SiO 2 properties

Experiments and modeling have been done on ultraSiO2 films on Si, as a way to determine how the SiO2 bandgap or band offsets to Si change with decreasing fithickness.12–15 In the study by Mulleret al.,12 electron en-ergy loss spectroscopy~EELS! was carried out on 7–15 ÅSiO2 layers on Si. It was found that the density of states~asmeasured by the oxygenK-edge in EELS, with a probe resolution ,2 Å! transition from the substrate into the SiO2 layerindicated that the full band gap of SiO2 is obtained after onlyabout two monolayers of SiO2. This indicates that within twomonolayers of the Si channel interface, oxygen atoms dohave the full arrangement of oxygen neighbors and therecannot form the full band gap that exists within the ‘‘bulkof the SiO2 film.


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An earlierab inito model by Tanget al.13 of extremelythin SiO2, which was modeled as a modified betcristoballite phase, showed an important result, in thatband gap of SiO2 did not begin to decrease until there wefewer than three monolayers of oxide. Moreover, estimaof the changes in the associated conduction and valanceoffsets for these systems indicated that a minimum of 7 Å ofSiO2 is required to obtain bulk properties. The recent fiprinciples study by Neatonet al.14 determined that the locaenergy gap in SiO2 is directly related to the number of Osecond nearest neighbors, for a given O atom. Thelast rowof O atoms~next to the Si substrate! by definitioncannothave the full six nearest neighbor O atoms. The secondof O atoms from the Si interface is thus the first layer ofatoms that have the required six second-nearest neighbatoms. The distance required to obtain the full band gapSiO2 at each interface is therefore given by 1.6 Å~the spac-ing of one Si–O bond length! 12.4 Å ~the distance betweenneighboring O atoms is 2.7 Å, but this is variable becauseSi–O bond bending. The distance is typically in the ran;2 to 2.4 Å!. The thickness at each interface required for tfull SiO2 band gap is therefore;3.5–4.0 Å. Counting bothinterfaces, the total thickness of 7–8 Å is required, in agrment with Tanget al.13 and with the experiment.12 Theseresults set anabsolutephysical thickness limit of SiO2 of 7Å. Below this thickness, the Si-rich interfacial regions frothe channel and polycrystalline Si gate interfaces usedMOSFETs overlap, causing an effective ‘‘short’’ through thdielectric, rendering it useless as an insulator.

The agreement between the experiment and simulain these cases indicates that the inherent band gap of2remains intact, even down to only a few monolayers of mterial. Other important properties of SiO2 have been reportedin the ultrathin, sub-20 Å regime, such as the conductband offsetDEC to Si @using x-ray photoelectron spectrocopy ~XPS!#,16 the tunneling electron effective massm*~from tunnelingI –V measurements!,17 and the photoelectronattenuation length.18 These measurements have further deonstrated very little change in fundamental SiO2 propertiesbetween bulk and ultrathin sub-20 Å films.

The apparent robust nature of SiO2, coupled with indus-try’s acquired knowledge of oxide process control, hhelped the continued use of SiO2 for the past several decadein CMOS technology. As experimental evidence of the ecellent electrical properties of such ultrathin SiO2 films, ithas been demonstrated that transistors with gate oxidethin as 13–15 Å continue to operate satisfactorily.19–24 Al-though high leakage current densities of 1–10 A/cm2 ~atVDD! are measured for such devices,25 transistors intendedfor high-performance microprocessor applications can stain these currents. As first reported by Timpet al.20–22scal-ing of CMOS structures with SiO2 gate oxides thinner thanabout 10–12 Å results in no further gains in transistor drcurrent. This result has been subsequently and independreported by other groups, thus 10–12 Å could serve apractical limit for reducing the SiO2 thickness.23,24,26


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In contrast to the high performance microprocessor mket, the rapidly growing market of low-power applicationrequires transistors with much lower (;1023 A/cm2) leak-age currents.5 This is illustrated in Fig. 5, where the curredensity and standby power consumption are plotted afunction of gate voltage. The curve for 15 Å oxide is bason measured values,17 but the curve for a high-k film ismeant to show the potential reduction in leakage currenta high-k dielectric with the sameteq value. Depending on thespecific materials and conditions, leakage current reducmay be less than shown. It is clear that a gate dielectric wa permittivity higher than that of SiO2 is required to meetlow-power application requirements.

B. Ultrathin SiO 2 reliability

An equally important issue regarding ultrathin SiO2 gateoxides has been understanding and predicting oxide reliaity. Considerable debate existed over whether SiO2 gate ox-ides ,22–27 Å thick would exhibit the stringent ten yereliability criteria,27 which is required for CMOS devicesThe first report of a sub-20 Å SiO2 gate oxide to meet reli-ability requirements was given by Weiret al.,25 where a 16Å oxide was shown to have reliability projections at 1.6operation for greater than ten years. This is much thinthan projected even three to five years ago.28,29 The highreliability of ultrathin oxides suggests that there is nointrin-sic ~i.e., not limited by intrinsic defects or thickness varitions! reliability limitation to SiO2 layers at least down tothicknesses of about 16 Å. In fact, more recent projectiindicate that oxides down to 14 Å~as measured by ellipsometry! at 1.4 V operating voltage will meet ten year reliabilirequirements.30 Several independent groups have alsocently reached similarly encouraging reliability projectiofor such thin SiO2 gate oxides.26,31 Otherextrinsicreliabilityfactors, however, such as particles or contaminants, costill yield an ultimately poorer oxide reliability.

Part of the difficulty in making reliability projectionsarises from the difference between test conditions and oating conditions. It is clearly not feasible to test individudevices for ten years prior to product incorporation, thus te

FIG. 5. Power consumption and gate leakage current density for awhich has a 15 Å thick SiO2 gate dielectric compared to the potential rduction in leakage current by an alternate dielectric exhibiting the sequivalent oxide thickness. Assumes at total gate area of 0.1 cm2.


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ing must be ‘‘accelerated’’ at higher voltages and tempetures than are actually experienced by typical devices. Ming reliability projections from accelerated to actuconditions requires proper scaling for area~from one devicearea to an entire chip area!, voltage, temperature, and thfailed fraction of devices.27,32 Recent results by Stathiet al.,31 Weir et al.,25 and Nicollian et al.33 show that ex-trapolations of reliability factors, such as the critical defe~trap! density, with voltage scaling changes dramaticallylower voltages, such as those used for testing oxides,20 Åthick. This realization of the change in voltage scaling bhavior at low voltages is the largest factor contributing to timproved reliability projections described earlier. In addtion, improved macroscopic oxide uniformity across the wfer and wafer-to-wafer has also been shown to give maccurate reliability projections.25,34 This analysis shouldnotbe misinterpreted as meaning that the oxide reliabilityitselfis improved. Rather, the reliabilityprojectionbecomes moreaccurate~regardless of whether the projection is for goodpoor oxide reliability! with higher macroscopic oxideuniformity.35 Improving microscopic oxide uniformityshould further produce more accurate reliability projectioaccording to simulation.36 It has also been demonstrated thmaking reliability measurements on a large numbersamples is important for obtaining better breakdown statics and accurate projections.34

A fundamental mechanism for oxide breakdown in thultrathin SiO2 regime was first reported by DeGraevet al.37,38as a percolation model. This model describes ultthin oxide breakdown as the buildup of many ‘‘defectswithin the SiO2 layer, where after a certain amount of stre~either constant voltage or constant current through the oxat a given temperature!, a complete path of defects formacross the oxide thickness.37 This point defines breakdown ofailure of the oxide. While there is general agreement onpercolation model for oxide breakdown, the defects whact as precursors to breakdown are not defined or speciThe mechanism which leads to the creation of these defis under debate, and has been proposed as an anodeinjection model36,39 and a hydrogen release model.40,41

It is also important to distinguish between previousreported leakage current projections by simulation for oxthicknesses measured in accumulation, and the presentlcepted methods.25,31,33 Extrapolated leakage current versgate oxide thickness data from three to five years agovaluable at the time, when sufficient data for oxides,16 Åwas not available. Caution should be used, however, wreferring to such extrapolations now,42 as data from morerecent measurement methodology must be adopted for uscomparisons. Much of the understanding for ultrathin oxidhave come about only in the past five years, despite decof research on SiO2. This suggests that understanding treliability and failure mechanisms in high-k dielectrics willrequire significant effort, especially if any material is to rplace SiO2 within five years, as most roadmaps suggest.

C. Boron penetration and surface preparation

In addition to leakage current increasing with scaled oide thickness, the issue of boron penetration through the

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ide is a significant concern. The large boron concentragradient between the heavily doped poly-Si gate electrothe undoped oxide and lightly doped Si channel causes bto diffuse rapidly through a sub-20 Å oxide upon thermannealing, which results in a higher concentration of boin the channel region. A change in channel doping thcauses a shift in threshold voltage, which clearly altersintended device properties in an unacceptable way.43 As willbe discussed in the next section, incorporating nitrogenthe oxide can greatly reduce boron diffusion.

Some approaches to enhance performance have alscused on surface preparation as a way to provide a flamore uniform Si interface in attempts to minimize electrchannel mobility degradation~due to scattering at the interface! and gate leakage.44,45 Growing or depositing sub-15 Åoxides has also been investigated as a potential meanproducing high-quality, reproducible and uniform gate oides, either for use as the gate dielectric or as the botlayer of a dielectric stack.46,47 Obtaining high-quality oxidesin this thickness regime is challenging, because intrinsic phole formation has been reported in ultrathin SiO2 films.48–50

Perhaps the most significant benefit resulting fromincorporation of an alternative gate dielectric with a relatpermittivity higher than SiO2 is the dramatic reduction in thoff-state tunneling~leakage! current which is observed indevices using ultrathin SiO2 gate dielectric films. Thus, thearea of alternative gate dielectrics has gained considerattention recently because technology roadmaps predicneed for a sub-20 Å Si-oxide gate dielectric for sub-0.1mmCMOS.4,5

D. SiOxNy and Si–N ÕSiO2 dielectrics

The concerns regarding high leakage currents, bopenetration and reliability of ultrathin SiO2 have led to ma-terials structures such as oxynitrides and oxide/nitride stafor near-term gate dielectric alternatives. These structuprovide a slightly higherk value than SiO2 ~pure Si3N4 hask;7! for reduced leakage~since the film is physicallyslightly thicker!, reduced boron penetration and better reability characteristics.51–53The addition of N to SiO2 greatlyreduces boron diffusion through the dielectric, and has bshown to result from the particular Si–O–N network bond-ing formed in silicon nitride and oxynitride.54,55Furthermore,small amounts of N~;0.1 at. %! at or near the Si channeinterface have been shown to improve device performanc56

Larger amounts of N near this interface degrade deviceformance, as discussed later.

The simplest approach is to use a pure nitride layer anear the channel interface, but device performance is tcally degraded in these structures. Recent work using remplasma enhanced chemical vapor deposition~PECVD! to de-posit Si-nitride directly on the Si channel57 resulted in poorpMOS performance, with significant degradation of chanmobility and drive current. This degradation is attributedseveral factors, including excess charge of pentavalent ngen atoms, a high defect density arising from bonding cstraints imposed at the interface58 ~which causes increasechannel carrier scattering!, and from the defect levels in thSi-nitride layer which reside near the valence band of Si


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contrast, improved electrical properties have been obtaiby using various oxynitrides. Yang and Lucovsky demostrated that an oxynitride alloy with a 1:1 ratio of SiO2:SixNy

can achieve teq,17 Å with a leakage current o;1023 A/cm2 at 1.0 V bias.56 This leakage current is;1003 lower than that for a pure SiO2 layer of the samethickness, and the leakage reduction arises from botphysically thicker film and from a small amount of N at thchannel interface. Songet al.59 have also shown that a propechoice of thermal processing steps using a NO passivalayer, SixNy deposition with SiH4 and NH3 and further an-neals in NH3 and N2O can achieve oxynitride layers witteq518 Å and a leakage current density of 1024 A/cm2 at 1.0V bias. Guo and Ma60 have reported results with jet vapodeposited nitrides demonstratingteq515 Å with a leakagecurrent density ofJ;1024 A/cm2 at 1.0 V.

Despite these encouraging results from a varietydeposition and growth techniques, scaling with oxynitridnitrides appears to be limited toteq;13 Å.61 Below this, theeffects of gate leakage, reliability or electron channel mobity degradation will most likely prevent further improvements in device performance. According to the most recindustry roadmaps, SiOxNy and SixNy /SiO2 dielectrics rep-resent current three year near-term solutions for scalingCMOS transistor.5

E. Fundamental limitations

Despite the current efforts with SiO2, oxynitrides andeven high-k gate dielectrics, several potential fundamenlimitations could seriously threaten the continued scalingall gate dielectrics, regardless of the material.26 First, theelectrical thickness of any dielectric is given by the distanbetween the centroids of charge in the gate and the substThis thickness, typically denoted byteq, therefore includesthe effective thickness of the charge sheet in the gate andinversion layer in the substrate~channel!. These effects canadd significantly to the expectedteq derived from the physi-cal thickness of the dielectric alone.6 Depletion in the poly-Sigate electrode arises from the depletion of mobile chacarriers in the poly-Si near the gate dielectric interface, pticularly in the gate bias polarity required to invert the chanel. The result is often that;3–4 Å in the poly-Si electrodenearest to the gate dielectric interface essentially behalike intrinsic Si, which adds;3–4 Å to the effective dielec-tric thickness~rather than acting as a metal with a Fermi sof electrons right up to the dielectric interface!. In the bestcase, the electrode depletion region can be reduced to;1–2Å for degenerately doped poly-Si electrode right up to tinterface, but this is difficult to obtain.

The nature of the inversion charge layer in the Si sustrate~or channel, for transistors! contributes about 3–6 Å tothe effective teq value, thus even for ideal, degeneratedoped poly-Si gates, it is difficult to realize an overallteq

,10 Å in MOSFETs using current process technologMetal gates offer a possible solution to the gate depletproblem, but the addition of 3–6 Å to theteq value from theSi channel will remain. We note that most of the highkdielectrics discussed later in this review are measuredcapacitors and transistors with metal gates. Although m


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gates are convenient for obtaining properties of the dietric, current CMOS technology does not use metal gaTherefore, for a given high-k dielectric, any realistic deviceusing current CMOS processing techniques should exhibteq value 4–8 Å larger than that reported in this review~ex-cept where poly-Si gates are noted as being used, and wno quantum mechanical correction has been performed!.

Second, the ideal scaling scenario is one in whichoperating voltage and transistor dimensions are reducethe same factor, thus maintaining a constant electric fiacross the gate dielectric for a given technology nodepractice, however, the feature dimensions have been redmore rapidly than the operating voltage, thereby causinrapidly increasing electric field across the gate dielectric. Tcontinually decreasingteq value for scaling CMOS also increases the effective electric field in the channel region. Tincreased electric field pulls the carriers in the channel cloagainst the dielectric interface, which causes increasednon scattering of more confined carriers and therebycreases the channel carrier mobility. At very high electfields in the channel, such as would exist forteq,10 Å, in-terface roughness scattering further reduces carrier mobThus, for teq,10 Å, the combination of these deleterioueffects may result in not only reducing the expected permance increase for a given increase in gate capacitancemay indeed evendecreasedevice performance at fixed supply voltage. If this effect on channel mobility is in fact reaized, then it may be the case thatno dielectric will be accept-able in the requiredteq range~since this effect depends onlon teq, not on the material!.

F. Device structures

In addition to ongoing work in scaling gate dielectricthere is also a substantial amount of research beingducted toward obtaining a device structure for CMOS, suthat the demand for scaling SiO2 or oxynitrides~and lithog-raphy! will be somewhat alleviated. In particular, efforhave been focused on structures such as vertransistors,62–65 and double gate planar transistors.66–68 Thepremise of double gate transistors arises from the potentiaachieving nearly twice the drive current over a planar, bCMOS device for a given channel length. Alternatively,nearly equal drive current could be produced while usinSiO2 layer that is twice the thickness as that required inplanar geometry~and thereby meet roadmap performancequirements with a much thicker gate oxide!. This potentialgain from a double gate device is explained simply byfact that there are two parallel, aligned channels operasimultaneously, compared to one channel in a standard,nar bulk device.

One particularly promising vertical transistor uses a vtical replacement gate~VRG! structure,62 where standardCMOS processes are used in an innovative way to remthe lithography constraint for defining the gate length.stead, a deposited oxide layer thickness defines thelength, which can thus be easily controlled below 50 nThis dummy oxide layer can then be etched away, followby growth and deposition of the gate oxide and poly-Si gelectrode, respectively. Figure 6 shows a cross-secti


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transmission electron microscopy~TEM! image of a VRGdevice with parallel 50 nm gate lengths and 25 Å gate oxi~as measured by ellipsometry! and a single crystal, epitaxially grown Si body.62 As an example of the potential foincreased performance with thicker gate oxides, VRG trsistors with 100 nm gate lengths, 25 Å gate oxides, aoperating voltage 1.5 V have shown an 80% increase in dcurrent63 compared to that required by the SIA Roadmap~atthe same off current! using much thinner, sub-20 A oxidesHigh-performance planar devices reported to date hshown only about 20% increase in drive current comparethat of the roadmap, under comparable operatconditions.23,24 For 50 nm gate length devices and 1.0operation, VRG transistors have been demonstrated to mthe requirements of the roadmap, whilestill using 25 Å gateoxides.63 In contrast,no reported planar CMOS devices tdate have been able to even approach the drive currentoff-current roadmap requirements for 50 nm gate length,V operation.

These device approaches to stave off CMOS scalingcontinue in parallel with investigations into high-k gate di-electrics. One of these structures may ultimately prove toa viable replacement for the planar, bulk CMOS transisand retard the need to scale SiO2 gate oxides. Most devicestructures under consideration therefore will not immediatsuffer from the limitations discussed in the previous sectibecause a thicker gate oxidereducesthe effects of dopantdepletion in the poly-Si gate electrode, as well as reduceselectric field present in the channel region. Since theseeterious effects become amplified as the gate oxide thickndecreases, even device structures would eventually sufrom these degradation mechanisms, but in the meantwould afford more time to find other solutions to these prolems. In this case, high-k dielectrics can be combined witthese device structures to further improve performancepower consumption.

V. ALTERNATIVE HIGH- k GATE DIELECTRICS

As an alternative to oxide/nitride systems, much wohas been done on high-k metal oxides as a means to provida substantially thicker~physical thickness! dielectric for re-duced leakage and improved gate capacitance. In the seto find suitable high-k gate dielectrics for use beyond oxyntride systems, several approaches have been used in fab

FIG. 6. Cross-sectional TEM image of a vertical replacement gate transiwith a 50 nm gate length and 25 ÅSiO2 gate oxide~as measured by ellip-sometry! ~see Ref. 63!. © 2000 IEEE, reprinted with permission from IEEE


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ing potential materials candidates. The following sectionsview the current status of work in this field. We also descrthe materials properties considerations that are necessardetermining the best high-k candidate to replace SiO2 as thegate dielectric for CMOS. It is important to note that wenot compile all of the relevant, measured electrical aphysical characteristics on high-k materials into one tableAlthough a table format can be helpful for organizationpurposes, at the present time for high-k gate dielectrics, it istoo cumbersome~and potentially misleading! to attempt toprovide all of the proper caveats~e.g., leakage current valuefor the same material system can vary widely dependingsurface preparation, deposition method and conditions,electrode type, bias voltage ramp rate, stated bias for a gcurrent~J@Vbias51 V, or VFB11 V, etc.!.

A. High- k candidates from memory applications

Many of the materials initially chosen as potential altenative gate dielectric candidates were inspired by memcapacitor applications42 and the resultant semiconductmanufacturing tool development infrastructure.

The most commonly studied high-k gate dielectric can-didates have been materials systems such as Ta2O5,

68–78

SrTiO3,79–84and Al2O3,

85–95which have dielectric constantranging from 10 to 80, and have been employed mainlyto their maturity in memory capacitor applications. With texception of Al2O3, however, these materials are not thermdynamically stable in direct contact with Si~this thermody-namic stability is not a requirement for memory capacitosince the dielectric is in contact with the electrodes, whare typically nitrided poly-Si or metal!. An excellent andthorough review on the Ta2O5 system, for both memory capacitor and transistor applications, has been given by Chliere et al.77 The Ta2O5 system is known to exhibit Frenkel–Poole and Schottky transport mechanisms, depending onpolarity, under typical voltage bias conditions. The mecnisms for relaxation or transient current of Ta2O5 have re-cently been attributed to a defect band near the conducband in thin Ta2O5 films, which allows ac transient conduction leakage that follows a widely observed power ladecay.78

Interfacial reaction, seen in Fig. 7, has been observedthe case of Ta2O5 on Si,75 as is expected based on thermdynamic arguments discussed later and in agreementprevious work in dynamic random-access memory capacapplications.76 As evidenced by these studies, the earlimentioned metal oxidesrequire that both the gate electrodand the channel interfaces be modified to limit the amounreaction.

Interface engineering schemes have been developeform oxynitrides and oxide/nitride reaction barriers betwethese high-k metal oxide materials and Si in an attemptprevent or at least minimize reaction with the underlyiSi.69–74The passivating properties of such reaction barrierwidely reported.94 In most cases, this amounts to furthscaling the approaches used to form oxynitrides, discussethe previous section. These barrier layers have been showreduce the extent of reaction between the high-k dielectric


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and Si, as well as to help maintain a high channel carmobility.

It is important to note, however, that using an interfaclayer of SiO2 or another low permittivity material, will limitthe highest possible gate stack capacitance, or equivalethe lowest achievableteq value@see Eq.~4!#. In addition, theincreased process complexity for the deposition and conof additional ultrathin dielectric layers, as well as scalabilto later technology nodes, remains a concern.

This effect of reduced capacitance can be seen by nothat when the structure contains several dielectrics in sethe lowest capacitance layer will dominate the overallpacitance and also set a limit on the minimum achievableteq

value. For example, the total capacitance of two dielectricseries is given by

1/Ctot51/C111/C2 , ~10!

where C1 and C2 are the capacitances of the two layerespectively. If one considers a dielectric stack structure sthat the bottom layer~layer 1! of the stack is SiO2, and thetop layer ~layer 2! is the high-k alternative gate dielectricEq. ~4! is simplified ~assuming equal areas! to

teq5tSiO21~kox /khigh-k!thigh-k . ~11!

It is clear from Eq.~11! that the minimum achievableequivalent oxide thickness@defined asteq in Eq. ~11!# willneverbe less than that of the lower-k ~in this case pure SiO2!layer. Therefore, much of the expected increase in the gcapacitance associated with the high-k dielectric is compro-mised. The implications of current transport through sustacked structures will be considered further later.

The largest benefit of using SiO2 as the underlayer of astack ~at the Si channel interface! is that the unparalleledquality of the SiO2– Si interface will help maintain a highchannel carrier mobility. The prospect of using such Si2

interface layers was examined by Kizilyalli and Roy.70,71 Inthat work, a Ta2O5 film was sandwiched between SiO2 layerslocated at the substrate and gate~poly-Si! interfaces. TheSiO2/Si substrate interface layer was formed by a low pr

FIG. 7. Reaction at the Ta2O5 /Si interface is observed resulting in thformation of a thin SiO2 layer ~see Ref. 75!.


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sure~850 mTorr! thermal anneal at 850 °C in O2, resulting ina ;10-Å-thick oxide layer. A Ta2O5 layer was then deposited by ~CVD!, followed by a 10 Å capping layer of CVDSiO2. The entire structure was then reoxidized in O2 or N2Oat 650 °C and 850 mTorr. Given the stacked structure ofdielectric, the total capacitance of the stack will be dimished by the presence of the two lower-permittivity layers

For the Ta2O5 sandwich,70,71 using Eq. ~11! for theTa2O5 layer ~t'50– 60 Å,k'20– 30), an equivalent oxidethicknessteq5101101(3.9/k)t525– 30 Å is expected. Theexperimentally determined value from capacitance–volt(C–V) measurements was in good agreement with this emate: 23 Å. No charge trapping was observed in theC–Vexperiments, as evidenced by a lack of hysteresis. This sis an important attempt to demonstrate the feasibility oftegrating Ta2O5 into a standard CMOS process, but it is clethat the presence of a SiO2 layer ~or any low-k layer! ateither interface limits the ultimate device performance.

Long channel transistor measurements utilizing tstack were also made using poly-Si gates and WSix contacts,as shown in Fig. 8. Figure 8~a! shows drain current andtransconductance for long-channel PMOS transistors afunction of gate voltage, and Fig. 8~b! shows a comparisonof drain current drive and saturation characteristics. Dop

FIG. 8. ~a! Drain current and transconductance for long channel PMtransistors incorporating a SiO2 /Ta2O5 /SiO2 dielectric stack~see Ref. 70!.~b! Comparison of drain current drive and saturation characteristics.


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activation anneals were accomplished with a relatively ltemperature~600–800 °C! rapid thermal anneal process, prsumably to avoid crystallization of the Ta2O5 layer and toprevent further SiO2 formation at the interfaces within thconstraints of a conventional CMOS process flow.70,71 Aninterface state density (D it) comparable to transistors incoporating only SiO2 as the gate dielectric was observed bason subthreshold slope measurements. The effective dielethickness estimate from the transistor transconductancedrain current measurements results in a larger value,;30 Å.The 20% discrepancy with the MIS capacitorC–V measure-ments was attributed to partial dopant activation~from therelatively low temperature anneal process!. Some degrada-tion in mobility, relative to SiO2, was also measured. Aexpected, leakage currents were well below 1 A/cm2 as aresult of the physically thicker dielectric.

It is essential at this point to distinguish between trequirements for memory42 and transistor applicationsMemory capacitors require extremely low leakage curre~typically J,1028 A/cm2! and very high capacitance densifor charge storage, but the interface quality is not as criticMemory capacitor applications require control of the inteface primarily to limit interfacial reactions to keep the totcapacitance high. Since the main requirement is that thepacitors store charge, however, current transport alongdielectric interface is not important. Furthermore, no elecfield penetration is required below the bottom electrode,the bottom electrode is often metal, or nitrided poly-~heavily doped!. All of the requirements amount to the important distinction that the bottom dielectric interface qualis not as critical to capacitor performance.

In contrast, a key requirement of a FET is that the eltric field penetrate into the Si channel to modulate carrtransport, and that the dielectric-channel interface be of vhigh quality. The channel must of course be Si, so anytential high-k dielectric must be compatible with Si. Transitors have more lenient leakage requirements~,102 A/cm2

for high-performance processors, and;1023 A/cm2 for low-power applications!, although high capacitance densities astill needed. The most critical distinction between highkmaterials requirements for capacitors versus gate dielecis the interface and materials compatibility: gate dielectrmust form an extremely high-quality interface with Si, analso be able to withstand CMOS processing conditions win contact~or near contact! with Si.

B. Issues for interface engineering

It is well known that the industry roadmap presentsmajor problem for the core transistor gate dielectric, becait calls for a much thinner effective thickness for future aternative gate dielectrics:teq<10 Å.4,5 This would then re-quire the SiO2 layer to be;5 Å thick. Such an extremelythin SiO2 layer is very difficult to obtain with high quality.22

The resulting voltage drop across the oxide could also leasignificant charge trapping in the film, especially since tinterface between such stacked dielectrics may almosttainly contain a large density of traps. Furthermore, sucthin interface layer most likely willnot prevent reaction be-tween the substrate and any high-k material which is not

S


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thermodynamically stable to SiO2 formation on Si, understandard thermal processing required for CMOS~previouslydiscussed pinhole formation in ultrathin SiO2 is also aconcern!.48

To illustrate this point, an example for obtaining a delectric stack withteq510 Å is considered in Fig. 9. Onway to achieve this would be to use 5 Å of SiO2(teq55 Å)as the lower~first! layer, at the Si interface, and 30 Å ofdielectric withk525 (teq,high-k;5 Å) as the upper~second!layer. Even for low applied voltages, such a thin layer whave a large enough electric field to create a significamount of charge trapping. In addition, an oxide layer tthin will allow a large amount of direct electron tunnelininto the high-k dielectric, likely causing further deleterioueffects to the electrical performance of the stack.

It is important to note, however, that if asingle layerdielectric can be used, thenteq510 Å can be achieved with40 Å ~physical thickness! of a material which only has amoderate permittivity ofk516 ~see Fig. 9!. This physicalthickness is greater than the total physical thickness ofstack in the earlier example~535 Å!, even though the permittivity of the single layer gate dielectric (k516) is muchlower than that of the alternate dielectric in the stackk525). In addition, any potential charge trapping atdielectric-dielectric interface would be avoided. These csiderations for the choice of the best high-k materials will becovered in more detail later.

The approach of using an epitaxial high-k gate dielec-tric, such as SrTiO3, requires submonolayer control of thchannel interface for dielectric deposition.79–84 As with theuse of all perovskites for dynamic random access mem~DRAM! applications ~e.g., BaxSr12xTiO3,PbxZr12xTiO3,etc.!, the dielectric must be crystalline~usually polycrystal-line! to obtain the enormous permittivities typically observ(k.300). The work done thus far on gate dielectrics thefore has required molecular beam epitaxy~MBE!, to obtaininterface control and layer-by-layer deposition. Since itdifficult to attain a crystalline oxide on Si, interface engneering has been employed to provide submonolayer dsition of several initial ‘‘template’’ Sr–Si–O layers.79,82,84

This interface helps reduce reaction due to the thermonamic instability of SrTiO3 on Si, and also helps accommodate the difference in lattice constants between SiSrTiO3. Transistors showing encouraging results have bfabricated using SrTiO3 gate dielectrics, with metal gates~toprevent reaction between SrTiO3 and poly-Si gates! andmodified device processing.80,82

FIG. 9. Comparison of stacked and single layer gate dielectrics in a hthetical transistor gate stack. Either structure results in the same overalstack capacitance or equivalent oxide thickness,teq510 Å.


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In the study by Eisenbeiseret al., TaN gate electrodeswere used, and devices exhibitedteq'8 Å ~with quantummechanical correction to theC–V data! with a leakage cur-rent densityJ;1022 A/cm2 at 1 V bias, for a 110 Å physi-cally thick SrTiO3 film.82 Transistors with a 1.2mm effectivechannel length showed electron and hole mobilities of 2and 62 cm2/V s, respectively. Device characteristics ashown in Fig. 10, with a subthreshold slope of 103 mdecade forn-channel devices, 95 mV/decade forp-channeldevices. The extracted interface state density showed aD it;631010/cm2, but the fixed, low work function (FB

54.2 eV) of the TaN gates produced undesirable threshvoltages forp-channel devices.82 Figure 11 shows that thedielectric deposition process can cause interfacial reactiooccur with Si, resulting in an amorphous SiOx-containinglayer.84 This layer most likely provides a better interfacethe Si channel than the SrTiO3 would, thereby exhibitingencouraging device properties. This MBE approach andimplications of the UHV conditions required for MBE wilbe discussed further in Sec. VI F.

C. Recent high- k results

Considering the potential problems and limitations in uing a ;5 Å SiO2 layer in a dielectric stack, it is highlydesirable to employ an advanced gate dielectric whichstable on Si,and exhibits an interface quality to Si which icomparable to that of SiO2. This would avoid the need for aninterfacial layer and at the same time, the high permittivitythe material could be fully realized. Table I is a compilatioof several potential high-k dielectric candidates, with the columns indicating the most relevant properties, which willdiscussed in detail throughout the remainder of this revieAlthough a substantial amount of work has been reportedTa2O5 as a gate dielectric,77 and it clearly has many attributefor memory capacitor applications, the inherent thermalstability when in direct contact with Si is a severe limitatioas a gate dielectric. We now examine the available resfrom the literature on such metal oxide and pseudobinsystems, and have categorized them for chemical similarby group in the periodic table.

o-ate

FIG. 10. Transistor results for effective gate lengthLeff51.3mm whichincorporate a high-k SrTiO3 gate dielectric~see Refs. 82–84!.


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1. Group IIIA and IIIB metal oxides

Among the group III candidate dielectrics, alumin(Al2O3) is a very stable and robust material, and has bextensively studied for many applications. Regarding its ufulness as an alternate gate dielectric, Al2O3 has many favor-able properties, as shown in Table I, including a high bagap, thermodynamic stability on Si up to high temperaturand is amorphous under the conditions of interest. The drback is that Al2O3 only hask;8 – 10, and would thereforemake it a relatively short-term solution for industry’s nee~1–2 generations!. If no longer-term solution is available bthe time that a replacement is required, however, sucshort-term solution may indeed be suitable. The otherw

FIG. 11. Reaction at the interface of the SrTiO3 gate dielectric and the Sinterface~see Ref. 82!.

TABLE I. Comparison of relevant properties for high-k candidates.

MaterialDielectric

constant~k!Band gapEG ~eV!

DEC ~eV!to Si

Crystalstructure~s!

SiO2 3.9 8.9 3.2 AmorphousSi3N4 7 5.1 2 AmorphousAl2O3 9 8.7 2.8a AmorphousY2O3 15 5.6 2.3a CubicLa2O3 30 4.3 2.3a Hexagonal, cubicTa2O5 26 4.5 1–1.5 OrthorhombicTiO2 80 3.5 1.2 Tetrag.c ~rutile, anatase!HfO2 25 5.7 1.5a Mono.b, tetrag.c, cubicZrO2 25 7.8 1.4a Mono.b, tetrag.c, cubic

aCalculated by Robertson~See Ref. 153!.bMono.5monoclinic.cTetrag.5tetragonal.


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desirable attributes of Al2O3 have resulted in several recestudies of both its physical and electrical properties as a gdielectric.

As mentioned before, Al2O3 is thermodynamically stableon Si against SiO2 formation, but any deposition techniquof interest typically operates under nonequilibrium contions. This means that reactions can occur, and phasesform which are not predicted by equilibrium phase diagramalthough further thermal processing~depending on the temperatures and times involved! will tend to drive the systemtoward the equilibrium state. Kleinet al.85 studied thin Al2O3

films deposited by CVD~using triethyldialuminum for the Alprecursor! at temperatures below 400 °C, and found evidenof an aluminum silicate phase formed at the interface wSi, as seen in Fig. 12. Nuclear resonance profiling~NRP!~which measures the Al concentration! of the films showed atwo-layered structure, with the expected Al concentrationAl2O3 in the top layer, and a marked decrease in Al contin the interface layer. XPS indicated the presence of AO–Si bonds in an interface layer for a 35 Å deposited Al2O3

film. A significant amount of carbon was also observed infilms ~;20 at. %!, but it is nevertheless apparent that kinetican play an important role in determining the interface strture, which is the most critical region for thin gate dieletrics.

Atomic layer CVD~ALCVD ! Al2O3 has been studied byGusevet al.87 both physically and electrically, in particulato better understand the interface formed between SiAl2O3 deposited by this technique. Using NRP, medium eergy ion scattering~MEIS! and high-resolution TEM, it wasdetermined that ALCVD-deposited Al2O3 ~using trimethyla-luminum and water as the Al and O precursors, respectiv!could be deposited on H-terminated Siwithout forming aninterfacial SiO2 layer, as shown in Fig. 13.87 This is an im-portant result, because even though Al2O3 is thermodynami-cally stable on Si~as mentioned previously!, all of the depo-sition and growth techniques discussed here occur unnonequilibrium conditions. It is therefore usually found than interfacial SiO2-containing layer forms during depositionbetween the high-k material~in this case Al2O3! and the Sisubstrate. The combination of the three physical analyused in the study by Gusevet al.87 show that it is possible tocontrol the interface reactions, at least for this case of pcursors and deposition conditions.

FIG. 12. HRTEM image of CVD Al2O3 on Si with an interfacial Al-silicatereaction layer evident~see Ref. 85!.


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Transistor results for 48 Å of Al2O3 ~thermally evapo-rated Al followed by thermal oxidation! were reported byChin et al.,88 which exhibitedteq521 Å with a leakage cur-rent of ;1028 A/cm2 at 1 V gate bias, compared t;1021 A/cm2 for 21 Å of pure SiO2. The Al2O3 films ex-hibited low stress-induced leakage current~SILC! effects,but did show a high interface state density,D it

.1011eV21 cm22. A follow-up study by Chin et al.89

achieved a thinner physical thickness of 21 Å Al2O3 to pro-duce Teq59.6 Å, with 22 mV of hysteresis andD it>331010cm22, and a flatband shiftDVFB;1600 mV, sug-gesting negative fixed charge in the film. Very good transtor properties were reported for these films, again with lSILC effects.

Buchananet al.91 reportednMOSFET results on AL-CVD Al2O3 for 0.08mm gate length transistors with poly-Sgates, using standard processing conditions, includinrapid-thermal dopant activation anneal atT.1000 °C. Aleakage current ofJ;1021 A/cm2 ~at Vbias5VFB11 V! wasmeasured forteq513 Å, showing a reduction in leakage curent of ;1003 compared to SiO2 of the sameteq value. Atrend in fixed charge correlated with Al2O3 thickness wasdemonstrated, showing that fixed charge increases withcreasing film thickness. Extrapolation of that data indicathat the fixed charge is concentrated near the top, polinterface. Furthermore, an interfacial layer was determine

FIG. 13. ~a! TEM image of Al2O3 film deposited by ALCVD methods on ahydrogen passivated surface from a HF-last process.~b! CorrespondingMEIS profile of the film. No interfacial layer is detected~see Ref. 87!. ©2000 IEEE, Fig. 13~a! reprinted with permission from IEEE.


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contribute;8 Å to the overall the overallteq value. Thecomposition of the interface reaction layer is currently nknown, but apparently has ak value larger than that of pureSiO2. At an effective field of 1 MV/cm, the channel carriemobility value for Al2O3 was measured to be smaller byfactor of;23 ~100 cm2/V s compared to 220 cm2/V s for theuniversal mobility curve! than that expected by the universmobility curve.91 Encouraging drive currents and reliabilitcharacteristics were demonstrated for these devices, busignificant mobility degradation clearly indicates some deterious effects of the ALCVD Al2O3 which warrant furtherinvestigation.

The study by Parket al.90 demonstrated that boron diffuses through ALCVD Al2O3 during dopant activation anneals, and indeed this may be a serious issue for any anative dielectric. It was reported that dopant activatianneals of 800–900 °C performed on boron implanpoly-Si gates on top of;60 Å Al2O3 caused significant dif-fusion of boron through the Al2O3 film and into then-Sisubstrate, as evidenced by a flatband shift of;1.5 V. Sec-ondary ion mass spectroscopy profiles also indicated anificant amount of boron in the substrate after anneal. Fthermore, the addition of an oxynitride layer, grown byN2O anneal before Al2O3 deposition, greatly reduced thflatband shift to 90 mV. In a different study by Leeet al.,92

phosphorous diffusion from then1 poly-Si electrode intoALCVD Al 2O3 was observed under reasonable anneaconditions of 850 °C for 30 min.C–V analysis showed aflatband shiftDVFB5670– 740 mV~depending on the particular dopant incorporation process!, which corresponds to.1012cm22 of negative fixed charge in the film. These rsults indicate that in this case, phosphorous not only diffuthrough the Al2O3 layer, but also introduced fixed charginto dielectric. The authors propose that phosphorous mfies the Al2O3 network, causing negatively charged Al–dangling bonds. It will continue to be extremely importantidentify and understand dopant diffusion in any potentialternative gate dielectric.

Most of the high-k films thus far exhibit a flatband voltage different from that expected for the given choice of eltrode and substrate type. As can be seen in Fig. 4, theband voltage is ideally determinedonly by the electrodework function and the electron affinity of the substrate. Wtherefore very roughly estimate flatband shifts from the dreported in the literature.~Note that this shift is differentfrom the hysteresis flatband shift, which is required to beleast an order of magnitude smaller, and arises from sweing theC–V curve in opposite polarity directions.! In moststudies,DVFB values are not reported by the authors. Westimate the value ofDVFB from publishedC–V curves,however, using work function values reported bMichaelson95 for a given electrode, along with electron afinity values of 4.18 and 5.3 eV forn-Si andp-Si substrates,respectively. TheDVFB values we estimate are not intendeto be extremely accurate, but rather to show an approximvalue, within a few hundred millivolts.

In the studies mentioned above for Al2O3 on Si, the mea-sured flatband voltage shiftDVFB is about1300 to 1800mV, compared to that expected by the electrode and s


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strate types used. This shift is typically interpreted as fixcharge within the film, although it can also arise from oxidamage associated with gate electrode deposition or oforms of processing treatments. As mentioned previouslpositiveDVFB value corresponds to a negative fixed charConsidering that largeDVFB values have been measuredseveral independent groups, using different processingditions and electrodes, this is currently being interpretedfixed charge within the films.

Several groups have studied the group IIIB metal oxidY2O3,

96–100 La2O389,99 and Pr2O3

101 for the purposes ofhigh-k gate dielectrics. Manchanda and Gurvitch96,97 ther-mally oxidized sputtered yttrium films to form Y2O3, forstructures with and without an intentional SiO2 layer be-tween the Y2O3 and Si substrate. It was found that structurwith ;260 Å Y2O3 showed very low leakage o,10210A/cm2 at 5 V bias and breakdown fields ofEBD

;4 MV/cm. Capacitors accumulated well with little hysteesis and dispersion, but showed an interface charge deof ;631011cm22 and showed an interface trap density;1011cm22 eV21. The dielectric constant of the Y2O3

grown on SiO2 was found to bek;17– 20, but for Y2O3

grown directly on Si, it was found thatk;12. This lowermeasured permittivity value likely resulted from growthinterfacial SiO2 during the thermal oxidation step.

Kwo et al. investigated Y2O3 and Gd2O3 films depositedby molecular beam epitaxy~see Secs. VI D and VI F!, inboth crystalline and amorphous phases~as measured byx-ray diffraction!.98 Amorphous films showed lower leakagcurrent densities than crystalline layers, and capacishowed teq510– 15 Å with leakage current densities ofJ51026– 1023 A/cm2, depending on morphology, depositioand postannealing conditions. Breakdown fields were msured asEBD;3 MV/cm, with interface state densityD it

,1012cm22 eV21. TheC–V curves for these films also exhibited frequency dependence between 100 Hz and 1 M

Guha et al. recently investigated relatively thick (teq

;45 Å) Y2O3 films using an atomic O and Y metal beaepitaxy approach.99 It was found that quasistatic and higfrequency ~100 kHz! C–V measurements using Al electrodes overlap well upon postmetallization annealing sgesting that interface state densities less than 1011cm22 wereobtained. Little or no flatband voltage shift was reporteLeakage currents at 1 V in thinner films (teq;21 Å) werereported to be;1028 A/cm2. High resolution TEM andMEIS studies, however, indicate the formation of a columpolycrystalline structure with;10% Si in the film and a15-Å-thick interfacial SiOx layer which was attributed tooxygen diffusion~possibly along grain boundaries! and/orcatalytic reaction.

Chambers and Parsons100 recently investigated the interface associated with Y2O3, Si and oxidized/nitrides Si surfaces. They found that silicides can readily form dependon the kinetics of the deposition process, and that subseqoxidation of the silicide yields an interfacial silicate layeThey also point out that such reaction kinetics may wellexpected for other metal–oxide systems used for altergate dielectrics. The flatband voltages for the Y2O3 filmsreported to this point are shifted byDVFB5300– 600 mV


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from that expected for an ideal capacitor using the respecelectrodes and substrate types in these studies. AsAl2O3, these are very large voltage shifts measured inbroad array of sample conditions.

Chin et al.89 reported results from La2O3 films whichwere formed by evaporation of La onto Si, followed by lowtemperature thermal oxidation andex situAl gate deposition.The actual composition and structure in the films mayquire further examination, as pure La is well known tovery volatile and reactive in air, and La2O3 will absorb watervapor from air. These characteristics signify that anyex situexposure of these films to air will certainly result in an ucontrolled reaction. Nevertheless, remarkable device reswere shown for these films, as a physical thickness33 ÅLa2O3 producedteq54.8 Å, J;1021 A/cm2 at 1.0 Vgate bias, andD it;331010eV21 cm22 ~almost no quantummechanical effect on theteq value because of the Al gate!.Long-channel transistors with the same films for the gdielectric exhibited very good turn-on characteristics, a sthreshhold slope of 75 mV/decade, and a high field effectmobility ~at 1 MV/cm! of meff.300 cm2/V s. These filmsalso showed a flat band voltage shift of;1700 mV.

Guha et al. also recently investigated thin (teq

;10– 14 Å) La2O3 films99 where leakage currents o1024– 1027 A/cm2 at 1 V are reported. An amorphous filmstructure with;10% Si and a thin interfacial SiOx layer wasreported. A large flat band voltage shift of21.4 V was alsoobserved.

There are clearly many attributes to the group III meoxides, as many promising and encouraging properties halready been demonstrated using these materials systemwill be discussed in Sec. VI, the beneficial propertiesM2O3 metal oxides arise in part because the mole fractioncations is higher~40 mol.%! compared to MO2 ~Group IV!metal oxides, with a cation fraction of 33.3 mol %.

The magnitude of the flatband voltage shifts measureall of these high-k systems, suggests a substantial fixcharge density ofQ.1012cm22 in the films, and must befurther investigated. Interface stability under standard pcessing conditions remains a concern, as the earlier cillustrate that uncontrolled reaction tends to occur duringnonequilibrium deposition process through kinetics~with theapparent exception of the ALCVD-deposited Al2O3!, despitesome thermodynamic predictions. Control of the Si chaninterface is a key issue for high-k gate dielectrics, and will berevisited later.

2. Group IVB metal oxides

A substantial amount of investigation has gone intogroup IVB metal oxides, specifically TiO2,

102–109

ZrO2,110–121 and HfO2,

110,120,122–126as these systems havshown much promise in overall materials properties as cdidates to replace SiO2.

The TiO2 system has been heavily studied for highkapplications both for memory capacitors andtransistors.102,106,107It is attractive because it has a high pemittivity of k580– 110, depending on the crystal structuand method of deposition. This anomalously high permittity, which arises through a strong contribution from so


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phonons involving Ti ions, is not exhibited by the othgroup IVB metal oxides. On the other hand, Ti has sevestable oxidation states of Ti31 and Ti41 which lead to a well-known problem with materials containing Ti–O bonds: aduced oxide. Such a reduced oxide has many oxygen vacies which act as carrier traps and high leakage paths. STiO2 crystallizes at temperatures much above 400 °C, ialso expected to exhibit a polycrystalline morphology, whis undesirable, as will be discussed in Sec. VI D. It is imptant to note that since TiO2 is not stable on Si during deposition by CVD,103 all of the studies on this high-k systemcontain both a reaction layer at the channel interface~eitherintentional or unintentional! and metal electrodes/gatesprevent reaction at the gate interface.

Transistors fabricated with TiO2 as the gate dielectrichave shown results withteq<20 Å, with a physical thicknessof 80–120 Å, and leakage current varies widely dependon deposition method and postdeposition processing.

Full transistors using CVD TiO2 as the gate dielectricwere first reported by Campbellet al.,102 using Pt electrodesto prevent reaction at the gate interface. A subthreshold sof 83–91 mV/decade was achieved for very large transis~1003100mm and 136 mm, respectively! and a transcon-ductance of 322mA/V was reported, indicating that the mobility is only ;160 cm2/V s. The transistor performance ithese devices, as illustrated in Fig. 14, was limited by a thinterfacial oxide layer which formed as a result of the CVprocess and postannealing of the structure, and the relatlarge interface state density (1012/cm2 eV). Leakage currentswere also unacceptably high in the transistors, and a rtively large interface state density (1012/cm2 eV) was re-ported. Although the role of carbon in high-k dielectrics isnot yet well understood in relation to leakage current, itpossible that carbon incorporated into the film creates de

FIG. 14. C–V curves for a 190 Å TiO2 gate dielectric in a Pt/TiO2 /p-typeSi MIS capacitor structure~150 mm2 area!. A gate bias-dependent accumulation capacitance was observed. Analysis which incorporates an estimathe accumulation layer thickness indicates the presence of a SiO2 interfaciallayer, resulting in an overallk;30 for the stack~see Ref. 102!. © 1997IEEE, reprinted with permission from IEEE.


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states that allow higher leakage currents. A carbon-fprecursor104 for Ti was synthesized and used to prevent cbon incorporation in the film, thereby attempting to reduleakage currents. Furthermore, a thermal nitride was groat the channel interface by an initial anneal in NH3. Theresulting devices showed values ofteq,20 Å, and leakagecurrents which were reduced by 1003 compared to comparable SiO2 films.105 A hysteresis of 80 mV measured in thdevices indicates the effect of fixed charge from the nitrlayer at the channel interface. The flatband voltage shift wDVFB;2200 mV, perhaps arising from the presencefixed charge in the film.

The jet vapor deposition~JVD! method has been used bGuo et al.106 to make long-channel transistors withTiO2/SiN stacked gate dielectric. An interfacial nitride barier ~15 Å thick! was first deposited by JVD at 25 °C anannealed by rapid thermal annealing~RTA! in N2 at 600 °C,in order to minimize any interfacial layer containing SiO2

which may form during postannealing of the structure. TTiO2 layer was subsequently deposited at a thickness;120 Å, followed by RTA in O2. These structures were seeto be stable up to 900 °C, but at higher temperatures,leakage and capacitance measurements were severelygraded. Devices using Al electrodes achievedteq,20 Å, andthe nMOS drive current obtained was 0.18 mA/mm for a 5mm gate length and 10mm gate width, atVD52.5 V and(VG2VT)51.5 V. No mobility values were reported.

Ma et al.107 reported that after forming TiO2 layers byCVD, a postprocessing treatment sequence of plasma o(O3) at 200 °C followed by rapid thermal anneals in N2O orO2 served to minimize the interfacial reaction between Ti2

and Si. This process had the effect of reducing the leakcurrent by four orders of magnitude~for TiO2 films less than100 Å thick!. The performance of MOSFETs with TiN gatewas also reported, and the relatively low drive currents;40 mA/mm ~at VG51.2 V, VD51 V! obtained for a 0.5mm device were attributed to nonuniformity in the polycrytalline TiO2 layer and corresponding roughness at the intface.

Work on alternate dielectric materials systems of groIVB metal oxides such as ZrO2 and HfO2 was reported in the1970’s and 80’s for the purpose of optical coatings aDRAM applications.

Balog et al.110 performedC–V measurements on verthick ~3000–4000 Å! polycrystalline HfO2 films inAl/HfO2/Si structures. For films grown~by CVD! at 450 °Cin pure O2, a large hysteresis was observed. It was indicathat subsequent anneals in inert ambients, such as in N2 at800 °C, led to a reduction in the observed hysteresis. Hever, HfO2 films grown atT>500 °C resulted in no observehysteresis andD it;1 – 631011/cm2. Breakdown fields forthese films were reported to be;1–2 MV/cm and k522– 25 at 1 MHz. Baloget al. also found essentially identical results for ZrO2 films in Al/ZrO2 /Si structures.110 Thepermittivity for these films ranged from 17 to 18. The flaband voltage shift for both HfO2 and ZrO2 thick films rangedfrom DVFB52600 to1200 mV. However, we note that threported Si surface preparation procedure most likely

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sulted in the formation of a native oxide prior to HfO2 andZrO2 deposition.

Shappiret al. examined thinner~300–600 Å! ZrO2 films~deposited by metalorganic CVD at 450 °C! in various MISstructures~with a native oxide on the substrate! that includedAl, Mo, and poly-Si gates.111 For Al gate capacitors, anneaing at T>800 °C in N2 resulted in a large reduction in leakage current. Interestingly, anneals in O2/HCl at 800 °C re-sulted in the largest reduction in leakage althoughreduction in the measured dielectric constant~due to poten-tial SiO2 formation! was observed. Breakdown fields ofMV/cm were reported for the subsequently annealed filmslarge hysteresis was observed in allC–V curves, with a shiftof ;600 mV for unannealed and N2-annealed samples, andshift of ;200 mV for O2/HCl-annealed samples. These filmwere estimated to haveD it;131012/cm2, which may havebeen even higher from the polycrystalline ZrO2 were it notfor the presence of the native oxide. A dielectric constan1 MHz ranging from 14 to 19 was observed~k decreasedwith increasing anneal temperature!, even with the nativeoxide present.111 Leakage currents in these very thick filmwere reported to be as low as 831029 A/cm2 at 1.5 MV/cm.

Mo gate devices exhibited similar dielectric constawith a higher~;103! loss tangent than that for the Al gastructures. Leakage currents were somewhat higherbreakdown was observed at a slightly lower value~;3.7MV/cm!. Since Mo has a larger work function (FB

54.5 eV)95 than that of Al (FB54.3 eV),95 Mo is expectedto result in a lower tunneling current for gate injection, bapparently reaction at the gate interface altered the tunneproperties. The increase in the leakage current was attribto MoO or MoN formation during the postdeposition anneing process.

It was found that poly-Si gates produced good perfmance when the amorphous Si was deposited at 550 °C,lowed by a POCl3 doping~885 °C! and drive step~920 °C for2.5 h!, which also served to crystallize the Si electrode.111 @Itwas reported that poly-Si deposition at higher temperatu~620 °C! results in the reduction of ZrO2 to form a Zr-richlayer near the poly-Si/ZrO2 interface, leading to very highleakage currents.# Leakage currents were comparable to thobserved for the Al or Mo gate structures, but the reporbreakdown field was lower than Al,;3 MV/cm. A dielectricconstant ofk;16 was measured, again with the presencea native oxide.

The large hysteresis and other shifts in theC–V curveswere observed for all of the electrodes and annealing cotions used in this study, which indicates that the shifts prably arise from mobile ion transport in the pure ZrO2

films.112 All of these studies on ZrO2 and HfO2 indicate crys-tallization of the metal oxides either during the depositiprocess or upon moderate postannealing conditions.

More recent work has shown encouraging resultsboth CVD and sputtered films. Using ALCVD, Copet al.113 demonstrated that a highly uniform layer of ZrO2

can be deposited as thin as 20 Å on top of an SiO2 layer~Fig.15!. In that work, the 15 ÅSiO2 layer was intentionallygrown by a thermal anneal, to form a very high quality iterfacial oxide.113 As mentioned previously, this layer limit


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the minimum achievableteq value, but it is also required fothe ZrCl4 precursors used in this ALCVD process. Withoutreactive SiO2 layer on the surface, the ZrCl4 precursors can-not easily displace the Si–H bonds present on the surfaca standard HF-last wet clean process. This initial oxidattherefore serves a dual purpose by providing a very hquality interface and at the same time a reactive surfacewhich to deposit the ultrathin layer of ZrO2. These ZrO2layers were found to be thermally stable under vacuumnealing up to 900 °C, which is important, but were observto decompose at higher-temperature vacuum anneals1000 °C.

The uniformity of these layers was found to be remaably good, with thickness variations less than a few percacross the wafer. It was additionally noted that ALCVfilms deposited on Si surfaces prepared by a HF-last prodid not produce flat and uniform films, but rather resultedthe nucleation of ZrO2 islands interspersed with disorderematerial. It was suggested that this undesirable morpholmight be controlled though further investigation of depotion parameters. Perkinset al.127 reported the electrical characteristics of polycrystalline ZrO2 ALCVD films depositedon chemically grown oxides. Using TiN electrodes, encoaging results ofteq,14 Å with a leakage current densityJ;231024 A/cm2 at (VG2VFB)51 V were achieved. Theflatband voltage shift in the ZrO2 films was DVFB;2600 mV, and hysteresis in the films varied with bias swerange, as63 V sweeps showed hysteresis of;80 mV and62 V sweeps showed;10 mV hysteresis, respectively, fothe same film.127 The combination of the observed flatbanvoltage and hysteresis suggests the presence of poscharge in the films, either at the interface or in the Zr2

layer.Device properties have been measured on sputtered

trathin films of ZrO2 and HfO2 using Pt electrodes.114,122By

FIG. 15. HRTEM images of ZrO2 deposited by ALCVD methods on~a!oxidized and~b! HF-last treated Si surfaces. Deposition on the H-passivasurface appears to result in island nucleation~see Ref. 113!.


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initially sputtering only Hf metal onto the Si substrate, folowed by reactive sputtering of Hf in an Ar/O2 ambient, lowteq values of 11.5 Å with a leakage currentJ;131022 A/cm2 ~at a bias ofVG2VFB51 V! were reported~no quantum corrections taken into account! with Ptelectrodes.122 Negligible hysteresis was reported for certaprocessing conditions, but a relatively highDVFB value of;1600 mV was reported in one case,122 and ;2300 mVwas reported in another,124 with slightly different processingconditions. These significant flatband shifts perhaps afrom a large amount of negative fixed charge~for positiveDVFB! and positive fixed charge~for negativeDVFB!, respec-tively, in the films. The breakdown appears to occur inHfO2 layer, as somewhat low breakdown fields ofEBD

;4 MV/cm were measured, as was previously reportedthicker films.110,134An interfacial layer always forms througthis sputtering deposition and postannealing process~Fig.16!, because of the well-known fast diffusion of oxygethrough ZrO2 and HfO2.

112 In this case, oxygen which diffuses through these metal oxides reacts with Si at the inface to form an uncontrolled interfacial layer.

Under optimized processing conditions,122 it was re-ported that the contribution from the interfacial layer isteq

;5 Å, although a significant level of interface states is sapparent in theC–V curves at low frequencies, as seenFig. 17. Although x-ray diffraction shows the HfO2 films tobe amorphous as-deposited, annealing above 700 °C waserved to cause crystallization in these thin films, as wpreviously reported for thick films.110 Polycrystalline gatedielectric films will most likely have higher leakage currenbe less uniform and less reproducible than amorphous fibut the correlation between gate dielectric morphology adevice performance requires more investigation.

In the case of ZrO2, it has been reported114,115that sput-tering Zr in a process similar to that described for HfO2

above leads to capacitors~using Pt electrodes! with teq

516 Å, and leakage current densityJ;331022 A/cm2 ~at abias ofVG2VFB50.5 V!. The interface once again showsreaction layer between the ZrO2 and Si, and this layer wareduced to a physical thickness of about 10 Å by optimizthe deposition conditions. The interface was seen to yiehysteresis of 50 mV, a flatband voltage shiftDVFB;1200 to1300 mV andD it;1011cm22 eV21, indicating the limitingquality of the reaction layer. The particularly large flatbavoltages may arise in part from processing conditions durdeposition and postannealing.

Houssaet al.118 reported a systematic attempt at undstanding the flatband voltage and fixed charge in ZrO2 layersdeposited by ALCVD on native silicon oxide. Their studshowed that the net fixed charge density could be altesignificantly depending only on the post-annealing contions. Using Eq.~9! to obtain values for the amount and sigof the fixed charge in the dielectric, it was found that adeposited ZrO2 /SiOx stacks exhibit negative fixed chargand that postannealing in O2 introduced compensating postive fixed chargeand at the same time increased the densof midgap interface states.118 These results are shown in Fig18~a!, where the as-deposited fixed charge density is emated to be22.531012cm22 ~with DVFB;1200 to1600


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FIG. 16. Effect of postdeposition annealing on HfO2 gate dielectrics.~a! N2

and O2 anneals,~b! equivalent oxide thickness, and~c! leakage current afterO2 anneals~see Refs. 122 and 124!. © 2000 IEEE, reprinted with permissionfrom IEEE.

FIG. 17. C–V curve of HfO2 after a rapid thermal anneal at 600 °C. Thdispersion forVG,22 V is attributed to higher leakage. Interface statesnoted nearVG;0.5 V ~see Ref. 122!. © 2000 IEEE, reprinted with permis-sion from IEEE.


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mV, depending on film thickness!. Postannealing in O2 atprogressively higher temperatures is seen to decrease thamount of negative fixed charge~presumably through compensation by the introduction of positive fixed charge!, untila netpositivefixed charge is observed for O2 anneals above600 °C ~a net positive fixed charge density of 231012cm22

results after a 700 °C anneal in O2!.118

Figure 18~b! shows that for the same annealing contions, the midgap interface state density also increases.der subsequent annealing in H2, the midgap interface stateare minimized, while little effect is seen on the net fixcharge. If the subsequent H2 anneals are carried out aftedeposition of the metal gate, however, the net fixed chargfound to become significantlymorenegative, such that evethe higher temperature anneals in O2 do not produce a nepositive fixed charge. It is proposed that the resulting sand amount of fixed charge is dependent on the anneaconditions, and that the positive fixed charge arises frover coordinated oxygen atoms, possibly induced bypresence of hydrogen,128 as has been proposed for the casepure SiO2.

129

We note that hafnium suffers the misconception thaexhibits sufficient radioactivity to cause sensitivity to singevent upsets in integrated circuits. It is well known thathas been used in nuclear reactors as the control rod matbecause it has a high thermal neutron capture cross secand shows little decrease in capture cross-section afterperiods of radiation exposure.130 Hafnium also shows highcorrosion resistance in hot water, which makes it a lomaintenance material for control rod purposes. Both zirnium and hafnium have naturally occurring, long-lived r

FIG. 18. Extrapolated values of~a! fixed charge densityQf and~b! midgapinterface state densityNit as a function of postannealing conditions in O2

and H2 for ALCVD ZrO2 ~see Ref. 118!.


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dioactive isotopes96Zr and 174Hf. The following analysissuggests, however, that neither element should be a conwith respect to radioactive decay.131

The naturally occurring radioactive isotope for zircnium is 96Zr. The natural abundance is 2.80 at. %. The halife T1/2 is .3.631017 years. Assuming reasonable valufor transistor dimensions, the number of Zr atoms resultfrom a ZrSiO4 stoichiometry associated with the gate dieletric is ;1.53106, resulting in 4.23104 96Zr atoms/gate. As-suming 109 transistors in a device, this results in 4.231013

96Zr atoms per device. The number of disintegrations/yeagiven by A* l, where A5number of atoms andl5probability for decay, viz. l50.693/T1/251.9310218yr21. As a result, one might expect 831025 disin-tegrations per device per year, or one disintegration ev1.23104 years per device. A similar analysis for174Hf indi-cates that one disintegration every 1.63103 years per deviceif HfSiO4 is used as the gate dielectric.

There is general agreement that the flux of particles tmight interact with a device consists of more than 97% ntrons at sea level.132 The relevant parameters~neutron crosssections and natural abundances! are given in Table II forhafnium and zirconium, as well as other materials that wbe found in future generation devices. Hafnium has a larthermal neutron cross section than zirconium, but to demine whether or not this cross section is significant, omust also consider the number of hafnium atoms presenthe gate dielectric. To determine if hafnium is more ofliability than copper for example, one must take into accothe relative number of hafnium atoms to copper atoms,even relative to silicon in the silicon substrates. Ziegler132

describes this as the active atoms/chip, given by

active atoms/chip

5~active area!•electrical depth•atom density.

TABLE II. Thermal neutron cross section data for device relevant mater~after Ref. 132!.

Element Isotope

Naturalabundance

~at. %!

Thermalneutron

cross section~b!

Weighted averagecross section

~b!

Zr 90 51.46 0.191 11.23 192 17.11 0.2 0.21394 17.4 0.0896 2.8 0.05

Hf 174 0.163 400176 5.21 30177 18.6 370178 27.1 50 97179 13.75 65180 35.22 10

Cu 63 69.1 4.565 30.9 2.3 3.82

Si 28 92.18 0.0829 4.71 0.3 0.091330 3.12 0.11

B 10 19.7 383711 80.3 0.005 756


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Assuming a 1 cm2 silicon-based device with 4% of thdevice active and a 1mm electrical depth, one arrives a(0.04 cm2)•(1023 cm)•(531022atoms/cm3)5231018 Siatoms. One must also determine the active cross sec~5active atoms•neutron cross section!, which takes into ac-count the differences in neutron cross sections for the difent elements~shown in Table II!. For Si, the weighted average neutron capture cross section is 9.13310226cm2

resulting in an active cross section of 231027 cm2. Otherrelevant elements are shown in Table II.

While this approximation does not provide an estimof the absolute single event upset rate, it should provideestimate of the relative sensitivity for different elementsthe device to cosmic rays. Thermal neutron cross-sectwere used as an estimate of the overall neutron cross sewhich is likely an overestimate of the interaction cross stion.

Table III compares these sensitivities for the differeelements and their associated isotopes discussed eaEven with the relatively high thermal neutron cross sectiofor Zr and Hf, these data would suggest that neither HfZr should cause as many upsets as Cu. The number oatoms was determined by assuming a copper metallizaprocess consisting of 0.3-mm-thick layers, five levels ofmetal, and 4% of each layer is made up of Cu. Boron westimated assuming an implant dose of 131015atoms/cm2.

The results obtained on the ZrO2 and HfO2 metal oxidesystems described earlier indeed are important demontions of the ability to achieve lowteq values with lower leak-age currents than would be achieved using comparable2films. The interface quality of these systems remains a ccal issue, however, since the materials in particular aretremely susceptible to O diffusion and reaction at the chaninterface. The ultimate device performance will depeheavily on the channel carrier mobility, which in turn caneasily degraded by high interface trap levels. A large hysesis or shift in flatband voltage for any gate dielectric walso result in unacceptable transistor threshold voltage shFinally, these metal oxides have not yet demonstratedrequired stability under the high temperatures requiredCMOS processing, including dopant activation anneals u1050 °C. At this point, lower thermal budget processes hbeen considered, such as the replacement gate process,69 butno proven manufacturable flow has yet emerged. Until toccurs, it should be considered a critical requirementhigh-k dielectrics to withstand such high-temperature aneals.

TABLE III. Active cross section for different elements, using the thermneutron cross section~after Ref. 132!.

Element Active atomsNeutron cross

sectionActive cross

section

Si 2.031018 9.0310226 1.83107

Zr 1.531015 2.1310225 3.2310210

Hf 1.131015 9.7310223 1.131027

Cu 3.031017 3.8310224 1.131026

B 1.031015 7.6310222 7.631027


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In the cases where a flatband voltage has been repofor the earlier oxide systems, the measured flatband voltshifts DVFB are substantial~compared to that expected fothe given electrode work function!, ranging from2600 to1800 mV for the high-k films discussed thus far. As mentioned previously, in this case the termDVFB doesnot referto a flatband shift arising fromC–V voltage sweeps in opposite polarities, but rather refers to thedifference in themeasured flatband voltage~for a single sweep! from that ex-pected for an ideal capacitor~for a given electrode and substrate doping level!.

This shift is normally interpreted as fixed charge withthe film, although it can also arise from oxide damage asciated with gate electrode deposition or other forms of pcessing treatments. Considering that largeDVFB values havebeen measured by so many independent groups, using dent processing conditions and electrodes, it is currently beattributed to fixed charge within the film. A large fixecharge~e.g., that which corresponds toDVT.50 mV! in agate dielectric can have a serious, deleterious effect ontransistor performance, because the threshold voltageVT be-comes too large for adequate compensation by dopantplants. Smaller fixed charges~;10–20 mV! can be accept-able, and even desirable, since this can adjust theVT suchthat smaller channel implant doses can be used~which re-sults in less ion impurity scattering of carriers in the chanel!.

Although it is not yet known whether the observed flband shifts arise from a fixed charge within the high-k di-electrics or from some other phenomenon, a large amounfixed charge in these films could have an enormous influeon the viability of their insertion into a CMOS process.these high-k gate dielectrics indeed prove to contain signicant amount of fixed charge, then the sign of the chargealso become extremely important. The band diagram in F4 illustrates the different effects on a device threshold voage for the cases of positive and negative flatband voltshifts. This observed phenomenon has been suggested11 toarise from the detailed bonding structure of the various cions near the Si interface, while another report by Houet al.,118 mentioned previously, suggested that the sign aamount of fixed charge depends only on the annealing cditions. It should be noted that only positiveDVFB valueshave been measured for Al2O2, but both positive and negative DVFB values have been measured for several higkdielectrics.

For example, TiO2, ZrO2, and HfO2 show a range ofDVFB52600 to 1800 mV, while Y2O3 and La2O3 showDVFB51300 to 11400 mV ~on much less data than fogroup IVB oxides!, but Al2O3 showsDVFB;1300 to1800mV. Since a negative value corresponds to positive fixcharge ~assuming again that these shifts are due to fixcharge! and vice versa, Al2O3 seems to show opposing behavior in that it may possess negative fixed charge. Thtwo cases clearly have different impacts onnMOS andpMOS devices. Much more work must be done to determif indeed there is a substantial amount of fixed chargethese high-k dielectrics on Si, and if so, how to remove it o

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at least make manageable adjustments for acceptable dperformance.

To summarize the many results reported thus far onunary, simple oxide systems, all high-k metal oxides inves-tigated to this point have demonstrated encouraging elecal properties. All of the unary oxides reported haachieved teq,15 Å, with J,1022 A/cm2 ~at VG2VFB

51 V!. Nearly all of the metal oxides, however, show sinificant frequency dependence, hysteresis and flatbandage shifts, as well as concerns regarding oxygen diffusand interface stability during subsequent high-temperathermal processing.

The following section focuses on alloys of these oxidin an attempt to combine and complement the desirable perties from several materials, and thereby overcome theficiencies associated with the individual materials. Theseloy systems are predominantly non-stoichiometric mixturand are therefore termedpseudobinary alloys.

3. Pseudobinary alloys

All of the earlier mentioned materials clearly have maadvantages as high-k gate dielectrics, but they also have udesirable properties which remain a concern regardingplacement of SiO2. An encouraging system of materials apseudobinaries, such as (ZrO2)x(SiO2)12x and(HfO2)x(SiO2)12x , which for this purpose combine two oxides, typically~although not necessarily! in nonstoichiomet-ric compositions. In this way, it is possible to combine tdesirable properties from two different oxides while elimnating the undesirable properties of each individual mate

It is instructive to consider the chemical and electriccharacteristics associated with Zr and Hf that serve to crsuch favorable electrical properties for the CMOS applitions ~and conversely why Ti is not favorable!. The four-foldcoordination of Si and the desire to minimize the presencdangling bonds at the interface suggests that high-Z elemin group IVB are desirable when incorporated into an inlator oxide or silicate.

Some work in the 1970’s and 80’s~as mentioned previ-ously, the work was primarily intended for use in optical lecoatings! was carried out on such pseudobinary materiaExamination of sputtered ZrO2– SiO2 codeposited, thick~;3000 Å! films has been reported by Russack aco-workers.133 X-ray diffraction analysis of the films indi-cated that the films with.10 %SiO2 remain amorphouseven upon annealing at 500 °C in air for 60 h. Films w,10 %SiO2 exhibited a crystalline ZrSiO4 diffraction patternunder similar annealing conditions. Composition analysistheir films, as deduced by Rutherford backscattering sptroscopy, indicated that the films have a metal:oxygen raof 2:1, signifying that they are fully oxidized.

Roberts et al. investigated HfO2:SiO2 films also pre-pared by sputter techniques.134 They found that Hf-silicatefilms provided superior performance to sputtered Ta2O5 filmsfor thin capacitor insulator film thicknesses~100–150 Årange!. A preferred stoichiometry of Hf4SiO10 was identifiedas a result of breakdown measurements andk513 was re-ported. It was noted that interfacial SiO2 growth occurs uponsubsequent O2 annealing above 800 °C for HfxSiO2x12 ,


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wherex,2 or x.4. Additionally, investigation of interfaceengineering using SiO2 /Hf4SiO10/Si3N4 insulator stacksprovided improved performance compared to similar strtures incorporating Ta2O5.

Recent work on two such systems of pseudobinarnamely silicates ~M–Si–O!, with M5Zr,Hf,115,116,135–138,143~a! La143~b! and Gd,143~c! and aluminates~M–Al–O!, with M5Zr,139,140 indicate that such materialsystems already exhibit encouraging gate dielectric propties toward this end. Both materials systems have the sunderlying principle of mixing a high-k ~crystalline! metaloxide with an amorphous, stable, lower-k material~SiO2 orAl2O3! to obtain a desirable morphology with suitable proerties for a CMOS gate dielectric. The effect of adding Si2

and Al2O3 to metal oxides such as ZrO2 is to produce anamorphous film that is thermodynamically stable on Si~forlow leakage currents!. The overall permittivity of thepseudobinary alloy is inevitably lower than that of the pumetal oxide, but this tradeoff can be very adequate, forimproved stability. In particular, ZrO2:SiO2 and HfO2:SiO2

silicates within an appropriate composition range have bdemonstrated to exhibit very low leakage currents andprovedk values with only small amounts of ZrO2 or HfO2 inthe material.135–137

Since Figs. 19~a! and~b! show that there are no apparethermodynamically stable ternary compounds for the TSi–O and Ti–Si–O systems, glassy silicates~TaxSiyOz orTixSiyOz! of these materials may be obtained. The subquent thermal processing that these materials experiencebe of key importance, though, as these systems are likelseparate into more stable MxOy and MxSiy phases. Further-more, an extension of constraint theory for glasses, asmulated by Phillips141 has recently been applied to glasphases of high-k gate dielectrics. It has been found142 thatthere is excellent agreement between the expected staband low defect densities specifically for certain compositranges of ZrO2:SiO2 and HfO2:SiO2 silicates.

FIG. 19. Ternary phase diagrams for~a! Ta–Si–O,~b! Ti–Si–O, and~c!Zr–Si-O compounds~after Refs. 156 and 158!.


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Many other silicate systems are possible, but the mconcerns for all of them are whether thek value is largeenough for gate dielectric applications, and whether orthey will tend to phase separate when placed next to Si atemperatures of interest. Ternary systems such as Al–SY–Si–O, or Sc–Si–O are possibilities, because their moxide phases are stable on Si, but these silicates may sfrom relatively low k values. Other possible silicate canddates which may work well are those which contain raearth metals with high atomic numbers, such as La–SiCe–Si–O, and Ba–Si–O. There may be some stability ccerns, however, for Ce–Si–O on Si, and BaO is notoriofor its hygroscopic nature.

Glassy phases of a ternary or quaternary system coning only metals and oxygen may also be obtained, butagain raises concerns of uncontrolled reaction at the Si cnel interface. For example, TiOx films have been doped withvarious metals to obtain an amorphous film, as a meanreducing leakage and improving thickness uniformity.107,109

In the study by Maet al.,139 Al and Zr were cosputteredto form (ZrO2)x(Al2O3)12x amorphous alloys withx50.75. Using TiN gates, these pseudobinary alloys achieteq;12 Å with J;0.1 A/cm2 at 1 V gate bias. The flatbanshift on capacitors wasDVFB51200 to1300 mV. Transis-tors fabricated using these alloys showed good characttics, with a subthreshold swing of 72 mV andI d51.3 mA fora 0.6mm31 mm pMOSFET, withVD5VG521.5 V. Holemobilities were found to be;30% lower than for comparable SiO2 FETs atEeff;1 MV/cm. The work by Manchandaet al.140 also used sputtered Zr–Al–Si on 5 Å SiO2 or Si–O–N films, followed by thermal oxidation, to form(ZrO2)x(Al2O3)12x pseudobinary alloys withx;0.75 ~therewas also;1.7% Si in the films!. The films were found toremain amorphous up to 800 °C for 30 min. TiN gates wused to form capacitors, andteq512 Å was achieved withJ50.1 A/cm2 at 1.5 V gate bias. An interface state densityD it;1 – 531011cm2 was reported for the Zr–Al–Si–Ofilms. No channel carrier mobilities were reported.

Other work by van Dover109 examined the effect of awide range of dopants in sputtered TiOx films on film struc-ture and leakage. The incorporation of up to 10% Nd, Tand Dy lanthanide dopants in Ti–O films produced amphous structures with low leakage and high specific captance~no postannealing was done!. Using Pt top electrodesand TiN bottom electrodes, permittivities ranging from 50135 were measured for 350-Å-thick films, while maintainian amorphous layer. Leakage currents of 531027 A/cm2

were obtained at an applied field of 2 MV/cm for each of tcases of Nd, Tb, and Dy doping. Although these matersystems are better-suited for memory capacitors thantransistors~due to thermal instability on Si!, the results indi-cate the importance of considering dopants as a meanreducing leakage current without substantially degradother electrical properties of the high-k dielectric. The par-ticular dopants presumably tie up dangling bond deeplevels associated with unsatisfied cation bonds~Ti in thiscase!, while not introducing deleterious trap levels of theown. A performance improvement is clearly attainable ushigh-k dielectrics such as TiO2. The ultimate success o


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these materials, however, depends on an extremelylevel of quality and control over the channel interface, whihas not yet been demonstrated.

Quaternary silicate films containing Zr and Hf, and posibly other elements, are certainly conceivable, but the mterial which satisfies the demands of technology whilequiring the least change, is preferred. At this point, we wfocus on the Hf–Si–O and Zr–Si–O systems becaof the combination of all their desirable propertielisted earlier and the promising results recenreported.115,116,135–137,143~a!,143~b!,143~c!

One potentially large advantage for silicates is that tclass of materials should have a silicate-Si interface thachemically similar to the SiO2–Si interface, which is unparalleled in quality for transistor channel regions. This is escially important since the channel interface is playingdominant role in determining device performance, andcause almost any simple oxide (MxOy) deposited on Si willform a silicate interfacial layer, even if it is very thin. In thlight, the tetravalent transition metal cations such as Zr aHf offer the advantage of substituting well at Si sites, whiform SiO4 tetrahedra. For the case of forming nonstoichmetric [email protected]., (ZrO2)x(SiO2)y#, wherex andy are notintegers!, a tetravalent cation such as Zr41 or Hf41 ionshould substitute well for Si41, to provide a favorable bonding for a silicate network with low defect densities. In thcase where stoichiometric compounds are formed, then ocations may also work, such as La31 in a compound(La2O3)x(SiO2)12x silicate, wherex50.5.42,143~b!

There has been much less information reported(HfO2)x(SiO2)y than on (ZrO2)x(SiO2)y , but the chemicalsimilarities between Hf and Zr allow for comparison btween the respective silicate systems. As describedBlumenthal,144 and Bragget al.,145 the Bravais lattice for thestoichiometric compound ZrSiO4 ~zircon! is body-centeredtetragonal, and belongs to point groupD4h . The crystal iscomposed of SiO4 tetrahedra interspersed with Zr atoms, bcan be considered as parallel chains of ZrO2 and SiO2 struc-tural unit molecules, as shown in Fig. 20. Each Zr andatom shares bonds to four O atoms within each chain,each successive pair of O atoms is oriented in a transvconfiguration, forming ZrO2 and SiO2 units. The Si–O bondlength is shorter than the Zr–O bond length within a cha

FIG. 20. Structure of crystalline ZrSiO4 showing the Zr bonding to SiO2units. Zr–O bonding also exists in and out of the plane of the page.


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as is represented in the figure. Figure 20 shows that eacatom also shares bonds with other O atoms in neighbochains~only two of the four bonds to neighboring chains ashown for each Zr atom, for clarity!, providing a three-dimensional stability to the material.

It is important to note that each Zr and Si atom has oO atoms as nearest neighbors. Chemical analysis of hogeneous silicate films is therefore expected to show oZr–O nearest-neighbor bonding, with a slight effect fromas a next-nearest neighbor. Although the films presentethis study are amorphous, it is reasonable to assume thaHf and Zr concentrations less than that of the stoichiomeMO2– SiO2 compound, nearly all bonds will be Zr–O~orHf–O! and Si–O bonds.115,116,135–137,143~c!

Using coordination chemistry arguments between Hf aZr, HfSiO4 should have the same structure as ZrSiO4. Avalue of k512.6 for bulk ZrSiO4 was reported byBlumenthal.144 Similarly, since HfO2 has reportedvalues110,146of k521225 ~Ref. 146 also reportsk540, butthis value has not been confirmed in more recent studies!, aHfSiO4 compound is expected to have a range ofk;13– 20. The exact value ofk will certainly depend stronglyon film composition, density and structure~amorphous ma-terials typically have less lattice polarizability than thecrystalline counterparts!. Considering all of the desired properties, (ZrO2)x(SiO2)12x and (HfO2)x(SiO2)12x should beexcellent materials candidates for advanced gate dielectand indeed some very encouraging results have been pously reported.115,116,135–137,143~c!

In the first demonstration of a stable gate dielectric wa teq,20 Å deposited directly on Si, a smooth interface wdemonstrated in the work by Wilk and Wallace for bothand Zr silicate films.135,136Figure 21 shows this interface foa HfO2:SiO2 dielectric with Si at both interfaces where itseen that the annealing required to activate and crystathe amorphous Si@Fig. 21~a!# does not result in a detectabinterfacial layer. Figure 22 shows the results of using Al aAu electrodes in MIS a capacitor evaluation of the Hsilicate layer. It is seen that somewhat lower accumulatcapacitance and somewhat higher leakage current is

FIG. 21. HRTEM image of Hf-silicate between Si layers.~a! After deposi-tion of amorphous Si at 500 °C and~b! after annealing at 1050 °C for 20 s iN2 ~see Ref. 137!.


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served for the Al gate electrode sample. High-resolutTEM ~HRTEM! results, not shown, also indicate a contrachange at the Al/silicate interface, similar to that observedthe case of Al/Zr-silicate structures.137 These results suggesthat Al/silicate reactions likely occur with postdepositioprocessing, as may be expected for silicate materialstems. Leakage current densities, however, remained welllow that for equivalent SiO2 gate dielectric films, withJ,1025 A/cm2 at VG2VFB51 V.

We further note that the potential use of silicate~andperhaps to a lesser extent aluminate! pseudobinary alloy systems as a replacement for SiO2 gate dielectrics, in conventional CMOS processing, arguably represents the historevolution of dielectrics in CMOS technology. Silicon dioxide has been unimaginably ideal for integrated circuits,cause it has been used for decades both as the interdielectric~ILD ! between successive metal interconnect levand as the gate oxide for MOSFETs. Recent technologymands, however, have required that SiO2 in the ILD bemodified to create a lower dielectric constant, so that lowRC time delays can be achieved. These changes havemade by simply incorporating H, F, and C into the SiO2 tolower thek value of the oxide. These modifications, whicertainly not trivial, have thus far proved to be manageain the integration process.

Similar demands for higher drive currents and lowleakage have required SiO2 in the gate dielectric to be altereby adding N, both in the form of doping and as a siliconitride layer on top of SiO2. This process slightly increasethe effective dielectric constant, allowing use of a physicathicker film, and thereby achieves a higher drive current w

FIG. 22. Comparison ofC–V and J–V performance for a MIS structureincorporating Hf silicate. The Al electrode results in interfacial reactio~see Ref. 137!.


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less leakage. With these trends in mind, silicate and alunate gate dielectrics should also be viewed as only anomodification of SiO2. These pseudobinary systems allow fcontrol in obtaining the desired materials properties‘‘doping’’ SiO2 or Al2O3 with Zr or Hf, to further improvedevice performance while remaining compatible with the rof well-established CMOS processing procedures. In facthese silicate films can be used, then by simply increasingdoping level of Zr or Hf from one technology node to thnext for gradually improved device performance, this samaterials system should fulfill the requirements on currroadmaps until the year 2010.

4. High- k device modeling and transport

The incorporation of stacked structures has been invtigated by a number of researchers in recent years. Ascussed previously, the layer within the stack that haslower dielectric constant will limit the overall capacitancethe stack. However, the minimization of interface states mrequire suitable interfacial layers that serve as a transiregion between the Si substrate and the dielectric. Onealso obviously envision a graded composition throughoutdielectric permitting control of interfacial state formatiowhich preserves, to some extent, the high-k propertiessought for the alternative gate dielectric in the gate stack

Vogel et al.147 considered such effects in a modelpotential gate stack materials. As acknowledged in the wthe model does not incorporate trap assisted tunnemechanisms but does provide an indication of the trendssociated with stack layers and scaling.

As seen in Fig. 23~a!, tunneling currents associated wiidealized gate dielectrics (teq52 nm) are reduced dramatcally in the voltage regime anticipated for future devic(VDD;1 V). Dielectric constants assumed for each cuarek53.9(SiO2), 7.5(Si3N4), 5.7(SiOxNy), 25 ~D1!, and 30~D2!. It is noted in that work, however, that it is more beeficial for a suitable alternate dielectric to exhibit a barrslightly higher thanVDD in order to minimize tunneling,rather than a slightly higher dielectric constant. This is sein the cross over point in the tunneling current for candiddielectrics D1 and D2.

The incorporation of an interfacial SiO2 layer ~0.5 and1.0 nm thick! as a part of a gate stack is examined in F23~b!. The effect of electron injection through this interfacilayer from either the gate or the substrate is also examby simply changing the direction of the electric field. In adition to the expected reduction in the overall tunneling crent, it is seen that the tunneling current changes substially depending on the dielectric layer first encounteredthe electron.

This can be understood by consideration of the dielecband diagrams associated with the stacked structure~Fig.24!. For a 1 nm SiO2 interfacial layer, it can be seen in Fig24~a! that an electron with a suitable energy~from Vins522.68 V! that first encounters the SiO2 layer avoids the bar-rier associated with the high-k layer, D1. Tunneling from theopposite direction, however, results in encounters withbarriers associated with both layers and a concomitant exsive reduction in tunneling~leakage! current.


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For an even thinner SiO2 layer, electrons of the samenergy as that in Fig. 24~a! encounter substantial regionassociated with the high-k barrier @Fig. 24~b!#. Hence, forhigher biases, the electron will eventually encounter onlybarrier associated with the interfacial layer and thereforsubstantial increase in tunneling current would be evid@cf. to Fig. 23~b!#.

In an attempt to predict the effect of high-k gate dielec-trics on transistor performance, Franket al.148 modeled gatedielectrics with various permittivities in a planar, buCMOS structure. It was reported that the upper limit of pmittivity would be limited to k;20 due to fringing field-induced barrier lowering at the drain region of the devic

FIG. 23. ~a! Tunneling current calculated for gate dielectrics in an 1pcapacitor structure exhibiting an equivalent oxide thickness ofteq52 nm.~b! Tunneling current calculated for stacked structures. The layer listedis the layer initially encountered by the tunneling electron. Interfacial S2

layers 0.5 and 1 nm thick are considered~see Ref. 147!. © 1998 IEEE,reprinted with permission from IEEE.


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This phenomenon is a large concern, because a signififringing field from the edge of a high-k dielectric couldlower the barrier for transport into the drain enough to seously degrade the on/off characteristics of the device. Krinanet al.149 reported similar modeling results for high-k gatedielectrics, but also claimed that a dielectric stack with S2at the channel interface could reduce any barrier-lowereffects from the high-k fringing fields.150

Perhaps even more important is the issue of field petration into the Si channel region.148 The inversion charge inthe channel experiences an increasing electric field withcreasing gate capacitance, regardless of the gate dielematerial. At a high enough electric field penetration throuthe gate dielectric, channel carriers will undergo increascattering, ultimately leading to adecreasein mobility anddrive current. Additionally, this inversion layer will have aassociated capacitance in series with the gate stack andalso eventually limit the ultimate gate stack capacitanceany high-k dielectric.26

This effect was first reported by Timpet al.20 using pureSiO2, as 30 nm gate length transistors showed that forteq

,13 Å, the drive current actually decreased. If this phenoenon causes a degradation in device performance forteq

,11– 13 Å, then tradeoffs may have to be consideredtechnologies using these materials.23

VI. MATERIALS PROPERTIES CONSIDERATIONS

All of the materials systems discussed earlier must ma set of criteria to perform as successful gate dielectric.

FIG. 24. Band diagrams for results in Fig. 23~b!. ~a! 1 nm SiO2 interfacelayer, ~b! 0.5 nm interface layer. The injection polarity~and energy! of theelectron results in sampling different portions of the barriers associatedeach dielectric~see Ref. 147!. © 1998 IEEE, reprinted with permission fromIEEE.


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now consider a summary of the appropriate materials prerties for the selection of materials for gate dielectric appcations.

A. Permittivity and barrier height

Selecting a gate dielectric with a higher permittivity thathat of SiO2 is clearly essential. For many simple oxidepermittivities have been measured on bulk samples ansome cases even on thin films, but for the more compmaterials~more elemental constituents!, the dielectric con-stants may not be as well known. Shannon151 used a methodinvolving the Classius–Mossoti equation for calculatiionic polarizabilities as a means to make predictions of pmittivities for many dielectrics. Good agreement has befound for some materials, but there are also many casepoor agreement between calculated and measured vaThis discrepancy between calculation and measurementbe attributed to many factors, including film thicknesmethod of film deposition, and local electronic structuwithin the dielectrics. It is clear that much more experimetal data is needed for measurements of dielectric constanthese high-k dielectrics, particularly below the 100 Å thickness regime.

The required permittivity must be balanced, howevagainst the barrier height for the tunneling process. For etrons traveling from the Si substrate to the gate, this isconduction band offset,DEC>q@x2(FM2FB)#; for elec-trons traveling from the gate to the Si substrate, this isFB

~see Fig. 4!. This is because leakage current increases exnentially with decreasing barrier height~and thickness! forelectron direct tunneling transport,9,10 as shown in Eq.~12!:

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Herel is the interval of separation between adjacent hping sites,n* is the density of free electrons in the dielectriandG is the mean hopping frequency. Leakage current adepends on other factors, including the structure of the laas discussed later in Sec. VI D. In order to obtain low leaage currents, it is desirable to find a gate dielectric that halargeDEC value to Si and perhaps to other gate metals whmay be used at some point. Reported values ofDEC for mostdielectric-Si systems are scarce in the literature, but reccalculations by Robertson and Chen152 indicate that many ofthe metal oxide and complex oxide materials, such as Ta2O5

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and SrTiO3, will have DEC,0.5 eV on Si. On the othehand, an expanded study by Robertsonet al.153 includesmany more high-k dielectrics which are currently under investigation ~see Fig. 25!. Robertson found thatDEC

;2.3–2.8 eV for Al2O3 and Y2O3, and DEC;1.5 eV forZrO2 and ZrSiO4, as illustrated in Fig. 25.153

These calculations are an important insight into preding relevant barrier height~such asDEC! values for manypotential dielectrics based on the charge neutrality levethe material. If the experimentalDEC values for these oxideare even much less than 1.0 eV, it will likely preclude usithese oxides in gate dielectric applications, since electransport~either by thermal emission or tunneling! wouldlead to unacceptably high leakage currents. Since manytential gate dielectrics do not have reportedDEC values, theclosest, most readily attainable indicator of band offset isband gap (EG) of the dielectric. A largeEG generally corre-sponds to a largeDEC ~see Table I!, but the band structurefor some materials has a large valence band offsetDEV

which constitutes most of the band gap of the dielectric. Tuncertainty places more importance on predictive methsuch as that demonstrated by Robertson.152,153

As noted before, it is extremely difficult to achieve thjuxtaposition of these high-k dielectrics on Si, as anSiO2-like interface usually forms. This interface layer will ocourse alter theDEC value of the system, and must be takinto consideration when comparing measured and calculresults.

Referring back to Table I, a list of several metal oxi~and nitride! systems, some of which have been investigaas gate dielectrics, compares values fork and EG , alongwith DEC values on Si where available. For these highkmaterials, Table I indicates thatEG will be somewhat lim-ited, since it can be seen that the dielectric constant and bgap of a given material generally exhibit an inverse relatiship ~although some materials have significant departufrom this trend!.

The detailed relationship between permittivity and bagap is by no means trivial, since many factors give riseboth properties. There are two main contributions of inter

FIG. 25. Band offset calculations for a number of potential high-k gatedielectric materials~see Refs. 152 and 153!.


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to the dielectric constant which give rise to the polarizabilielectronic and ionic dipoles~the molecular dipole contribution is not relevant to this study!. Figure 26 illustrates thefrequency ranges where each contribution is important,also highlights the current frequency range for CMOS opetion ~100 MHz–10 GHz!.154 In general, atoms with a largeionic radius~e.g., high atomic number! exhibit more electrondipole response to an external electric field, because theremore electrons to respond to the field~electron screeningeffects also play a role in this response!. This electronic con-tribution tends to increase the permittivity for oxides of ements with higher atomic numbers.

The ionic contribution to the permittivity can be muclarger than the electronic portion in cases such as perovscrystals of ~Ba, Sr!TiO3 and ~Pb, Zr!TiO3 ~which exhibitferroelectric behavior below the Curie point!. In these casesTi ions in unit cells throughout the crystal are uniformdisplaced in response to an applied electric field~for the caseof ferroelectric materials, the Ti ions reside in one of twstable, nonisosymmetric positions about the center ofTi–O octahedra!. This displacement of Ti ions causes aenormous polarization in the material, and thus can giveto very large dielectric constants of 2000–3000. Since iorespond more slowly than electrons to an applied field,ionic contribution begins to decrease at very high frequcies, in the infrared range of;1012Hz, as shown in Fig. 26.

We note that some of the potential candidate matermay have other contributions to the permittivity, which dnot exhibit the same phenomena as the perovskites. Thedition of certain levels of network modifier ions~e.g., Zr orHf! to materials such as SiO2 can produce an increased delectric constant even at low incorporation levels, througdiscernable change in the bond order of the material. Lucsky and Rayner155 describe this effect for several experimetal cases, where the localized bonding order, which chanwith Zr ~or Hf! concentration, results in substantial changin the vibrational modes in the associated infrared spectrthe silicate. This effect can be further modeled to demstrate that a transverse effective charge scales inverselyZr ~Hf! concentration, and the contribution of the vibrationmode to the dielectric constant is proportional to the squof this effective charge. As a result, an enhancement indielectric constant, over that expected by simple linear inpolation between SiO2(k53.9) and ZrSiO4(k512), may beexpected at low concentrations for these materials~see bond-

FIG. 26. The frequency dependence of the real (« r8) and imaginary (« r9)parts of the dielectric permittivity. In CMOS devices, ionic and electroncontributions are present~see Ref. 154!.


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ing model in Fig. 20!. Recent independent measurementsthe enhanced dielectric constants have also bconfirmed.143~a!,143~b!,143~c!

Another phenomenon which can contribute to ancreased dielectric constant involving atom motion is sphonons. This differs from a non-volatile polarization~e.g.,as found in ferroelectrics!, in that the atoms do not remaidisplaced after the electric field is removed~ferroelectricityis the limit at which certain cations remain displaced in oof two stable positions after the external field is remove!.Rather, higher atomic number atoms can resonate in tbonding structures at low vibrational frequency modwhich produces a soft phonon~since it is at relatively lowfrequency!. These phonons then make a lattice contributto the overall polarizability, and therefore to the permittiviof the material. It appears that some of the high-k dielectricsof interest exhibit the earlier-mentioned effects, leadingsubstantially increased permittivities even at compositiwith low metal levels. By achieving good bonding modelsthese materials, some of these materials properties can bto be better understood and predicted, as a way to optimthe choice of dielectric for this application.

It is therefore reasonable to expect any intrinsic conbution to the dielectric constant will be maintained for resonable device operation frequencies, although other exsic factors such as defects may lead to an effective decrin permittivity at much lower frequencies.

In contrast to the general trend of increasing permittivwith increasing atomic number for a given cation in a meoxide, the band gapEG of the metal oxides tends todecreasewith increasing atomic number, particularly within a particlar group in the periodic table. An intuitive explanation fthis phenomenon is that the corresponding bonding and abonding orbitals of the metal-oxygen atoms form a valenband and a conduction band, respectively. For the casSiO2, the s bonds formed by thesp hybrid orbitals~whicharise from Si s,p and O p orbitals! have as bonding orbitalenergy level and a highers* antibonding orbital energylevel. The energy separation between these levels definband gap, but this may or may not be the minimum bandin the material. For even the simple case of SiO2, wherethere are onlys and p electron orbitals that are all filledduring bonding, the oxygen electron lone pair energy leactually defines the valence band maximum~rather than thes bonding energy level!. The result is the often reporteband gap of SiO2 ,EG;9 eV. If thes ands* bonds definedthe valence band maximum and conduction band minimrespectively, then the band gap of SiO2 would be larger.

Thus for the transition metal oxides, which all have fid electron orbitals and other non-bondingp orbitals, the bandgaps of these oxides can be significantly decreased bypresence of partially filledd orbitals, which have availablestates for electron occupancy. These orbital energy letend to lie within the gap defined by thes ands* orbitals.The d orbital levels which lie within the gap defined bysands* levels are all therefore available for electron condution at significantly lower energy levels than would be epected froms ands* alone. This effect offers a somewhintuitive explanation regarding the lower band gaps that


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often observed for higher atomic number metal oxides, pticularly for the transition metals. It is important to note ththese partially filled and nonbonding levels arenot the resultof defects within the material, but rather areintrinsic to suchatomic constituents where many orbitals are availableelectron conduction. This general band gap reductionhigher-k materials is a limitation that must be realized aexpected when selecting a suitable high-k gate dielectric.

In the cases of Ta2O5 and TiO2, both materials havesmall EG values and correspondingly smallDEC values.These smallDEC values directly correlate with high leakagcurrents for both materials, making pure Ta2O5 and TiO2

unlikely choices for gate dielectrics. Table I also showhowever, that La2O3, HfO2, and ZrO2 offer relatively highvalues for bothk andEG . It is important to note that all ofthe high-k metal oxides listed in Table I, which includethose studied for gate dielectric applications, are crystalat relatively low temperature~except Al2O3!. The signifi-cance of the film structure will be further discussed in SVI D.

Although many researchers originally assumed thatlecting a dielectric withk.25 would be necessary to replacSiO2, the more relevant consideration is whether the desdevice performance~i.e., drive current! can be obtained athe prescribed operating voltage without producing unceptable off-state~leakage! currents and reliability characteristics. It is therefore more appropriate to find a dielectwhich provides even a moderate increase ink, but whichalso produces a large tunneling barrier and high-qualityterface to Si. With this in mind, if a single dielectric layecan be used, then even a material withk;12– 20 will allowa physical dielectric thickness of 35–50 Å to obtain theteq

values required for 0.1mm CMOS and beyond.

B. Thermodynamic stability on Si

For all thin gate dielectrics, the interface with Si playskey role, and in most cases is the dominant factor in demining the overall electrical properties. Most of the highkmetal oxide systems investigated thus far have unstableterfaces with Si: that is, they react with Si under equilibriuconditions to form an undesirable interfacial layer. Thematerials therefore require an interfacial reaction barriermentioned previously. Any ultrathin interfacial reaction barier with teq,20 Å will have the same quality, uniformityand reliability concerns as SiO2 does in this thickness regime. This is especially true when the interface plays atermining role in the resulting electrical properties. It is important to understand the thermodynamics of these systeand thereby attempt to control the interface with Si.

An important approach toward predicting and undstanding the relative stability of a particular three-componsystem for device applications can be explained throughnary phase diagrams.156,157 An analysis of the Gibbs freeenergies governing the relevant chemical reactions forTa–Si–O and Ti–Si–O ternary systems, as shown in F19~a! and 19~b!, indicates that Ta2O5 and TiO2 ~or mixtureswith Si!, respectively, are not stable to SiO2 formation whenplaced next to Si. Rather, the tie lines in~a! and~b! show that


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Ta2O5 and TiO2 on Si will tend to phase separate into SiO2

and metal oxide~MxOy , M5metal!, and possibly silicide(MxSiy) phases. The phase diagrams in Figs. 19~a! and 19~b!are shown for temperatures of 700–900 °C, but these rtions are also valid at much lower temperatures. As mtioned in Sec. I, this instability to SiO2 formation has beenobserved experimentally for both of these metal oxides,75,103

which leads to the necessity for an additional interfaclayer.

In contrast to the Ta and Ti systems, the tie lines inphase diagram for the Zr–Si–O system,158 shown in Fig.19~c!, indicate that the metal oxide ZrO2 and the compoundsilicate ZrSiO4 will both be stable in direct contact with Si uto high temperature. The gray shaded area in Fig. 19~c! de-notes a large phase field of (ZrO2)x(SiO2)12x compositionswhich are expected to be stable on Si up to high temptures. Other (ZrO2)x(SiO2)12x compositions outside of thegray area are also stable on Si, but since it is desirablprevent any Zr–Si bonding, film compositions within thgray area may be preferable. Furthermore, even withinshaded area, compositions with high O levels~closer toZrSiO4! are preferred because this will be more likelyprevent M–Si bond~and silicide phase! formation. In fact,the existence of this large phase field of sta(ZrO2)x(SiO2)12x compositions implies yet another potetial advantage, in that the level of Zr~or Hf! incorporatedinto the silicate film could be gradually increased from otechnology node to the next. This gradual shift in film coposition could provide a continually higherk value ~up to apoint!, as is needed to meet device performance requments.

This behavior is expected to be the same for the HSi–O system based on coordination chemistry argumeAlthough the thermodynamic information is incomplete fthe Hf–Si–O system, the available data suggests that H2

and HfSiO4, as well as a large range of (HfO2)x(SiO2)12x

compositions, will be stable in direct contact with Si uphigh temperatures.159–161 This fundamental difference fromthe Ta and Ti systems is extremely important, becaussuggests that there is potential to control the dielectricinterface. While it is certainly the case that all deposititechniques of interest are done under nonequilibrium cotions, it is unlikely that a desirable, metastable phase, sucamorphous Ta2O5 ~which can be obtained under nonequilirium deposition conditions!, will be maintained throughouall of the thermal cycling required for CMOS processinEven in the case of process modifications such as a repment gate flow,69 which allows the high-temperature processing to be done before deposition of the final gate dietric, the continued thermal cycling afterward is sufficientresult in poor electrical properties.69 It is therefore importantto select a materials system in which the desired final staa stable one.

Figure 19~c! indicates that use of (ZrO2)x(SiO2)12x

@and therefore (HfO2)x(SiO2)12x# should allow for controlof the Si interface, which may solve a key problem for thigh-k gate dielectric materials approaches. Thek values of(HfO2)x(SiO2)12x and (ZrO2)x(SiO2)12x are substantiallylower than those of pure HfO2 and ZrO2, but as mentioned in


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Sec. VI A, this tradeoff for interfacial control will be accepable as long as the resulting leakage currents are low eno

C. Interface quality

A clear goal of any potential high-k gate dielectric is toattain a sufficiently high-quality interface with the Si chanel, as close as possible to that of SiO2. It is difficult toimagine any material creating a better interface than thaSiO2, since typical production SiO2 gate dielectrics have amidgap interface state densityD it;231010states/cm2. Mostof the high-k materials reported in this paper showD it

;1011– 1012states/cm2, and in addition exhibit a substantiaflatband voltage shiftDVFB.300 mV ~possibly from fixedcharge density*1012/cm2 at the interface!. It is crucial tounderstand the origin of the interface properties of ahigh-k gate dielectric, so that an optimal high-k–Si interfacemay be obtained.

Recent work by Lucovskyet al.58 previously has shownthat bonding constraints must also be considered at thedielectric interface. It is shown empirically58 that if the av-erage number of bonds per atomNav.3, the interface defecdensity increases proportionally, with a corresponding dradation in device performance. Metal oxides which contelements with a high coordination~such as Ta and Ti! willhave a highNav, and form an overconstrained interface wiSi. Degradation in leakage current and electron channelbility is therefore expected. Similarly, cations with low coordination~e.g., Ba, Ca! compared to that of Si lead to underconstrained systems in the corresponding metal oxiThese systems~metal oxides, ternary alloys, etc.! which areeither over- or underconstrained with respect to SiO2, lead toformation of a high density of electrical defects near tSi-dielectric interface, resulting in poor electrical propertie

These bonding arguments can be extended to silicformation in the gate dielectric, or even to any M–Si boning ~not necessarily a full silicide phase!. Any silicide bond-ing which forms near the channel interface~as may resultwhen a metal oxide is placed in direct contact with, or neSi!, will tend to produce unfavorable bonding conditionleading to poor leakage current and electron channel moties. In order to maintain a high-quality interface and chanmobility, it is expected to be important to have no meoxide or silicide phases present at or near the channel inface.

It is interesting to consider the binary oxides which amore thermally stable than SiO2, some of which are shownin Table I, including Al2O3, Y2O3, La2O3, ZrO2, and HfO2

~also covered in a thorough study by Hubbard aSchlom!.157 The requirement on bonding constraints metioned earlier, however, may significantly reduce the listmaterials. Although Al2O3 is a special case in the way thaAl cations bond within the network~alternating Al–O tetra-hedra and octahedra!, Y2O3 and La2O3 are underconstrainedand may therefore form very high defect densities atchannel interface. More highly coordinated metals suchNb, V, and Mn are not only overconstrained, but each ahas several different stable oxidation states, and will thefore lead to oxygen vacancies and electron trap sites. In


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dition to binary systems, pseudobinary systems are excecandidates for gate dielectrics. Adding a third componenan alloy or network may favorably affect the materialterms of thermal stability, bonding constraints and in mphology.

Several simple oxides such as ZrO2 and HfO2 have beenpreviously reported as having high oxygen diffusivities.112

This is a serious concern regarding control of the interfonce it is initially formed. Any annealing treatments whichave an excess of oxygen present~either from the ambient ofrom a sidewall oxide, for example!, will lead to rapid oxy-gen diffusion through the oxides, resulting in SiO2 orSiO2-containing interface layers. Although we have alreashown that SiO2 is an ideal interface with Si, an uncontrolleamount of SiO2 formation at the interface will severely compromise the capacitance gain from any high-k layers in thegate stack. Caution must therefore be used in assessininterface stability of high-k dielectrics, as resistance to oxygen diffusion in annealing ambients should be characterizAnother annealing ambient of concern is forming gas~typi-cally 90% N2:10%H2!, which is a standard final anneal ithe CMOS process and is believed to passivate interfatraps ~dangling bonds! with hydrogen. Since many high-kdielectrics will be reduced in the presence of H2 ~the Ti-containing perovskites are all severely reduced by eventemperature anneals in forming gas!, high-k gate dielectricsalso need to be characterized with respect to the effecanneals in reducing ambients.

The ideal gate dielectric stack may well turn out to haan interface comprised of several monolayers of Si–O~andpossibly N! containing material, which could be a pseudonary layer, at the channel interface. This layer could servpreserve the critical, high-quality nature of the SiO2 interfacewhile providing a higher-k value for that thin layer. Thesame pseudobinary material could also extend beyondinterface, or a different high-k material could be used on toof the interfacial layer.

D. Film morphology

Most of the advanced gate dielectrics studied to dateeither polycrystalline or single crystal films, but it is desable to select a material which remains in a glassy ph~amorphous! throughout the necessary processing treatmeAs shown in Table I, nearly all metal oxides of interest, wthe exception of Al2O3, will form a polycrystalline film ei-ther during deposition or upon modest thermal treatmeHfO2 and ZrO2 are no exceptions. It is important to nothowever, that the phases listed in Table I are bulk properand there will certainly be some suppression of crystallition for very thin films such as gate dielectrics, at tempetures where crystallization would otherwise be expectedoccur. The extent of crystallization suppression for a givoxide will depend on composition and thermal processin

Polycrystalline gate dielectrics may be problematic bcause grain boundaries serve as high-leakage paths, anmay lead to the need for an amorphous interfacial layereduce leakage current. In addition, grain size and orientachanges throughout a polycrystalline film can cause sign


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cant variations ink, leading to irreproducible properties. Thpreviously mentioned studies by Houssaet al.118 and Perkinset al.,127 however, appear to be counter-examples, as breported very encouraging electrical properties for ALCVZrO2. It should be noted, however, that both studies aused a gate dielectric stack, with the ZrO2 film on top of anamorphous SiO2 layer. It is unclear at this point to whaextent the amorphous SiO2 layer affords the encouraginelectrical properties, but this issue will become important,the SiO2 layer presents a limit to the minimum achievableteq

value for these structures.Work by van Dover,109 as previously discussed, use

lanthanide dopants in TiOx films to create and maintain aamorphous film for capacitor applications, even though T2

is typically crystalline even at low temperatures~see TableI!. Very encouraging results were obtained, as both high pmittivities and low leakage currents were achievable wNd, Tb, and Dy dopants. Although these particular films anot stable on Si, similar approaches may be useful for gdielectrics.

Single crystal oxides grown by MBE methods82,98can inprinciple avoid grain boundaries while providing a good iterface, but these materials also require submonolayer dsition control, which may only be obtainable by MBE aproaches~see Sec. VI F for further discussion on the MBdeposition method!. Kwo et al.98 formed capacitors withsingle-domain, crystalline Gd2O3 films on Si by MBE, whichhad no apparent interfacial layer according to infraredsorption spectroscopy~not shown in the article!. The leakagecurrent for these films was 1023 A/cm2 at 1 V bias, andC–Vanalysis showedk;14, while some frequency dependenwas observed and the permittivity decreased with decreafilm thickness.98 For perovskite materials such as SrTiO3,where the structure consists of alternating SrO and T2

planes, each single atomic-height step edge~which alwaysexist on the surface of Si wafers! may possibly serve asnucleation site for an antiphase boundary and possiblgrain boundary. As will be discussed in Sec. VI E, anythese dielectrics which require interfacial layers on thechannel~to avoid reaction between the high-k material andSi! will also require metal gate, or perhaps a buffer layerthe poly-Si gate interface. In contrast, amorphous films wexhibit isotropic electrical properties, will not suffer fromgrain boundaries, and can easily be deposited by manuturable techniques.

Given the concerns regarding polycrystalline and sincrystal films, it appears that an amorphous film structurethe ideal one for the gate dielectric~although some initialelectrical results for a polycrystalline ZrO2 layer on an amor-phous SiO2-containing layer look encouraging!. This is yetanother clear virtue of SiO2. The Zr–Si–O system in Fig17~c!, and analogously the Hf–Si–O system, indicates tthe only stable ternary crystalline compound is ZrSiO4 ~orHfSiO4!. While it is possible that other ternary crystallincompounds do exist, it is unlikely. Bulk thermodynamitherefore suggests that a phase field@gray shaded area in Fig17~c!# exists for relatively low levels of Zr or Hf in which a(ZrO2)x(SiO2)12x or (HfO2)x(SiO2)12x composition can beobtained which will remain amorphous and stable on Si up


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E. Gate compatibility

A significant issue for integrating any advanced gateelectric into standard CMOS is that the dielectric shouldcompatible with Si-based gates, rather thanrequire a metalgate. Si-based gates are desirable because dopant imconditions can be tuned to create the desired thresholdageVT for bothnMOS andpMOS, and the process integration schemes are well established in industry. Nearly allthe potential advanced gate dielectrics investigated topoint, however, require metal gates. This is expected becthe same instability with Si, mentioned in Sec. VI B, wexist at both the channel and the poly-Si gate interfaces

Specifically, metal gates such as TiN and Pt have bused with most of the high-k gate dielectrics mentioneabove to prevent reaction at the gate interface. Attempts hbeen made to use doped poly-Si gates with Ta2O5, by depos-iting a CVD SiO2 reaction barrier, which is of lower electrical quality than thermal oxide, on top of the Ta2O5 layer.71

The presence of SiO2 at both the channel and gate interfapredictably limited the device performance, and the lowobtainable oxide equivalent wasteq523Å. Even initial at-tempts to use poly-Si gates with ZrO2

116,120 have been un-successful~recent work, however, has shown improvpoly-Si stability on HfO2!,

125,126as reaction layers have beeobserved at the interface. On the other hand, another beof a pseudobinary system such as a silicate116,137 in contactwith a poly-Si electrode is more inherent stability, sincesignificant amount of Si is already contained within theelectric. Al2O3 has been shown to be stable with respectreaction with the poly-Si gates throughout typical CMOprocessing, as expected.90–92 As mentioned previously inSec. V C 1, however, both boron and phosphorous dopdiffusion have been observed with Al2O3 gate dielectrics,which cause significant, undesired shifts ofVFB and VT

values.90,92These results place more emphasis on the neebetter understand dopant diffusion through all potenhigh-k candidates.

Metal gates are very desirable for eliminating dopadepletion effects and sheet resistance constraints. In adduse of metal gates in a replacement gate process69,139 canlower the required thermal budget by eliminating the nefor a dopant activation anneal in the poly-Si electrode. Thare two basic approaches toward achieving successful intion of metal electrodes: a single midgap metal or two serate metals. The energy diagrams associated with theseapproaches are shown in Fig. 27.

The first approach is to use a metal~such as TiN! thathas a work function that places its Fermi level at the midgof the Si substrate, as shown in Fig. 27~a!. These are generally referred to as ‘‘midgap metals.’’ The main advantageemploying a midgap metal arises from a symmetricalVT

value for bothnMOS andpMOS, because by definition thsame energy difference exists between the metal Fermi land the conduction and valence bands of Si. This affordsimpler CMOS processing scheme, since only one mask


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one metal would be required for the gate electrode~no ionimplantation step would be required!.

For the case of sub-0.13mm bulk CMOS devices, how-ever, a major drawback is that the band gap of Si is fixed1.1 eV, thus the threshold voltage for any midgap metalSi will be ;0.5 V for bothnMOS andpMOS. Since voltagesupplies are expected to be<1.0 V for sub-0.13mm CMOStechnology,VT;0.5 V is much too large, as it would bdifficult to turn on the device. Typical threshold voltages fthese devices are expected to be 0.2–0.3 V. Compensaimplants can be made in the channel to lower theVT , butother concerns then arise regarding increased impurityscattering, which would degrade the channel carrier mobilFurthermore, midgap work function metal gate systems hbeen predicted not to provide a performance improvemworthy of the added process complexity to replace Si-bagates.162

The second main approach toward metal electrodesvolves two separate metals, one forpMOS and one fornMOS devices. As shown in Fig. 27~b!, two metals could bechosen by their work functions,FM , such that their Fermilevels line up favorably with the conduction and valenbands of Si, respectively. In the ideal case depicted in F27~b!, the FM value of Al could achieveVT;0.2 V fornMOS, while the higherFM value of Pt could achieveVT

;0.2 V for pMOS. In practice, Al is not a feasible electrodmetal because it will reduce nearly any oxide gate dielecto form an Al2O3-containing interface layer. Other metawith relatively low work functions, such as Ta and TaNhowever, are feasible gate metals fornMOS. Similarly forpMOS, Pt is not a practical choice for the gate metal, sinit is not easily processed, does not adhere well to mostelectrics, and is expensive. Other elemental metals with hFM values such as Au are also not practical, for the sareasons as for Pt.

As an alternative to elemental metals, conducting meoxides such as IrO2 and RuO2, which have been studied foyears in DRAM applications,1 can provide highFM valuesin addition to affording the use of standard etching and pcessing techniques. Alloys of these and similar conductoxides can also potentially be fabricated to achieve a deswork function. Regarding potential gate electrodespMOS devices, Zhonget al.163,164 made initial measure-ments of the important properties of RuO2, including thermalstability up to 800 °C, a low resistivity of 65mV cm, and ameasured work function ofFM55.1 eV. All of the measure-ments were made on capacitors with both SiO2 and Zr-

FIG. 27. Energy diagrams of threshold voltages fornMOS and pMOSdevices using~a! midgap metal gates and~b! dual metal gates.


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silicate dielectrics. More work must be done to better undstand alternative metal electrodes, both for midgap metaldual metal approaches, as a means to alleviate potentlimiting properties of doped poly-Si.

It should also be noted that for the scaling trend to s0.1 mm CMOS, other efforts are focused on using poSi12xGex gates for achieving higher boron activatiolevels165,166 and therefore better performance inpMOS de-vices, and potentially better performance innMOS devicesas well.166 It is therefore still desirable to employ a gadielectric which will be compatible in direct contact witSi-based gates. The pseudobinary alloys mentioned inV C 3 are predicted to be stable next to Si-based gatesas wellas metal gates. Since doped poly-Si is the incumbent gelectrode material, however, dopant diffusion studies mbe carried out to determine how dopants in poly-Si diffuthrough any potential high-k gate material.

For CMOS scaling in the longer term, however, curreroadmap predictions indicate that poly-Si gate technolowill likely be phased out beyond the 70 nm node, after wha metal gate substitute appears to be required.5 It is thereforealso desirable to focus efforts on dielectric materials systewhich are compatible with potential metal gate materialskey issue for gate electrode materials research will becontrol of the gate electrode work function~Fermi level! af-ter CMOS processing.

F. Process compatibility

A crucial factor in determining the final film quality anproperties is the method by which the dielectrics are depited in a fabrication process. The deposition process fordielectric must be compatible with current or expectCMOS processing, cost, and throughput. Since all of thesible deposition techniques available occur under nonequrium conditions, it is certainly possible to obtain propertidifferent from those expected under equilibrium conditioIt is therefore important to consider the various methodsdepositing the gate dielectrics, and the following techniqwill be discussed here: physical vapor deposition~PVD!~e.g., sputtering and evaporation!, CVD, ALCVD, and MBE.

PVD methods have provided a convenient meansevaluate materials systems for alternate dielectric appltions. The damage inherent in a sputter PVD process, hever, results in surface damage and thereby creates unwainterfacial states. Additionally, device morphology inhereto the scaling process generally rules out such line-of-sPVD deposition approaches. For this reason, CVD methhave proven to be quite successful in providing uniform cerage over complicated device topologies.

As pointed out, the reaction kinetics associated with fiCVD deposition require careful attention in order to continterfacial layer formation. The precursor employed in tdeposition process must also be tailored to avoid unwanimpurities in the film as well as permit useful final compsitions in the dielectric film. Indeed, a graded compositfor dielectric films may be a key requirement in ordercontrol interface state formation to a level comparableSiO2. The recent application of ALCVD methods for depo


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vide much promise, where self-limiting chemistries are eployed to control film formation in a layer-by-layer fashioAs discussed before, attention to the surface preparationthe resultant chemistry must be carefully considered.

In addition to the examples discussed above which eploy PVD and CVD methods, very high-k dielectrics, suchas SrTiO3 have been deposited directly on Si using MBmethods~Fig. 11!. An equivalent oxide thickness of less tha10 Å was reported~physical thickness 110 Å! with dramaticimprovements in transistor performance~Fig. 10!. More re-cently, crystalline ZrO2 ~stabilized by Y2O3) has also beenexamined by MBE methods.167 However, a manufacturablescaled CMOS process incorporating MBE methods, withinherent poor throughput relative to present Si-based facation operations, remains a clear challenge. Furthervances in ALCVD approaches, however, may make spolycrystalline dielectrics a reality in the manufacturing evironment.

G. Reliability

As previously discussed in Sec. IV B, the electrical reability of a new gate dielectric must also be considered crcal for application in CMOS technology. The determinatiof whether or not a high-k dielectric satisfies the strict reliability criteria requires a well-characterized materiasystem—a prospect not yet available for the alternate dietric materials considered here. The nuances of~1! the depen-dence of voltage acceleration extrapolation on dielecthickness and~2! the improvement of reliability projectionarising from improved oxide thickness uniformity, both dicussed in Sec. IV B, have only recently become understodespite decades of research on SiO2. This further emphasizesthe importance and urgency to investigate the reliabicharacteristics of alternative dielectrics, as these mateare sure to exhibit subtleties in reliability that differ fromthose of SiO2.

This being stated, some preliminary projections for reability, as determined by stess-induced leakage cur~SILC!, time-dependent dielectric breakdown, and metime to failure measurements, appear to be encouragingAl2O3

89–91 and HfO2 films.122,124 Similar preliminary mea-surements of ZrO2 films appear to be somewhat mixed,both very promising114 and less encouraging139 results havebeen reported. Despite excellent ten-year reliability projtions at high applied voltages of 2.0–2.5 V reported for thematerials,89–91,114,122,124it is essential to carry out proper arescaling conversion, to account for the difference betweindividual capacitors in these cases, and a full chip arearealistic situation.32 Proper area scaling can significantly dgrade the ten-year reliability projection. Results of reliabilinvestigations for pseudobinary alloys are not yet publishIt is clear, however, that the determination of the preferdielectric constituent composition has yet to be complethus making even initial reliability extrapolations problematic. Moreover, recent lessons from the scaling changessociated with ultrathin SiO2 may come into play with thesenew materials. Clearly, more work in production-worthy d


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velopment fabrication facilities will be required to criticalladdress these issues.

VII. CONCLUSIONS

A review of the state-of-the-art of the ongoing reseafor an alternative gate dielectric to SiO2 for Si-based CMOSwas presented. Key materials considerations discussedclude:~a! permittivity, band gap, and barrier height,~b! ther-modynamic stability on Si,~c! interface quality,~d! filmmorphology,~e! gate compatibility,~f! process compatibility,and ~g! reliability. A material which satisfies all of thesconsiderations has yet to be determined, but several proing candidates have been identified. The pseudobinary mrials systems, however, currently offer the most promiseward the ultimate goal of integrating a gate dielectric infuture CMOS technology nodes. Whether pseudobinaryterials are best-suited as an interfacial layer to Si withhigher-k layer on top, or are able to comprise the entire gdielectric stack remains to be determined. Extensive reseand development efforts are underway to narrow the fieldcandidates further.

Any potential alternative dielectric faces several fundmental concerns, in addition to those outlined earlier, regaing CMOS scaling which must be better understood aovercome before successful insertion of a new materialoccur. These fundamental limitations include fixed chardopant depletion in the poly-Si gate electrode, and ancreasing electric field in the channel region, which decreadevice performance. Furthermore, dopant diffusion chateristics, failure mechanisms, and reliability of any potenhigh-k dielectric need to be understood. The semiconducindustry has enjoyed the excellent reliability characterisof SiO2 for many years, but any new material will certainexhibit different behavior, which may or may not have deterious effects on device performance. The stringentquirements for ten year reliability of CMOS devices will ba demanding challenge on any high-k materials candidates.

An even greater challenge is the adoption of a new cdidate in the time frame required by the industry roadm~;4–5 years! in order to maintain cost/performance trendThe industry has enjoyed the fruits of over 30 years ofsearch and development on the SiO2/Si materials system—afact not always recognized in technology development plning. A new generation of scientists and engineers willchallenged by not only integrating these new materials itimely manner, but also by avoiding the mistakes of the pOpportunities to revolutionize an industry like these aredeed rare!

ACKNOWLEDGMENTS

The authors acknowledge useful discussions with SSummerfelt of Texas Instruments in the early work onand Zr silicates. The authors also gratefully acknowledgediscussions and data provided by Professor Bruce GnadUniversity of North Texas, and Professor Gerry Lucovsand Professor Greg Parsons of North Carolina State Unisity prior to publication. The authors thank Don Monroe aJack Hergenrother of Agere Systems~formerly of Bell Labo-ratories!, David Muller of Bell Laboratories, Lucent Tech


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nologies, and Luigi Colombo of Texas Instruments, for mauseful discussions. The authors are grateful to Charles Wfor several insightful suggestions regarding the manuscrOne of the authors~R.M.W.! gratefully acknowledges thesupport of the Texas Advanced Technology Program,Semiconductor Research Corporation, and the Defensevanced Research Projects Agency in the preparation ofreview.

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