• Why Behavioral• Wait statement• Signal Timing• Examples of Behavioral

Descriptions–ROM

VHDL Behavioral DescriptionsVHDL Behavioral Descriptions

• The process concept

• Wait statements and time modeling

• Behavioral versus data-flow descriptions

• Modeling of basic hardware components

• Mixed descriptions

• VHDL data-flow descriptions model simple devices whose outputs are always a function of their inputs.

• A more general capability is required to model devices with internal (hidden) state information.

• A technique is required to describe device behavior in algorithmic (sequential) terms.

• The process statement provides a compact representationfor arbitrary deterministic behavior of hardware components.

• The subprogram encapsulates a sequence of sequential statements.

VHDL Behavioral DescriptionsVHDL Behavioral Descriptions

Why Behavioral Description?Why Behavioral Description?

• Designers can first concentrate on the behavior of a system, and then work on different implementations later.

• Manufacturers can release a functionality definition without revealing proprietary details of implementation.

• Support top-down design methodologies.

• Support multi-level simulation

ProcessesProcesses• A process consists of a set of sequential statements, which

are executed one by one according to their textual order.• The sequential statements are similar to those in a high-level

programming language:- Variable assignment statements- If and case statements- Loop statements- Procedure call and return statements

• Unique to VHDL- Signal assignment statements- Wait statements- Assertion statements

ProcessesProcesses• EXAMPLE architecture behavior of E is

begin P1: process variable V: Natural := 0; begin for i in 1 to 100 loop V := V + 1; end loop;

S <= V after 10ns wait for 20ns; end process P1;...end behavior;

Process SemanticsProcess Semantics• All processes start execution at simulation

time zero.

• A process stops execution when it reaches a wait statement.

• The process resumes when the conditions specified by the wait statement are met.

• When the last statement of a process is executed the process begins again at the first statement.

Process SemanticsProcess Semantics• If a process never waits then it will loop forever.

• A process which is being executed is said to be active; otherwise the process is said to be suspended.

• Process statements which do not assign values to signals are said to be passive. – A passive process has no outputs (it does not assign to

any signals) and, therefore, cannot cause the activation of another process.

– Passive process can be placed in the entity declaration.

Process SemanticsProcess Semantics

Example of process semantics

The Wait StatementsThe Wait Statements

The Wait StatementsThe Wait Statements• Wait statements are used to control the

change of state of processes.

• We can also use a sensitivity list to define a set of signals which a process is always sensitive to. – In this case, it is illegal to include any wait

statements in the process (or in subprograms called by the process).

The Wait StatementsThe Wait Statements

Signal Signal TimingTiming

• The three models of time delay are applicable here to the behavioral description.

• - Signals are never assigned to directly.

What will be the result?

The Simulation CycleThe Simulation Cycle• If no driver is active, the simulation time advances to the

next time at which a driver becomes active or a process times out on a “wait for”

• Processes that have timed out are the initial members of a list of pending processes

• Each active explicit signal (other than implicit) in the model is updated— events may occur on signals as a result

• Each implicit signal (such as GURAD, ‘DELAYED,

‘STABLE, ‘QUIET, or ‘TRANSACTION) in the model

is updated— events may occur on signals as a result

The Simulation CycleThe Simulation Cycle• Every process waiting on a signal which has just

experienced

an event is added to the list of pending processes

• Each pending process is executed until it suspends

• Repeat the cycle

• Simulation is complete when the simulation time has advanced to the value time'high

Process CommunicationProcess Communication• Processes can

communicate with each other via signals (not variables).

• Signals are used to transmit information between processes.

• If there is more than one parallel assignment to the same signal the signal must be declared as a resolved signal

Process Communication - Process Communication - zoomzoom

Process Communication - Process Communication - zoomzoom

• A concurrent signal assignment statement corresponds to a process

Behavioral Behavioral vs. Data-flow vs. Data-flow DescriptionsDescriptions

An example of Behavioral An example of Behavioral Description: ROMDescription: ROM

• Behavioral description of a memory board:

An example An example (cont’d)(cont’d)

An example (cont’d - zoom)An example (cont’d - zoom)

An example (cont’d An example (cont’d - zoom)- zoom)

Variable AssignmentVariable Assignment• In VHDL 87, variables can only be declared in a

process or a subprogram.• A variable assignment will take effect immediately.• A variable will retain its value throughout the

simulation if it is declared in a process.• Variables declared in subprograms are reinitialized

whenever the subprogram is called.• Ex.

SourcesSources• Krzysztof Kuchcinski