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This document is downloaded from DR‑NTU (https://dr.ntu.edu.sg)Nanyang Technological University, Singapore.

The multiple temperature heater platforms forsolder Electromigration test conducted at roomtemperature

Hou, Yuejin; Tan, Cher Ming

2008

Hou, Y., & Tan, C. M. (2008). The multiple temperature heater platforms for solderElectromigration test conducted at room temperature. In proceedings of the 10thElectronics Packaging Technology Conference: Singapore, (pp.1148‑1153).

https://hdl.handle.net/10356/90846

https://doi.org/10.1109/EPTC.2008.4763584

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The multiple temperature heater platforms for solder Electromigration test conducted at roomtemperature

Yuejin Hou12 and Cher Ming Tan"3'School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639 798

2email: [email protected]: [email protected]; Tel: +65-67904567; Fax: +65-67920415

Abstract there exists a current crowing region near the intersection ofTo accommodate the increasing input-out (I/O) counts in the chip interconnect and the solder bump where the current

future integrated circuits, the size of the solder bumps has to density changes abruptly in the solder bump. A non-uniformshrink and current density through each solder bump is current density within the bump, particularly at the UBMincreasing. With the ever-increasing current density through interface, creates several complications affecting the time tothe solder bumps, electromigration (EM) remains as a main failure for the bumps [2]. The current crowing can increase theconcern for the reliability of future solder bumps. This temperature of the region significantly due to Joule heating.phenomenon is responsible for the structural damage of solder This Joule heating problem is more severe with a smallerbumps in the form of void formation caused by ionic diffusion dimension of the solder joint because the conductive heatdriven by high electron wind force. transfer through the solder joint is lesser owing to the small

Conventional solder bump EM test is performed in high surface area, making the heat dissipation less efficient.temperature oven with high stress current. Besides the high Simulation of current density distribution in the soldercost oven, the total test time can be very long as the EM test bump of a flip chip structure showed that the current densityhas to be performed at several different temperatures and EM in the current crowd region is much higher than the averagedfailure for solder bumps is usually much longer than their current density inside the solder bump [1]. This current non-interconnect counterpart. In this work, we propose a multiple uniformity affects the spatial and temporal distributions of thetemperature heater platform for solder EM test conducted at intermetallic and void formation. The solder bumproom temperature. This platform eliminates the use of high temperature can be very much larger than the ambient ovencost oven. In addition, the solder joints can be tested at temperature under the Joule heating effect, leading to thedifferent temperatures simultaneously, shorting the total thermo-migration failure in the solder bump [3] or local meltrequired EM test time. This proposal is verified by ANSYS@ of the solder bump [4].finite element simulations through the corresponding With the limitation in test temperature and current, theelectrical-thermal analysis. time taken for solder EM test can be very long. On the other

Introduction hand, in order to obtain the activation energy Ea of the solderEM from the Black's equation [5], the solder bump EM testFofi-hipacags tesode ntrcnecs evea needs to be performed at three different temperatures. As a

electrical and thermal paths as well as structural supports, ne solde testowill t thedetemerm.inatwhich~~~~~~~~~~~~~~~rede itimotnei'hCreiblt hrt single solder EM test will take a long time, the determinationwhgradatichrend seritsimortyanfct the Iunctrinablity wftheentire of the Ea at three test temperatures will require a very longdegradkatio can seriously affect the functionality of theentire duration unless three ovens are used simultaneously. Besides,IC package. package level EM test in ovens requires special test boards

O t o h and test sockets that are reliably at the high test temperatures.packages is decreasing owing to the increase in the number of The cost of these ovens, boards and sockets are very high.I/O contact pads on the chip in order to enhance the.'.In this work, we propose a novel multiple-temperatureperformance and functionality of electrical devices. This heater platform for solder EM test conducted at roomcontinuous down scaling of the size of the solder joint temperature, hence the use of high cost oven is eliminated. Inincreases the current density through the joint, making addition, the solder bumps can be tested at differentelectromigration (EM) a serious threat to the reliability of temperatures simultaneously, shorting the total EM test time.solder.joints[1]. A heater is realized by implementing poly-Si stripesElectromigration of solder bumps is a failure mechanism embedded in the Si die as heat sources. Due to the highthat leads to increased resistance with accompanying events resistivity of the PolySi stripes, moderate current is able tosuch as the formation of intermetallic compounds (IMC), achieve a die temperature above 150 .C in ambient testvoids and cracks that can disrupt the solder joint andsilicon/package metallization leading into the bump. The.. . . .- 1 -- bum-p and the heater iS veiry small by assuming a one-driving forces for this EM failure are current density ad bm n h etri eysalb suigaoean dimensional heat conduction mechanism. [6] This will beelevated temperature. Typical solder EM test is performed in vrfemnor3Dsle bm iuain.Ti aean oven at a constant high temperature with a constant current decisthdtalofheetpafrm swllstesource. The highest temperature allowed in solder bump EM smlto eut yfnt lmn nlss(E)test iS limited by the melting point of the solder alloy system,and as such, the device temperature should be kept to be at Model descriptionleast 25 °C below the melting point. Eutectic SnPb solder is chosen for illustration in this work

The applied test current to the solder bump is also although the same methodology can be applied to other typesrestricted. This is due to the geometry ofthe solder bump, and of solder joints. The proposed test platform comprises of five

978-1-4244-21 18-3/08/$25.00 ©2008 IEEE 2008 1 0th Electronics Packaging Technology Conference1148

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components: ceramic substrate, heater, solder balls, poly-Sistripes inside the heater, and Si chip. The schematic drawingof the model is shown in Fig. 1. It has a 5x5 solder ball arrayat 0.45 mm pitch. The number of the solder bumps in Si Chipsimulation is determined as a compromise between thesimulation time and overall model accuracy. The componentsize is listed in Table 1. The structural parameter of the solder Unde iljoint is shown in Table 2.

Heter

Si chip UN eramicsbstrate

Solder ball

Heater M__

Epoxy adhesive

Fig. 2. Geometry created by Design Modeler(@ for theCeramic substrate solder bump electromigration test platform.

Fig. 1. Schematic drawing of the solder bump ielectromigration test platform.

Finite element model is constructed using ANSYSWorkbench(@ and the simulation is carried out in the ANSYSClassic@ environment. The geometry of the entire platform isdrawn using the Design Modeler@ in ANSYS Workbench@ asshown in Fig. 2. The model is then meshed in workbenchsimulation environment with 4 node tetrahedral elements(solid69). The model after meshing is passed to ANSYSClassic@ through ANSYS input files. There are 97391 nodesand 539441 elements in the model. The meshed model isoleshown in Fig. 3. The meshing density in solder bump is much bumhigher than that in the substrate so the accuracy will not besacrificed in the solder bumps. Si chip and underfill areremoved for clearer illustration in Fig. 3. An individual GMmeshed solder joint is shown in Fig. 4. 5Q0.

Table 1. Component dimensions Fig. 3. Finite element model for the solder bumpl l ~~~~~~~~~~~~~~~~electromigration test platform.Component Length (mm) Width (mm) Thickness (mm)

Si chip 1.6 1.6 0.3

Heater 1.6 1.6 0.3 AlCeramic substrate 2 2 0.3

Poly Si 1.6 0.05 0.05

Table 2. Structural dimensions of the solder bumpSolder height 0.11 mm

Pad diameter 0.1 mm

Solder width 0.15 mm SPSodr oum .95x03m3Cu S

Fig. 4. Finite element model for an individual solderbump.

2008 10th Electronics Packaging Technology Conference

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Poly-Si stripes are embedded in the heater as heat Table 3. Material properties used in the simulationsgenerating sources and their layout will affect the temperature Thermal Specific Density Resistivitydistribution of the whole EM test system. In this work, ten Component conductivity heat Kg/m3 (pMQ cm)poly-Si stripes are placed horizontally in the heater as shown (W/m.K) J/kg-Kin Fig. 5. The three axial directions x, y, z are along the poly- Copper 698 385 8960 1.7Si length, width and thickness directions, respectively. During Aluminu 232 900 8700 2.7EM test, moderate current will be applied to the poly-Si mstripes and the generated heat will be transferred to the solder Ceramic 3 1112 3100 -bumps on top. Therefore, by controlling the amount of current Underfill 0.2 2000 1630 -applied to poly-Si stripes, the solder bumps can be heated tothe desired EM test temperature. Also, the number of the poly- EutecticSnPb 50 190 8420 14.6Si stripes powered will affect the temperature distribution of Silicon 61.9 702 2329 -the heater and the solder bumps on top. The temperature Poly-Si 61.9 702 2329 5100distributions will be more uniform if more poly-Si stripes arepowered simultaneously. It is noteworthy that the layout of the The temperature distribution of the solder bumps on top ofpoly-Si can always be modified to meet the specific geometryofteode um es yse i cta ipemnatoi*h the heater is shown in Fig. 6. It can be seen that the solder

futures bumps at the edge of the die are at a lower temperature thanfuture.those at the center. This is because current is applied only tothe two poly-Si stripes at the center of the chip in simulation.As shown in Fig. 6, the temperature distribution is moreuniform along the poly-Si direction (x direction). Thetemperature distribution along y direction is non-uniform.Therefore, these solders can be tested simultaneously atdifferent temperatures along the y direction. By performingthe steady state analysis with different input current, therelationship between maximum solder bump temperature andinput current is shown in Fig. 7. The maximum temperature inthe solder bump is proportional to the square of input current,Ceramic

S+i 0e~~~~~~~~~resistivity (TCR) method with Cu thin films embedded nearx the solder bump [8]. For Cu metallization, TCR and R are

Fig. 5. The layout of poly silicon stripes, linear below 200 °C, which can provide high accuracy for thetemperature estimation.

Simulation resultsANSYS element Solid69 is chosen for the coupled field AN

electrical-thermal analysis. The electrical and thermalproperties of the materials used in simulation are shown in a ITable 3. In the simulation, all materials are assumed to be l

homogenous and isotropic. The interfacesate thrugh te betweenre different o

Mmaterials are assumd to be . T _ we t f e n

Since simulation resultsheareeraffectedFr Cumetabyzathe, boundaryar

simulation, the substrate bottom iS fixed at an ambient _temperature of 25°C. The rest of the substrate surfaces are |t_il

Siubjetitonnaturltcnetosihacnvcincefceto

l0 W/mmaK[7]. In order to obtain different temperaturedistribution over the solder bumps, current is applied only attwo poly-Si stripes in the center of the heater. The steady stateb 13..19analysis snow tat with input poly-ir current Of 250 ma, thesolder bumps can be heated up to 170°C, which is suitable for Fig. 6. Temperature distribution ofthe solder bumps witheutectic SnPb EM test. an input current of 250mA. (Unit: degree)


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180 / 0

2D 120- 1 |_

Q_ 90E

80

60-60

40

30

0 50 100 150 200 250 TIMEInput current (mA) Fig. 9. Maximum solder bump temperature change with

Fig. 7. Maximum solder bump temperature change with time simulated by transient thermal-electrical analysis.the input current.

180-Figure 8 shows the temperature distribution across the l I

heater surface for different amounts of input cua)ent applied to 175 42 Poly-Si

the poly-Si stripes. The temperature profile direction is along ...170 8 Poly-Siy axial direction. As shown in Fig. 8, the temperature at the 1center of the heater is the highest since only two poly-Sistripes at the center of the heater are powered. Withdecreasing poly-Si current, the temperature on top surface of1S160the heater also decreases and the temperature distribution is amore uniform.dil E

Transient analysis is also performed to estimate the aamount of time for the system to reach the steady state oncethe current is applied. This duration is also called thermal 145response time. Transient analysis is performed with the timeduration of )Os and the sub-step is set at 0dis. The simulated 140 200 y600 In ote wmaximum solder bump temperature changing with time is 0P20s40t60o80 100 100140n60shown in Fig. 9. It can be seen that the temperature increases Psto ~mdramatically initially and stabilizes to the steady state Fig. 10. Temperature distribution profile across the heatertemperature in 5 seconds. The simulated thermal response surface for the case of different number of poly-Si stripes aretime may be dependent on the finite element model and more powered.verification is needed in our future work.

Fig. 10 shows the temperature distribution profile across the2 800 . ..heater surface for different number of poly-Si strips being

250..- . -mA .- powered along y axial direction. As shown in Fig. 10, with180-200 mA .I more number of poly-Si being powered, the temperature

1 -------------~~~~--------- ----- --W........................ 15 mA

100inm) edistribution is more uniform along y direction. In other words,the uniformity of the temperature distribution can be1u40acontrolled by the number of poly-Si stripes powered during

a, actual test.co Discussions and future works

U) 0It is well-known that the trace routing in the chip side tothe solder bump introduces significant current crowding. The

0 200 400 600 800 1000 1200 1400 1600 eutectic SnPb slderjoins [9].aTherefre,nitoisnecessaryct

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trace without applying any poly-Si current. It is obvious thatthe maximum current density site is located at the intersectionof the chip interconnect and the solder bump. The Al trace hasto be thick enough so that EM failure only occurs in the solderjoint. Figure 12 shows the temperature gradient distribution Alfor the same current applied in Fig. 11. The maximumtemperature gradient site is located at the same location as the aximum Tmaximum current density site. This is because the temperature gaingradient is mainly contributed by the current crowding effect.

It is noteworthy that the maximum temperature gradient is0.01 °C/tm in Fig. 12, far below the value (0.15 °C/tm) for SnPbthermo-migration to appear. With the heater current of 250 CumA to the two poly-Si stripes in the center, the temperaturegradients in the solder bump at the center and edge of the dieare at a level of 0.145 and 0.1 °C/tm, respectively. Under

008431010113

such a high temperature gradient, the voiding from EM testmay be contributed by thermo-migration, complicating theanalysis. Fig. 12. Temperature gradient distributions in the solder

In order to reduce the temperature gradient introduced by bump. (Unit: °C/tm)the poly-Si heater, the EM test platform can be modifiedslightly. As shown schematically in Fig. 1, poly-Si stripes can Conclusionsalso be implemented in the Si Chip on top of the solder In this work, we propose a multiple temperature heaterbumps. In this case, the poly-Si stripes at both sides of solder platform for solder EM test conducted at room temperature.bumps contribute to the temperature gradient and the two This platform eliminates the use of high cost oven. In addition,temperature gradients can cancel each other in the solder the solder joints can be tested at different temperaturesbump, leading to reduced temperature gradient in the solder simultaneously, shorting the total required EM test time. Thisbumps. The verifications will be done in our future works. proposal has been verified by ANSYS(@ finite element

simulations through the corresponding electrical-thermalAN analysis.

The proposed solder EM test platform has three advantages.Firstly, solder bump can reach a high temperature by

\ controlling the heater input current. Hence, the test current canAl be reduced under such high temperature without compromise

on the EM failure time. Secondly, solder bumps can be testedMaximum J on EM at different temperatures simultaneously. This is

achieved by controlling the layout of the poly-Si stripes in theheater so that the top surface of the heater is at differenttemperatures with the edge of the die at a lower temperature

Cu SnPb than that at the center. Therefore solder bump at center of theheater will be tested at higher temperature than that at the edge.Lastly, the EM test can be carried out at room temperature,eliminating the use of high-cost oven.

0327E+0 To reduce the temperature gradient in the solder bumpcontributed by the heater, poly-Si stripes can be implementedin the chip on top of the solder bumps. The temperature

Fig. 11. Current density distributioninthe solderbump. (Unit: gradients produced from both sides of poly-Si stripes canpA/m2) cancel each other, leading to reduced temperature gradient.

This will be done in our future works.

References1. L. Yi-Shao and K. Chin-Li, "Characteristics of current

crowding in flip-chip solder bumps," MicroelectronicsReliability, vol. 46, pp. 915-22, 2006.

2. W. Dauksher, W. Dauksher, D. H. Eaton, and J. D.Rowatt, "A Finite-Element-Based Methodology forEvaluating Solder Electromigration Current Limits ofSn/Pb Eutectic Solder Bumps," Device and MaterialsReliability, IEEE Transactions on, vol. 8, pp. 222-228,2008.


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3. H. Ye, C. Basaran, and D. Hopkins, "Thermomigration in 7. J. Legierski and B. Wiecek, "Steady state analysis ofPb--Sn solder joints under joule heating during electric cooling electronic circuits using heat pipes," IEEEcurrent stressing," Applied Physics Letters, vol. 82, pp. Transactions on Components and Packaging1045-1047, 2003. Technologies, vol. 24, pp. 549-553, 2001.

4. C. M. Tsai, Y. L. Lin, J. Y. Tsai, L. Yi-Shao, and C. R. 8. "Standard Method for Measuring and Using theKao, "Local melting induced by electromigration in flip- temperature Coefficient of Resistance to Determine thechip solder joints," Journal of Electronic Materials, vol. Temperature of a Metallization Line," JEDEC SOLID35, pp. 1005-9, 2006. STATE TECHNOLOGY ASSOCIATION

5. J. R. Black, "Electromigration A brief survey and some a. JEDEC Standard No. 33B, Dec 2004.recent results," IEEE Trans. Electron Devices, vol. 16, pp. 9. A. T. Huang, A. M. Gusak, K. N. Tu, and Y.-S. Lai,338-347, 1969. "Thermomigration in SnPb composite flip chip solder

6. S.-Y. Jang, in Taejon(Korea) Ph. D Thesis, 2002. joints," Applied Physics Letters, vol. 88, p. 141911, 2006.


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