webinar: practical ddr testing for compliance, validation and debug
TRANSCRIPT
Agenda Basics of DDR testing
Basics of a DDR interface Types of testing Signals of interest
Common DDR test challenges Signal access Burst separation
Preparing for physical layer testing Choosing test equipment Optimizing oscilloscope setup
DDR compliance testing Compliance testing background The compliance testing process
DDR validation and debug Case study – tracking down a potential
signal fidelity issue
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Basics of DDR testing
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Basics of a DDR interface Each DRAM chip
transfers data to/from the controller via several data lines, accompanied by a strobe
Since data can flow both from the controller to the DRAM (write operation) and from the DRAM to the controller (read operation), these lines are bi-directional
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Strobe + Data
DRAM chip
Controller
Basics of a DDR interface Common clock,
command and address lines are used for all DRAM chips
Since they control the operation of the interface, they are unidirectional (controller-to-DRAM)
The layout shown here is the “fly-by” topology used from DDR3 onwards
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Strobe + Data
Clock, Command, Address
DRAM chip
Controller
Three types of physical-layer test
Compliance: “Do the device’s output signals comply to the JEDEC specification?”
Validation: “Do the devices interact correctly within the system environment?”
Debug: “Why isn’t my device/system behaving correctly?”
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Which signals are important? In physical layer compliance testing
and validation, the fastest signals are the most critical: Clock (CK) Strobe (DQS) Data (DQn)
These signals need to be analyzed as analog waveforms to fully characterize their signal fidelity
While there will be many Data lines in an interface, testing them all can be time-consuming Often, board-level simulation is used to
find the expected “worst-case” data lines and test only those
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Strobe
Data
Clock
Which signals are important? The command bus controls the operation of
the interface, and indicates the desired activity on the high-speed signals
Knowing the logic state of the command bus signals in a time-correlated way to the analog behavior of the high-speed CK, DQ and DQS signals enables much deeper insight into the system’s behavior
Possible command states vary by DDR protocol, but can include: Deselect No operation Read Write Bank Activate Precharge Refresh Mode Register Set
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Strobe
Data
CMD bus
A complete analysis system
Analog signals High-bandwidth
oscilloscope Low-loading
differential analog probes
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Analysis software Identify bursts Perform
measurement
Digital signals High-sample-
rate digital analyzer
High-bandwidth digital probe
Common DDR test challenges
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Test challenge 1: accessing signal points
All modern DRAM chips are BGA-packaged, which presents a challenge for testing – how do you access signals which are under the chip?
3 common approaches: Backside vias Interposers DIMM series resistors
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Access option 1: Backside vias
If the BGA balls are accessible on the back side of the board, this is an ideal place to probe the signals of interest
Pros Usually good signal fidelity (probing
near the termination) Relatively easy access
Cons Many devices (dual-rank DIMMs,
dense embedded systems) don’t allow for this method
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Backside via probe on single-rank DIMM
Backside via probing on “chip-down” system
Access option 2: interposers
Interposers install between the DRAM chip and the board, and provide points to connect probes
Pros Useful in difficult access situations Generally reasonable signal fidelity
Cons Additional complexity to install
socket correctly Interposer footprint can cause
problems on crowded boards
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Access option 3: DIMM series resistors
For dual-rank (2-sided) DIMMs, the backside vias aren’t accessible – the resistors are a good alternate location
Pros A relatively accessible probing
point when the vias are not accessible
Cons The distance between the probe
and the termination on the DRAM means reflections from the receiver can be a problem
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Single-ended Data line: resistor to ground
Differential Strobe line
Test challenge 2: burst separation Read and Write bursts share a bus, but must be analyzed separately:
Read bursts originate from the DRAM Write bursts originate from the controller Bus is “tri-state” (high-Z at both ends) when neither side is transmitting It’s critical to be able to identify and isolate the bursts of interest for analysis
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Idle
Write
Idle
Read
Burst separation option 1: DQ/DQS phase
We can use the phase difference between the Data and Strobe to differentiate Reads and Writes
Pros Identification is simple and requires
only the signals being tested Cons
Signals with lots of noise, reflections, or slow rise/fall times can make phase measurements, and hence burst separation, unreliable
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Write
Read
Clean signals make phase-based separation easy
Reflections can make DQ/DQS phase relationship unclear
Burst separation option 2: Command bus
Acquiring or triggering on the command bus removes any uncertainty about the coming burst type
Pros Very reliable separation Insight into command bus
activity and relationship to DQS/DQ
Cons Requirement to probe several
extra signals
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Preparing for DDR physical-layer testing
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System bandwidth Testing DDR systems always
requires the use of probes, so we should look at the scope and probes as a complete acquisition system
DDR interfaces have very fast slew rates relative to their data transfer (baud) rates
In order to characterize the system with acceptable rise-time accuracy, a relatively high-bandwidth oscilloscope and probes are required
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DDR3 slew rate specification
Recommended equipment for common DDR variants
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Probe loading
Probe loading gets blamed for a lot of observed issues
In our experience, signal fidelity issues can almost always be traced to the signal path within the device
Probes with insufficiently low loading are much more likely to cause functional failures in devices
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Teledyne LeCroy WaveLinkDxx30 differential probes have ideal characteristics for testing higher-rate DDR systems
Probe mechanical connection Solder-in probe tips are used in the
vast majority of DDR testing applications
Most critical considerations tend to be: Small physical size - typically
many signals need to be probed Physical flexibility reduces torque
on delicate solder connections when probe amplifier is moved
Measurement flexibility – doing several jobs with one tip reduces test setup complexity
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Teledyne LeCroy QuickLinkprobe tips are low-cost, high bandwidth, 9-inch flexible tips that can be interchanged between analog and digital instruments
Preparing to measure: deskewing
Deskewing is critically important in all applications where probes are used for timing measurements, but even more so in a DDR environment
The importance of the DQ/DQS phase in many measurements makes them particularly sensitive to skew issues
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Deskewing probes using the oscilloscope’s fast edge output
These probing points are close together, so the same reference plane can be used
Preparing to measure: maximize dynamic range
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Signals are using ~50% of the grid
This reduces Signal-to-Noise ratio by about 6dB
Signal is “clipping” – it could be overdriving the oscilloscope’s front-end
What not to do.
Preparing to measure: maximize dynamic range
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Each signal has its own grid
Maximizes dynamic range without sacrificing viewability
Each signal occupies about 6 vertical divisions
Good practice
Preparing to measure: checking signal levels Make sure the signal levels appear as
specified for the DDR variant you’re working on Many automated measurements rely on
“the basics” being correct If they don’t, it might be…
A probing problem (wrong reference, cross-probed, inverted)
A device/system problem (Wrong Vdd, wrong Vref)
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DDR2 LPDDR2 DDR3 LPDDR3 DDR4 LPDDR4
VppSingle-ended 0 to 1.8 V 0 to 1.2 V 0 to 1.5 V 0 to 1.2 V 0 to 1.2 V
Differential -1.8 to 1.8 V -1.2 to 1.2 V -1.5 to 1.5 V -1.2 to 1.2 V -1.2 to 1.2 V
Vref(reference voltage)
Single-ended 0.9 V 0.6 V 0.75 V 0.6 V 0.6 V
Differential 0 V 0 V 0 V 0 V 0 V
DDR Compliance Testing
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Why do compliance testing?
DRAM and/or controller vendors Must be able to prove to their
customers that their devices abide by the standards as defined by JEDEC
There is no formal certification process for DDR “compliance” –manufacturers essentially self-certify
This makes documentation of test procedures and results critical
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System designers No explicit need to prove JEDEC
compliance to “downstream” customers
Validation of device functionality is much more critical
System layout is often not optimal for signal fidelity testing
But a compliance report is often desirable as concrete verification that design goals have been met
Probing for compliance testing
Specification assumes the signal is probed directly at the balls of the DRAM BGA
This is not always feasible Access issues Need to connect twice as many probes
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CK DQS DQ Add/CtrlDDR4 Differential Differential Single-Ended Single-EndedDDR3 Differential Differential Single-Ended Single-EndedLPDDR3 Differential Differential Single-Ended Single-EndedDDR2 Differential Differential or
Single-EndedSingle-Ended Single-Ended
LPDDR2 Differential Differential Single-Ended Single-Ended
Compliance testing is complicated!Fully covering the JEDEC standard for any given DDR variant means doing a lot of tests.
Automated compliance test software options for the oscilloscope… Make testing less
time-consuming Reduce errors due
to measurement complexity
Increase repeatability
Generate test reports automatically
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Test coverage of Teledyne LeCroy QPHY-DDR4 automated compliance test option
Step 1: acquire signals Lots of data
makes for more reliable, repeatable results
We take a long acquisition to ensure good statistical confidence in the measurements
High traffic density during testing is important Run memtest
or another script to induce lots of traffic
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Clock
Strobe
Data
Address
Step 2: separate read/write bursts Read and Write bursts must be
analyzed separately They come from different transmitters Some of their parameters are defined
differently
For systems with high-quality signals and/or using low speed grades, DQ/DQS phase produces good separation results
At higher rates or in low-signal-quality situations, phase measurement can become unreliable In these situations, we recommend
acquiring the CMD bus to ensure reliable burst separation
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Step 3: perform measurements
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Measurements are performed on all bursts in the acquired waveform Results, statistics and screenshots are retained for report generation
Possible reasons for problems/failures: Signal quality issues due to system/board signal paths Probes not connected correctly Burst separation problems (possibly due to the above) The device does not meet the specification
Step 4: Generate eye diagrams Eye diagrams
are only required for compliance testing in DDR4 and LPDDR4 variants
But they are an incredibly useful tool for visualizing overall signal quality, so they form part of the automated test package for all variants
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Step 4: Generate eye diagrams
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Write burst
Read burst
Write burst eye pattern
Read burst eye pattern
Step 5: Generate report
Reports contain: A summary of the test results,
including pass/fail status More details of each individual
test Screenshots of the tests being
performed
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DDR Validation and DebugA case study using Teledyne LeCroy’s DDR Debug Toolkit
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The complete system view
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Analog probes: DQ/DQS/CK waveforms for waveshape analysis and eye diagrams
Digital Acquisition: For better burst separation and insight into command bus behavior
What signals are we probing and how? Strobe (DQS): Analog C2 Data (DQn): Analog C3 Command bus:
Chip Select (CS): Digital D0 Write Enable (WE): Digital D1 Row Address Select (RAS): Digital
D2 Column Address Select (CAS):
Digital D3 Clock (CK): Digital D4 or Analog
C1 QuickLink probe tips can be used
for both digital and analog signals
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Deskew
Make sure to deskew all analog and digital signals to the same timing reference
Teledyne LeCroy oscilloscopes have a Fast Edge output to make deskewing easy.
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First look at the analog signals Looking at just
the DQ and DQS analog signals, we can see some strange non-monotonicitieson the edges
DDR Debug Toolkit is the ideal tool for tracking down this kind of issue
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Bus view
Annotating bus states and corresponding DQ/DQS activity makes system analysis easier
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Bus view
The bus view also gives a direct reference from the system behavior to the JEDEC spec
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Look closer with triggers
We can use the CMD bus to trigger on an event of interest
Let’s trigger on Read bursts
They all show non-monotonous edges
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Look closer with triggers
Triggering on Write bursts doesn’t show any evidence of bad edges
Will the bad Read edges affect our eye diagrams?
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Eye diagrams and burst separation The non-
monotonous edges on the Read bursts are hindering the phase-based burst separation approach It’s hard to
measure phase with a discontinuity right at the Vref crossing point
We can see some Reads end up in with the Writes as a result
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Eye diagrams and burst separation Using the CMD
bus to separate Reads and Writes leads to “clean” eye diagrams
But that non-monotonicity will cause problems for other measurements
Is it a real phenomenon?
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Where’s the signal being probed?
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PCB
DRAM Memory Controller
So what’s going on here?
DRAM ControllerZ0 = 50Ω
RT >> 50Ω
VA VBVA
VB
T1 T2 T3
Measure the propagation delay
We can use the signal itself as a TDR pulse
Here, the round-trip delay is approximately 680ps
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Now we have a simple model
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Z0 = 50Ω
RT >> 50Ω
VA VB
TD = 340ps
DRAM Controller
This gives us “virtually probed” read bursts
The probing point has been “moved” to the termination using Virtual Probe technology, eliminating the reflections
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Original Virtual
Make sure you pick the correct probe point
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PCB
DRAM Memory Controller
You should still analyzeWrite bursts from here
Read burst analysisshould come from here
“Real” probe Virtual probe
The final eye diagram view
When we view each signal from the correct probing point, both Read and Write bursts look good
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