PRACTICAL RECORDNAME :

REGISTER NO :

COURSE : B.Sc Computer Science

SEMESTER / YEAR : I /I

SUBJECT CODE : UCS15103

SUBJECT NAME : Digital Logic Fundamentals Laboratory

NOVEMBER 2016

FACULTY OF SCIENCE AND HUMANITIES

Ramapuram, Chennai.

______________________________________________________

Department of Computer Applications

FACULTY OF SCIENCE AND HUMANITIES

Ramapuram, Chennai.

________________________________________________________

Department of Computer Applications

BONAFIDE CERTIFICATE

THIS IS TO CERTIFY THAT THIS IS THE BONAFIDE WORK DONE BY ___________________IN THE

SUBJECT Programming in Digital Logic Fundamentals Laboratory [UCS15103] AT SRM

UNIVERSITY, RAMAPURAM CAMPUS, IN NOV 2016.

STAFF IN-CHARGE HEAD OF THE DEPARTMENT

SUBMITTED FOR THE UNIVERSITY PRACTICAL EXAMINATION HELD AT SRM UNIVERSITY,

RAMAPURAM ON ___________________________

INTERNAL EXAMINER EXTERNAL EXAMINER

REGISTER NUMBER:

INDEX

S.No Date Name of the Program PageNo. Signature

1 STUDY OF LOGIC GATES AND THEIR TRUTH TABLE   

2 VERIFICATION OF BOOLEAN LAWS USING DIGITAL LOGIC GATES    

3 DESIGN AND IMPLEMENTATION OF CODE CONVERTOR    

4 DESIGN AND IMPLEMENTATION OF CODE CONVERTOR    

5 DESIGN AND IMPLEMENTATION OF HALF ADDER AND FULL ADDER    

6 DESIGN AND IMPLEMENTATION OF HALF SUBTRACTOR AND FULL SUBTRACTOR    

7 DESIGN AND IMPLEMENTATION OF 4-BIT BINARY ADDER    

8 DESIGN AND IMPLEMENTATION OF 4-BIT BINARY SUBTRACTOR    

9 DESIGN AND IMPLEMENTATION OF PARITY GENERATOR    

10 DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR  

 

11 DESIGN AND IMPLEMENTATION OF MULTIPLEXER

12 DESIGN AND IMPLEMENTATION OF DEMULTIPLEXER

13CONSTRUCTION AND VERIFICATION OF 4 BIT RIPPLE COUNTER AND MOD 10 COUNTER

14 SHIFT REGISTER - PARALLEL IN PARALLEL OUT

Ex No: 1 Name:

Date: RegisterNo:

STUDY OF LOGIC GATES AND THEIR TRUTH TABLE

Aim:-Verification and interpretation of truth tables for AND, OR, NOT, NAND, NOR

Exclusive OR (EX-OR), Exclusive NOR (EX-NOR) Gates.

Theory:-Logic gates are electronic circuits which perform logical functions on one or more

inputs to produce one output. There are seven logic gates. When all the input combinations of a logic gate are written in a series and their corresponding outputs written along them, then this input/ output combination is called Truth Table. OR, AND and NOT are basic gates. NAND, NOR are known as universal gates.

OR GATE:-

The OR gate performs a logical addition commonly known as OR function. The output is high when any one of the inputs is high. The output is low level when both the inputs are low.

Logic Circuit Design

Output for OR Gate:

AND GATE:

The AND gate performs a logical multiplication commonly known as AND function. The output is high when both the inputs are high. The output is low level when any one of the inputs is low.

Logic Circuit Design

Output for AND Gate

NOT GATE:

The NOT gate is called an inverter. The output is high when the input is low. The output is low when the input is high.

Logic Circuit Design

Output for NOT Gate

NAND GATE:

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low and any one of the input is low .The output is low level when both inputs are high.

Logic Circuit Design

Output for NAND Gate:

NOR GATE: The NOR gate is a contraction of OR-NOT. The output is high when both inputs are

low. The output is low when one or both inputs are high.

Logic Circuit Design

Output for NOR Gate

X-OR GATE:

The output is high when any one of the inputs is high or low. The output is low when both the inputs are low and both the inputs are high

Logic Circuit Design

Output for X-OR Gate

XNOR Gate:

The XNOR gate is called as inverter of XOR gate. The output is high when both inputs are high and both the inputs are low. The output is low when any one of the inputs is low or high

Result :

Thus logic gates operation was verified.

Ex No:2 Name:

Date: RegisterNo:

VERIFICATION OF BOOLEAN LAWS USING DIGITAL LOGIC GATES

Aim

To verify Boolean laws using logic gates

Theory:-

Commutative Law

The Commutative law for addition of two variables is written as

A+B=B+A

This means that the order in which the variables are OR-ed makes no difference.

In a similar way, the Commutative law for multiplication of two variables is

AB=BA

Output:-

Associative Law

The associative law for addition of three variables is written as

A+(B+C)=(A+B) + C

This means that the result is the same regardless of the order in which the variables are grouped.

In a similar way, the Associative law for multiplication of three variables is

A(BC)=(AB)C

Output

Distributive Law

The distributive law for three variables is written as

A(B+C)=AB+AC

Logic Circuit Design

Output

Result :

Thus all Boolean law was verified and implemented successfully.

Ex No:3 Name:Date: RegisterNo:

VERIFICATION OF DEMORGAN’S THEOREMS USING DIGITAL LOGIC GATES 4

Aim:-To Verify of DeMorgan’s Theorems using Digital Logic Gates

Theory

DeMorgan proposed two theorems that are used frequently in Boolean algebra.

The first theorem states:

The complement of two variables ANDed is equivalent to the OR of the complements of the individual variables.

This theorem can be expressed using the following formula:

Logic Circuit Design

OUTPUT:

The second theorem states: The complement of two variables ORed is equivalent to the AND of the complements of the individual variables. This theorem can be expressed using the following formula:

`

Result :

Thus all Boolean theorems was verified and implemented successfully.

Ex No: 4 Name:Date: RegisterNo:

DESIGN AND IMPLEMENTATION OF CODE CONVERTOR

Aim :-

To Design and Implement the Code Convertor using logic gates

Theory

The input variable are designated as B3, B2, B1, B0 and the output variables are

designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed.

A code converter is a circuit that makes the two systems compatible even though each

uses a different binary code. To convert from binary code to Excess-3 code, the input lines

must supply the bit combination of elements as specified by code and the output lines

generate the corresponding bit combination of code. Each one of the four maps represents

one of the four outputs of the circuit as a function of the four input variables.

A two-level logic diagram may be obtained directly from the Boolean expressions

derived by the maps. These are various other possibilities for a logic diagram that implements

this circuit. Now the OR gate whose output is C+D has been used to implement partially each

of three outputs.

Binary code to Gray Code

TRUTH TABLE:| Binary input | Gray code output |

B3 B2 B1 B0 G3 G2 G1 G00000000011111111

0000111100001111

0011001100110011

0101010101010101

0000000011111111

0000111111110000

0011110000111100

0110011001100110

Output

Gray to Binary

Output

TRUTH TABLE:

| Gray Code | Binary Code |

G3 G2 G1 G0 B3 B2 B1 B00000000011111111

0000111111110000

0011110000111100

0110011001100110

0000000011111111

0000111100001111

0011001100110011

0101010101010101

Result :Thus code convertor was designed and implemented successfully.

Ex No: 5 Name:Date: RegisterNo:

DESIGN AND IMPLEMENTATION OF HALF ADDER AND FULL ADDER Aim:

To design and construct half adder, full adder circuits and verify the truth table using

logic gates.

Theory

HALF ADDER:

A half adder has two inputs for the two bits to be added and two outputs one from the

sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is called as

a carry signal from the addition of the less significant bits sum from the X-OR Gate the carry

out from the AND gate.

Logic Circuit Design :

Output

FULL ADDER:

A full adder is a combinational circuit that forms the arithmetic sum of input; it

consists of three inputs and two outputs. A full adder is useful to add three bits at a time but a

half adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry output

will be taken from OR Gate.

Logic Circuit Design :

Output

Result :

Thus Half adder and full adder was designed and implemented successfully.

Ex No: 6 Name:Date: RegisterNo:

DESIGN AND IMPLEMENTATION OF HALF SUBTRACTOR AND FULL SUBTRACTOR

Aim:

To design and construct half subtractor and full subtractor circuits and verify the truth

table using logic gates.

HALF SUBTRACTOR:

The half subtractor is constructed using X-OR and AND Gate. The half subtractor has

two input and two outputs. The outputs are difference and borrow. The difference can be

applied using X-OR Gate, borrow output can be implemented using an AND Gate and an

inverter.

Logic Circuit Design :

Output

FULL SUBTRACTOR:

The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full

subtractor the logic circuit should have three inputs and two outputs. The two half subtractor

put together gives a full subtractor .The first half subtractor will be C and A B. The output

will be difference output of full subtractor. The expression AB assembles the borrow output

of the half subtractor and the second term is the inverted difference output of first X-OR.

Logic Circuit Design :

Output :

Result :

Thus Half subtractor and full subtractor was designed and implemented successfully.

Ex No: 7 Name:Date: RegisterNo:

DESIGN AND IMPLEMENTATION OF 4-BIT BINARY ADDERAim:

To design and implement 4-bit adder using Logic Gates

Theory:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two binary

numbers. It can be constructed with full adders connected in cascade, with the output carry

from each full adder connected to the input carry of next full adder in chain. The augends bits

of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from right to left, with

subscript 0 denoting the least significant bits. The carries are connected in chain through the

full adder. The input carry to the adder is C0 and it ripples through the full adder to the output

carry C4.

Logic Circuit Design :

Output

Result :

Thus 4 bit binary adder was designed and implemented successfully.

Ex No: 8 Name:

Date: RegisterNo:

DESIGN AND IMPLEMENTATION OF 4-BIT BINARY SUBTRACTOR

Aim:

To design and implement 4-bit subtractor using Logic GatesTheory:

4 BIT BINARY SUBTRACTOR:

The circuit for subtracting A-B consists of an adder with inverters, placed between

each data input ‘B’ and the corresponding input of full adder. The input carry C0 must be

equal to 1 when performing subtraction.

Logic Circuit Design :

OUTPUT:

Result :

Thus 4 bit binary Subtractor was designed and implemented successfully.

Ex No: 9 Name:

Date: RegisterNo:

DESIGN AND IMPLEMENTATION OF PARITY GENERATORAim:

To design and implement Parity generator/checker using Logic GatesTheory :

Parity Generator

A parity generator is a combinational logic circuit that generates the parity bit in the transmitter. On the other hand, a circuit that checks the parity in the receiver is called parity checker. A combined circuit or devices of parity generators and parity checkers are commonly used in digital systems to detect the single bit errors in the transmitted data word.

The sum of the data bits and parity bits can be even or odd. In even parity, the added parity bit will make the total number of 1s an even amount whereas in odd parity the added parity bit will make the total number of 1s odd amount.

The basic principle involved in the implementation of parity circuits is that sum of odd number of 1s is always 1 and sum of even number of 1s is always zero. Such error detecting and correction can be implemented by using Ex-OR gates (since Ex-OR gate produce zero output when there are even number of inputs).

Logic Circuit Design

4 bit parity generator

Output

Parity Check

It is a logic circuit that checks for possible errors in the transmission. This circuit can be an even parity checker or odd parity checker depending on the type of parity generated at the transmission end. When this circuit is used as even parity checker, the number of input bits must always be even.

When a parity error occurs, the ‘sum even’ output goes low and ‘sum odd’ output goes high. If this logic circuit is used as an odd parity checker, the number of input bits should be odd, but if an error occurs the ‘sum odd’ output goes low and ‘sum even’ output goes high.

Logic Circuit Design :

Output

Result :

Thus Parity generated and checked was designed and implemented successfully.

Ex No: 10 Name:

Date: RegisterNo:

DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATORAim:

To design and implement 2 – bit magnitude comparator using basic gates.

Theory

The comparison of two numbers is an operator that determines one number is greater

than, less than (or) equal to the other number. A magnitude comparator is a combinational

circuit that compares two numbers A and B and determine their relative magnitude. The

outcome of the comparator is specified by three binary variables that indicate whether A>B,

A=B (or) A<B.

A = A3 A2 A1 A0

B = B3 B2 B1 B0

The equality of the two numbers and B is displayed in a combinational circuit

designated by the symbol (A=B).

This indicates A greater than B, then inspect the relative magnitude of pairs of

significant digits starting from most significant position. A is 0 and that of B is 0.

We have A<B, the sequential comparison can be expanded as

A>B = A3B31 + X3A2B2

1 + X3X2A1B11 + X3X2X1A0B0

1

A<B = A31B3 + X3A2

1B2 + X3X2A11B1 + X3X2X1A0

1B0

The same circuit can be used to compare the relative magnitude of two BCD digits.

Where, A = B is expanded as,

A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)

x3 x2 x1 x0

Result :

Thus 2 bit magnitude comparator was designed and implemented successfully.

Ex No: 11 Name:Date: RegisterNo:

DESIGN AND IMPLEMENTATION OF MULTIPLEXER

Aim:

To design and implement multiplexer using basic gates.

Theory:

A multiplexer (or mux) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the output. Multiplexers are mainly used to increase the amount of data that can be sent over the network within a certain amount of time and bandwidth.. A multiplexer is also called a data selector. Multiplexers can also be used to implement Boolean functions of multiple variables.

Result :

Thus 4 – 1 multiplexer was designed and implemented successfully.

Ex No: 12 Name:Date: RegisterNo:

DESIGN AND IMPLEMENTATION OF DEMULTIPLEXER

Aim:

To design and implement multiplexer using basic gates.

Theory

A demultiplexer (or demux) is a device that takes a single input line and routes it to one of several digital output lines. A demultiplexer of 2n outputs has n select lines, which are used to select which output line to send the input.

Result :

Thus demultiplexer was designed and implemented successfully.

Ex No: 13 Name:

Date: RegisterNo:

CONSTRUCTION AND VERIFICATION OF 4 BIT RIPPLE COUNTER AND MOD 10 COUNTER (Asynchronous)

AIM:

To design and verify 4 bit ripple counter mod 10 counter.

THEORY:

A counter is a register capable of counting number of clock pulse arriving at its clock

input. Counter represents the number of clock pulses arrived. A specified sequence of states

appears as counter output. This is the main difference between a register and a counter. There

are two types of counter, synchronous and asynchronous. In synchronous common clock is

given to all flip flop and in asynchronous first flip flop is clocked by external pulse and then

each successive flip flop is clocked by Q or Q output of previous stage. A soon the clock of

second stage is triggered by output of first stage. Because of inherent propagation delay time

all flip flops are not activated at same time which results in asynchronous operation.

Logic Circuit Diagram

Output

TRUTH TABLE:

CLK QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

4 0 0 1 0

5 1 0 1 0

6 0 1 1 0

7 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10 0 1 0 1

11 1 1 0 1

12 0 0 1 1

13 1 0 1 1

14 0 1 1 1

15 1 1 1 1

Result :

Thus 4 bit ripple counter mod 10 counter designed and implemented successfully.

Ex No: 14 Name:

Date: RegisterNo:

SHIFT REGISTER - PARALLEL IN PARALLEL OUT

AIM:

To design and implement Parallel in parallel out

THEORY:

A register is capable of shifting its binary information in one or both directions is

known as shift register. The logical configuration of shift register consist of a D-Flip flop

cascaded with output of one flip flop connected to input of next flip flop. All flip flops

receive common clock pulses which causes the shift in the output of the flip flop. The

simplest possible shift register is one that uses only flip flop. The output of a given flip flop is

connected to the input of next flip flop of the register. Each clock pulse shifts the content of

register one bit position to right.

Logic Circuit Diagram

Output

TRUTH TABLE:

CLK

DATA INPUT OUTPUT

DA DB DC DD QA QB QC QD

1 1 0 0 1 1 0 0 1

2 1 0 1 0 1 0 1 0

Result :

Thus parallel in parallel out designed and implemented successfully