COMPARATIVE ANALYSIS FOR HARDWARE CIRCUIT

ARCHITECTURE OF WALLACE TREE MULTIPLIER

 

Fast multipliers are essential parts of digital signal processing systems.

The speed of multiply operation is of great importance in digital signal processing as well as in the general purpose processors, especially since the media processing took off.

With advances in technology, many researchers have tried and strive to design multipliers which offer either of the following- high speed, low power consumption, less area combination of them in multipliers, thus making them compatible for various high speed, low power, and compact VLSI implementations.

Objective

The new architecture enhances the speed performance of the widely acknowledged Wallace tree multiplier.

The structural optimization is performed on the conventional Wallace multiplier, in such a way that the latency of the total circuit reduces considerably.

The Wallace tree basically multiplies two unsigned integers. The conventional Wallace tree multiplier architecture comprises of an AND array for computing the partial products, a carry save adder for adding the partial products so obtained and a carry propagate adder in the final stage of addition.

Contin.,

In the conventional 8 bit Wallace tree multiplier design, more number of addition operations is required.

Using the carry save adder, three partial product terms can be added at a time to form the carry and sum.

The sum signal is used by the full adder of next level. The carry signal is used by the adder involved in the

generation of the next output bit, with a resulting overall delay proportional to log 3/2 n, for n number of rows.

EXISTING SYSTEM

Implementation of Wallace tree multiplier is made using TGA,GXFA and ZFA.

Where area and power are the main criteria, GXFA is a best suited and where speed is the only criteria, ZFA is best suited as an adder circuit.

Whereas Wallace tree multiplier using TGA gives good result in all the criteria. It consumes little more area than GXFA but very less than ZFA.

We can observe, 42% transistors are saved, results in reduction of area, and reduction in power at improved speed of operation.

PROPOSED SYSTEM

BLOCK DIAGRAM

Transmission gate based full adder circuit

A fast process for a multiplication of two numbers was developed by Wallace.

The structure of this method is looks like a tree that’s why the method is known as Wallace Tree

multipliers. Wallace tree multiplier is indicate A three-step process is used

to multiply two numbers by using this method is described as: (1)Formation of bit products (2) Reduction of the bit product matrix into a two row matrix by means of a carry save adder. (3) Summation of remaining two rows using a faster Carry Propagation Adder (CPA).

Wallace Tree Multiplier

Software Tools: Xilinx ISE 10.1 Model SIM ISE

TOOLS USED

C. N.Marimuthu, Dr. P. Thangaraj, Aswathy Ramesan, " Low powershift and add multiplier design", International Journal of ComputerScience and Information Technology, June 2010, Vol. 2, Number 3. battery life and high end circuits avoiding cooling packages and

reliability issues that are too complex. It is generally accepted that during logic synthesis power tracks well with area. This means that a larger design will generally consume more power. The multiplier is an important kernel of digital signal processors. Because of the circuit complexity, the power consumption and area are the two important design considerations of the multiplier. In this paper a low power low area architecture for the shift and add multiplier is proposed. For getting the low power low area architecture, the modifications made to the conventional architecture consist of the reduction in switching activities of the major blocks of the multiplier, which includes the reduction in switching activity of the adder and counter. This architecture avoids the shifting of the multiplier register.

Literature Survey

Marc Hunger, Daniel Marienfeld, “New Self-Checking Booth Multipliers”, International Journal of Applied Mathematics Computer Sci., 2008, Vol. 18, No. 3, 319–328.

This work presents the first self-checking Booth-3 multiplier and a new self-checking Booth-2 multiplier using parity prediction. We propose a method which combines error-detection of Booth-3 (or Booth-2) decoder cells and parity prediction. Additionally, code dis-jointness is ensured by reusing logic for partial product generation. Parity prediction is applied to a carry-save-adder with the standard sign-bit extension. In this adder almost all cells have odd fan-outs and faults are detected by the parity. Only one adder cell has an even fan-out in the case of Booth-3 multiplication. Especially, for even-number Booth-2 multipliers parity prediction becomes efficient. Since that prediction slightly differs from previous work which describes CSA-folded adders, formulas to predict the parity are developed here. The proposed multipliers are compared experimentally with existing solutions. Only 102% of the area of Booth-2 without error detection is needed for the self-checking Booth-3 multiplier.

Contin.,

1) C. N.Marimuthu, Dr. P. Thangaraj, Aswathy Ramesan, " Low power shift and add multiplier design", International Journal of Computer Science and Information Technology, June 2010, Vol. 2, Number 3.

2) Marc Hunger, Daniel Marienfeld, “New Self-Checking Booth Multipliers”, International Journal of Applied Mathematics Computer Sci., 2008, Vol. 18, No. 3, 319–328

3) C. Jaya Kumar, R. Saravanan, “VLSI Design for Low Power Multiplier using Full Adder”, European Journal of Scientific Research, ISSN 1450-216X Vol.72 No.1 (2012), pp. 5-16

4) Ravi Nirlakalla, Thota Subba Rao, Talari Jayachandra Prasad, “Performance Evaluation of High Speed Compressors for High Speed Multipliers”, Serbian Journal of Electrical Engineering, Vol. 8, No. 3, November 2011, 293-306

5) C. H. Chang, J. Gu, M. Zhang, “A review of 0.18μm full adder performances for tree structured arithmetic circuits”, IEEE Transactions Very Large Scale Integration System., Vol. 13, No. 6, June 2005, pp. 686 - 695.

REFERENCES