wafer probe technology application overview
TRANSCRIPT
Wafer Probe Technology & Application Overview
Ira Feldman650‐472‐[email protected]
1Silicon Valley Test Conference 2010© 2010 Ira Feldman
Agenda
• Introduction
• Application Examples
• Contact Technologies / Probe Types
• Top Vendors
• Hot Topics
• Summary
• Resources
Silicon Valley Test Conference 2010 2
Devices & Packages –Have Evolved!
Silicon Valley Test Conference 2010 3
UV EPROM circa 1974http://www.cpushack.com/EPROM.html
Peripheral Pads ‐ Logic
Silicon Valley Test Conference 2010 4
http://www.chipworks.com/uploadedImages/Blog/blogimagessq310/AKM8975_6210_cal_branded.JPG
SWTW 2009: MEMS Technology – Enabling Design Flexibility for Fine Pitch ProbingBahadir Tunaboylu, SV Probe
Fine Pitch Logic
Silicon Valley Test Conference 2010 5
Kulicke & Soffa: http://www.imaps.org/imaps2005/keynote.pdf
SWTW 2009: MEMS Technology – Enabling Design Flexibility for Fine Pitch ProbingBahadir Tunaboylu, SV Probe
Area Array – Logic, µP, etc.
Silicon Valley Test Conference 2010 6http://www.tradekorea.com/product-detail/P00032217/Solder_Bump.html
Marketing Version of a CPU…
Silicon Valley Test Conference 2010 7
Intel Core i7-980X Extreme 6-Core Processor (32nm Q1 ’10)http://hothardware.com/News/Intel-Core-i7980X-Extreme-6Core-
Processor-Review/
…What Probe Really Sees
Silicon Valley Test Conference 2010 8
Intel Technology Journal (6/2008):45 nm process ~50 µm tall Cu bumps
No One Solution Fits All
Silicon Valley Test Conference 2010 9
150 100 6080 2040Approximate Pitch (µm)
15
1050
100
App
roxi
mat
e P
robe
Cou
nt (K
)
TSV
Microprocessor&
Logic(Area Array)
DRAM&
NOR FLASHMemory
SOC&
Logic LCD /Display
NAND FLASH Memory
Many Other Parameters
• “Pad” type – bond pad, BGA, column, bump
• Pad Configuration – peripheral, LOC, DLOC, array
• Die Size
• Pad Size ‐ passivation opening & keep away
• Pad Metal – Al, Cu, Au, solder, etc.
• Force Requirements
• Scrub Depth
• Frequency / Bandwidth
• Pad Density (probes / mm2)
• Active Area (size of probe array)
• TemperatureSilicon Valley Test Conference 2010 10
Contact Technologies / Probe Types
• Cantilever
• Blade
• Vertical
• MEMS– Vertical
– Micro Cantilever
– Torsional
• Spring
• Membrane
Silicon Valley Test Conference 2010 11
Cantilever
Silicon Valley Test Conference 2010 12
Technoprobe
K&S: http://www.imaps.org/imaps2005/keynote.pdf
Blade
Silicon Valley Test Conference 2010 13SV Probe
Vertical‐ Buckling Beam
Silicon Valley Test Conference 2010 14
Mann: SWTW Tutorial 2004
SV Probe “Trio”
FormFactor: “MEMS for ProbeCard Applications” Chong Chan Pin – Semicon Singapore 2010
JEM “VC”
Vertical‐ Buckling Beam
Silicon Valley Test Conference 2010 15
MicroProbe: Apollo Vertical
JEM: VC
SV Probe: Trio
MEMS ‐ Vertical
Silicon Valley Test Conference 2010 16
Microfabrica MicroProbe
MicroProbe (Vx-MP)
FormFactor (T1)
MEMS ‐Micro Cantilever
Silicon Valley Test Conference 2010 17
Microfabrica
http://www.mjc.co.jp/eng/ir/pdf/MJC070226-s.pdf
MJC (U Probe)
FormFactor (T3)
JEM
MEMS ‐ Torsional
Silicon Valley Test Conference 2010 18
Touchdown Technologies (ACCU-TORQ)
SWTW 2010: “Low-Force MEMS Probe Solution for Full Wafer Single Touch Test” Matt Losey
Spring Pins
Silicon Valley Test Conference 2010 19
http://www.nhkspg.co.jp/eng/mc/products/wlt.html
http://www.ksdk.co.jp/eng/spring-probes.htmlJEM VS
Membrane
Silicon Valley Test Conference 2010 20
Cascade Microtech Pyramid Probe
Top Vendors ‐ Technology
Silicon Valley Test Conference 2010 21
Revenue per VLSI Research press releasehttps://vlsiwebserver.vlsiresearch.com/public/cms_pdf_upload/458310.pdf
Based upon website and company responses to marketing inquires.
Top Vendors ‐ Applications
Silicon Valley Test Conference 2010 22
Based upon website and company responses to marketing inquires.
Hot Topics (1)
• Bump / ball damage
• Cu probing
• High current
Silicon Valley Test Conference 2010 23
Most Inspirational
Most Inspirational
Hot Topics (2)
• High Frequency / high bandwidth– Advanced space transformers
– Modeling
– Direct Dock
Silicon Valley Test Conference 2010 24
Hot Topics (3)
• Operational – lower cost, quicker cycle time
Silicon Valley Test Conference 2010 25
Summary
• Device product requirements drive both packaging and test complexity– Essential to partner with suppliers from day one
• Careful selection of probe card vendors– Know strengths & weaknesses for your devices
– Technology may limit performance & impact cost
– No one solution fits all
Silicon Valley Test Conference 2010 26
Resources
• IEEE Semiconductor Wafer Test Workshopwww.swtest.org
• International Test Conferencewww.itctestweek.org
• My blogswww.hightechbizdev.com
www.ateforum.com/tothepoint
Silicon Valley Test Conference 2010 27
Credits
Thank you to the vendors who provided photos!
• FormFactor
• Technoprobe
• MicroProbe
• JEM
• SV Probe
• Cascade Microtech
Silicon Valley Test Conference 2010 28