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W83781D Winbond H/W Monitoring IC

W83781D Data Sheet Revision History Pages Dates Version Version

on Web Main Contents

1 n.a. n.a. All the version before 0.60 are internal use.

2 n.a. 11/07/97 0.60 n.a. First published.

3 5 11/19/97 0.61 n.a. Pin 18-20: I/O Type • I/O12ts

4 4 5 6

12/17/97 0.62 n.a. Pin18-20:I/O Type • Fan 1, Pin18:Fan1• Fan3 Pin23: I/O Type • OUT8t Pin42: I/O Type • OUT12

5 33 37 40 43 48

1/13/98 0.63 A1 8.24 index 55h(Bank 0) • Winbond Test Register 8.30 index 52h(Bank 1) bit2 • Reserve 8.37 index 52h(Bank 2) bit2 • Reserve 9.2 I/O 12ts TTL DC Characteristics Package QFT • LQFP

6 13 05/19/98 0.64 A1 Divisor table 1,2,3,4 • 1,2,4,8

7 n.a. 04/11/02 1.0 1.0 Change all version include version on web site to 1.0

8 48 10/25/02 1.1 1.1 Verify ISA Bus RD Timing.(210=>330ns)

9

10

Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.

W83781DWinbond H/WMonitoring IC

Publication Release Date: Oct. 2002 - I - Version 1.1

TABLE OF CONTENTS

1. GENERAL DESCRIPTION.................................................................................................. 1 2. FEATURES ......................................................................................................................... 1

2.1 MONITORING ITEMS ..................................................................................................................................1

2.2 ACTIONS ENABLING ..................................................................................................................................2

2.3 GENERAL ....................................................................................................................................................2

2.4 PACKAGE ....................................................................................................................................................2

3. KEY SPECIFICATIONS ...................................................................................................... 2 4. BLOCK DIAGRAM.............................................................................................................. 3 5. PIN CONFIGURATION........................................................................................................ 4 6. PIN DESCRIPTION ............................................................................................................. 5 7. FUNCTIONAL DESCRIPTION ............................................................................................ 7

7.1 GENERAL DESCRIPTION...........................................................................................................................7

7.1.1 The first serial bus access timing are shown as follow: .......................................................................9

7.1.2 The serial bus timing of the temperature 2 and 3 is shown as follow: ...............................................10

7.2 ANALOG INPUTS ......................................................................................................................................12

7.3 FAN INPUTS AND FAN CONTROL ..........................................................................................................13

7.4 TEMPERATURE MEASUREMENT MACHINE .........................................................................................14

8. CONTROL AND STATUS REGISTERS ........................................................................... 16 8.1 ADDRESS REGISTER (PORT X5H) .........................................................................................................16

8.2 DATA REGISTER (PORT X6H) .................................................................................................................19

8.3 CONFIGURATION REGISTER ¾- INDEX 40H (BANK 0) ........................................................................19

8.4 INTERRUPT STATUS REGISTER 1¾ INDEX 41H (BANK 0) ..................................................................20

8.5 INTERRUPT STATUS REGISTER 2 ¾ INDEX 42H (BANK 0) .................................................................21

8.6 SMI# MASK REGISTER 1 ¾ INDEX 43H (BANK 0) ................................................................................21


Publication Release Date: Oct. 2002 - II - Version 1.1

8.7 SMI# MASK REGISTER 2 ¾ INDEX 44H (BANK 0) .................................................................................22

8.8 IRQ MASK REGISTER 2 ¾ INDEX 45H (BANK 0) ...................................................................................22

8.9 IRQ MASK REGISTER 2 ¾ INDEX 46H (BANK 0) ...................................................................................23

8.10 VID/FAN DIVISOR REGISTER ¾ INDEX 47H (BANK 0)........................................................................23

8.11 SERIAL BUS ADDRESS REGISTER ¾ INDEX 48H (BANK 0) ..............................................................24

8.12 VALUE RAM ¾ INDEX 20H- 3FH OR 60H – INDEX 7FH (AUTO-INCREMENT) (BANK 0) ..................25

8.13 VOLTAGE ID (VID7-4) – INDEX 49H (BANK 0) ......................................................................................27

8.14 TEMPERATURE 2 AND TEMPERATURE 3 SERIAL BUS ADDRESS REGISTER INDEX 4AH (BANK 0).....................................................................................................................................................................28

8.15 PIN CONTROL REGISTER – INDEX 4BH (BANK 0)..............................................................................29

8.16 IRQ/OVT# PROPERTY SELECT – INDEX 4CH (BANK 0) ....................................................................30

8.17 FAN IN/OUT AND BEEP/GPO# CONTROL REGISTER -- INDEX 4DH (BANK 0) ................................31

8.18 REGISTER 50H ~ 5FH BANK SELECT -- INDEX 4EH (NO AUTO INCREASE) (BANK 0) ...................32

8.19 WINBOND VENDOR ID -- INDEX 4FH (NO AUTO INCREASE) (BANK 0)............................................32

8.20 RESISTOR-TEMPERATURE TABLE REGISTER – INDEX 50H - 51H (BANK 0)..................................33

8.21 WINBOND TEST REGISTER 1 – INDEX 52H (BANK 0) ........................................................................33




8.25 BEEP CONTROL REGISTER 1— INDEX 56H (BANK 0) (AUTO-INCREMENT)...................................34

8.26 BEEP CONTROL REGISTER 2— INDEX 57H (BANK 0) ( NO AUTO-INCREMENT) ...........................34

8.27 CHIP ID- INDEX 58H (BANK 0) ...............................................................................................................35

8.28 TEMPERATURE SENSOR 2 TEMPERATURE REGISTER - INDEX 50H (BANK 1).............................36


8.30 TEMPERATURE SENSOR 2 CONFIGURATION REGISTER - INDEX 52H (BANK 1)..........................37

8.31 TEMPERATURE SENSOR 2 HYSTERESIS (HIGH BYTE) REGISTER - INDEX 53H (BANK 1) ..........37

8.32 TEMPERATURE SENSOR 2 HYSTERESIS (LOW BYTE) REGISTER - INDEX54H (BANK 1) ............38

8.33 TEMPERATURE SENSOR 2 OVER-TEMPERATURE(HIGH BYTE) REGISTER - INDEX 55H (BANK 1).....................................................................................................................................................................38

8.34 TEMPERATURE SENSOR 2 OVER-TEMPERATURE (LOW BYTE) REGISTER - INDEX 56H (BANK 1).....................................................................................................................................................................39



8.37 TEMPERATURE SENSOR 3 CONFIGURATION REGISTER - INDEX 52H (BANK 2)..........................40


Publication Release Date: Oct. 2002 - III - Version 1.1

8.38 TEMPERATURE SENSOR 3 HYSTERESIS (HIGH BYTE) REGISTER - INDEX 53H (BANK 2) ..........41

8.39 TEMPERATURE SENSOR 3 HYSTERESIS (LOW BYTE) REGISTER - INDEX 54H (BANK 2) ...........41

8.40 TEMPERATURE SENSOR 3 OVER-TEMPERATURE (HIGH BYTE)REGISTER - INDEX 55H (BANK 2).....................................................................................................................................................................42

8.41 TEMPERATURE SENSOR 3 OVER-TEMPERATURE (LOW BYTE) REGISTER - INDEX 56H (BANK 2).....................................................................................................................................................................42

9. SPECIFICATIONS............................................................................................................. 43 9.1 ABSOLUTE MAXIMUM RATINGS.............................................................................................................43

9.2 DC CHARACTERISTICS ...........................................................................................................................43

9.2.1 AC Characteristics..............................................................................................................................45

9.2.2 ISA Read/Write Interface Timing........................................................................................................45

9.2.3 Serial Bus Timing Diagram ................................................................................................................46

10. HOW TO READ THE TOP MARKING ............................................................................ 47 11. PACKAGE DIMENTIONS ............................................................................................... 48 12. APPLICATION CIRCUITS OF W83781D........................................................................ 49

W83781D

Publication Release Date : Oct. 2002

Revision 1.1

1

1. GENERAL DESCRIPTION The W83781D is a hardware status monitoring IC for personal computers, server computers, or microprocessor based systems. W83781D can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stable and properly. W83781D provides both ISA and I2CTM serial bus interface. A 8-bit analog-to-digital converter (ADC) was built inside W83781D. The W83781D can monitor 3 external thermistor temperature sensors, 5 positive analog voltage inputs, two inverting inputs (for monitoring negative voltages), and also three fan tachometer outputs. There is also one input for case open detection circuits. With the application software, the users can read all the monitored parameters of system from time to time. The application software could be the popular IntelTM LDCM (LANDesk Client Management) or Winbond• application software. Also the users can set up the upper and lower limits of these monitored parameters and to activate two programmable and maskable interrupts. An optional beep tone could be used as warning signal when the monitored parameters is out of the preset range. Additionally, 5 VID inputs are provided to read the VID of CPU (such as PentiumTM II) if applicable. This is to provide the Vcore correction automatically. Also W83781D uniquely provides an optional feature: early stage (before BIOS was load) beep warning. This is to detect if the fatal elements present --- VcoreA, +3.3V voltage fail, and the system can not be boomed up.

W83781D


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2. FEATURES

2.1 Monitoring Items • 3 thermal inputs from remote thermistors • 5 positive voltage inputs (typical for +12V, +5V, +3.3V, VcoreA, VcoreB) • 2 op amps for negative voltage monitoring (typical for -12V, -5V) • 3 fan speed monitoring inputs • Case open detection input • WATCHDOG comparison of all monitored values • Programmable hysteresis and setting points for all monitored items

2.2 Actions Enabling • Warning signal pop up in application software • Beep tone warning • Fan ON/OFF control • Issue SMI#, IRQ to activate system protection

2.3 General • ISA and I2CTM serial bus interface • 5 VID input pins for CPU Vcore identification • Initial power fault beep (for +3.3V, VcoreA) • Master reset input to W83781D • Independent power plane of digital Vcc and analog Vcc (input to IC) • Intel LDCMTM compatible • Winbond monitoring application software support • Input clock rate optional for 24, 48, 14.318 MHz

2.4 Package • 48-pin LQFP

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3. KEY SPECIFICATIONS • Voltage monitoring accuracy ±1% (Max) • Monitoring Temperature Range and Accuracy - 40°C to +120°C ± 3°C(Max) • Supply Voltage 5V • Supply Current Operating: 1 mA typ. Shutdown: 10 µA typ. ADC Resolution 8 Bits

4. BLOCK DIAGRAM

8-Bit A/Dand Mux16mV LSB0~4.096VInput

::

IN0 :IN6

::

VTIN3 :VTIN1

FAN Speed Counter

::

FAN3 :FAN1

SDA

SCL

CLKIN

IOWR#

IORD#

CS#

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

ISA/Serial Bus Interface

Configure and ControlRegisters

Watch-Dog and Interrupt Status Registers

BEEP / GPO#

RSTOUT#

CASEOPEN

(Serial Bus) (ISA Bus Interface)

SMI#

IRQ

MR

OVT#

::

VID0 :VID4

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5. PIN CONFIGURATION

V C CGND D

S C LS D A

IOW#

CLK IN

D0

D1

D2

D3

D4

D5

D6

D7

W83781D

1 1213

2425

MR

36

37

48

VCOREA

VCOREB

+3.3 V

+5V I

+12 V

-12 V

-12 V O

-5VOUT

-5V I

GNDA

V ID

CASEOPEN

IOR#

V ID1

BEEP/GPO#

CS#A0A1A2

SMI#IRQ

OVT#VID0VTIN1

VTIN3VTIN2

VREF

VID4FAN3 IN/OUTFAN2 IN/OUTFAN1 IN/OUT

RSTOUT#VID2

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6. PIN DESCRIPTION I/O12t - TTL level bi-directional pin with 12 mA source-sink capability I/O12ts - TTL level and schmitt trigger OUT12t - TTL level output pin with 12 mA source-sink capability OUT8t - TTL level output pin with 8 mA source-sink capability AOUT - Output pin(Analog) OD8 - Open-drain output pin with 8 mA sink capability OD12 - Open-drain output pin with 12 mA sink capability OD48 - Open-drain output pin with 48 mA sink capability INt - TTL level input pin INts - TTL level input pin and schmitt trigger AIN - Input pin(Analog)

Pin Name Pin No.

Type Description

IOR# 1 INt s An active low standard ISA bus I/O Read Control. IOW# 2 INt s An active low standard ISA bus I/O Write Control. CLKIN 3 INt System clock input. Can select 48MHz or 24MHz or 14.318MHz.

The default is 24MHz. D7~D0 4-

11 I/O12t Bi-directional ISA bus Data lines. D0 corresponds to the low order

bit, with D7 the high order bit. VID1 12 INt Voltage Supply readouts from P6.This value is read in the VID/Fan

Divisor Register. VCC (+5V) 13 POWER +5V VCC power. Bypass with the parallel combination of 10µF

(electrolytic or tantalum) and 0.1µF (ceramic) bypass capacitors. GNDD 14 DGROUND Internally connected to all digital circuitry. MR 15 INt s Master reset input. CASEOPEN 16 I/O12t CASE OPEN. An active high input from an external circuit which

latches a Case Open event. This line can go high without any clamping action intrusion regardless of the powered state of the W83781D. The W83781D provides an internal open drain on this line, controlled by Bit 7 of IRQ Mask Register 2, to provide a minimum 20 ms reset of this line.

VID4 17 INt Voltage Supply readouts from P6.This value is read in the bit <0> of Device ID Register.

FAN3-FAN1 IN/OUT

18-20

I/O12ts 0V to +5V amplitude fan tachometer input / Fan on-off control output. These multifunctional pins can be programmable input or output.

SCL 21 INt s Serial Bus Clock. SDA 22 I/O12ts Serial Bus bi-directional Data. RSTOUT#

23 OUT8t 8 mA driver (open drain), active low output with a 20 ms minimum pulse width. Available when enabled via Bit 7 in SMI# Mask Register 2.

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6. Pin Description , continued Pin Name Pin

No. Type Description

VID2 24 INt Voltage Supply readouts from P6.This value is read in the VID/Fan Divisor Register.

VID3 25 INt Voltage Supply readouts from P6.This value is read in the VID/Fan Divisor Register.

BEEP/GPO# 26 OD48 Beep function or General purpose output (active low). This pin is open drain driving 48 mA. This multifunctional pin is programmable selected by CR4D bit 6.

GNDA 27 AGROUND Internally connected to all analog circuitry. The ground reference for all analog inputs.

-5VIN 28 AIN Ground-referred inverting op amp input. -5VOUT 29 AOUT Output of inverting op amp for Input 6. -12VOUT 30 AOUT Output of inverting op amp for Input 5. -12VIN 31 AIN Ground-referred inverting op amp input. +12VIN 32 AIN 0V to 4.096V FSR Analog Inputs. +5VIN 33 AIN This pin is Analog Vcc and connects internal monitor channel IN3

with fixed scale. +3.3VIN 34 AIN 0V to 4.096V FSR Analog Inputs. VCOREB 35 AIN 0V to 4.096V FSR Analog Inputs. VCOREA 36 AIN 0V to 4.096V FSR Analog Inputs. VREF 37 AOUT Reference Voltage. VTIN3 38 AIN Thermistor 3 terminal input. VTIN2 39 AIN Thermistor 2 terminal input. VTIN1 40 AIN Thermistor 1 terminal input. VID0 41 INt Voltage Supply readouts from P6.This value is read in the VID/Fan

Divisor Register. OVT# 42 OD12 Over temperature Shutdown Output. IRQ 43 OUT12t Interrupt Request. SMI# 44 OD12 System Management Interrupt (open drain). This output is enabled

when Bit 1 in the Configuration Register (CR40) is set to 1. The default state is disabled.

A2-A0 45-47

INt The three lowest order bits of the 16-bit ISA Address Bus. A0 corresponds to the lowest order bit.

CS# 48 INt Chip Select input from an external decoder which decodes high order address bits on the ISA Address Bus. This is an active low input.

# Indicates Active Low("Not")

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7. FUNCTIONAL DESCRIPTION

7.1 General Description The W83781D provides 5 analog positive inputs, 2 analog negative input, 3 fan speed monitors or fan ON/OFF control, 3 thermistor voltage inputs, case open detection and beep function output when the monitor value exceed the set limit value. When start the monitor function on the chip, the watch dog machine monitor every function and store the value to registers. If the monitor value exceeds the limit value, the interrupt status will be set to 1. The W83781D provides two interface for microprocessor to read/write internal registers. The first interface use ISA Bus to access which the ports of low byte (bit2~bit0) are defined in the port 5h and 6h. The high byte of these ports is decoded by Chip Select (CS#), the general decoded address is set to port 295h and port 296h. These two ports are described as following: Port 295h: W83781D Index register port. Port 296h: Data port. The register structure is showed as the diagram next page. The second interface use Serial Bus. In the W83781D has three serial bus address. That is, the first address defined at CR48 can read/write all registers excluding Bank 1 and Bank 2 temperature 2/3 registers, the second address defined at CR4A.bit2-0 only read/write temperature sensor 2 registers, and the third address defined at CR4A.bit6-4 only can access (read/write) temperature sensor 3 registers.

W83781D


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Configuration Register40h

Interrupt Status Registers41h, 42h

SMI# & IRQ Mask Registers42h, 43, 44h, 45h

VID<3:0>/Fan Divisor Register47h

Serial Bus Address48h

Monitor Value Registers20h~3Fh

and60h~7Fh (auto-increment)

VID<4>/Device ID49h

Temperature 2, 3 Serial Bus Address

4Ah

Pin Control Register4Bh

IRQ Polarity Select4Ch

Fan IN/OUT and BEEP/GPO# Control Register

4Dh

Select Bank for 50h~5Fh Reg.4Eh

Winbond Vendor ID4Fh

BANK 0 R-T Table ValueBEEP Control RegisterWinbond Test Register

50h~58h

BANK 1Temperature 2 Control/Staus Registers

50h~56h

BANK 2Temperature 3 Control/Staus Registers

50h~56h

DataRegister

Port 6h

Port 5h

Index Register

ISADataBus

ISAAddress

Bus

W83781D


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7.1.1 The first serial bus access timing are shown as follow: (a) Serial bus write to internal address register followed by the data byte

0

Start ByMaster

0 1 0 1 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0Ackby781D

R/WAckby781D

SCL

SDA

D7 D6 D5 D4 D3 D2 D1 D0Ackby781D

Stopby

Master

SCL

SDA (Continued)

7 8 0 7 8

07 8

Frame 2Internal Index Register Byte

(Continued)

Frame 3Data Byte

Frame 1Serial Bus Address Byte

Serial Bus Write to Internal Address Register followed by the Data Byte (b) Serial bus write to internal address register only

0

Start ByMaster

0 1 0 1 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0Ackby781D

R/WAckby781D

SCL

SDA

7 8 0 7 8

0



Serial Bus Write to Internal Address Register Only

Stop byMaster

(c) Serial bus read from a register with the internal address register prefer to desired location

0

Start ByMaster

0 1 0 1 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0Ackby

Master

R/WAckby781D

SCL

SDA

7 8 0 7 8

0



Serial Bus Write to Internal Address Register Only

Stop byMaster

W83781D


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7.1.2 The serial bus timing of the temperature 2 and 3 is shown as follow: (a) Typical 2-byte read from preset pointer location (Temp, TOS, THYST)

0

Start ByMaster

0 1 0 1 1 0 1 D7 D1 D0Ackby

Master

R/WAckby781D

SCL

SDA

7 8 0 7 8

Frame 2MSB Data Byte


Typical 2-Byte Read From Preset Pointer Location

D7 D1 D0

0 7

Stop byMaster

...

... ...

Ackby

Master

...Frame 3

LSB Data Byte

(b) Typical pointer set followed by immediate read for 2-byte register (Temp, TOS, THYST)

0

Start ByMaster

D7 D1 D0Ackby

MasterAckby781D

SCL

SDA

7 8 0 7 8

0



Typical Pointer Set Followed by Immediate Read for 2-Byte Register

D7 D1 D0

0 7

Stop byMaster

...

... ...

No Ackby

Master

...Frame 5

LSB Data Byte

0

Start ByMaster

1 0 0 1 A2 A1 A0 R/WAckby781D

SCL

SDA

7 8 0


4

D1 D0Ackby781D

Frame 2Pointer Byte

1 0 0 1 A2 A1 A0 R/W

0 0 0 0 0 0

(c) Typical read 1-byte from configuration register with preset pointer

0

Start ByMaster

D7 D2Ackby781D

SCL

SDA

7 8 0

Frame 2Data Byte


Typical 1-Byte Read From Configuration With Reset Pointer

D0

7

Stop byMaster

No Ackby

Master

1 0 0 1 A2 A1 A0 R/W D1D5 D4 D3D6

8

W83781D


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(d) Typical pointer set followed by immediate read from configuration register

0

RepeaStart

ByMaster

D7 D5 D4Ackby781D

SCL (Cont..)

SDA (Cont..)

7 8 0



Typical Pointor Set Followed by Immediate Read from Temp 2/3 Configuration Register

D2 D1 D0

7

Stop byMaster

No Ackby

Master

0

Start ByMaster

1 0 0 1 A2 A1 A0 R/WAckby781D

SCL

SDA

7 8 0


4

D1 D0Ackby781D

Frame 2Pointer Byte

1 0 0 1 A2 A1 A0 R/W

...

...

D6 D3

8

7 8

0 0 0 0 00

(e) Temperature 2/3 configuration register Write

0

Ackby781D

SCL (Cont...)

SDA (Cont...)

7 8

Frame 3Configuration Data Byte

Configuration Register Write

0

Start ByMaster

1 0 0 1 A2 A1 A0 R/WAckby781D

SCL

SDA

7 8 0


4

D1 D0Ackby781D

Frame 2Pointer Byte

0 0 D4 D3 D2 D10 D0Stopby

Master

0 0 0 0 0 0 0

7 8

W83781D


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(f) Temperature 2/3 TOS and THYST write

0

Ackby781D

SCL (Cont...)

SDA (Cont...)

7 8


Configuration Register Write

0

Start ByMaster

1 0 0 1 A2 A1 A0 R/WAckby781D

SCL

SDA

7 8 0


4

D1 D0Ackby781D

Frame 2Pointer Byte

D6 D5 D4 D3 D2 D1D7 D0

0 7 8

D6 D5 D4 D3 D2 D1D7 D0Ackby781D

Stopby

MasterFrame 4

LSB Data Byte

7 8

0 0 0 0 0 0

7.2 Analog Inputs The maximum input voltage of the analog pin is 4.096 because the 8-bit ADC has a 16mv LSB. Really, the application of the PC monitoring would most often be connected to power suppliers. The CPU V-core voltage and 3.3V can directly connected to these analog inputs. The +5V and +12V inputs should be reduced a factor with external resistors so as to obtain the input range. As followed figure is shown.

Pin 36+2.5VINA

+2.5VINB Pin 35

+3.3VIN

+12VIN

Pin 34

Pin 32Pin 33VDD(+5V)

-

+

-

+

-12VIN

-12VOUT

Pin 31

Pin 30

R2

R1

RF

RIN

Vs

Vs

Positive Input

Negative Input

8-bit ADCwith

16mV LSB

Typical Thermister Connection

10K, 1%

RTHM

VREF Pin 37

VTIN3

VTIN2

VTIN1

Pin 38

Pin 39

Pin 40

-5VIN

-5VOUT Pin 29

Pin 28

Positive Inputs

The input voltage can be expressed as following equation.

W83781D


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V VR

R RIN s= ×+

2

1 2

The value of R1 and R2 can be selected to 28K Ohms and 10K Ohms, respectively, when the input voltage is 12V. The Pin 33 is connected to +5V power supply to provide analog power, and this voltage is connected to internal resistors to monitor the +5V voltage. The negative voltage should be connected an op amps to invert and reduce the -5V and -12V voltage. The input voltage can be calculated by following equation.

V VRRS IN

F

IN= − × ( )

The Winbond recommended value is RIN=90.9K Ohms and RF=60.4K Ohms for -5V voltage input, RIN=210K Ohms and RF=60.4K Ohms for -12V voltage input. The temperature sensors are connected by a 10K Ohms, then connect to VREF (Pin 37). The sensors should choose 10K Ohms at 25°C and β-value is 3435 for default R-T table. If the β-value is not 3435, the R-T table should be re-program to generate a correct temperature.

7.3 FAN Inputs and FAN Control Inputs are provides for signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and maximum input voltage can not be over +5.5V. If the input signals from the tachometer outputs are over the VCC, the external trimming circuit should be added to reduce the voltage to obtain the input specification. The normal circuit and trimming circuits are shown as following. Determine the fan counter according to:

CountRPM Divisor

=×

×135 106.

The default divisor is 2 and defined at CR47.bit7~4 and CR4B.bit7~6. The followed table is an example for the relation of divisor, PRM, and count.

Divisor Nominal PRM

Time per Revolution

Counts 70% RPM Time for 70%

1 8800 6.82 ms 153 6160 9.74 ms 2 4400 13.64 ms 153 3080 19.48 ms 4 2200 27.27 ms 153 1540 38.96 ms 8 1100 54.54 ms 153 770 77.92 ms

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FANConnector

FAN Out

+12V

GND

Pull-up resister4.7K Ohms

+5V+12V

Fan InputPin 18/19/20

W83781D FANConnector

FAN Out

+12V

GND

Pull-up resister4.7K Ohms

+12V


W83781D

14K~39K

10K

Fan with Tach Pull-Up to +12V, or Totem-PoleOutput and Register AttenuatorFan with Tach Pull-Up to +5V

FANConnector

FAN Out

+12V

GND

Pull-up resister> 1K

+12V


W83781D FANConnector

FAN Out

+12V

GND

Pull-up resister < 1Kor totem-pole output

+12V


W83781D

> 1K

Fan with Tach Pull-Up to +12V, or Totem-PolePutput and Zener Clamp

Fan with Tach Pull-Up to +12V and Zener Clamp

3.9V Zener3.9V Zener

7.4 Temperature Measurement Machine The temperature data format is 8-bit two•-complement for sensor 1 and 9-bit two•-complement for sensor 2/3. The table are expressed the temperature data as following. Temperature 8-Bit Digital Output 9-Bit Digital Output

8-Bit Binary 8-Bit Hex 9-Bit Binary 9-Bit Hex +125°C 0111,1101 7Dh 0,1111,1010 0FAh +25°C 0001,1001 19h 0,0011,0010 032h +1°C 0000,0001 01h 0,0000,0010 002h

+0.5°C - - 0,0000,0001 001h +0°C 0000,0000 00h 0,0000,0000 000h

-0.5°C - - 1,1111,1111 1FFh -1°C 1111,1111 FFh 1,1111,1110 1FFh -25°C 1110,0111 E7h 1,1100,1110 1CEh -55°C 1100,1001 C9h 1,1001,0010 192h

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The W83781D temperature interrupt has two mode: (1) The first is Interrupt Mode--exceeding TOI causes an interrupt until reset by reading Interrupt Status Register 1 (CR41). Once an interrupt event has occurred over TOI, the interrupt will occur again by the temperature going below THYST. (2) Comparator Mode--setting the THYST limit to 127°C will cause the comparator mode. When temperature exceeds TOI, the interrupt will be generate Interrupt. If the temperature goes below the TOI, the interrupt will be reset. Two interrupt modes are shown as below.

TOI

THYST

* * *

(1) Interrupt Mode

*Interrupt Reset when Interrupt Status Register 1 is read

TOI

THYST

(2) Comparator Mode

127 C

IRQ IRQ

The temperature sensor 2 or 3 Over-Temperature (OVT) response is same as temperature sensor 1 IRQ signal.

TOI

THYST

* * *

Over-Temperature Response Diagram

*Interrupt Reset when Temperature 2/3 is read

OVT#

OVT#

*

(Comparator Mode; default)

((Interrupt Mode)

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8. CONTROL AND STATUS REGISTERS

8.1 Address Register (Port x5h) The main register is the INDEX Register located at Port x5h. The bit designations are as follows:

7 6 5 4 3 2 1 0

INDEX Pointe

Busy

Bit7: Read Only

The logical 1 indicates the device is busy because of a Serial Bus transaction or another ISA bus transaction. With checking this bit, multiple ISA drivers can use W83781D without interfering with each other or a Serial Bus driver.

It is the user's responsibility not to have a Serial Bus and ISA bus operations at the same time.

This bit is:

Set: with a write to Port x5h or when a Serial Bus transaction is in progress.

Reset: with a write or read from Port x6h if it is set by a write to Port x5h, or when the Serial Bus transaction is finished.

Bit 6-0: Read/Write

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INDEX of Control and Status Registers. See the tables below for detail. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Busy Index Pointer (Power On default 00h)

(Power On default 0) A6 A5 A4 A3 A2 A1 A0 Index Pointer (A6-A0)

Registers Bank A6-A0 in Hex

Power On Value of Registers: <7:0>in Binary

Notes

Configuration Register 0 40h 00001000 Interrupt Status Register 1 0 41h 00000000 Auto-increment to the

address of Interrupt Status Register 2 after a read or write to Port x6h.

Interrupt Status Register 2 0 42h 00000000 SMI# Mask Register 1 0 43h 00000000 Auto-increment to the

address of SMI# Mask Register 2 after a read or write to Port x6h.

SMI# Mask Register 2 0 44h 00000000 IRQ Mask Register 1 0 45h 00000000 Auto-increment to the

address of IRQ Mask Register 2 after a read or write to Port x6h

IRQ Mask Register 2 0 46h 00000000 VID/Fan Divisor Register 0 47h <7:4> = 0101;

<3:0> = VID3-VID0

Serial Bus Address Register

0 48h <6:0> = 0101101; <7> = 0

Voltage ID 0 49h <7:6> is Reserved <5:4> is 01 binary <0> is mapped to VID <4>

Temperature 2 and Temperature 3 Serial Bus Address Register

0 4Ah <7:0> = 0000,0001 binary

Pin Control Register 0 4Bh <7:0> 44h RQ/OVT# Property Select 0 4Ch <7:0> ---0,0001 FAN IN/OUT and BEEP/GPO# Control Register

0 4Dh <7:0> 0001,0101

Register 50h ~ 5Fh Bank Select

0 4Eh <6:3> = Reserved, <7> = 1, <2:0> = 0

Winbond Vendor ID 0 4Fh <15:0> = 5CA3h Resistor-Temperature 0 50-51h

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Table Register Index Pointer (A6-A0),continued

Registers Bank A6-A0 in Hex

Power On Value of Registers:

<7:0>in Binary

Notes

FAN Input Clock Pre-Divisor Register 2

0 55h <7:0> -000,0001

BEEP Control Register 1 0 56h <7:0> 0000,0000 BEEP Control Register 2 0 57h <7:0> 1000-0000 Chip ID 0 58h <7:0> 0001-0000 Temperature Sensor 2 Temperature Register

1 50-51h

Temperature Sensor 2 Configuration Register

1 52h <7:0> = 0x00

Temperature Sensor 2 Hysteresis (High Byte) Register

1 53h <7:0> = 0x4B

Temperature Sensor 2 Hysteresis (Low Byte) Register

1 54h <7:0> = 0x0

Temperature Sensor 2 Over-temperature(High Byte) Register

1 55h <7:0> = 0x50

Temperature Sensor 2 Over-temperature (Low Byte) Register

1 56h <7:0> = 0x0

Temperature Sensor 3 Temperature Register

2 50-51h

Temperature Sensor 3 Configuration Register

2 52h <7:0> = 0x00

Temperature Sensor 3 Hysteresis (High Byte) Register

2 53h <7:0> = 0x4B

Temperature Sensor 3 Hysteresis (Low Byte) Register

2 54h <7:0> = 0x0

Temperature Sensor 3 Over-temperature (High Byte)Register

2 55h <7:0> = 0x50

Temperature Sensor 2 Over-temperature (Low Byte) Register

2 56h <7:0> = 0x0

Value RAM 0 20-3Fh Value RAM 0 60-7Fh Auto-increment to the next

location after a read or write to Port x6h and stop at 7Fh.

Note: Index Pointer (A6-A0) and Value RAM only can be read at the � accurate bank� .

8.2 Data Register (Port x6h) Data Port: Port x6h

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Power on Default Value 00h Attribute: Read/write Size: 8 bits

7 6 5 4 3 2 1 0

Data

Bit 7-0: Data to be read from or to be written to RAM and Register.

8.3 Configuration Register - Index 40h (Bank 0) Register Location: 40h Power on Default Value 00000001 binary Attribute: Read/write Size: 8 bits

7 6 5 4 3 2 1 0

STARTEN_SMI#EN_IRQINT_CLEARRST_OUT#IRQPOLBEEP/GPO#INITIALIZATION

Bit 7:The logical 1 restores power on default value to all registers except the Serial Bus Address register. This bit clears itself since the power on default is zero.

Bit 6:The logical 1 in this bit drives a zero on GPO# pin.

Bit 5:IRQ polarity select. When set to 0, IRQ active high. Set to 1, IRQ active low. Default 0.

Bit 4:The logical 1 outputs at least a 20 ms active low reset signal at RST_OUT# if <7> = 1 in SMI# Mask Register 2. This bit is cleared once the pulse has gone inactive.

Bit 3:The logical 1 disables the SMI# and IRQ outputs without affecting the contents of Interrupt Status Registers. The device will stop monitoring. It will resume upon clearing of this bit.

Bit 2:The logical 1 enables the IRQ Interrupt output.

Bit 1:The logical 1 enables the SMI# Interrupt output.

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Bit 0: 1 enables startup of monitoring operations

0 puts the part in standby mode. Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "INT_CLEAR'' bit.

8.4 Interrupt Status Register 1 Index 41h (Bank 0) Register Location: 41h Power on Default Value 00h Attribute: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

IN0IN1IN2IN3TEMP1TEMP23FAN1FAN2

Bit 7: The logical 1 indicates the fan count limit has been exceeded.


Bit 5: The logical 1 indicates a High or Low limit has been exceeded from temperature sensor 2 or sensor 3. The high and low limits value are defined in index registers: 53h-56h of the Bank 1.

Bit 4: The logical 1 indicates a High or Low limit has been exceeded from temperature sensor 1.

Bit 3-0: The logical 1 indicates a High or Low limit has been exceeded.

8.5 Interrupt Status Register 2 Index 42h (Bank 0) Register Location: 42h Power on Default Value 00h Attribute: Read Only Size: 8 bits

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7 6 5 4 3 2 1 0

IN4-IN5-IN6FAN3Case OpenReservedReservedReserved

Bit 7-5:Reserved.This bit should be set to 0.

Bit 4: The logical 1 indicates Case Open has gone high.


Bit 2-0: The logical 1 indicates a High or Low limit has been exceeded.

8.6 SMI# Mask Register 1 Index 43h (Bank 0) Register Location: 43h Power on Default Value 00h Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

IN0IN1IN2IN3TEMP1TEMP23FAN1FAN2

Bit 7-0: The logical 1 disables the corresponding interrupt status bit for SMI# interrupt.

8.7 SMI# Mask Register 2 Index 44h (Bank 0) Register Location: 44h Power on Default Value 00h Attribute: Read/Write Size: 8 bits

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7 6 5 4 3 2 1 0

IN4-IN5-IN6FAN3Case OpenReservedReservedRST_OUT# Enable

Bit 7: <7> = 1 in SMI# ask Register 2 enables the RST_OUT# in the Configuration Register. 13.8 IRQ Mask Register 1Index 45h

Bit 6-5: Reserved. This bit should be set to 0.

Bit 4-0: The logical 1 disables the corresponding interrupt status bit for SMI# interrupt.

8.8 IRQ Mask Register 2 Index 45h (Bank 0) Register Location: 45h Power on Default Value 00h Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

V25INAV25INBV33INV5INVTHIN1VTHIN23FAN1FAN2

Bit 7-0: The logical 1 disables the corresponding interrupt status bit for IRQ interrupt.

8.9 IRQ Mask Register 2 Index 46h (Bank 0) Register Location: 46h Power on Default Value <7:0> = 01000000 binary Attribute: Read/Write Size: 8 bits

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7 6 5 4 3 2 1 0

IN4-IN5-IN6FAN3Case OpenReservedReservedChassis Clear

Bit 7:The logical 1 outputs a minimum 20 ms active low pulse on the Case Open pin. The register bit self clears after the pulse has been output.

Bit 6-5:Reserved. This bit should be set to 0.

Bit 4-0:The logical 1 disables the corresponding interrupt status bit for IRQ interrupt.

8.10 VID/Fan Divisor Register Index 47h (Bank 0) Register Location: 47h Power on Default Value <7:4> is 0101, <3:0> is 0000 Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

VID0VID1VID2VID3FAN1 RPM ControlFAN1 RPM ControlFAN2 RPM ControlFAN2 RPM Control

Bit 7-6: FAN2 Speed Control.

<7:6> = 00 - divide by 1;

<7:6> = 01 - divide by 2;

<7:6> = 10 - divide by 4;

<7:6> = 11 - divide by 8.

Bit 5-4: FAN1 Speed Control.

<5:4> = 00 - divide by 1;

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<5:4> = 01 - divide by 2;

<5:4> = 10 - divide by 4;

<5:4> = 11 - divide by 8.

Bit 3-0: The VID <3:0> inputs

8.11 Serial Bus Address Register Index 48h (Bank 0) Register Location: 48h Power on Default Value Serial Bus address <6:0> = 0101101 and <7> = 0 binary Size: 8 bits

7 6 5 4 3 2 1 0

Serial Bus Address

Reserved

Bit 7: Read Only - Reserved.

Bit 6-0: Read/Write - Serial Bus address <6:0>.

8.12 Value RAM Index 20h- 3Fh or 60h – Index 7Fh (auto-increment) (Bank 0)

Index A6-A0 Index A6-A0 with Auto-Increment

Description

20h 60h IN0 reading 21h 61h IN1 reading 22h 62h IN2 reading 23h 63h IN3 reading 24h 64h IN4 reading 25h 65h -IN5 reading 26h 66h -IN6 reading 27h 67h Temperature reading 28h 68h FAN1 reading

Note: This location stores the number of counts of the internal clock per revolution.

29h 69h FAN2 reading Note: This location stores the number of counts of the internal clock per revolution.

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2Ah 6Ah FAN3 reading Note: This location stores the number of counts of the internal clock per revolution.

2Bh 6Bh IN0 High Limit, default value is defined by Vcore Voltage +0.2V.

2Ch 6Ch IN0 Low Limit, default value is defined by Vcore Voltage -0.2V.

2Dh 6Dh IN1 High Limit, , default value is defined by Vcore Voltage +0.2V.

2Eh 6Eh IN1 Low Limit, default value is defined by Vcore Voltage -0.2V.

2Fh 6Fh IN2 High Limit 30h 70h IN2 Low Limit 31h 71h IN3 High Limit 32h 72h IN3 Low Limit 33h 73h IN4 High Limit 34h 74h IN4 Low Limit 35h 75h -IN5 High Limit 36h 76h -IN5 Low Limit 37h 77h -IN6 High Limit

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8.12 Value RAM Index 20h- 3Fh or 60h – Index 7Fh (auto-increment) (Bank 0),continued

Index A6-A0 Index A6-A0 with Auto-Increment

Description

38h 78h -IN6 Low Limit 39h 79h Over Temperature Limit (High) 3Ah 7Ah Temperature Hysteresis Limit (Low) 3Bh 7Bh FAN1 Fan Count Limit

Note: It is the number of counts of the internal clock for the Low Limit of the fan speed.

3Ch 7Ch FAN2 Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed.

3Dh 7Dh FAN3 Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed.

3E- 3Fh 7E- 7Fh Reserved Setting all ones to the high limits for voltages and fans (0111 1111 binary for temperature) means interrupts will never be generated except the case when voltages go below the low limits. Note1: For the high limits of the voltages, the device is doing a greater than comparison. For the low

limits, however, it is doing a less than or equal comparison. Note 2: V-Core Table:

Processor Pins 0 = Connected to Vss

1 = Open or pull-up to Vin

Vcore Processor Pins 0 = Connected to Vss


Vcore

VID4 VID3 VID2 VID1 VID0 (VDC) VID4 VID3 VID2 VID1 VID0 (VDC) 0 1 1 1 1 * 1 1 1 1 1 No CPU 0 1 1 1 0 * 1 1 1 1 0 2.1 0 1 1 0 1 * 1 1 1 0 1 2.2 0 1 1 0 0 * 1 1 1 0 0 2.3 0 1 0 1 1 * 1 1 0 1 1 2.4 0 1 0 1 0 * 1 1 0 1 0 2.5 0 1 0 0 1 * 1 1 0 0 1 2.6 0 1 0 0 0 * 1 1 0 0 0 2.7 0 0 1 1 1 * 1 0 1 1 1 2.8

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Note 2: V-Core Table, continued

Processor Pins 0 = Connected to Vss


Vcore Processor Pins 0 = Connected to Vss


Vcore

VID4 VID3 VID2 VID1 VID0 (VDC) VID4 VID3 VID2 VID1 VID0 (VDC) 0 0 1 1 0 * 1 0 1 1 0 2.9 0 0 1 0 1 1.80 1 0 1 0 1 3.0 0 0 1 0 0 1.85 1 0 1 0 0 3.1 0 0 0 1 1 1.90 1 0 0 1 1 3.2 0 0 0 1 0 1.95 1 0 0 1 0 3.3 0 0 0 0 1 2.00 1 0 0 0 1 3.4 0 0 0 0 0 2.05 1 0 0 0 0 3.5

8.13 Voltage ID (VID7-4) – Index 49h (Bank 0) Register Location: 49h Power on Default Value <7:1> is 000,0001b

<0> is mapped to VID <4> Size: 8 bits

7 6 5 4 3 2 1 0

DID<6:0>

VID4

Bit 7-1: Read Only - Device ID<6:0>

Bit 0: Read/Write - The VID4 inputs/outputs. Reset by MR.

8.14 Temperature 2 and Temperature 3 Serial Bus Address Register Index 4Ah (Bank 0) Register Location: 4Ah Power on Default Value <7:0> = 0000,0001 binary. Reset by MR Attribute: Read/Write

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Size: 8 bits

7 6 5 4 3 2 1 0

I2CADDR2I2CADDR2I2CADDR2DIS_T2I2CADDR3I2CADDR3I2CADDR3DIS_T3

Bit 7: Set to 1, disable temperature sensor 3 and can not access any data from Temperature Sensor 3.

Bit 6-4: Temperature 3 Serial Bus Address. The serial bus address is 1001xxx. Where xxx are defined in these bits.

Bit 3: Set to 1, disable temperature Sensor 2 and can not access any data from Temperature Sensor 2.

Bit 2-0: Temperature 2 Serial Bus Address. The serial bus address is 1001xxx. Where xxx are defined in these bits.

InterfacePointer

Temperature

Configuration

T

OS

Register

T

HYST

Register

Register

Register

(Read Only)Data

Address(Select Register)

SCL

SDA

(Select which register will be read from or written to):

P7 P6 P5 P4 P3 P2 P1 P0

P7-P2: Must be kept 0. P1-P0: Register select:

P1 P0 Index Register Selection (Bank1 & Bank2) 0 0 Temperature (Read only) (Power up default) CR50h & CR51h

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0 1 Configuration (Read / Write) CR52h 1 0 THYST (Read / Write) CR53h & CR54h 1 1 TOS (Read / Write) CR55h & CR56h

8.15 Pin Control Register – Index 4Bh (Bank 0) Register Location: 4Bh Power on Default Value <7:0> 44h. Reset by MR. Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

ReservedReservedCLKINSELCLKINSELADCOVSELADCOVSELFAN3_DIVFAN3_DIV

Bit 7-6:Fan3 speed divisor. <1:0> = 00 - divide by 1;<1:0> = 01 - divide by 2; <1:0> = 10 - divide by 4;<1:0> = 11 - divide by 8;Reset by MR. Bit 5-4: Select A/D Converter Clock Input. <5:4> = 00 - default. <5:4> = 01- divided by 4. <5:4> = 10 - divided by 16. <5:4> = 11 - divided by 64. Bit 3-2: Clock Input Select. <3:2> = 00 - Pin 3 (CLKIN) select 14.318M Hz clock. <3:2> = 01 - Default. Pin 3 (CLKIN) select 24M Hz clock. <3:2> = 10 - Pin 3 (CLKIN) select 48M Hz clock . <3:2> = 11 - Reserved. Pin3 no clock input. Bit 1-0: Reserved. User defined.

8.16 IRQ/OVT# Property Select – Index 4Ch (Bank 0) Register Location: 4Ch Power on Default Value <7:0> ---0,0001. Reset by MR. Attribute: Read/Write Size: 8 bits

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7 6 5 4 3 2 1 0

ReservedIRQEDGEOVTPOLDIS_OVT1DIS_OVT2ReservedReservedReserved

Bit 7-5: Reserved. User Defined.

Bit 4: Disable temperature sensor 3 over-temperature (OVT) output if set to 1. Default 0, enable OVT2 output through pin OVT#.

Bit 3: Disable temperature sensor 2 over-temperature (OVT) output if set to 1. Default 0, enable OVT1 output through pin OVT#.

Bit 2: Over-temperature polarity. Write 1, OVT# active high. Write 0, OVT# active low. Default 0.

Bit 1: When set to 1, IRQ Edge Active. Set to 0, IRQ Level trigger. Default 0, level trigger interrupt.

Bit 0: Reserved. User Defined.

8.17 FAN IN/OUT and BEEP/GPO# Control Register -- Index 4Dh (Bank 0) Register Location: 4Dh Power on Default Value <7:0> 0001,0101. Reset by MR. Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

FANINC1FANOPV1FANINC2FANOPV2FANINC3FANOPV3GPOSELDIS_ABN

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Bit 7: Disable power-on abnormal the monitor voltage including V-Core A,, and +3.3V. If these voltage exceed the limit value, the pin (Open Drain) of BEEP will drives low and high frequency signal. Write 1, the frequency will be disable. Default 0. After power on, the system should set this bit to 1 in order to disable BEEP.

Bit 6: BEEP/GPO# Pin Function Select. Write 1 Select GPO# function. Set 0, select BEEP function. This bit default 0.

Bit 5: FAN 3 output value if FANINC3 sets to 0. Write 1, then pin 18 always generate logic high signal. Write 0, pin 18 always generates logic low signal. This bit default 0.

Bit 4: FAN 3 Input Control. Set to 1, pin 18 acts as FAN clock input, which is default value. Set to 0, this pin 18 acts as FAN control signal and the output value of FAN control is set by this register bit 5. This output pin can connect to power PMOS gate to control FAN ON/OFF.


Bit 2: FAN 2 Input Control. Set to 1, pin 19 acts as FAN clock input, which is default value. Set to 0, this pin 19 acts as FAN control signal and the output value of FAN control is set by this register bit 3. This output pin can connect to power NMOS gate to control FAN ON/OFF.


Bit 0: FAN 1 Input Control. Set to 1, pin 20 acts as FAN clock input, which is default value. Set to 0, this pin 20 acts as FAN control signal and the output value of FAN control is set by this register bit 1. This output pin can connect to power PMOS gate to control FAN ON/OFF.

8.18 Register 50h ~ 5Fh Bank Select -- Index 4Eh (No Auto Increase) (Bank 0) Register Location: 4Eh Power on Default Value <6:3> = Reserved, <7> = 1, <2:0> = 0. Reset by MR Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

BANKSEL0BANKSEL1BANKSEL2ReservedReservedReservedReservedHBACS

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Bit 7: HBACS- High byte access. Set to 1, access Register 4Fh high byte register.

Set to 0, access Register 4Fh low byte register. Default 1.


Bit 2-0: Index ports 0x50~0x5F Bank select.

8.19 Winbond Vendor ID -- Index 4Fh (No Auto Increase) (Bank 0) Register Location: 4Fh Power on Default Value <15:0> = 5CA3h Attribute: Read Only Size: 16 bits

15 8 7 0

VIDH

VIDL

Bit 15-8: Vendor ID High Byte if CR4E.bit7=1.Default 5Ch.

Bit 7-0: Vendor ID Low Byte if CR4E.bit7=0. Default A3h.

8.20 Resistor-Temperature Table Register – Index 50h - 51h (Bank 0) Note: Index will be auto-increased when read Data Port 0x6, and Index will stop at 0x5F if continue reading Data Port. Any no defined register is read will return 0xFF.

A6-A0 Name Read/Write Description 50h RT_IDX Read/Write R-T Table index port, which is mapped to data port

51h. The default value is 0x00. 51h RT_DATA Read/Write R-T Table data port, which is selected by RT_IDX.

8.21 Winbond Test Register 1 – Index 52h (Bank 0)


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8.25 BEEP Control Register 1— Index 56h (Bank 0) (Auto-increment) Register Location: 56h Power on Default Value <7:0> 0000,0000. Reset by MR. Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

EN_V25A_BPEN_V25B_BPEN_V33_BPEN_V5_BPEN_T1_BPEN_T23_BPEN_FAN1_BPEN_FAN2_BP

Bit 7: Enable BEEP Output from FAN 2 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default value is 0.

Bit 6: Enable BEEP Output from FAN 1 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default value is 0.

Bit 5: Enable BEEP Output from Temperature Sensor 2 and 3 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default value is 0.

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Bit 4: Enable BEEP output for Temperature Sensor 1 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default value is 0.

Bit 3: Enable BEEP output from VDD (5V), Write 1, enable BEEP output if the monitor value exceed the limits value. Default 0, that is disable BEEP output.

Bit 2: Enable BEEP output from 3.3V. Write 1, enable BEEP output. Default value is 0.

Bit 1: Enable BEEP output from V-Core B. Write 1, enable BEEP output. Default value is 0.

Bit 0: Enable BEEP Output from V-Core A if the monitor value exceed the limits value. Write 1, enable BEEP output. Default value is 0.

8.26 BEEP Control Register 2— Index 57h (Bank 0) ( No Auto-increment) Register Location: 57h Power on Default Value <7:0> 1000-0000. Reset by MR. Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

EN_V12_BPEN_NV12_BPEN_NV5_BPEN_FAN3_BPEN_CASO_BPReservedReservedEN_GBP

Bit 7: Enable Global BEEP. Write 1, enable global BEEP output. Default 1. Write 0, disable all BEEP output.


Bit 4: Enable BEEP output for case open if the monitor value exceed the limit value. Write 1, enable BEEP output. Default 0.

Bit 3: Enable BEEP Output from FAN 3 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default 0.

Bit 2: Enable BEEP output from -5V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default 0, that is disable BEEP output.

Bit 1: Enable BEEP output from -12V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default 0, that is disable BEEP output.

Bit 0: Enable BEEP output from +12V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default 0, that is disable BEEP output.

8.27 Chip ID- Index 58h (Bank 0)

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Register Location: 58h Power on Default Value <7:0> 0001-0000. Reset by MR. Attribute: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

CHIPID

Bit 7: Winbond Chip ID number. Read this register will return 10h.

8.28 Temperature Sensor 2 Temperature Register - Index 50h (Bank 1) Register Location: 50h Attribute: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

TEMP2<8:1>

Bit 7: Temperature <8:1> of sensor 2, which is high byte.


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7 6 5 4 3 2 1 0

TEMP2<0>

Reserved

Bit 7: Temperature <0> of sensor2, which is low byte.


8.30 Temperature Sensor 2 Configuration Register - Index 52h (Bank 1) Register Location: 52h Power on Default Value <7:0> = 0x00 Size: 8 bits

7 6 5 4 3 2 1 0

STOP2INTMODReservedFAULTFAULTReserved ReservedReserved

Bit 7-5: Read - Reserved. This bit should be set to 0.

Bit 4-3: Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping due to noise.

Bit 2: Read - Reserved. This bit should be set to 0.

Bit 1: Read/Write - Interrupt mode select. This bit default is set to 0, which is compared mode. When set to 1, interrupt mode will be selected.

Bit 0: Read/Write - When set to 1 the sensor will stop monitor.

8.31 Temperature Sensor 2 Hysteresis (High Byte) Register - Index 53h (Bank 1) Register Location: 53h Power on Default Value <7:0> = 0x4B Attribute: Read/Write

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Size: 8 bits 7 6 5 4 3 2 1 0

THYST2<8:1>

Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C.

8.32 Temperature Sensor 2 Hysteresis (Low Byte) Register - Index54h (Bank 1) Register Location: 54h Power on Default Value <7:0> = 0x0 Attribute: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

THYST2<0>

Reserved

Bit 7: Temperature hysteresis bit 0, which is low Byte.


8.33 Temperature Sensor 2 Over-temperature(High Byte) Register - Index 55h (Bank 1) Register Location: 55h Power on Default Value <7:0> = 0x50 Attribute: Read/Write Size: 8 bits

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7 6 5 4 3 2 1 0

TOVF2<8:1>

Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C.

8.34 Temperature Sensor 2 Over-temperature (Low Byte) Register - Index 56h (Bank 1) Register Location: 56h Power on Default Value <7:0> = 0x0 Size: 8 bits

7 6 5 4 3 2 1 0

TOVF2<0>

Reserved

Bit 7: Read/Write - Over-temperature bit 0, which is low Byte. Bit 6-0: Read Only - Reserved. This bit should be set to 0.


7 6 5 4 3 2 1 0

TEMP2<8:1>

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Bit 7-0: Temperature <8:1> of sensor 2, which is high byte.


7 6 5 4 3 2 1 0

TEMP2<0>

Reserved

Bit 7: Temperature <0> of sensor2, which is low byte. Bit 6-0: Reserved. This bit should be set to 0.

8.37 Temperature Sensor 3 Configuration Register - Index 52h (Bank 2) Register Location: 52h Power on Default Value <7:0> = 0x00 Size: 8 bits

7 6 5 4 3 2 1 0

STOP3INTMODReservedFAULTFAULTReserved ReservedReserved

Bit 7-5: Read - Reserved. This bit should be set to 0.

Bit 4-3: Read/Write - Number of faults to detect before setting OVF# output to avoid false tripping due to noise.

Bit 2: Read - Reserved. This bit should be set to 0.

Bit 1: Read/Write - Interrupt Mode select. This bit default is set to 0, which is Compared Mode. When set to 1, Interrupt Mode will be selected.

Bit 0: Read/Write - When set to 1 the sensor will stop monitor.

W83781D


Revision 1.1

40

8.38 Temperature Sensor 3 Hysteresis (High Byte) Register - Index 53h (Bank 2) Register Location: 53h Power on Default Value <7:0> = 0x4B Attribute: Read/Write Size: 8 bits

7 6 5 4 3 2 1 0

THYST3<8:1>

Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C.

8.39 Temperature Sensor 3 Hysteresis (Low Byte) Register - Index 54h (Bank 2) Register Location: 54h Power on Default Value <7:0> = 0x0 Attribute: Read Only Size: 8 bits

7 6 5 4 3 2 1 0

THYST3<0>

Reserved

Bit 7: Temperature hysteresis bit 0, which is low Byte. Bit 6-0: Reserved. This bit should be set to 0.

8.40 Temperature Sensor 3 Over-temperature (High Byte)Register - Index 55h (Bank 2) Register Location: 55h Power on Default Value <7:0> = 0x50 Attribute: Read/Write Size: 8 bits

W83781D


Revision 1.1

41

7 6 5 4 3 2 1 0

TOVF3<8:1>

Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C.

8.41 Temperature Sensor 3 Over-temperature (Low Byte) Register - Index 56h (Bank 2) Register Location: 56h Power on Default Value <7:0> = 0x0 Size: 8 bits

7 6 5 4 3 2 1 0

TOVF3<0>

Reserved

Bit 7: Read/Write - Over-temperature bit 0, which is low Byte.

Bit 6-0: Read Only - Reserved. This bit should be set to 0.

9. SPECIFICATIONS

9.1 Absolute Maximum Ratings

W83781D


Revision 1.1

42

PARAMETER RATING UNIT

Power Supply Voltage -0.5 to 7.0 V

Input Voltage -0.5 to VDD+0.5 V

Operating Temperature 0 to +70 ° C

Storage Temperature -55 to +150 ° C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.

9.2 DC Characteristics (Ta = 0° C to 70° C, VDD = 5V ± 10%, VSS = 0V)

PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS

I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA Input Low Voltage VIL 0.8 V

Input High Voltage VIH 2.0 V

Output Low Voltage VOL 0.4 V IOL = 12 mA

Output High Voltage VOH 2.4 V IOH = - 12 mA

Input High Leakage ILIH +10 µA VIN = VDD

Input Low Leakage ILIL -10 µA VIN = 0V

I/O12ts - TTL level bi-directional pin with source-sink capability of 12 mA and schmitt-trigger level input Input Low Threshold Voltage Vt- 0.5 0.8 1.1 V VDD = 5 V

Input High Threshold Voltage Vt+ 1.6 2.0 2.4 V VDD = 5 V

Hysteresis VTH 0.5 1.2 V VDD = 5 V


Output High Voltage VOH 2.4 V IOH = - 12 mA


Input Low Leakage ILIL -10 µA VIN = 0V

OUT12t - TTL level output pin with source-sink capability of 12 mA

W83781D


Revision 1.1

43

9.2 DC Characteristics, continued



Output High Voltage VOH 2.4 V IOH = -12 mA

OD8 - Open-drain output pin with sink capability of 8 mA Output Low Voltage VOL 0.4 V IOL = 8 mA



INt - TTL level input pin Input Low Voltage VIL 0.8 V

Input High Voltage VIH 2.0 V


Input Low Leakage ILIL -10 µA VIN = 0 V

9.2 DC Characteristics, continued


INts - TTL level Schmitt-triggered input pin Input Low Threshold Voltage Vt- 0.5 0.8 1.1 V VDD = 5 V

Input High Threshold Voltage Vt+ 1.6 2.0 2.4 V VDD = 5 V

Hysteresis VTH 0.5 1.2 V VDD = 5 V


Input Low Leakage ILIL -10 µA VIN = 0 V

W83781D


Revision 1.1

44

9.2.1 AC Characteristics

9.2.2 ISA Read/Write Interface Timing

AEN

SA[2:0],CS#

IOR#

SD[7:0]

IRQ

tAR

t RVDVALID DATA

t RD

t RA

t RDH

t RI

t RCU

RC

ISA Bus Read Timing

IOW#

AEN

SA[2:0],CS#

IOW#

SD[7:0]

IRQ

tAW

t DS

VALID DATA

t WR

t WA

t DH

t WI

t WCU

WC

IOR#

VALID VALID

ISA Bus Write Timing ISA Read/Write Timing

W83781D


Revision 1.1

45

PARAMETER SYMBOL MIN. MAX. UNIT

Valid Address to Read Active t-AR 10 nS

Valid Address to Write Active tAW 10 nS

Data Hold tDH 5 nS

Data Setup tDS 80 nS

Address Hold from Inactive Read tRA 40 nS

Read Cycle Update tRCU 200 nS

Read Strobe Width tRD 120 nS

Read Data Hold tRDH 40 nS

Read Strobe to Clear IRQ tRI 60 nS

Active Read to Valid Data tRVD 115 nS

Address Hold from Inactive Write tWA 5 nS

Write Cycle Update tWCU 80 nS

Write Strobe to Clear IRQ tWI 60 nS

Write Strobe Width tWR 120 nS

Read Cycle = tAR + tRD+tRCV RC 330 nS

Write Cycle = tAW+tWR+tWCV WC 210 nS

9.2.3 Serial Bus Timing Diagram

VALID DATA

SCL

SDA IN

SDA OUT

t HD;SDA

t SCL

t HD;DATt SU;STO

t SU;DAT

Serial Bus Timing Diagram Serial Bus Timing

W83781D


Revision 1.1

46

PARAMETER SYMBOL MIN. MAX. UNIT

SCL clock period t-SCL 10 uS

Start condition hold time tHD;SDA 4.7 uS

Stop condition setup-up time tSU;STO 4.7 uS

DATA to SCL setup time tSU;DAT 120 nS

DATA to SCL hold time tHD;DAT 5 nS

SCL and SDA rise time tR 1.0 uS

SCL and SDA fall time tF 300 nS

10. HOW TO READ THE TOP MARKING

The top marking of W83781D

W83781D745AA

Left: Winbond logo

1st line: Type number W83781D, D means LQFP (Thickness = 1.4 mm). 2nd line: Tracking code 745 A A 745: packages made in '97, week 45 A: assembly house ID; A means ASE, O means OSE A: IC revision; A means version A, B means version B

11. PACKAGE DIMENTIONS

(48-pin QFP)

W83781D


Revision 1.1

47

2

1A

H

D

D

e b

E H E

y

AA

Seating Plane L

L 1

See Detail F

Detail F

c

37

48

1 12

13

24

2536

1. Dimensions D & E do not include interleadflash.

2. Dimension b does not include dambarprotrusion/intrusion.

3. Controlling dimension: Millimeters4. General appearance spec. should be based

on final visual inspection spec.

Notes:

Symbol Min. Nom. Max. Max.Nom.Min.Dimension in inch Dimension in mm

A

bcD

eHD

HE

L

y0

AA

L1

1

2

E

1.40

0.20

0.50

1.00

7.00

9.00

9.00

7.00

---

------ 1.60

0.15

1.451.35

0.05

0.17 0.27

---0.09 0.20

0.45 0.60 0.75

0.08

0 3.5 7

--- ---

Headquarters No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/ Taipei Office 9F, No. 480, Rueiguang Road, Neihu District, Taipei, 114, Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579

Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064

Winbond Electronics (North America) Corp. 2727 North First Street San Jose, California 95134 TEL: 1-408-9436666 FAX: 1-408-9436668

Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

12. APPLICATION CIRCUITS OF W83781D

0.6

APPLICATION OF W83781D

WINBOND ELECTRONICS CORP.

B

1 2Wednesday, February 24, 1999

Title

Size Document Number Rev

Date: Sheet of

VCC+12V +3.3V

VCC

-12V -5V

VCC

PIIX4_3V

PIIX4_3VPIIX4_3V

48M , 24M OR 14.318M

NOTE:

1. Selected CLKIN of

2. Pin OVT# connects with PIIX4 Pin THRM#(H19)

(+5V)

Note3.

Note3.

3. If there originally exists Pull-up Resistor

on these lines, these resistors are not needed.

Note4.

4. SMI# is connected to PIIX4 EXTSMI# .

Note5.

5. To eliminate noise and to be VCC line,

(about 15-20 mil)

this line is as wider as better.

Note1.

Note2.

ApplicationNotice 2

(Reserve R & C)

(MB)(CPU)

Ver Contents

0.5

0.6 Add R30

Ver0.5 schematicAP1,AP2,AP3

Erase R10 in Ver0.5

IOR# +2.5VINAIOW# +2.5VINBCLKIN +3.3VIND7 +5VIND6 +12VIND5 -12VIND4 -12VOUTD3 -5VOUTD2 -5VIND1 GNDAD0VID1 VID3

A[2..0]

D[7..0]

VC

CA

0G

ND

DA

1M

RA

2C

AS

EO

PE

NS

MI#

VID

4IR

QF

AN

1OU

TO

VT

#F

AN

1INV

ID0

FA

N2IN

VT

IN1

SC

LV

TIN

2S

DA

VT

IN3

RS

TO

UT

#V

RE

FO

UT

VID

2

C1

.1uF

C2

.1uF

C3

.1uF

C4

.1uF

C5

.1uF

C6.1uF

C7

.1uF

RT1

10K 1%

t

RT210K 1%

t

RT310K 1%

t

R110K 1%

R210K 1%

R310K 1%

R4210K 1%

R590.9K 1%

C8

.1uF

C9

.1uF

C10

.1uF

R610K 1%

C1110uF

L1

INDUCTOR

R760.4K1%

R860.4K1%

C12

.1uF

C13

.1uF

C14

.1uF

C15

.1uF

C16

10uF

R910K 1%

R1310

R1428K 1%

R15R

R1610K 1%

R1710K 1%

R18R

U1

W83781D

IOR#1

IOW#2

CLKIN3

D74

D65

D56

D47

D38

D29

D110

D011

VID112

VC

C13

GN

DD

14M

R15

CA

SE

OP

EN

16V

ID4

17F

AN

3 IN/O

UT

18F

AN

2 IN/O

UT

19F

AN

1 IN/O

UT

20S

CL

21S

DA

22R

ST

OU

T#

23V

ID2

24

VID3 25BEEP/GPO# 26GNDA 27-5VIN 28-5VOUT 29-12VOUT 30-12VIN 31+12VIN 32+5VIN 33+3.3VIN 34VCOREB 35VCOREA 36

VR

EF

37

VT

IN3

38

VT

IN2

39

VT

IN1

40

VID

041

OV

T#

42

IRQ

43

SM

I#44

A2

45

A1

46

A0

47

CS

#48

R25

R100

C18CAPACITOR NON-POL33p

R11 R 4.7K

R12 R 4.7K

R304.7K

D[7..0]

A[2..0]

CS#

FAN1OUT

CASEOPEN

OVT#IRQ

RSTOUT#

SDASCL

IOR#IOW#

CLKIN

VCOREA

VCOREB

ResetDrv

SMI#

BEEP/GPO#

FAN2INFAN1IN

0.6

APPLICATION OF W83781D

WINBOND ELECTRONICS CORP.

B

2 2Wednesday, February 24, 1999

Title

Size Document Number Rev

Date: Sheet of

+12V

+12V

VCC

5VSB BAT

These two inveters consume

CaseOpenSwitch QQ'

open 1 0

close 0 1

open

open

0 1

1 0

normal state

after reset

ps. 'Switch Open' means 'Case Close'

Q

Q'

FanBlock

CaseBlock

VRTC

VRTC

On-board RTC Power Switch Circuit

if W83781D does not reset(let Q=0), then stable

SpeakerBlock

R194.7K

R20

10K

R21

2.2M

S1CASEOPEN SW

U2A

74HC14

1 2

U2B

74HC14

34

C17

1000pF10% 50V

R224.7K

JP1

HEADER 3CPU FANConnecter

123

JP2

HEADER 3MB FANConnecter

123

D1

DIODE

D2

DIODE

C1810uF

Q1NPN

R23

4.7K

LS1

SPEAKER

R24100

R27R10K

R29R10K

R26

R20-27K

D3DIODE

R28

R20-27K

D4DIODE

FAN2IN

FAN1IN

FAN1OUT

CASEOPEN

BEEP/GPO#

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