IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 4, APRIL 2013 1523

Voltage and Power Balance Control for a CascadedH-Bridge Converter-Based Solid-State Transformer

Tiefu Zhao, Senior Member, IEEE, Gangyao Wang, Student Member, IEEE,Subharshish Bhattacharya, Member, IEEE, and Alex Q. Huang, Fellow, IEEE

Abstract—The solid-state transformer (SST) is an interface de-vice between ac distribution grids and dc distribution systems. TheSST consists of a cascaded multilevel ac/dc rectifier stage, a dual ac-tive bridge (DAB) converter stage with high-frequency transform-ers to provide a regulated 400-V dc distribution, and an optionaldc/ac stage that can be connected to the 400-V dc bus to provideresidential 120/240 Vac . However, due to dc-link voltage and powerunbalance in the cascaded modules, the unbalanced dc-link volt-ages and power increase the stress of the semiconductor devicesand cause overvoltage or overcurrent issues. This paper proposes anew voltage and power balance control for the cascaded H-Bridgeconverter-based SST. Based on the single-phase dq model, a novelvoltage and the power control strategy is proposed to balance therectifier capacitor voltages and the real power through parallelDAB modules. Furthermore, the intrinsic power constraints of thecascaded H-Bridge voltage balance control are derived and an-alyzed. With the proposed control methods, the dc-link voltageand the real power through each module can be balanced. TheSST switching model simulation and the prototype experimentsare presented to verify the performance of the proposed voltageand power balance controller.

Index Terms—Cascaded H-Bridge converter, dq vector control,solid-state transformer (SST), voltage and power balance.

I. INTRODUCTION

A S the interface between power transmission grids and theconsumers, the distribution power system currently re-

quires 60 Hz transformers for voltage transformation. Theseconventional copper-and-iron based transformers possess manyundesirable properties including bulky size, environmental con-cerns and especially power quality susceptibility. As the de-velopment of the dc distribution system and the increase of thepenetration of distributed generations, an intelligent transformerwith the capability to actively manage the power and allowingfor the easy connection of the distribution resources is becomingindispensable.

The solid-state transformer (SST) is the interface device be-tween the distribution system and the electricity consumers in

Manuscript received February 28, 2012; revised June 20, 2012; acceptedAugust 6, 2012. Date of current version October 26, 2012. Recommended forpublication by Associate Editor J. Liu.

T. Zhao is with the Eaton Corporation Innovation Center, Milwaukee, WI53216 USA (e-mail: TiefuZhao@eaton.com).

G. Wang, S. Bhattacharya, and A. Q. Huang are with the Future RenewableElectric Energy Delivery and Management (FREEDM) Systems Center, NorthCarolina State University, Raleigh, NC 27695 USA (e-mail: gwang@ncsu.edu;sbhattacharya@ncsu.edu; aqhuang@ncsu.edu).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2012.2216549

Fig. 1. SST at one residential home (SST: solid-state transformer, DRER: dis-tributed renewable energy resource, DESD: distributed energy storage device).

future smart grid systems. In the proposed electric configura-tion of the smart grid system shown in Fig. 1, low voltage(120 V), residential class distributed renewable energy resource(DRER), distributed energy storage device (DESD), and loadsare connected to the 400-V dc distribution bus and then to distri-bution bus (12-kV three phase or 7.2-kV single phase) througha SST. The SST is used to enable active management of DRER,DESD, and loads, rather than a 60-Hz conventional transformer.The SST has the features of instantaneous voltage regulation,voltage sag compensation, fault isolation, power factor correc-tion, harmonic isolation, and dc output [1]–[4]. The SST has a400-V dc port that will facilitate more efficient connection ofcertain classes of DRERs and DESDs. Acting very much like anenergy router, each SST has bidirectional energy flow controlcapability allowing it to control active and reactive power flowand to manage the fault currents on both low- and high-voltagesides. Its large control bandwidth provides the plug-and-playfeature for distributed resources to rapidly identify and respondto changes in the system.

This paper proposes a 20-kVA cascaded H-Bridge multilevelconverter-based SST to directly interface with 7.2-kV single-phase distribution voltage level. As shown in Fig. 2, the SSTconsists of a cascaded multilevel ac/dc rectifier, dual activebridge (DAB) converters with high-frequency transformers. Theregulated 400-V dc bus is distributed for easier connection ofbattery and other distributed resources. The rectifier stage isa seven-level cascaded H-Bridge converter, which controls theinput power factor and regulates the 3.8-kV high-voltage dclink. The DAB converter regulates the 400-V-low-voltage dcbus and additional dc/ac inverters can be added to provide a60 Hz 120/240-V ac residential voltage.

0885-8993/$31.00 © 2012 IEEE

1524 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 4, APRIL 2013

Fig. 2. Topology of the proposed SST.

One of the main disadvantages of the cascaded H-bridge rec-tifier is the voltage unbalance of the dc-link voltages at differ-ent H-Bridges [5]–[7], [12], [13], [18], [20]. Relevant researchmainly focuses on the unbalance issues in static synchronouscompensator (STATCOM) or drive applications and no power-control method has been mentioned. The proposed voltage andbalance control in this paper have the following features: bal-anced dc-bus voltage, balanced real power, equally distributedreactive power between H-bridges, and using simple phase-shiftpulsewidth modulation (PWM).

In [5]–[7], low-frequency PWM techniques for STATCOMare presented. The dc-link voltage is balanced by using differentswitching patterns to charge and discharge each H-Bridge ca-pacitor, but the reactive power is not controlled. Barrena et al. [8]present an individual voltage-balancing strategy to balance thedc-link voltage with PWM. The method maintains deliveredreactive power equally distributed among all H-Bridges. How-ever, the method is based on the STATCOM application andno power unbalance constraints are mentioned in this paper.Iman-Eini et al. [9] present a method that ensures the dc-linkvoltages converge to the reference value when load power aredifferent. The method results in different switching frequenciesfor the H-Bridges and a complicated controller implementation.Leon et al. [10] and Barrena et al. [11] present different PWMmethods to balance the dc-link voltages, however the balancerange and power control are not included. In contrast to theSTATCOM and drive application, the SST requires a high-frequency modulation and both real and reactive power control.Furthermore, due to the intrinsic constraint of the cascaded rec-tifier topology, the voltage balance control is limited and thepower balance control is therefore required.

In this paper, the modeling of the SST, including ac/dc rec-tifier, DAB converter are developed. A single-phased dq vec-tor controller is designed for the rectifier stage; therefore thereal power and reactive power can be controlled independently.Based on the single-phase dq control, a voltage balance controlmethod is proposed to resolve the voltage unbalance that couldappear on the dc links of different H-bridges. The limitationand the power unbalance range of the cascaded H-Bridge rec-tifier are derived. Meanwhile, a power balance control methodis proposed to regulate the real power transferring through theDAB parallel modules. The proposed voltage and power controlare verified by the switching model simulation. Finally, a SSTscale-down prototype is implemented by using 600-V insulated-gate bipolar transistor (IGBT) devices. The experiments are pre-sented to verify the real and reactive power control, power factorcorrection, voltage sag compensation, and proposed voltage bal-ance control.

II. SST MODELING AND CONTROL

The modeling and control of the SST, including the cascadedmultilevel ac/dc rectifier, DAB converters with high-frequencytransformers are developed in this section.

The basic configuration of the proposed 20-kVA SST is shownin Fig. 2. The SST is rated as single-phase input voltage 60 Hz,7.2 kV, output voltage 400-V dc. The first stage of the SST isa high-voltage cascaded H-Bridge ac/dc rectifier that converts60 Hz, 7.2-kV ac to three cascaded 3.8-kV dc links. The secondstage consists of three high-voltage high-frequency dc/dc con-verters that convert 3.8 kV to 400-V dc bus and then additionalinverter can be connected to 400-V dc bus to invert 400-V dc

ZHAO et al.: VOLTAGE AND POWER BALANCE CONTROL FOR A CASCADED H-BRIDGE CONVERTER-BASED SOLID-STATE TRANSFORMER 1525

to 60-Hz, 240/120 V. The switching devices in high-voltageH-bridges and low-voltage H-bridges are 6.5-kV IGBT and600-V IGBT, respectively. The switching frequency of the 6.5-kV IGBT devices is 1 kHz, because the device current is verylow resulting in low switching losses. The 20-kVA SST unitis envisioned as a building block for construction of a largerrated SST. The controller of each stage in the SST is indepen-dent from each other. The rectifier controller regulates the inputpower factor and 3.8-kV high-voltage dc link. The DAB con-troller regulates the 400-V low-voltage dc bus, and the invertercontroller regulates the 240/120-V output ac voltage.

A. Rectifier Single-Phase dq Vector Control

The ac/dc rectifier stage converts the single-phase 7.2-kV acvoltage to three dc-link voltages while controlling the reactivepower at the input side. The rectifier consists of three cascadedH-bridges with each reference dc-link voltage 3.8 kV. The av-erage differential equations of the rectifier are

diadt

=3E

Lsda − Vpcca

Ls− Rs

Lsia (1)

dE

dt= − E

RLC− daia

C(2)

where, ia is the input current, Vpcca is the input voltage, Rs isthe input line resistance, Ls is the input inductor, E is the dc-linkvoltage, RL is the equivalent output impedance of the rectifierstage, C is the rectifier dc capacitor, and da is the rectifier PWMduty cycle.

The single-phase dq vector control is applied in the rectifiercontroller. An imaginary phase M, lagging the original phaseA by 90◦, is hypothesized. The differential equations for theimaginary phase are

dimdt

=3E

Lsdm − Vpccm

Ls− Rs

Lsim (3)

dEm

dt= − Em

RLC− dm im

C(4)

where, im is the input current of the imaginary phase, Vpccmis the input voltage of the imaginary phase, Em is the dc-linkvoltage of the imaginary phase, dm is the rectifier PWM dutycycle of the imaginary phase. Based on the small ripple approx-imation, Em =E. Then, combine the equations for two phases,and rewrite the equations

d�iam

dt=

3E

Ls

�dam −�Vpccam

Ls− Rs

Ls

�iam (5)

dE

dt= − E

RLC−

�dTam

�iam

2C(6)

where

�iam =[

iaim

], �dam =

[da

dm

], �Vpccam =

[VpccaVpccm

].

The single-phase dq transformation is applied to the (5) and(6) [14], and the differential equations in dq coordinates are

Fig. 3. Rectifier single-phase dq decoupled controller.

derived

[x]dq = [T ] · [x]am (7)

where

T = [ sin (θ) − cos(θ)cos(θ) sin(θ) ], θ = ωt, ω = 2πfL , fL is line

frequency.Then, the dq-axis equation of the single-phase H-bridge rec-

tifier is given in (8) and (9)

d

dt

[id

iq

]=

3E

Ls

[dd

dq

]− 1

Ls

[vpccd

vpccq

]−

⎡⎢⎢⎣

Rs

Ls−ω

ωRs

Ls

⎤⎥⎥⎦

[id

iq

]

(8)

dE

dt= − E

RLC− 1

2C

[dd

dq

]T [id

iq

]. (9)

The function of the rectifier controller is to control the reactivepower (or power factor) and regulate the dc-link voltages. Withthe chosen phase-locked loop, the voltage vector is aligned withthe direction of the d-axis during steady state. The grid-voltagecomponent in the d-direction is equal to its peak value andthe q-component of the grid voltage is equal to zero. Thus, thed-component of the current vector (in steady state parallel tothe grid-voltage vector) becomes the active current component(d-current) and the q-component of the current vector becomesthe reactive current component (q-current) [15]. The decoupleddq vector controller for each H-bridge is shown in Fig. 3. Thethree sinusoidal pulse width modulation (SPWM) carriers forthe cascaded H-bridge are phase shifted so that the rectifierhas seven voltage levels to reduce the voltage stress andharmonics. Depending on the reactive power reference in theSST controller iqref , the SST can generate or absorb reactivepower to the power grid.

B. Modeling and Control of DAB

The DAB consists of a high-voltage H-Bridge, a high-frequency transformer and a low-voltage H-bridge as shownin Fig. 4. The rectifier regulates the high-voltage dc-link volt-age and controls the input current to be sinusoidal from the acinput. The low-voltage dc link is regulated by the DAB con-verter [16], [19].

1526 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 4, APRIL 2013

Fig. 4. (a) DAB circuit and (b) DAB voltage controller.

The DAB topology offers zero voltage switching, relativelylow-voltage stress for the switches, low passive componentratings and complete symmetry of configuration that allowsseamless control for bidirectional power flow. Real power flowsfrom the bridge with leading phase angle to the bridge withlagging phase angle, the amount of transferred power is con-trolled by the phase angle difference and the magnitudes of thedc voltages at the two ends as given by (10) [16]

Po =VdcHV ′

dcL

2LfHddc(1 − ddc) (10)

where, VdcH is input side high dc-link voltage, fH is switchingfrequency, L is leakage inductance, V ′

dcL is output side low dcbus voltage referred to input side, and ddc is the ratio of timedelay between the two bridges to one-half of switching period.

For the DAB converter, the phase-shift control is applied toregulate the low-voltage dc voltage to the reference 400 V underdifferent load conditions. First the difference between the lowdc voltage Vdc and the reference voltage is compared. Then, thephase-shift angle is adjusted by the proportional-integral (PI)controller to regulate VdcL according to this voltage error.

III. VOLTAGE AND POWER BALANCE CONTROL

Since the rectifier stage of the SST consists of three H-Bridgesin series, the voltage unbalance could appear on the dc-linkvoltages (E1 , E2 , and E3 , as shown in Fig. 5) due to the deviceloss mismatching and H-Bridge real power differences. The un-balance issue worsens when the SST operates at no load or lightload condition, because a small power difference is a significantpercentage of the real power and will result in a large voltageunbalance at no load or light load condition. The unbalancedvoltage will cause the capacitor or IGBT device overvoltage inthe H-Bridge and trigger the system overvoltage protection.

The DAB stage consists of three DAB modules in parallel.The power unbalance (P1 , P2 , and P3 , as shown in Fig. 5) canbe caused by the transformer parameter mismatching (such asleakage inductance or turns ratio) and dc-link voltage differ-

ences. The power unbalance will cause a device overcurrentissue and result in unbalance heat distributions. Section III-Aintroduces the proposed voltage balance control for the cascadedH-Bridge rectifier and illustrates the three dc-link voltages canbe balanced in a 20% power unbalance condition. Section III-Bderives the maximum real power unbalance range in which thevoltage balance control can maintain the balanced dc links. Ifthe power unbalance is out of the derived range, the voltagebalance control will not be able to balance the dc-link voltages,therefore the DAB power balance control is needed to regulatethe H-Bridge real power. Section III-C describes the proposedpower balance control method, which guarantees the power un-balance of the DAB modules is within the required range sothat the three dc-link voltages can always be balanced with theproposed voltage balance control.

A. Voltage Balance Control

The single-phase dq vector controller for the rectifier stageregulates the total dc-link voltage and controls the reactivepower. Based on the single-phase dq control, a voltage bal-ance control method is proposed to resolve the voltage unbal-ance on the dc links of different H-bridges. The voltage balancecontrol basically adjusts the modulation signals da1 , da2 , andda3 individually to achieve different real power distributions ofthe H-Bridges. Fig. 6 illustrates the proposed voltage balancecontroller. In Fig. 6, the dd and dq are calculated accordingto the single-phase dq vector control. The individual dc-linkvoltages of the first two H-Bridges, E1 and E2 are comparedwith the dc-link voltage reference Eref to generate d-axis com-pensation Δdd1 and Δdd2 by a PI regulator. Then, Δdd1 andΔdd2 are added to the original dd . Therefore, dd1 for the firstH-Bridge and dd2 for the second H-Bridge are adjusted so thatthe real power distribution can be changed. The real power of theH-Bridge with a lower dc-link voltage is increased, and the realpower with a higher dc-link is decreased to eliminate the voltageunbalance. For the third H-Bridge, Δdd3 = −Δdd1 − Δdd2 ,so the total dc-link voltage regulation is not affected. Mean-while, the q-axis current references are still independent formthe d-axis, which means the reactive power can be controlledindependently.

In order to verify the proposed voltage control, the switch-ing model simulation of the 20-kVA SST is implemented inMATLAB/Simulink. The SST topology is shown in Fig. 5 andthe simulation parameters are shown in Table I. The parameterselections are described in [17].

In the simulation, the real power P1 , P2 , and P3 of the threeH-Bridges are controlled by connecting different resistors to the3.8-kV dc links, E1 , E2 , and E3 as shown in Fig. 5. Before0.83 s, the three H-Bridges transfer the same amount of realpower, P1 = P2 = P3 = 1.0 p.u. (20 kW/3). Then, at 0.83 s, P2and P3 are decreased to 0.8 p.u., P1 = 1.0 p.u., P2 = P3 = 0.8p.u. (20% load unbalance).

Two different cases are simulated. Fig. 7 shows the threedc-link voltages without voltage balance control. The threeH-Bridge dc-link voltages become unbalanced after the powerchange. The H-bridge that transfers more power has the highestdc-link voltage. Fig. 8 shows the three dc-link voltages with

ZHAO et al.: VOLTAGE AND POWER BALANCE CONTROL FOR A CASCADED H-BRIDGE CONVERTER-BASED SOLID-STATE TRANSFORMER 1527

Fig. 5. Voltage and power unbalance in SST topology.

voltage balance control. With the voltage balance controller,the three dc-link voltages are equally regulated in the steadystate. This simulation demonstrates that with voltage balancecontrol, even if there is 20% power unbalance from the paralleldc/dc converters, the dc-link voltages can still be balanced. Thedifferent resistors simulate a 20% power difference, which iscaused by no power balance control in the DAB modules. Sowhen the power balancing control is implemented in DAB, thepower difference is dominated by converter power losses, thepower unbalance is much smaller than 20%. This guarantees thethree dc-link voltage can always be balanced with the proposedvoltage balance control.

B. Voltage Balance Constraints

The proposed voltage controller can maintain the balanceddc-link voltage when the real power is different for each H-Bridge. However, due to the intrinsic constraints of the cascadedH-Bridge structure, in order to maintain the dc-link balanced,the real power unbalance range of the H-Bridges is limited. Thislimitation is determined by the input ac voltage, dc-link voltagereference, input inductance, and the number of H-bridges. Asshown in Fig. 9, the constraints of the voltage vectors are givenby (11)–(21). The derivations are based on the assumption of aunity power factor at the SST rectifier input

V1 + V2 + V3 = Vline − jωLIline (11)

V1 = (d1 + jq1)E, V2 = (d2 + jq2)E

V3 = (d3 + jq3)E (12)

where, Vn is the Nth H-Bridge voltage vector, Vline is the singlephase input ac voltage, Iline is the input ac current, dn and qn

are the d-axis and q-axis duty cycle generated by the controller,and E is the dc-link reference voltage of each H-Bridge.

Fig. 6. Proposed voltage balance control based on the single-phase dq vector.

TABLE ISIMULATION PARAMETERS

Fig. 7. DC-link voltages without voltage balance control.

Rearrange the (11) and (12)

Vline − jωLIline = (d1 + jq1 )E + (d2 + jq2 )E + (d3 + jq3 )E

= E(d1 + d2 + d3 ) + jE(q1 + q2 + q3 ). (13)

So, d1 + d2 + d3 =Vline

E, q1 + q2 + q3 =

−jωLIline

E. (14)

1528 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 4, APRIL 2013

Fig. 8. DC-link voltages with voltage balance control.

Fig. 9. Rectifier voltage vector constrains.

The real power PN and reactive power QN of the Nth H-Bridge is calculated as

P1 + jQ1 = IlineV1 = Iline(d1 + jq1)E (15)

P2 + jQ2 = IlineV2 = Iline(d2 + jq2)E (16)

P3 + jQ3 = IlineV3 = Iline(d3 + jq3)E. (17)

So from (15)–(17)

P1 = Ilined1E, P2 = Ilined2E, P3 = Ilined3E. (18)

The total input power Pin =N =3∑

1Pn = IlineVline , so

Iline =Pin

Vline. (19)

Substitute Iline in (14) with (19), then d1 , d2 , and d3 arederived as

d1 =P1

Pin

Vline

E, d2 =

P2

Pin

Vline

E, d3 =

P3

Pin

Vline

E. (20)

Without loss of generality, assume d1 ≥ d2 ≥ d3 , the reactivepower is equally distributed and no overmodulation d2

1 + q21 ≤1.

According to (14) q1 + q2 + q3 = −jωLI l i n eE , so d1 ≤√

1 − (ωLI l in e3E )2 .

Substitute d1 with (20), then the maximum power P1 shouldmeet the

P1∑N1 Pn

≤ E

Vline

√1 −

(ωLIline

NE

)2

(21)

where, N is the number of H-Bridges.

Fig. 10. Power balance controller.

In order to balance the dc-link voltages, the real power ofeach H-Bridge has to be within the range presented in (21). Inother words, if the power unbalance is too large, the H-Bridgewill not be able to maintain the balanced dc-link voltage. For thedesigned SST system, according to (21), the maximum powerunbalance occurs when the maximum power P1 = 37% Pin .

When the SST is under light load condition, the power un-balance becomes much more severe because the device lossand transformer parameter mismatch account for a significantpercentage of the total power, the power balance equation (21)cannot be assured. Therefore, a power balance control is neededto regulate the H-Bridge real power.

C. Power Balance Control

Due to the parameter variation of the high-frequency trans-formers, such as leakage inductance and turns ratio, the threeDAB currents can be different, which results in a power unbal-ance of the three DAB modules. A power balance control methodis proposed to regulate the real power transferring through theDAB parallel modules. As shown in Fig. 10, the voltage regu-lator compares the low-voltage dc voltage VdcL with the refer-ence VdcL ref and generates the power references Pref for thethree DAB modules. Then, the power regulator compares thecalculated average power of each DAB module with Pref andgenerates the phase-shift angles ϕ1 , ϕ2 , and ϕ3 for the threeDAB modules. Fig. 11 shows how the average power calculatorcalculates the average power in each switching cycle. In thecalculation, P =

∫ π

0 VdcH ipdt, the primary dc voltage VdcH canbe considered constant in a switching cycle. So the power cal-culation involves only the summation of current, which is easilyimplemented in DSP.

The switching model simulation is implemented to verify theproposed power balance control. In the simulation, differentleakage inductance values are simulated for the three trans-formers: 165, 165, and 115 mH (30% variation). Figs. 12 and14 are the DAB primary currents and power without powerbalance control. The DAB module with smaller leakage in-ductance has large current and transfers more power. Figs. 13and 15 illustrate the DAB primary currents and power withpower balance control. The transformer current and the powertransferring through each DAB module is balanced. So the

ZHAO et al.: VOLTAGE AND POWER BALANCE CONTROL FOR A CASCADED H-BRIDGE CONVERTER-BASED SOLID-STATE TRANSFORMER 1529

Fig. 11. DAB average power calculation.

Fig. 12. DAB current without power balance control.

Fig. 13. DAB current with power balance control.

power balance control guarantees the power unbalance of theparallel DAB modules meets the (21), so that the dc-link volt-ages can always be balanced with the proposed voltage balancecontrol.

Fig. 14. DAB power without power balance control.

Fig. 15. DAB power with power balance control.

TABLE IISST PROTOTYPE PARAMETERS

IV. SST EXPERIMENTAL RESULTS

To verify the proposed SST controller and voltage balancecontrol, a scaled-down SST prototype is implemented. TheSST prototype is designed for single-phase input voltage 60 Hz240 V, and dc output 400 V. The prototype consists of a cascadedH-Bridge ac/dc rectifier that converts 60 Hz, 240-V ac to 400-Vdc bus, a dc/dc converter that converts 400 V to 400-V dc buswith 1:1 high-frequency transformer. The prototype is imple-mented by using 600 V 75-A intelligent power modules. TheSST control algorithm is programmed in DSP TMS320F28335.The experiment parameters are shown in Table II.

The single-phase dq vector control is implemented in the DSPcontroller by using a model-based program. The phase A voltage

1530 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 4, APRIL 2013

Fig. 16. Experimental results of SST rectifier stage (Ch1, input ac voltage Vac ,100 V/div; Ch2, dc-link voltage of H -Bridge #2 E2 , 20 V/div; Ch3, rectifierPWM voltage Vpwm , 100 V/div; Ch4, input current Iac , 10 A/div).

is delayed by 1/4 cycle to synthesize the imaginary phase M. Inthe experiment, the dc bus voltage reference is 400 V and thereactive power reference is zero, which means a unity powerfactor. Fig. 16 demonstrates the steady-state experiment resultsof the SST rectifier stage with single-phase dq vector controller.The dc-link voltage is regulated to the reference 400 V total(133 V each H-Bridge) and the input current is in phase withthe input voltage, which indicates a unity power factor.

The SST rectifier stage not only converts the input ac to reg-ulated dc voltages, but also has reactive power compensationcapabilities. Depending on the reactive power reference in theSST controller, the SST can generate or absorb reactive powerto the power grid. As shown in Fig. 17(a), the input currentis leading the input voltage, so the SST is generating reactivepower to the input. In Fig. 17(b), the input current is laggingthe input voltage, so the SST is absorbing reactive power fromthe system. The reactive power reference can be generated bythe higher level smart grid system and communicated to theSST DSP controller. Fig. 18 shows experimental results of SSTvoltage sag compensation. The input ac voltage has a 23% volt-age sag, the input current increases to maintain the same inputpower. The dc-link voltage decreases when the voltage sag hap-pens, and then recovers back to normal. The overshoot voltageof the dc-link voltage is 14% of the normal voltage and thetransient time is eight cycles with a 10-Hz voltage control loopbandwidth.

In order to verify the voltage balance controller, the load re-sistors R1 , R2 , and R3 connected to the three dc links E1 , E2 ,and E3 are dynamically changed to create the real power dif-ferences. In this experiment, the input voltage is 90 Vac andthe dc-link Reference voltage is 150 V (50 V each H-Bridge);the load resistor R3 changes from 32 to 46 Ω while R2 and R3maintain as 32 Ω. Fig. 19 illustrates the three dc-link voltageswithout the voltage balance control. The three dc-link voltagesare all regulated at 50 V when the loads are the same. However,after the load change, the dc-link voltages become 43, 43, and56 V (25% voltage unbalance), respectively. The H-Bridge with

Fig. 17. Experimental results of SST capacitive mode (a) and reactive mode(b) (Ch1, input ac voltage Vac , 100 V/div; Ch2, dc-link voltage E2 , 20 V/div;Ch3, rectifier PWM voltage Vpwm , 100 V/div; Ch4, input current Iac , 10 A/div).(a) Capacitive mode. (b) Reactive mode.

Fig. 18. Experimental results of SST voltage sag compensation (Ch1, inputac voltage Vac , 100 V/div; Ch2, dc-link voltage E2 , 20 V/div; Ch3, rectifierPWM voltage Vpwm , 100 V/div; Ch4, input current Iac , 10 A/div).

ZHAO et al.: VOLTAGE AND POWER BALANCE CONTROL FOR A CASCADED H-BRIDGE CONVERTER-BASED SOLID-STATE TRANSFORMER 1531

Fig. 19. DC-link voltages without balance control (Ch1, dc-link voltage ofH -Bridge #1 E3 , 20 V/div; Ch2, dc-link voltage of H -Bridge #2 E1 , 20 V/div;Ch3, dc-link voltage of H -Bridge #3 E2 , 20 V/div; Ch4, rectifier PWM voltageVpwm , 200 V/div).

Fig. 20. DC-link voltages with balance control (Ch1, dc-link voltage of H -Bridge #1 E3 , 20 V/div; Ch2, dc-link voltage of H -Bridge #2 E1 , 20 V/div;Ch3, dc-link voltage of H -Bridge #3 E2 , 20 V/div; Ch4, rectifier PWM voltageVpwm , 200 V/div).

a larger load resister has a higher dc-link voltage (E3 in theFig. 19). Fig. 20 shows the three dc-link voltages with the volt-age balance control. The balance controller regulates the dc-linkvoltage when there is a load change. The dc-link voltages havea transit time of about 4 cycles, then settle down to be the samevoltage. The experiment verifies the effectiveness of the voltagebalance controller.

According to (21), the maximum power unbalance happenswhen the load resistor R3 is 65 Ω and R1 = R2 = 32 Ω. Fig. 21demonstrates the dc-link voltages when R3 changes from 32to 65 Ω (power balance limit). The unbalanced power does notmeet the (21), the dc-link voltage will inevitably become unbal-anced as shown in Fig. 21. The experimental results verify theanalysis of maximum power unbalance limit; therefore the pro-posed power controller is indispensable to guarantee the power

Fig. 21. DC-link voltages with balance control, R3 changes from 32 Ωe to65 Ω (Ch1, dc-link voltage of H -Bridge #1 E1 , 20 V/div; Ch2, dc-link voltage ofH -Bridge #2 E2 , 20 V/div; Ch3, dc-link voltage of H -Bridge #3 E3 , 20 V/div;Ch4, input current Iac , 10 A/div).

unbalance is always limited within the required range so thatthe dc-link voltages can be balanced.

V. CONCLUSION

In this paper, a cascaded H-Bridge converter-based SST isproposed to interface between 7.2-kV ac grid and a 400-V dcdistribution in smart grid systems. The single-phase dq vectormodeling and control of the SST, including ac/dc rectifier, DABconverter is developed. A new voltage balance control method isproposed to resolve the voltage unbalance of the dc links in dif-ferent H-bridges. The power intrinsic unbalance constraints ofthe voltage balance control for the cascaded H-Bridge rectifieris derived and verified by simulations and experiments. Mean-while, a power balance control method is proposed to regulatethe real power transferring through the parallel modules. Finally,the switching model simulation and SST scale-down prototypeare implemented with the proposed controller. The experimen-tal results verify the performance of the SST, including powerfactor correction, real and reactive power control, voltage sagecompensation, and the proposed voltage balance control.

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Tiefu Zhao (S’06–M’10–SM’12) received the B.S.and M.S. degrees from Tsinghua University, Beijing,China, in 2003 and 2005, respectively, and the Ph.D.degree from North Carolina State University, Raleigh,in 2010, all in electrical engineering.

From 2003 to 2005, he was at the State KeyLaboratory of Control and Simulation of Power Sys-tem and Generation Equipment, Tsinghua University,China. From 2006 to 2010, he was a Research Assis-tant at the Semiconductor Power Electronics Center,and the National Science Foundation Future Renew-

able Electric Energy Delivery and Management (FREEDM) Systems Center,North Carolina State University. Since 2010, he has been a Lead Engineer atEaton Corporation Innovation Center, Milwaukee, WI. He has published morethan 20 technical papers in international journals and conference proceedings,and has one Chinese patent and three U.S. patents pending. His research interestsinclude power converter topology and control, renewable energies, solid-statetransformers, SiC devices, motor drives, and flexible AC transmission systems(FACTS).

Gangyao Wang (S’09) received the B.Sc. degree inelectrical engineering from the Nanjing Universityof Aeronautics and Astronautics, Nanjing, China, in2004. He is currently working toward the Ph.D. de-gree at the Future Renewable Electric Energy De-livery and Management (FREEDM) Systems Center,Department of Electrical and Computer Engineering,North Carolina State University, Raleigh.

From 2005 to 2007, he was an Electrical Engi-neer at Delta Electronics Shanghai Design Center,Shanghai, China. His current research interests in-

clude solid-state transformer design, SiC power-device application, and thecontrol and modeling of the power converters.

Subhashish Bhattacharya (M’85) received the B.E.(Hons.) degree from the Indian Institute of Technol-ogy Roorkee, Roorkee, India, in 1986, the M.E. de-gree in electrical engineering from the Indian Instituteof Science (IISc), Bangalore, India, in 1988, and thePh.D. degree in electrical engineering from the Uni-versity of Wisconsin, Madison, in 2003.

He worked in the Flexible AC TransmissionSystems (FACTS) and Power Quality group atWestinghouse R&D Center in Pittsburgh which laterbecame part of Siemens Power Transmission & Dis-

tribution, from 1998 to 2005. He joined the Department of Electrical and Com-puter Engineering at North Carolina State University (NCSU) as an AssistantProfessor in August 2005, where he is the ABB Term Associate Professor sinceAugust 2011, and also a Faculty Member of NSF ERC FREEDM systems center(www.freedm.ncsu.edu) and Advanced Transportation Energy Center [ATEC](www.atec.ncsu.edu) at NCSU. His research interests are Solid-State Trans-formers, FACTS, Utility applications of power electronics and power qualityissues; high-frequency magnetics, active filters, high power converters, convertercontrol techniques, integration of energy storage to the grid, and application ofnew power semiconductor devices such as SiC for converter topologies.

Alex Q. Huang (S’91–M’94–SM’96–F’05) was bornin Zunyi, Guizhou, China. He received the B.Sc. de-gree from Zheijiang University, China, in 1983 andthe M.Sc. degree from Chengdu Institute of RadioEngineering, China, in 1986, both in electrical en-gineering. He received the Ph.D. from CambridgeUniversity, U.K. in 1992.

From 1992 to 1994, he was a Research Fellow atMagdalene College, Cambridge. From 1994 to 2004,he was a Professor at the Bradley Department of Elec-trical and Computer Engineering, Virginia Polytech-

nic Institute and State University, Blacksburg. Since 2004, he has been withNorth Carolina State University, Raleigh, North Carolina and he is currentlythe Progress Energy Distinguished Professor of Electrical and Computer Engi-neering and the director of the NSF FREEDM Systems ERC, NCSU AdvancedTransportation Energy Center (ATEC) and NCSU Semiconductor Power Elec-tronics Center (SPEC). Since 1983, he has been involved in the developmentof modern power semiconductor devices and power integrated circuits. He fab-ricated the first IGBT power device in China in 1985. He is the inventor andkey developer of the emitter turn-off thyristor technology. His current researchinterests are power electronics, power management microsystems and powersemiconductor devices. He has published more than 300 papers in the interna-tional conferences and journals, and has nineteen U.S. patents.

Dr. Huang is the recipient of the NSF CAREER award, the prestigious R&D100 Award and the MIT Technology Review’s 2011 Technology of the Yearaward.

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