vlsilab

VLSI LAB MANUAL 2010

VLSI LAB MANUAL

(06ESL77)

Mahesh .A .ADepartment of Electronics and Communication

1 Bangalore Prepd. By, Mahesh. A.A Dept. Electronics and Communication


INDEX

I. VLSI DESIGN FLOW AND THE TOOLS USED IN CADENCE

II. PART A: Digital SimulationPROCEDURE FOR CREATING DIGITAL SIMULATION USING VERILOG AND CADENCE DIGITAL TOOL.Experiment1: InverterExperiment2: BufferExperiment3: Transmission Gates(TG)Experiment4: Logic Gates

AND,OR,NAND,NOR,XOR,XNORExperiment5: Flip Flops

JK,MS,SR,D,TExperiment6: Synchronous CounterExperiment7: Asynchronous CounterExperiment8: Parallel AdderExperiment 9: Serial Adder

III. PART B: Analog Design

PART B[1] : Schematic SimulationPROCEDURE FOR CREATING THE SCHEMATIC SIMULATION

Experiment 1(a): Inverter Schematic and test Cell View Experiment 2(a): Common Source Amplifier Schematic and test Cell View Experiment 3(a): Common Drain Amplifier Schematic and test Cell View Experiment 4(a): Differential Amplifier Schematic and test Cell View Experiment 5(a): Operational Amplifier Schematic and test Cell View Experiment 6(a): R-2R DAC Schematic and test Cell View

PART B[1] : Layout SimulationLayout Design Rules PROCEDURE FOR CREATING THE LAYOUT AND SIMULATINGExperiment 1(b): Inverter Layout Design Experiment 2(b): Common Source Amplifier Layout Design Experiment 3(b): Common Drain Amplifier Layout DesignExperiment 4(b): Differential Amplifier Layout DesignExperiment 5(b): Operational Amplifier Layout Design



IV. VLSI Viva Questions 1) VLSI DESIGN FLOW AND TOOLS USED IN CADENCE

PDK stands for Process Design Kit. A PDK contains the process technology and needed

information to do device-level design in the Cadence DFII environment.



PART - A



2) PART A: Digital Simulation

PROCEDURE FOR CREATING DIGITAL SIMULATION USING VERILOG AND

CADENCE DIGITAL TOOL.

Open Terminal Window and use the following commands

#csh #source cshrc

#ls (ls can be skipped if you know which is the next directory to go)-this will list out the directories likeCadence_digital_labscadence_analog_labs … then

#cd Cadence_digital_labs/Workarea

Crate a directory for the experiment presently executed by using following command.mkdir directory name Ex: mkdir Inverter

Create the module file/s(Verilog module ): Vi modulename.v Ex: vi inverter.v The file name can be changes with respect to the experiments.

A Text Editor window will open.To enter text in editor window PRESS “I” and then type

the program and exit to terminal window by save and exit command --- Press Esc :wq! Repeat the steps for test bench by following above TWO steps with different file name.

Ex: vi test_inverter.v

Now to compile

Compile the module file/s with message option:ncvlog modulefilename.v-messagesEx: ncvlog inverter.v –messages (RTL code compilation)

Compile the test bench file with message option:ncvlog testbenchname.v-messageEx: ncvlog inverter.v –messages

Note: Check out for error and warnings. If any then go back to text editor and edit and the compile

Elaborate the top level design(test bench)



ncelab toplevelmodulename-access+rwc-messageTop level module name to be elaborated is the name of test bench modulencelab inv_test –access +rwc –messages

Simulate the top level design Non GUI mode

ncsim toplevelmodulenamencsim inv_test

In GUI Mode Ncsim toplevelmodulename-guincsim inv_test -gui

Now a console and Design Browser windows of Simvision are opened.In the Design Browser Window,Select the toplevelmodulename scope(Ex:inv_test) and

select all the signals displayed and click on the waveform button in the toolbar.Waveform Window opens.Press run to run the simulation for a time period specified in

the time field.

Synthesize procedure using Cadence Tool



# cd csh #source cshrc # cd Cadence_digital_labs/Workare #cd rclabs --- for digital synthesis enter into rclabs #cd rtl --- The verilog file to be sythesizd must be copied into this

directory form the directory where the simulated code is present. i.e from your directory created under Workarea.

cd .. --- Come back rclabs directory #cd work --- Get into work directory under rclabs to synthesize the hdl file

present in rtl directory. #rc –gui --- this would start a GUI window for synthesizing. rc:/>set_attr lib_search_path ../library rc:/>set_attribute hdl_search_path ../rtl rc:/>set_attr library slow_highvt.lib (if this step gives an error then close the rc

window by closing the GUI window and then type the following) #cd / #cd root/Cadence_digital_labs #tar -xzvf Cadence_digital_labs.tar.gz (this should work and then continue

with RC labs again) rc:/>read_hdl {file_name.v} Ex:read_hdl {ff1.v} (ff1.v must be in rtl directory of

rclabs) rc:/>read_sdc ../constraints_filename.g (if any constraints file they must be read here) rc:/>elaborate rc:/>synthesize -to_mapped -effort medium ---now you must be able to see the

schematic else go to file and click on update GUI in GUI window. rc:/>write > any_name.v rc:>report timing - This gives the timing reports like delay, propagation so on rc:/>report power - This gives the power dissipation report static and dynamic

power dissipation rc:/>report area - This gives no of cell used and the area used for the calls.

Experiment1: Inverter



Verilog code for inverter

`resetall`timescale 1 ns / 1 ns`view vlog

//Define our own Inverter,

module inverter( out , in );

// Declarations of I/O ,Power and Ground Lines output out; input in; supply1 pwr; supply0 gnd;

// Instantiate pmos and nmos switchespmos (out,pwr,in);nmos (out,gnd,in); endmodule`noview

Test bench for inverter

`resetall



`timescale 1 ns / 1 ns`view vlog

// Testbench for Inverter Module

module inv_test; wire out ; reg in ; `uselib view = vlog

// Instantiate inverter Module

inverter i1 ( out, in ) ;`nouselib

// Display task display ; begin $display ( "time=%0d" , $time , " ns" , " Input=" , in , " Output=", out ) ; end endtask

// Apply Stimulus

initial begin in = 1'b0 ; #10 ; display ; in = 1'b1 ; #10 ; display ; in = 1'bx ; #10 ; display ; in = 1'bz ; #10 ; display ; end

endmodule

`noview

Experiment 2: BUFFER



Verilog code for BUFFER


//Define our own Inverter,module inverter( Y, A );// Declarations of I/O ,Power and Ground Lines output Y; input A; supply1 pwr; supply0 gnd; // Instantiate pmos and nmos switchespmos (Y,pwr,A);nmos (Y,gnd,A); endmodule

// Define our own Buffermodule buffer( out, in);

// Declarations of I/O Lines output out; input in;

// Wire Declaration wire a;



// Instantiate Inverter moduleinverter i1 (a,in);inverter i2 (out,a);endmodule`noview

Test bench for BUFFER


// Testbench for Buffer Module

module buf_test; wire out ; reg in ; `uselib view = vlog

// Instantiate Buffer Module

buffer b1 ( out, in ) ;`nouselib

// Display task display ; begin $display ( "time=%0d" , $time , " ns" , " Input=" , in , " Output=", out ) ; end endtask// Apply Stimulus initial begin in = 1'b0 ; #10 ; display ; in = 1'b1 ; #10 ; display ; in = 1'bx ; #10 ; display ; in = 1'bz ; #10 ; display ; endendmodule`noviewExperiment 3: TRANSMISSION GATE(TG)



Verilog code for TG

`resetall`timescale 1 ns / 1 ns`view vlog//Define our own Transmission Gate,module trangate( out , in , cntrl1, cntrl2 );// Declarations of I/O and Control Lines output out; input in; input cntrl1,cntrl2;// Instantiate pmos and nmos switchespmos (out,in,cntrl1);nmos (out,in,cntrl2);endmodule`noview

Test bench for TG




// Testbench for Inverter Module

module trangate_test; wire out ; reg in ; reg cntrl1,cntrl2;`uselib view = vlog

// Instantiate trangate Module trangate t1 ( out, in, cntrl1, cntrl2 ) ;

`nouselib

// Display task display ; begin $display ( "time=%0d" , $time , " ns" , " Input=" , in , " Output=", out , " Control1=",cntrl1 , " Control2=",cntrl2 ) ; end endtask

// Apply Stimulus initial begin in = 1'b0 ; cntrl1 = 1'b0 ; cntrl2 = 1'b1 ; #10 ; display ; in = 1'b0 ; cntrl1 = 1'b1 ; cntrl2 = 1'b0 ; #10 ; display ; in = 1'b1 ; cntrl1 = 1'b0 ; cntrl2 = 1'b1 ; #10 ; display ; in = 1'b1 ; cntrl1 = 1'b1 ; cntrl2 = 1'b0 ; #10 ; display ; endendmodule

`noviewExperiment 4: LOGIC GATES



4.1 NAND GATE

Verilog code for NAND GATE

`resetall`timescale 1 ns / 1 ns`view vlog//Define our own Nand Gate, module nandgate ( out , in1 , in2 );// Declarations of I/O ,Power and Ground Lines output out; input in1,in2; supply1 pwr; supply0 gnd; // Declaration of Wire wire contact;// Instantiate pmos and nmos switches pmos (out,pwr,in1); pmos (out,pwr,in2); nmos (out,contact,in1); nmos (contact,gnd,in2);endmodule`noviewTest bench for NAND GATE




// Testbench for Nand Gate Module

module nand_test; wire out ; reg in1,in2 ;`uselib view = vlog

// Instantiate Nand Gate Module nandgate n1 ( out, in1, in2 ) ;`nouselib

// Display task display ; begin $display ( "time=%0d" , $time , " ns" , " Input1=" , in1 , " Input2=" , in2 , " Output=" , out ) ; end endtask

// Apply Stimulus

initial begin in1 = 1'b0 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b0 ; in2 = 1'b1 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b1 ; #10 ; display ; end

endmodule

`noview

4.2 AND GATE



Verilog code for AND GATE


//Define our own And Gate, module andgate ( out , in1 , in2 );// Declarations of I/O ,Power and Ground Lines output out; input in1,in2; supply1 pwr; supply0 gnd; // Declaration of Wires wire contact; wire nout;// Instantiate pmos and nmos switches to form Nand gate pmos (nout,pwr,in1); pmos (nout,pwr,in2);



nmos (nout,contact,in1); nmos (contact,gnd,in2); // Instantiate pmos and nmos switches to form Inv pmos (out,pwr,nout); nmos (out,gnd,nout);endmodule`noviewTest bench for AND GATE

`resetall`timescale 1 ns / 1 ns`view vlog// Testbench for And Modulemodule and_test; wire out ; reg in1,in2 ;`uselib view = vlog// Instantiate And Gate Module andgate a1 ( out, in1, in2 ) ;`nouselib// Display task display ; begin $display ( "time=%0d" , $time , " ns" , " Input1=" , in1 , " Input2=" , in2 , " Output=" , out ) ; end endtask// Apply Stimulus initial begin in1 = 1'b0 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b0 ; in2 = 1'b1 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b1 ; #10 ; display ; endendmodule`noview

4.3 NOR GATE



Verilog code for NOR GATE


//Define our own Nor Gate, module norgate ( out , in1 , in2 );// Declarations of I/O ,Power and Ground Lines output out; input in1,in2; supply1 pwr; supply0 gnd; // Declaration of Wire wire contact;

// Instantiate pmos and nmos switches pmos (contact,pwr,in1);



pmos (out,contact,in2); nmos (out,gnd,in1); nmos (out,gnd,in2);endmodule`noview

Test bench for NOR GATE

`resetall`timescale 1 ns / 1 ns`view vlog// Testbench for Nor Gate Module module nor_test; wire out ; reg in1,in2 ;`uselib view = vlog

// Instantiate Nor Gate Module norgate n1 ( out, in1, in2 ) ;`nouselib// Display task display ; begin $display ( "time=%0d" , $time , " ns" , " Input1=" , in1 , " Input2=" , in2 , " Output=" , out ) ; end endtask// Apply Stimulus initial begin in1 = 1'b0 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b0 ; in2 = 1'b1 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b1 ; #10 ; display ; endendmodule`noview4.4 OR GATE



Verilog code for OR GATE


//Define our own Or Gate, module orgate ( out , in1 , in2 );// Declarations of I/O ,Power and Ground Lines output out; input in1,in2; supply1 pwr; supply0 gnd; // Declaration of Wires wire contact; wire nout;// Instantiate pmos and nmos switches for Nor gate pmos (contact,pwr,in1); pmos (nout,contact,in2); nmos (nout,gnd,in1);



nmos (nout,gnd,in2); // Instantiate pmos and nmos switches for Not gate pmos (out,pwr,nout); nmos (out,gnd,nout);endmodule

`noview

Test bench for OR GATE

`resetall`timescale 1 ns / 1 ns`view vlog// Testbench for Nor Gate Modulemodule or_test; wire out ; reg in1,in2 ;`uselib view = vlog// Instantiate Orgate Module orgate n1 ( out, in1, in2 ) ;`nouselib// Display task display ; begin $display ( "time=%0d" , $time , " ns" , " Input1=" , in1 , " Input2=" , in2 , " Output=" , out ) ; end endtask// Apply Stimulus initial begin in1 = 1'b0 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b0 ; in2 = 1'b1 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b1 ; #10 ; display ; endendmodule`noview4.5 XNOR GATE



Verilog code for XNOR GATE


//Define our own XNOR Gate,

module xnorgate( out , in1 , in2 );

// Declarations of I/O ports

output out; input in1,in2; wire in2bar;

assign in2bar = ~in2;

// Instantiate pmos and nmos switches :



pmos (out,in2bar,in1);nmos (out,in2,in1);pmos (out,in1,in2bar);nmos (out,in1,in2);endmodule`noviewTest bench for XNOR GATE

`resetall`timescale 1 ns / 1 ns`view vlog// Testbench for Xnor Modulemodule xnor_test; wire out ; reg in1,in2 ;`uselib view = vlog

// Instantiate Xnor gate Module xnorgate x1 (out, in1, in2 ) ;`nouselib// Display task display ; begin $display ( "time=%0d" , $time , " ns" , " Input1=" , in1 , " Input2=" , in2 , " Output=" , out ) ; end endtask// Apply Stimulus initial begin in1 = 1'b0 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b0 ; in2 = 1'b1 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b1 ; #10 ; display ; endendmodule`noview

4.6 XOR GATE



Verilog code for XOR GATE


//Define our own XOR Gate,module xorgate( out , in1 , in2 );// Declarations of I/O ports output out; input in1,in2; wire in2bar; assign in2bar = ~in2;// Instantiate pmos and nmos switches : pmos (out,in2,in1); nmos (out,in2bar,in1); pmos (out,in1,in2); nmos (out,in1,in2bar);endmodule`noviewTest bench for XOR GATE



`resetall`timescale 1 ns / 1 ns`view vlog// Testbench for Xor Modulemodule xor_test; wire out ; reg in1,in2 ;`uselib view = vlog// Instantiate Xorgate Module xorgate x1 (out, in1, in2 ) ;`nouselib// Display task display ; begin $display ( "time=%0d" , $time , " ns" , " Input1=" , in1 , " Input2=" , in2 , " Output=" , out ) ; end endtask// Apply Stimulus initial begin in1 = 1'b0 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b0 ; in2 = 1'b1 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b0 ; #10 ; display ; in1 = 1'b1 ; in2 = 1'b1 ; #10 ; display ; endendmodule`noview

Experiment 5: FLIP FLOPS



5.1 D Flipflop:

Verilog File for D fillip flopmodule d_ff(d,clk, q,qb);input d,clk;output reg q,qb;always@(posedge(clk))beginq = d;qb = ~d;endendmodule

Test Bench for D fillip flopmodule d_test;reg d,clk;wire q,qb;d_ff my_ff(d,clk,q,qb);initialclk = 1'b1;always#5 clk = ~clk;initialbegind = 0; #10;d = 1; #10;d = 0; #10;d = 1; #10;endendmodule5.2 JK FLIP FLOP



Verilog Code for JK-FF

module jk_ff(j, k, clk, q, qb);input j,k,clk;output reg q,qb;reg kk = 1'b0;reg [1:0] t;always@(posedge(clk))begint={j,k};case(t)2'b00 : kk = kk;2'b01 :kk = 1'b0;2'b10 : kk = 1'b1;2'b11 :kk = ~kk;default: ;endcaseq = kk; qb = ~q;endendmodule

Test Bench for JK-FF



module jk_test;reg j,k,clk;wire q,qb;jk_ff my_ff (j,k,clk,q,qb);initial clk = 1'b0;always#5 clk = ~clk;initialbeginj = 0; k = 0; #10;j = 1; k = 1; #20;j = 0; k = 1; #10;j = 1; k = 1; #20;j = 1; k = 0; #10;endendmodule

5.3 MS FLIP FLOP



Verilog Code MS- FF

module ms_ff(j,k,clk, q,qb);input j,k,clk;output q,qb;jk_ff u1(j,k,clk,qm,qmb);jk_ff u2(qm,qmb,~clk,q,qb);endmodule

Test Bench for MS-FF

module ms_test;reg j,k,clk;wire q,qb;ms_ff my_ff (j,k,clk,q,qb);initialclk = 1'b0;always#5 clk = ~clk;initialbeginj = 1; k = 0; #10;j = 0; k = 1; #10;



j = 1; k = 0; #10;j = 0; k = 1; #10;j = 1; k = 1; #10;endendmodule

5.4 SR FLIP FLOP



Verilog Code SR FF

module sr_ff(s,r, q,qb);input s,r;output reg q,qb;reg st = 1'b0;reg [1:0] k;always@(s|r)begink = {s,r};case(k)2'b00 : st = st;2'b01 : st = 1'b0;2'b10 : st = 1'b1;2'b11 : st = 1'bz;default: ;endcaseq = st;qb = ~q;endendmodule

Test Bench SR FLIP FLOP

module sr_test;



reg r,s;wire q,qb;sr_ff my_ff(s,r,q,qb);initialbeginr = 0; s = 0; #10;r = 0; s = 1; #10;r = 1; s = 0; #10;r = 1; s = 1; #10;r = 0; s = 0; #10;r = 0; s = 1; #10;r = 1; s = 0; #10;r = 1; s = 1; #10;endendmodule

5.5 T FLIP FLOP



Verilog Code for T FF

module t_ff(t,clk, q,qb);input t,clk;output q,qb;jk_ff u1(t,t,clk,q,qb);endmodule

Test Bench Code for T FF

module t_test;reg t,clk;wire q,qb;t_ff my_ff(t,clk,q,qb);initialclk = 1'b0;always#5 clk = ~clk;initialbegint = 0; #10;t = 1; #10;t = 0; #10;t = 1; #10;endendmodule

Experiment 6: SYNCRONOUS COUNTER



Verilog code for SYNCRONOUS COUNTER

module count(clk,UpDown, reset, q);input clk,UpDown;input reset;output reg [3:0] q;reg [3:0] t=4'd0;always@(posedge(clk))beginif(reset==0)t=4'd0;else if(UpDown == 1)t = t + 1;elset = t - 1;q=t;endendmodule

TEST BENCH for SYNCRONOUS COUNTER



module Test_updown;reg clk,reset,updown;wire [3:0] q;count my_count (clk,updown,reset,q);initialclk=1'd0;always#5 clk = ~clk;initialbeginreset = 0;updown = 1;#5;reset = 1;#160;updown = 0;#160;updown = 1;endendmodule

Experiment 7: ASYNCRONOUS COUNTER



Verilog code for ASYNCRONOUS (RIPPLE)COUNTER

module count_ashyn(clk,rst,updown, count);input clk,rst,updown;output reg [3:0] count;always@(posedge(clk),posedge(rst))beginif(rst == 1)count = 4'd0;else if(clk == 1)if( updown == 1)count = count + 1;elsecount = count - 1;endendmodule

TEST BENCH for ASYNCRONOUS (RIPPLE)COUNTER



module test_asyn;reg clk,rst,updown;wire [3:0] count;count_ashyn uut (clk,rst,updown,count);initialclk = 1'd0;always#5 clk = ~clk;initialbeginupdown = 1;rst = 0;#10;rst = 1;#20;rst=0;#83;rst = 1;#10;rst = 0;updown = 0;#33;rst = 1;endendmodule

Experiment 8: PARALLEL ADDER



Cin A3 A2 A1 A0 B3 B2 B1 B0 Cout S3 S2 S1 S0

0 1 0 0 1 1 0 0 1 1 0 0 1 00 0 1 1 1 0 0 0 1 0 1 0 0 01 1 0 0 1 1 0 0 0 1 0 0 0 11 0 0 0 1 0 0 1 1 0 1 1 1 0

Verilog code for FULL ADDER

module fulladd (cin,x,y,s,cout);

input cin,x,y;output s,cout;assign s = x^y^cin;assign cout =( x & y) | (x & cin) |( y & cin);

endmodule

Verilog code for PARALLEL ADDER

module adder4 ( carryin,x,y,sum,carryout);

input carryin; input [3:0] x,y; output [3:0] sum; output carryout; fulladd stage0 (carryin,x[0],y[0],sum[0],c1); fulladd stage1 (c1,x[1],y[1],sum[1],c2); fulladd stage2 (c2,x[2],y[2],sum[2],c3); fulladd stage3 (c3,x[3],y[3],sum[3],carryout);

endmodule

TEST BENCH for PARALLEL ADDER

module adder4_t ;



reg [3:0] x,y;reg carryin;wire [3:0] sum;wire carryout;adder4 a1 ( carryin,x,y,sum,carryout);initial begin $monitor($time,"SUM=%d",sum); x = 4'b0000; y= 4'b0000;carryin = 1'b0; #20 x =4'b1111; y = 4'b1010; #40 x =4'b1011; y =4'b0110; #40 x =4'b1111; y=4'b1111; #50 $finish;endendmodule

Note: Simulation and synthesis of parallel adder uses a full adder in it’s module .Therefore, In simulation process it is necessary to compile full adder verilog file and parallel adder with test bench.In synthesis it is necessary to read_hdl file of full adder as well as parallel adder

Experiment 9: SERIAL ADDER



Verilog code for SERIAL ADDER

module serial_adder ( A,B, reset, clock, sum);input [7:0] A,B;input reset,clock;output [7:0] sum;reg [3:0] count;reg s,y,Y;wire [7:0] qa,qb,sum;wire run;parameter G=0,H=1;

shiftrne shift_A (A,reset,1'b1,1'b0,clock,qa);shiftrne shift_B (B,reset,1'b1,1'b0,clock,qb);shiftrne shift_sum (8'b0,reset,run,s,clock,sum);

//adder fsm //output and next state combinational circuitalways @(qa or qb or y) case (y) G: begin s = qa[0]^qb[0]; if (qa[0] & qb[0]) Y = H; else Y = G; end

H: begin s = qa[0] ~^qb[0]; if (~qa[0] & ~qb[0]) Y =G; else Y = H; end default : Y = G;

endcase

//sequential blockalways @(posedge clock) if (reset) y <= G; else y <= Y;



//control the shifting processalways @(posedge clock) if (reset) count = 8; else if (run) count = count - 1;

assign run=|count;

endmodule

TEST BENCH for SERIAL ADDER

module serial_adder_t ;reg [7:0] A,B;reg reset,clock;wire [7:0] sum ;

initial clock = 1'b0;

always #5 clock =~clock;

serial_adder s1 (A,B,reset,clock,sum);

initial begin reset = 1'b0;A = 8'b10101010; B = 8'b11111111; #20 reset = 1'b1; #20 reset = 1'b0; #150 reset = 1'b1; A = 8'b11110000 ; B = 8'b11110011; #20 reset = 1'b0;

#200 $finish;end

initial$monitor ($time, " SUM = %d ", sum);

Endmodule

Verilog code for SHIFT REGISTER



module shiftrne ( R,L,E,w,clock,q);

parameter n=8;input [n-1:0] R;input L,E,w,clock;output [n-1:0] q;reg [n-1:0] q;integer k;

always @(posedge clock) if (L) q <= R; else if (E) begin for (k=n-1;k>0;k=k-1) q[k-1] <= q[k]; q[n-1] <= w; end

endmodule

Note: Simulation and synthesis of serial adder uses a shift register in it’s module.Therefore,In simulation of Serial adder It is necessary to compile shift register verilog file and serial adder with test bench.In Synthesis of Serial adder it is necessary to read_hdl file for shift register as well as serial adder.



PART – B



3) PART B[1]: SCHEMATIC SIMULATION

PROCEDURE FOR CREATING THE SCHEMATIC SIMULATION

I. Commands to get into Cadence

1. Right Click and open the terminal window2. Type the following commands as follows and press enter.

i) csh ii) source cshrciii) ls – shows the directories – check for existence of cadence_analog_labs_613.If

not found inform the system admin else go to next stepiv) cd cadence_analog_labs_613v) virtuoso &

II. Procedure for Schematic simulation using Cadence1. Now two windows must open i)virtuoso/command interpreter window ii)”Whats New…”2. Close the 2nd window

3. Use 1st window i.e virtuoso window(CIW) for further processing.

i) Create a New Libraryii) Create Schematic Cell view.iii) Create the Symbol for schematic Cell view.iv) Create the test Cell view.v) Analog simulation by spectre

i) Procedure for Creating New Library.a. File –New – Library b. Name : Give name for ur library Ex: VLSILABc. Enable Attach to an existing technology library, Click OKd. Attach the library to the technology library gpdk180.Click OK

ii) Create Schematic Cell view.a. Go to 1st window i.e virtuoso(CIW)b. File-New-Cell viewc. Setup the new file form

Library: Select the one you a created.Cell : Give the experiment name Ex: InverterView: SchematicType: Schematic press OK



d. Add the required components from the libraries and make the connections.1. Go to instance fixed menu or use shortcut key “I” from keypad to go

instances2. Click on browse. This opens the library browser3. Now select the appropriate library for components like

Gpdk180 ----------------- nmos, pmosAnalog library ---------- Vdd, Gnd, Vcc, Vpulse, Vsin

4. Make the connections by using fixed narrow wire key5. Click Check and Save button

iii) Creating the Symbol for schematic Cell view

a. In the schematic window, executeCrate – Cell view – From Cell viewThe cell view from cell view window appears Check Lib Name, Cell Name, From View name must be schematic Press ok

b. Now Symbol generation form appears. Click Ok If No changes requiredc. A new window with with default symbol is created.d. Edit the symbol if you want to give actual symbol shape else continue.

i. Execute Create-Cell view-from cell viewii. Library Name and Cell Name must be same which you have used

for schematic. Press OKiii. Check for the position of pin side.Prss OKiv. Edit for the shape by Create-Shape-Choose required options to

edit.

iv) Creating the new test cell view

a. Go to CIW window, Execute File-New-Cell viewb. Setup the new file form

Library: Select the one you a created.Cell: Cell name must be different from the name used in schematic cell view. Ex: Inverter_testView: SchematicType: Schematic press OK

c. Follow the step 3(ii) d to make the required connections

v) Analog simulation by SPECTRE.



a. In test cell view window Launch – ADE L(Analog Design Environment)

b. Execute Setup—Simulation/directory/Host A new window opens c. Set the simulation window to spectre and click okd. Execute Setup-Model Library. Anew window opens, Check of gpdk.scs as

lib and section type as stat then press OK.e. Execute Analysis – Choose. A window opens.f. Select the type and set the specifications and press OKg. Execute Output s—to be plotted – Select on Schematich. Then Select the INPUT WIRE(Vin ) and OUTPUT WIRE(Vout) from your

test Schematic using mousei. Execute Simulation -- Net list and Run

Experiment 1(a): Inverter Schematic Cell View



Specifications: nmos NM0 W=2u L=.180U & NM1 W=2U L=.180UInput Pins Vdd,Vss,Vin,VbiasOutput pin Vout

Specifications: Vpulse V1 = 0 Vdd = 1.8 V2 = 1td = 0,tr=tf=1 n, ton= 10n ,T=20n

Simulation Settings



Setup for transient analysis:1. Stop time =

Setup for D.C analysis1. Component to be selected in schematic is_______for d.c analysis2. Start = -5 Stop = 5 resp.

Setup for A.C analysis

1. Turn on Frequency button2. In sweep range section – Start ____ stop ______3. Select point per decade = _____

Check enables and apply

Expected Waveform:

Transient analysis

DC Analysis

Experiment 2(a): Common source Amplifier schematic Cell view



The common-source (CS) amplifier may be viewed as a transconductance amplifier or as a voltage amplifier. As a transconductance amplifier, the input voltage is seen as modulating the current going to the load. As a voltage amplifier, input voltage modulates the amount of current flowing through the FET, changing the voltage across the output resistance according to Ohm's law. The easiest way to tell if a FET is common source is to examine where the signal enters, and leaves. The remaining terminal is what is known as "common". In this example, the signal enters the gate, and exits the drain. The only terminal remaining is the source. This is a common-source FET circuit.

Specifications: nmos PM0 W=50u L=1U Pmos NM0 W=10U L01UInput Pins Vdd,Vss,Vin,VbiasOutput pin Vout

Common source Amplifier schematic test Cellview

Specifications: Vsin a.c magnitude = 1 Vdd = 2.5 d.c voltage = 0 Vss = -2.5offset voltage = 0 Vbias = 2.5amplitude =5mfrequency =1K



Simulation Settings

Setup for transient analysis:2. Stop time = 5m

Setup for D.C analysis3. Component to be selected in schematic is Vsin for d.c analysis4. Start = -5 Stop = 5 resp.


4. Turn on Frequency button5. In sweep range section – Start 7 stop – 150 to 100M6. Select point per decade = 20




Expected Waveform:

Transient analysis

DC Analysis

AC Analysis- Frequency



Experiment 3(a): Common drain amplifier schematic Cell view

A common-drain amplifier, also known as a source follower, is one of three basic single-stage field effect transistor (FET) amplifier topologies, typically used as a voltage buffer. In this circuit the gate terminal of the transistor serves as the input, the source is the output, and the drain is common to both (input and output), hence its name. The analogous bipolar junction transistor circuit is the common-collector amplifier. In addition, this circuit is used to transform impedances. For example, the Thévenin resistance of a combination of a voltage follower driven by a voltage source with high Thévenin resistance is reduced to only the output resistance of the voltage follower, a small resistance. That resistance reduction makes the combination a more ideal voltage source. Conversely, a voltage follower inserted between a small load resistance and a driving stage presents an infinite load to the driving stage, an advantage in coupling a voltage signal to a small load.

Specifications: nmos NM0 W=50u L=1U & NM1 W=10U L=1UInput Pins Vdd,Vss,Vin,VbiasOutput pin Vout

Common drain amplifier test cellview

Specifications: Vsin a.c magnitude = 1 Vdd = 2.5 d.c voltage = 0 Vss = -2.5offset voltage = 0 Vbias = 2.5amplitude =5mfrequency =1K



Simulation Settings

Setup for transient analysis:1. Stop time = 5m

Setup for D.C analysis1. Component to be selected in schematic is Vsin for d.c analysis2. Start = -5 Stop = 5 resp.


1. Turn on Frequency button2. In sweep range section – Start 7 stop – 150 to 100M3. Select point per decade = 20




Expected Waveform:

Transient analysis

DC Analysis

AC Analysis- Frequency



Experiment 4(a): Differential Amplifier schematic Cell view

Specifications: nmos NM0&NM1 W=3u L=1U , NM2,NM3 4.5U L=1U

Pmos PM0 & PM1 W=15U L=1UInput Pins V1,V2,IdcOutput pin VoutBidrectional pins Vdd,Vss

Differential Amplifier schematic test Cellview

Specifications: Vsin a.c magnitude = 1 Vdd = 2.5 amplitude =5m Vss = -2.5frequency =1K Idc = d.c.current=30u



Simulation Settings






Expected Waveform:



Experiment 5(a) : OPAMP schematic Cell view

\Specifications: Diff_Amplifier From your library

Cs_amplifier From your libraryInput Pins Vinv,Vnoninv,Id.c,Vdd,VssOutput pin Vout

OPAMP schematic test Cell view

Specifications: Vsin a.c magnitude = 1 Vdd = 2.5 d.c voltage = 0 Vss = -2.5offset voltage = 0 Idc = d.c current=30 uamplitude =5mfrequency =1K



Simulation Settings






Expected Waveform:



Experiment 6(a) : R-2R DAC schematic Cell view

Table for component building: Lib Name Cell Name Propertiesgpdk180 polymer R=2K and 1Kanalog lib Idc,gnd idc=30uMy.Library op-amp symbol

D0,D1,D2,D3 –Input pins Vout-output pin Vdd and Gnd –Input pins

R-2R DAC Test Cellview



Table for component building:

Lib Name Cell Name Properties analog lib Vpulse V0: V1=0V V2=2 Total period(T)=10n Pulse width(Ton)=5n

V1: V1=0V V2=2 Total period(T)=20n Pulse width(Ton)=10n V2: V1=0V V2=2 Total period(T)=40n Pulse width(Ton)=20n V3: V1=0V V2=2 Total period(T)=80n Pulse width(Ton)=40n

Vdc,gnd Vdd=2 Vss=-2

My.Library R-2R DAC symbol

Simulation Settings








Output Waveform:

PART B[2]: LAYOUT DESIGNING 61 Bangalore Prepd. By,

Mahesh. A.A Dept. Electronics and Communication


I) Layout Design Rules

0A Minimum NBURIED width 1.0um

0B Minimum NBURIED space 1.0um

1A Minimum NWELL width 1.0um

1B Minimum NWELL space 1.0um

1C Minimum NBURIED enclosure of NWELL 0.3um

1D Minimum PWELL width 1.0um

1E Minimum PWELL space 1.0um

1F Minimum NBURIED enclosure of PWELL 0.3um

2A Minimum OXIDE width 0.4um

2B Minimum OXIDE space 0.3um

2C Minimum NWELL enclosure of OXIDE 0.5um

2D Minimum NWELL to OXIDE space 0.5um

3A Minimum NIMP width 0.4um

3B Minimum NIMP space 0.4um

3C Minimum NIMP enclosure of OXIDE 0.2um

3D Minimum NBURIED enclosure of NIMP 0.6um

4A Minimum PIMP width 0.4um

4B Minimum PIMP space 0.4um

4C Minimum PIMP enclosure of OXIDE 0.2um

4D Minimum NBURIED enclosure of PIMP 0.6um

4E PIMP and NIMP cannot overlap

5A Minimum POLY width 0.18um

5B Minimum POLY space 0.3um

5C Minimum POLY extension beyond OXIDE (poly endcap) 0.2um

5D Minimum OXIDE extensions beyond gate POLY 0.4um

5E Minimum Poly to OXIDE spacing 0.2um

6A Minimum and maximum width of CONT 0.2um

6B Minimum CONT space 0.2um



6C Minimum OXIDE enclosure of CONT 0.2um

6D Minimum POLY enclosure of CONT 0.2um

6E Minimum POLY to CONT space 0.2um

6F Minimum NIMP enclosure of CONT 0.2um

6G Minimum PIMP enclosure of CONT 0.2um

6H Minimum CONT to Oxide space 0.2um

7A Minimum METAL1 width 0.3um

7B Minimum METAL1 space 0.3um

7C Minimum METAL1 enclosure of CONT 0.1um

8A Minimum and maximum width of VIA1 0.2um

8B Minimum VIA1 space 0.3um

8C Minimum METAL1 enclosure of VIA1 0.1um










11D Minimum METAL3 enclosure of VIA2 for metal capacitor 0.1um

12A Minimum CAPMETAL width 0.5um

12B Minimum METAL2 enclosure of CAPMETAL 0.4um

12C Minimum CAPMETAL enclosure of VIA2 0.2um

12D Minimum CAPMETAL enclosure of METAL3 0.3um

13A Maximum distance from a source/drain OXIDE region to the nearest well tie 10um





















20A Minimum BONDPAD width 45.0um

20B Minimum BONDPAD space 10.0um

20C Minimum and Maximum METAL1 enclosure BONDPAD 3.0um

20D Minimum and Maximum METAL2 enclosure BONDPAD 3.0um

20E Minimum and Maximum METAL3 enclosure BONDPAD 3.0um

20F Minimum and Maximum METAL4 enclosure BONDPAD 3.0um

20G Minimum and Maximum METAL5 enclosure BONDPAD 3.0um

20H Minimum and Maximum METAL6 enclosure BONDPAD 3.0um

Some of the important design rules mentioned above are pictorially represented in next page.

(p.t.o)N WELL RULE



OXIDE RULE

N imp/ P imp RULES



Poly RULE

PMOS LAYOUT: (W/L) = (2um / .18 um )



The PMOS is designed with respect to the design rules mentioned. The PMOS is designed

with a respect to the W/L ratio.

W Width of channel Nimp

L Width of POLY1



Layout of PMOS: ( W/L ) = (2um/.18um)

NMOS LAYOUT : (W/L) = (2um / .18 um )



LAYOUT OF NMOS : (W/L) = ( 2um/.18um)



II ) LAYOUT GENERATION & TESTING PROCEDURE

1. Open the Inverter schematic window2. Launch → Lay out XL3. A window opens, Enable create New option, A New – cell view form open

set the cell Name: Inverter ( Same as Schematic )View Name : Layout and click OK.A LSW [ Layout schematic window] & blank Layout window opens.

4. In Layout window,Execute Connectivity – Generate – All from source.In the layout editor window, A Generate Layout form appears. In this form enable Labels options & Click OK.

5. Now, we can view the components and Area of silicon [boundary]. The Area defines that the required layout can be fitted in to that. There for try to restrict to this area.NOTE: As a beginner extend the height of area by maximum of 2 units.

6. Stretch the area by using stretch Key from edit window.7. Move the components in to specified area and arrange them at required positions properly.8. Press shift – F to observe the internal view of the NMOS & PMOS.9. Now Zoom the layout editor window and align the NMOS & PMOS exactly. [That is poly

of both MOS must match to avoid the DRC errors].10. Make the required connections by selecting the required material from LSW window like

poly, metal then create the required shapes by executing Create → Shape → Path / Rectangle

11. Once the required connection are made, the next step is to connect the required overlapping materials by using corresponding connectors (via)sEx: The input ‘A’ in inverter layout Input A - Contact made up of metal 1 Gate terminal shorted is poly.As input A is placed on poly, now these two different layers are connected by using corresponding connectors.That is M1 – POLY1 ViaThere for Execute Create – Via

In the Vias form, select the corresponding connector required and click Hide and the place on required position in layout by double click.

12. Finally save the layout.



13. Testing [Running DRC, ERC, LVS & RCX]

A) Running DRC( Design Rule Checker)

i) Execute Assura – Run DRC.The DRC form opensCheck:ii) Library: ? Cell: ? View: ? [Layout].

This should be same what you have setiii) Technology – gpdk 180.

Then click OK.iv) A progress form appears.[Don’t click on OK]v) When DRC finishes, a dialog box appears asking you if you want to view your

DRC results, and then click yes to view the results of this form.vi) If any DRC errors exist, a Error Layer window [ELW] appears. Open ELW

window and rectify the errors by selecting the errors one by one.vii) Then follow step (i) to (v) mentioned above unit you get a message as “ No

DRC errors found” then clck on close to terminate the DRC run.

B) Running LVS( Layout Vs Schematics) .i) Assura – LVS in Layout windowii) A Assura – Run LVS window opens.

Check:→Schematic Design SourceLib: Cell: View:→Layout Design SourceLib: Cell: View:

These should be have Schematic & Layout to be compared CLICK OK.iii) The LVS begins and progress. Form appears.iv) If schematic & Layout matches completely, you will get the form displaying

“Schematic and Layout Match”If Not matching, a form informs LVS completed successfully and asks if you want view the results of this run.CLICK Yes in the form.

v) The LVS debug form opens indicating the mismatches and you need to correct all these mismatches and Re – run the LVS.



C) Running RCX.i) Assura – Run RCX.ii) Assura RCX form opens.

Set the output type under setup tab as extracted View. [ It may be preset].CLICK OK.Under filtering tab of the form, Enter Power Nets as Vdd!, Vss! And Enter ground nets as gnd! Then Click OK for the form.

iii) RCX progress form appears, wait until it completes the process.iv) Whwn RXC complete, a dialog box appears, informs you that Assura RCX run

Completed Successfully.v) Go to CIW (Virtuso window)

File – open – av- extracted view form the corresponding library.Then, the av-extracted view window opens with parasitic components (RC). Observe the view by zooming

III) Creating Configuration Viewi) Creating Config View

a. Go to CIW window, Execute File-New-Cell viewb. Setup the new file form

Library: Select the one you a created.Cell: Cell name must be different from the name used in schematic cell view. Ex: Inverter_testView: ConfigType: Schematic press OKA Hierarchy Editor window and New Configuration Form opens

c. In the New Configuration form, Click on Use Templates present at the bottom of form. A use Templates window opens.

d. In Use Template form set Name: SPECTRE by scroll down button, then Click OK.

e. Now,In the New Configuration window Change Top Cell View: Schematics and Set the Library Link: BLANK, Then CLICK OK in New Configuration window. Now, Hierarchy Editor Window Opens.

f. In Hierarchy Editor Window, Press Table View tab and check cell building.g. In Hierarchy Editor Window, Press Tree View tab and check occurances.h. Press Recompute the Hierarchy iconi. Save the current configuration.j. Close the hierchy Editor window. Execute File – Close Window



IV) RUNNING circuit without parasites.

a. Go to CIW window and open (Inverter_test) Config view, Top cell view form opens.

b. Enable Yes and Yes in Top Cell View form c. Launch – ADE L(Analog Design Environment)d. Execute Setup—Simulation/directory/Host A new window opens e. Set the simulation window to spectre and click okf. Execute Setup-Model Library. Anew window opens, Check of gpdk.scs as

lib and section type as stat then press OK.g. Execute Analysis – Choose. A window opens.h. Select the type and set the specifications and press OKi. Execute Output s—to be plotted – Select on Schematicj. Then Select the INPUT WIRE(Vin ) and OUTPUT WIRE(Vout) from your

test Schematic using mousek. Execute Simulation -- Net list and Run

Propagation Delay CalculationAfter completing STEP (IV) ,A waveform window will be opened.

a. In the waveform window execute Tool – Calculator. A calculator window appears

b. Click on special function tab. A window with different functions open, In this select delay.

c. A addition form for calculation will be present to select and the parameters for delay calculation.

i. Place the curser in signal1 text box, Enable Wave button and enable the input Net(Vin) (Line) in the schematic window.

ii. Repeat above step for Signal 2.iii. Set threshold values w.r.t experiment ( Ex: For Inverter ; Threshold

Value 1 & Threshold Value 2 to 0.9,this directs the calculator to calculate the delay at 50% i.e at 0.9 volts( 1.8V/2)

iv. Click OK and observe the expression created in the calculator buffer.d. Click on the Evaluate the buffer icon to perform the calculation and note down

the valued returned after execution.e. Close the calculator window.



IV) RUNNING circuit with parasites.

a. Open the same hierarchy Editor window which is already set for config.b. Select the TREE VIEW tab,this will show the design hierarchy in tree format.c. CLICK right button on IO (lib name Inverter schematic) in TREE VIEW and

Select set instances view as av_extracted view.d. Press Recompute the Hierarchy icon, the configuration is now updated from

schematic to av_extracted viewe. Then,go output waveform window( analog design environment) and click

Netlist and RUNf. Observe the waveform with additional nets and parameters.g. Calculate the delay again and match with the previous one.

Now you can conclude how much delay is introduced by parasites by comparing delay with and without parasites and based on this we need to optimize the parasitic effect and reduce the delay due to parasites. This finally leads to an optimized layout



LSWWhat is LSW? It is a layout Vs Schematic window which consists of different layers used for layout.

The layers to drawn or traced has to be selected from the LSW window and the required type of shape has to be created by using the

Create Shape Select the required shapes.

The Shapes may be a Rectangle, Circle, Path so on.

Rectangle: This shape is chosen when the shape to be drawn is rectangular and but the size is not defined.

Path: This shape is chosen when the path to be drawn is with predefined with.

The drawn shapes must follow the design rules.



Experiment 1(b): Inverter layout



Experiment 2(b): Common Source layout

Experiment 3(b): Common Drain layout



Experiment 4(b): Differential Amplifier layout



Experiment 5(b): Operational Amplifier layout



4) VLSI Questions



Why don’t we use just one NMOS or PMOS transistor as a transmission gate? Because we can't get full voltage swing with only NMOS or PMOS .We have to use both of them together for that purpose. Why don’t we use just one NMOS or PMOS transistor as a transmission gate? nmos passes a good 0 and a degraded 1 , whereas pmos passes a good 1 and bad 0. for pass transistor, both voltage levels need to be passed and hence both nmos and pmos need to be used. What are set up time & hold time constraints? What do they signify? Setup time: Time before the active clock edge of the flip-flop, the input should be stable. If the signal changes state during this interval, the output of that flip-flop cannot be predictable (called metastable). Hold Time: The after the active clock edge of the flip-flop, the input should be stable. If the signal changes during this interval, the output of that flip-flop cannot be predictable (called metastable). Explain Clock Skew?

clock skew is the time difference between the arrival of active clock edge to different flip-flops’ of the same chip. Why is not NAND gate preferred over NOR gate for fabrication? NAND is a better gate for design than NOR because at the transistor level the mobility of electrons is normally three times that of holes compared to NOR and thus the NAND is a faster gate. Additionally, the gate-leakage in NAND structures is much lower. What is Body Effect? In general multiple MOS devices are made on a common substrate. As a result, the substrate voltage of all devices is normally equal. However while connecting the devices serially this may result in an increase in source-to-substrate voltage as we proceed vertically along the series chain (Vsb1=0, Vsb2 0).Which results Vth2>Vth1. Why is the substrate in NMOS connected to Ground and in PMOS to VDD? we try to reverse bias not the channel and the substrate but we try to maintain the drain, source junctions reverse biased with respect to the substrate so that we don’t loose our current into the substrate. What is the fundamental difference between a MOSFET and BJT ? In MOSFET, current flow is either due to electrons(n-channel MOS) or due to holes(p-channel MOS) - In BJT, we see current due to both the carriers.. electrons and holes. BJT is a current controlled device and MOSFET is a voltage controlled device

In CMOS technology, in digital design, why do we design the size of pmos to be higher than the nmos. What determines the size of pmos wrt nmos. Though this is a simple question try to list all the reasons possible?

In PMOS the carriers are holes whose mobility is less[ aprrox half ] than the electrons, the carriers in NMOS. That means PMOS is slower than an NMOS. In CMOS technology, nmos helps in pulling down the output to ground PMOS helps in pulling up the output to Vdd. If the sizes of PMOS and NMOS are the same, then PMOS takes long time to charge up the output node. If we have a larger PMOS than there will be more carriers to charge the node quickly and overcome the slow nature of PMOS . Basically we do all this to get equal rise and fall times for the output node. Why PMOS and NMOS are sized equally in a Transmission Gates?



In Transmission Gate, PMOS and NMOS aid each other rather competing with each other. That's the reason why we need not size them like in CMOS. In CMOS design we have NMOS and PMOS competing which is the reason we try to size them proportional to their mobility. What happens when the PMOS and NMOS are interchanged with one another in an inverter? If the source & drain also connected properly...it acts as a buffer. But suppose input is logic 1 O/P will be degraded 1 Similarly degraded 0 Why are pMOS transistor networks generally used to produce high signals, while nMOS networks are used to product low signals? This is because threshold voltage effect. A nMOS device cannot drive a full 1 or high and pMOS can’t drive full '0' or low. The maximum voltage level in nMOS and minimum voltage level in pMOS are limited by threshold voltage. Both nMOS and pMOS do not give rail to rail swing. What’s the difference between Testing & Verification? What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up? A latch up is the inadvertent creation of a low-impedance path between the power supply rails of an electronic component, triggering a parasitic structure(The parasitic structure is usually equivalent to a thyristor or SCR), which then acts as a short circuit, disrupting proper functioning of the part. Depending on the circuits involved, the amount of current flow produced by this mechanism can be large enough to result in permanent destruction of the device due to electrical over stress - EOS What is slack?

The slack is the time delay difference from the expected delay(1/clock) to the actual delay in a particular path. Slack may be +ve or -ve.

Difference between Synchronous and Asynchronous reset. What is DRC ?What is LVS ? what are the differences between SIMULATION and SYNTHESIS ?

Simulation <= verify your design. synthesis <= Check for your timing Simulation is used to verify the functionality of the circuit.. a)Functional Simulation: study of ckt's operation independent of timing parameters and gate delays. b) Timing Simulation :study including estimated delays, verify setup, hold and other timing requirements of devices like flip flops are met. Synthesis: One of the foremost in back end steps where by synthesizing is nothing but converting VHDL or VERILOG description to a set of primitives(equations as in CPLD) or components(as in FPGA'S)to fit into the target technology. Basically the synthesis tools convert the design description into equations or components.

FPGA vs ASIC Definitions FPGA: A Field-Programmable Gate Array (FPGA) is a semiconductor device containing programmable logic components called "logic blocks", and programmable interconnects. Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combinational functions such as decoders or mathematical functions. ASIC: An application-specific integrated circuit (ASIC) is an integrated circuit designed for a particular use, rather than intended for general-purpose use. Processors, RAM, ROM, etc are examples of ASICs.



Speed ASIC rules out FPGA in terms of speed. As ASIC are designed for a specific application they can be optimized to maximum, hence we can have high speed in ASIC designs. ASIC can have high speed clocks. Cost FPGAs are cost effective for small applications. But when it comes to complex and large volume designs (like 32-bit processors) ASIC products are cheaper. Size/Area FPGA are contains lots of LUTs, and routing channels which are connected via bit streams(program). As they are made for general purpose and because of re-usability. They are in-general larger designs than corresponding ASIC design. For example, LUT gives you both registered and non-register output, but if we require only non-registered output, then it’s a waste of having an extra circuitry. In this way ASIC will be smaller in size. Power FPGA designs consume more power than ASIC designs. As explained above the unwanted circuitry results wastage of power. FPGA won’t allow us to have better power optimization. When it comes to ASIC designs we can optimize them to the fullest. Time to Market

FPGA designs will still take less time, as the design cycle is small when compared to that of ASIC designs. No need of layouts, masks or other back-end processes. It’s very simple: Specifications -- HDL + simulations -- Synthesis -- Place and Route (along with static-analysis) -- Dump code onto FPGA and Verify. When it comes to ASIC we have to do floor planning and also advanced verification. The FPGA design flow eliminates the complex and time-consuming floor planning, place and route, timing analysis, and mask / re-spin stages of the project since the design logic is already synthesized to be placed onto an already verified, characterized FPGA device.

Type of Design ASIC can have mixed-signal designs, or only analog designs. But it is not possible to design those using FPGA chips. Customization ASIC has the upper hand when comes to the customization. The device can be fully customized as ASICs will be designed according to a given specification. Just imagine implementing a 32-bit processor on a FPGA!



Prototyping Because of re-usability of FPGAs, they are used as ASIC prototypes. ASIC design HDL code is first dumped onto a FPGA and tested for accurate results. Once the design is error free then it is taken for further steps. It’s clear that FPGA may be needed for designing an ASIC. Non Recurring Engineering/Expenses NRE refers to the one-time cost of researching, designing, and testing a new product, which is generally associated with ASICs. No such thing is associated with FPGA. Hence FPGA designs are cost effective. Simpler Design Cycle Due to software that handles much of the routing, placement, and timing, FPGA designs have smaller designed cycle than ASICs. More Predictable Project Cycle

Due to elimination of potential re-spins, wafer capacities, etc. FPGA designs have better project cycle. Tools Tools which are used for FPGA designs are relatively cheaper than ASIC designs. Re-Usability A single FPGA can be used for various applications, by simply reprogramming it (dumping new HDL code). By definition ASIC are application specific cannot be reused.


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