vlsi test structures for process characterization

7/30/2019 Vlsi Test Structures for process characterization

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VLSI TEST STRUCTURES FOR PROCESSCHARACTERIZATION

BY:SUMEET SAURAV

SHEET RESISTANCE AND

CONDUCTIVITY MEASUREMENT


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Outline

Introduction

Sheet Resistance Measurement

Four-Probe Resistivity Measurements with the Model

4200-SCS Van der Pauw Resistivity Measurement Method

Hall Effect Measurement

Contactless measurement of electrical conductivity of

semiconductor wafers using the reflection of millimeterwaves

Types of Test Structures

Process Test Structures 5/25/2013

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Introduction

Microelectronic test structures are typically included in

Integrated Circuit (IC) designs to enable measurementsof process or device parameters for characterization or

process control.

The major use of test structures is to extract device andprocess parameters at the end of the production line in

order to verify that the process has been successful .

If the parametric test results are satisfactory then the

product wafer can be passed on for functional testing.

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The main problem with the inclusion of test structures is

that they take up valuable space on a wafer which could

be occupied by product.

Test patterns can be introduced into a process either as

individual structures placed in the scribe channels

between the product die or as dropinswhich are

complete test structure chips.

Drop in test chips will replace one or more of the product

die on the wafer and their use must be traded off againstthe loss of product.

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Electrical test structures are connected to the test

equipment through metal pads (typically 80-120um

square) which can be contacted either with manual

probe needles moved by micromanipulators or throughthe use of a probe card.

A2xNprobe card can be used to probe any device on

the chip. While the use of the 2 x N type structure is

very good from the point of view of flexibility it doessuffer from increased testing times due to the extra

prober movement required within the chip.

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Uses of test structures Equipment Characterization

Reliability Evaluations

Defect Monitoring

Transistor Parameter Extraction and

Process Verification and Development.

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Outline Introduction Sheet Resistance Measurement


4200-SCS

Van der Pauw Resistivity Measurement Method



semiconductor wafers using the reflection ofmillimeter waves


Process Test Structures5/25/20137


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Resistivity

Resistivity is probably the most basic parameter for a

conductor or semiconductor material and it is denotedby the symbol with units of .

A bar of conducting material with uniform resistivity

is shown in the fig below and the resistance between

the electrodes is given by

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Derivation

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The expression for the Electric Field is

The voltage at point P at a distance r from the probe in

fig a, is then

For the configuration in Fig b the voltage is

the voltage at probe 2 is

And at probe3 it is


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For most four-point probes the probe spacing's are

equal. With s=s1=s2=s3,the above equation

reduces to


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Contactless method of resistivity

measurement

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Eddy current Method

The eddy current measurement technique is based

on the parallel resonant tank circuit of Fig below

The quality factor Q of such a circuit is reduced

when a conducting material is brought close to

the coil due to the power absorbed by the

conducting material.

The absorbed power Pa is


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One of the most common techniques used to

measure resistivity is the four-point probe(FPP)

method where four point contacts are made to thesurface of the material being measured.

Typical values for the tip spacing range from 0.5 to

1.5mm.5/25/201314


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If the sample being measured can be considered

semi-infinite (i.e. the thickness, width and length of

the sample are each much greater than the tapspacing) then the resistivity can be calculated using

However , this technique is commonly used to

measure samples which are not semi-infinite and in

that case a correction factor F is added to theequation to correct for the sample geometry .

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Sheet Resistance

When the thickness t of the conducting material is much

less than the tap spacing. In this case, the equation forresistivity can be reduced to

This will apply to a wafer coated with a thin film of

aluminium or a diffused or implanted conducting layer at

the surface

Because of the difficulty in measuring the thickness ofsuch a conducting layer they are often characterized by

their sheet resistance which is expressed in units of ohms

per square.

The sheet resistance is calculated from four-point probe5/25/201316


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Van der pauw structures

A more practical method of measuring the sheet

resistance of a thin film, given that the sample is toosmall for the FPP technique, is to use a van der Pauw

type test structure.

The method requires that the contacts be small, tending

towards point contacts and the sample material be

homogeneous in thickness and resistivity .

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If the sample is as shown below with the contacts A,B,C

and D then R(AB,CD) is defined as

If R(BC,DA) is defined similarly then

Which can be solved numerically to find

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If the sample is having 90 rotational symmetry and the

contacts are equally spaced around the boundary then

R(AB,CD)=R(BC,DA) and the formula reduces to

This is similar to equation for the resistivity extracted

with a four-point probe technique and can of course be

changed to an expression for sheet resistance by

dividing both sides by t.

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Al i f f V d V


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Alternative form of Van der Vauw

formula

Where f is the correction factor which is a function of the

ratio r=R(AB,CD)/R(BC,DA) and can be found by thenumerical solution of

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Greek Cross Structures One of the main sources of error in van der Pauw

measurements is that the contacts are non-ideal and

have a finite size.

Van der Pauw found that the effect can be reduced by

using a clover leaf shaped sample as shown

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These measurement techniques and structures were

developed for the measurement of the resistivity of large

discrete samples of semiconductor materials.

The next development in this field was the evolution of

structures which could be made using standard micro

fabrication techniques, and on the same scale as

microelectronic devices in order to measure the sheet

resistance of thin films or diffused layers.

The Greek cross sheet resistor is a special case of thefour-terminal van der Pauw structure which meets these

requirements .

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Although extraction of sheet resistance from an ideal

structure would only need one resistance measurement

in practice four measurements are required:

two at the zero-degreemeasurement position and

two at the ninety-degree orientation.

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and

These results are averaged together to get R(

+_I) which is used to calculate the sheetresistance with

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Where f is a correction factor for asymmetry in the

structure and is calculated using the formula given

below

Where r is given by

The asymmetry is quantified with the asymmetry factorFA which can be calculated from r using the relation

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Equipotential contours in a Greek cross

structure. The contour spacing is 50mV , running

from 1V at terminal A to 0V at terminal B.

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Equipotential contours in a box cross structure.

The contour spacing is 50mV ,running from 1V at

terminal A to 0V at terminal B

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Greek cross structures and variants such as the box

cross are widely used in the characterization of thin

film sheet resistances.

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Performing van der Pauw Sheet Resistance

Measurements Using the Keithley S530 Parametric Tester

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Outline

Introduction Sheet Resistance Measurement

Four-Probe Resistivity Measurements with the

Model 4200-SCS




semiconductor wafers using the reflection ofmillimeter waves




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Semiconductor Characterization

System

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Four Probe Resistivity Measurements


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Four-Probe Resistivity Measurements

with the Model 4200-SCS The Four-Point Collinear Probe Method

The two outer probes are used for sourcing current and

the two inner probes are used for measuring the resulting

voltage drop across the surface of the sample. The

volume resistivity is calculated as follows:

= volume resistivity (W-cm)

V = the measured voltage (volts)

I = the source current (amperes)

t = the sample thickness (cm)

k* = a correction factor based on the ratio of the probe to

wafer diameter and on the ratio of wafer thickness to5/25/201332


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Using the Model 4200-SCS to Make Four Point

Collinear Probe Measurements

The Model 4200-SCS can make four-point collinearprobe measurements using either three or four SMUs

(source- measure units).

When using three SMUs, all three SMUs are set to

Current Bias (voltmeter unit). However, one SMU will

source current and the other two will be used to

measure the voltage difference between the two innerprobes.

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SMU Designation for Four-Point

Collinear Probe Measurement

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SCS with the Four-Point Probe

Project

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Outline



4200-SCS








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Van der Pauw Resistivity

Measurement Method

This method is particularly useful for measuring very

small samples because geometric spacing of the

contacts is unimportant. Effects due to a samples

size, which is the approximate probe spacing, areirrelevant.

Using this method, the resistivity can be derived from

a total of eight measurements that are made aroundthe periphery of the sample.

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Conventions

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Once all the voltage measurements are taken, two

values of resistivity, A and B are derived as follows:

Where

A and B are volume resistivities in ohm-cm.

ts is the sample thickness in cm.

V1-V8 represents the voltage measured by the

voltmeter.I is the current through samples in ampers

fA and fB are the geometrical factors based on

sample symmetry

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They are related to the two resistance ratios QA and

QB as shown in the following equations (fA= fB= 1 for

perfect symmetr y).

QAand QB are calculated using the measured

voltages as follows:

Also, Q and f are related as follows:

Once AandB are known, the average resistivity

(AVG) can be determined as follows:

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SMU Configurations for van der


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SMU Configurations for van der

Pauw Measurements

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Screen Capture of van der Pauw Resistivity

Application on Model 4200-SCS

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Outline



4200-SCS







H ll V lt M t


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Hall Voltage Measurement

Hall effect measurements are important to

semiconductor material characterization because fromthe Hall voltage, the conductivity type, carrier density,

and mobility can be derived.

With a positive magnetic field, B, apply a current

between terminals 1 and 3, and measure the voltagedrop (V24+) between terminals 2 and 4. Reverse the

current and measure the voltage drop (V42+).

Next, apply current between terminals 2 and 4, and

measure the voltage drop (V13+) between terminals 1and 3. Reverse the current and measure the voltage

(V31+) again.

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Reverse the magnetic field, B, and repeat the

procedure again, measuring the four voltages: (V24

), ( V42), ( V13), and (V31).

From the eight Hall voltage measurements, the

average Hall coefficient can be calculated as follows:

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O RHC d RHD h b l l t d th


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Once RHC and RHD have been calculated, the average

Hall coefficient (RHAVG) can be determined as follows:

From the resistivity (AVG) and the Hall coefficient

(RHAVG), the mobility (H) can be calculated:

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D t i i C d ti it T


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Determining Conductivity Type

of a Semiconductor Material

There are several methods for determining

conductivity type.

The rectification method is used on high resistivity

material; the thermoelectric method is used on

low resistivity materials.

Both methods involve using a four-point collinear

probe, an AC current source, and a DC voltmeter

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The Rectification Method. This method involves determining the sign of the majority

carrier based on the polarity of a rectified AC signal at the

point of contact with the semiconductor material.

When the four-point collinear probe comes in contact with the wafer, a

metal semiconductor diode is created at the interface between each

probe and the wafer. An AC current is sourced between the first two

probes and a DC voltmeter is used to sense the polarity of the voltage

between probes 2 and 3. The metal-semiconductor Schottky diode at

probe 2 will be either forward- or reversed biased, depending on the

polarity of the current, as well as the conductivity type. As a result, the

voltmeter will read a positive voltage for p-type material and a negative

voltage for n-type material.

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Th Th l t i V lt M th d


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The Thermoelectric Voltage Method.

For highly doped (low resistivity) materials, the voltage

developed between probes 2 and 3 becomes too smalland the rectification mode no longer works well.

For this case, the thermoelectric voltage method

determines the conductivity type by the polarity of the

thermoelectric (or Seebeck) voltage that is generated bya temperature gradient on the material.

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With this method an AC current flows between probes 1 and


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With this method, an AC current flows between probes 1 and2 and causes joule heating of the semiconductor.

The Seebeck voltage is generated between probes 3 and 4by the diffusion of thermally generated carriers from the hotregion of the material to the cold region.

This diffusion creates a non-equilibrium carrier concentrationin the cold region, which generates an electric field, opposingfurther diffusion.

This diffusion of carriers from the hot probe (probe 3) to thecold probe (probe 4) continues until the generated electricfield is sufficient to

overcome the tendency of the carriers to diffuse.

For example, in p-type material, the thermally generatedholes diffuse to the cold probe, building up a positive spacecharge, which prevents

further diffusion.

As a result, the cold probe (4) is more positive than the hot

probe. Thus, for p-type material the voltmeter will read a5/25/201350

Conductivity Type using wafer flat


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Conductivity Type using wafer flatlocation

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The semiconductor conductivity type can bedetermined by wafer flat location, thermal emf,

rectification, optically, and Hall effect


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Outline



4200-SCS



Contactless measurement of electrical

conductivity of semiconductor wafers using thereflection of millimeter waves


Process Test Structures

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A contactless method to measure the conductivity of


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y

semiconductor wafers is the coil method, which

measures small impedance changes of an inductive coil

placed in close proximity to a sample

Although the conductance of the sample affects the

magnitude of induced eddy currents and thus the

effective impedance of the coil, to determine the

conductivity of the sample, the thickness of the sample

has to be measured by another technique

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I thi i t hi h f illi t


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In this experiment, a high-frequency millimeter wave

was used in order to ensure the transmitted millimeter

wave attenuated rapidly inside the wafer, so that the

reflection from the bottom surface of the wafer can beneglected.

The millimeter wave response signal is not affected by

the thickness of the wafer

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The principle of the technique described here is based on


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The principle of the technique described here is based onthe interaction of the millimeter wave with the semiconductorwafer.

When a millimeter wave signal irradiates a semiconductorwafer, reflections occur at both the top and bottom surfacesof the wafer due to the discontinuity of medium.

The millimeter wave signal reflected from the wafer will bethe sum of the two components reflected from the top and

bottom surfaces. Since the reflected component from the bottom surface

varies with the thickness of the wafer, generally thisthickness will affect the measurement results.

However, since the attenuation of the millimeter waveincreases rapidly

inside the wafer with increasing operating frequency, thereflected component from the bottom surface can bedecreased to a negligible value by using a high operating

frequency. 5/25/201355

Working


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Working

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A network analyzer was used to generate a millimeterwave signal fed to a focusing sensor and to measure

both the amplitude and phase of the reflectioncoefficient.

A millimeter wave of 110 GHz was used.

Under this condition, the reflection from the bottomsurface was calculated to be four orders of magnitudesmaller than that from the top surface of the wafer for a

silicon wafer having a thickness of 500 mm andconductivity of 200 S/m.

A computer was used to control the stage and to

recode the data measured by the network analyzer.


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Where

and

Here the reflection coefficient

intrinsic impedance of the semiconductor

wafer

intrinsic impedance of the semiconductor

of free space For nonmagnetic materials, considering and

using the above equations, the reflection coefficient

can finally be written as5/25/2013

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Outline



4200-SCS







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A Test Structures for Device


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A. Test Structures for Device

Parameter Extraction

NMOS W/L=4/16

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A T t St t f D i


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A. Test Structures for Device


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B T t St t f P


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B. Test Structures for Process


These structures are used to evaluate theuniformity of the semiconductor doping process,interface quality, quality of etching.

Examples:-

Cross-bridge sheet resistorContact resistors for metal-to-silicon or metal-to

polysilicon contact resistance measurement.

MOS Capacitors for oxide thickness, interface

state measurements, flat band voltage, dopantdensity measurement

Diodes for leakage current measurement.

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B T t St t f P


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B. Test Structures for Process


Van der Pauw Method

R=(V2V1)/(I 1I 2)

W=RS L I* /V*

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C T t St t f L t R l


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C. Test Structures for Layout Rule

Checking

Used to evaluate those geometrical circuit layoutfeatures that form the layout rules.

Examples are:

Cross-bridge sheet resistor for line width

measurements.

Alignment resistor or a comb resistor to evaluate

feature to feature spacing.

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C Test Str ct res for La o t R le


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C. Test Structures for Layout Rule

Checking

As, we increase the contact size, yield increases.

Each Sub array is tested for

open circuit fault condition.5/25/201364

D Test Structures for Random Fault


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D. Test Structures for Random Fault

Analysis

Used to evaluate the physical fault in thesemiconductor material system.

Knowledge of faults is necessary for logic design,

logic simulation and test vector generation.

Test structure arrays are constructed out ofseries, parallel, or addressable arrays of

elements.

Examples:

Serpentine resistor for metal step coverage

Comb resistor for quality of etching process.

MOS capacitor for oxide integrity(pinhole)

measurements5/25/201365


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Metal Step-Coverage Resistor

Used to evaluate breaks in the metallization atoxide steps.

In order to identify unintended failures(probe pad,

failure of the photomasking process) ,

addressable MOSFET array was developed topinpoint the location of physical failure.

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E Test Structures for Circuit


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E. Test Structures for Circuit


These structures are used to extract parametersthat characterize ac, dc and transient process.

Examples:

Inverters for measuring the threshold , gain and

noise immunity

Ring Oscillators for measuring the frequency and

stage delay

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E Test Structures for Circuit


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E. Test Structures for Circuit


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Outline



4200-SCS








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PROCESS TEST STRUCTURES

Purpose Extract very specific electrical information about

the process.

Identify process problems.

Improve process.

Sheet resistance

Contact Chain

Contact Resistance Continuity and Isolation

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Sheet Resistance

4-Point Probe Structure

Van der Pauw Structure

Force a current and measure the resulting voltage.

4-point probe vs. van der Pauw

Compare measured results with simulated and hand-calculated values.

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Contact Chain

Test contact integrity.

Verify linear relationship between chain length

and resistance (I-V sweep).

Not a good structure to measure contact

resistance5/25/201372

One contact on source and drain (no Kelvin)


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One contact on source and drain (no Kelvin)

One contact on source and two contacts on drain

(Kelvin-Drain)

Two contacts on source and one on drain(Kelvin-

Source)

And two contacts on source and drain (Full Kelvin)

C t t R i t


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Contact Resistance Measure resistance across contact interface Ohmic

or Schottky behavior?

Force a vertical current through contact and measure

voltage above and below.

Examine dependences on material and contact size.

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Continuity and Isolation

Complementary tests to detect unwanted openand short circuits.

Common sources of failure:

incomplete etch stringers

overetch

material failure (breakage) over

aggressive topography

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vlsi test structures for process characterization

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