JYOTHISHMATHI INISTITUTE OF TECHNOLOGY & SCIENCE

JYOTHISHMATHI INSTITUTE OF TECHNOLOGY & SCIENCE

NUSTULAPUR, KARIMNAGAR

M. Tech. (VLSI DESIGN, EMBEDDED SYSTEM, DIGITAL SYSTEMS AND COMPUTER ELECTRONICS)I Semester 2015VLSI TECHNOLOGY AND DESIGNII MID EXAMINATIONS - MARCH 2015

Time: 2 Hours Max. Marks: 40

PART A ( Compulsory) 4 x 4 = 16 MarksQ1) a) Explain the single row layout design for combinational logic networks.

b) Write short notes on latches and flip flops.

c) Explain the power optimization in combinational circuits.

d) Explain test methods for sequential circuits.

PART B

Note: Answer Any THREE Questions

3 x 8 = 24 Marks All Questions carry Equal Marks

Q2) Explain different types of simulation.

Q3) Explain the combinational logic testing with an example.

Q4) Draw the stick and layout diagram of dynamic latch .

Q5) Explain the floor planning methods in detail.

Q6) Explain the I/O Architecture for off-chip connections.

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