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Review of MOST

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L

W

tox

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Threshold voltage

ox

SiA

FSBFTT

CqN

VVV

2

220

Bodyeffect

coefficient

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Body effect

VT0

VSB (V)

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MOS transistor characteristics

Linear I-V Equation for VDS < VGS - VT

221

DSDSTGSoxnD VVVV

L

WCI

Saturation I-V Equation for VDS > VGS - VT

ID = n Cox (W/L) (VGSVT)

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Channel Length Modulation

As VDS is increased, pinch-off point moves closer to

source - Effective channel length becomes shorter -

Current increases due to shorter channel

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Summary: MOS I-V

Drain voltage VDS

DraincurrentIDS

VGS1

VGS2

VGS3

Linear

Saturation

without

channel-lengthmodulation

withchannel-

length

modulation

VDS = VGS-VT

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MOS Energy Band Diagram

qMEC

EiEFp

EV

qSi

EC,oxide

EFmoxidebandgap

8evMetal

p-type Si

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EFpEV

EC

Bands must bend for Fermi levels to line up - Part of

voltage drop occurs across oxide, rest occurs next to O-S

interface - Amount of bending is equal to work function

difference: qM - qSi

Ei

EFm

qFqS

F = Fermipotential in bulk

S = surfacepotential

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Definition of Inversion

Surface potential is same as F, but of different sign

EV

EFp

Ei

EC

qFqS = -qF

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ox

ox

ox

BFFBT

C

Q

C

QVV 00 2

VFB = m - Si

FSiAB qNQ 220

Qox = qNox

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MOS capacitances

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Oxide Capacitance

Gate to Source overlap

Gate to Drain overlap

Gate to Channel/Bulk

Junction Capacitance

Source to Bulk junction

Drain to Bulk junction

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Oxide capacitances - overlap

Gate electrode overlaps source and drain

LD is overlap length on each side

source drain

LD

DoxGDOGSO WLCCC

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Oxide capacitancesgate voltage & channel charge

Gate-to-source: Cgs

Gate-to-drain: Cgd

Gate-to-bulk: Cgb

At Cutoff - No channel links surface to source and drain.Hence, Cgs = Cgd = 0,

Cgb is approximated as Cgb = CoxWL

source drainCgb

CgdCgs

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Linear mode - Channel spans from S to D - Capacitance

split approximately equally between S and D

WLCC oxGS2

1 WLCC oxGD

2

1

0GBCInversion layer shields substrate from gate field.

Saturation mode - Channel is pinched off:

0GDC 0GBC WLCC oxGS 3

2

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Oxide capacitances

VGS

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Junction Capacitance

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P-N Junction Capacitance

Zero-bias cap/area =ad

adSi

j NN

NN

V

q

C 00 2

m

j

j

V

V

ACC

0

0

1General form:

Vo is the built-in junction potential

m is the grading coefficient

= for abrupt junction, = 1/3 for linearly graded junction

(A is the junction area)

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Junction Capacitance

Junction with substrate

Bottom area = W * LS (length of drain/source)

Side facing channel: area = W * Xj

Total cap = Cj

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Junction Capacitance

Junction with sidewalls

Channel-stop implant - p+

Perimeter = 2LS + W

Area = P * Xj _Total cap = Cjsw

Total junction cap C = Cj + Cjsw

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Linearizing the Junction Capacitance

Replace non-linear capacitance by a large-signal

equivalent linear capacitance which displaces equal

charge over voltage swing of interest

Reverse bias across the junction is assumed to change

from V1 to V2

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The equivalent linear cap is obtained by integrating

Cj(V) between V1 and V2, where Cj(V) is given by:

m

j

j

VV

ACC

0

0

1

0

1

0

1

1

0

2

12

0011

1jeq

mm

j

eq CAKV

V

V

V

mVV

VACC

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1020

12

02VVVV

VV

VK

eq

(for m = )

00)( jsweqswjjeqjdb CKPXCKWXWLC s

0 < Keq < 1

0

1

0

1

1

0

2

12

0011

1jeq

mm

j

eq CAKV

V

V

V

mVV

VACC

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Electrostatic Discharge (ESD)

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The thin and, therefore, very vulnerable gate oxide of the

MOST makes protection against destruction as a result

of electrostatic discharges, essential. The protective

precaution that was taken initially, and which is still the

best method, is the integration of clamping diodes, which

limit the dangerous voltages and conduct excess currents

into regions of the circuit that are safe. The safe regions

consist primarily of the supply-voltage connections.

ESD-Protection Circuits

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In the simplest case, the protection circuits consist of

diodes that are oriented to be blocking in normal

operation, and are situated between the connection to the

component to be protected and the supply voltage lines

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The diode approach can be made to work better by a

series resistor added in front of the diodes to limit the

magnitude of the ESD current and a bulk capacitance

added across the power supply rails.

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To tolerate even higher energy levels, and to protect the

more sensitive parts of a circuit, two-stage protection

circuits frequently are used at the inputs. With this

arrangement, the coarse protection conducts away the

higher energy levels.

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Diode D1 protects against negative voltages .

Positive voltages are first limited by transistor Q1, which begins to

conduct as soon as the input voltage (Vin > Vdd + 0.7 V) allows

current to flow through resistor R1. If the input voltage increases

further, at about 22 V to 26 V, the thick-oxide MOS field-effect

transistor Q2 conducts. Q2 provides additional base current to the

base of transistor Q1. In this way, the energy in the interfering

pulse is conducted away reliably.

The fine protection circuitry, which should protect the next device

(primarily the gate oxide of the transistors) from excessive

voltages, consists of resistor R2 and Zener diode D2/D3.

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Power supply noise

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Voltage drops across parasitics cause variation in the

voltage of a single supply ( VDD or GND) from one point

in the system

If signal is referenced to local supply, this variation

results in additive voltage noise

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Latch-up

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Isolation of the individual diodes, transistors, and capacitors

from each other in an IC is achieved by reverse-biased P-N

junctions.

During the development of the circuit, precautions are taken

to ensure that these junctions always are reliably blocking

under the conditions that can be expected in the application.

However, these P-N junctions form N-P-N and P-N-P

structures with other adjacent junctions.

The result of this is parasitic npn or pnp transistors, which

can be undesirably activated.

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The current gain of these transistors is usually very

small ( < 1). As a result, considerable input current is

usually necessary to activate these transistors.

With sensitive analog circuits, interference and other

undesirable effects can occur.

Also, the transit frequency of these transistors is

comparatively low (fT ~ 1 MHz), which means that very

short pulses are not able to turn on such transistors.

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Here, the N-doped regions for source and drain of the N-channel

transistor and the cathodes of the clamping diodes have been

diffused into a P-doped substrate. The substrate is connected to the

most negative point in the circuit, usually the ground connection

(GND).

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In normal operation, the N-doped regions have a voltage that

is more positive than the ground connection. In this way,

these P-N junctions are blocking.

The substrate now forms the base of a parasitic npn

transistor, while all N-doped regionsthat is, the drain and

source of the N-channel transistor and cathode of the

clamping diodesfunction as emitters.

The collector belonging to this transistor forms the well in

which the complementary P-channel transistor is located.

The latter, with its connections, forms a parasitic pnp

transistor.

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The npn and pnp transistors form a

thyristor. The anode and cathode of

this thyristor are connected to thesupply voltage of the IC, while all

other pointsinputs and outputs

function as the gate of the thyristor.As long as the voltages on the latter

connections stay more positive than

the ground connection and more

negative than VCC, correct operation

occurs. The base-emitter diodes are

blocking.

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If there is a voltage at the input or output that is more positive

than the supply voltage, or more negative than the ground

connection , current flows into the gate of the thyristor.

If the amplitude and duration of the current are sufficient, the

thyristor is triggered.

With lines of several meters in length and overshoots of

correspondingly longer duration, the probability that the

thyristor might be triggered must be taken into account.This applies at the interfaces with the outside world;

unacceptable over-voltages also often occur at this point.

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An electrostatic discharge can trigger the parasitic

thyristor.

Even if the electrostatic discharges have a duration of

only a few tens of nanoseconds, when this happens, the

complete chip may be flooded with charge carriers,

which then flow away slowly, resulting in

the triggering of the thyristor.

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Latch-up was a major problem in early CMOS

processes

Now, latch-up is mainly an issue for I/O circuits with

high current demands and possibly noisy voltages

G d Ri i CMOS Ci it

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Guard Rings in a CMOS Circuit

These guard rings form additional collectors for the parasitic

transistors. Such collectors are connected either to the positive or

negative supply-voltage connection of the IC

i i i

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These additional collectors are placed considerably closer to

the base-emitter region of the transistor in question than the

corresponding connections of the complementary transistor.

As a result, the charge carriers injected into one of the two

transistors is diverted largely via these auxiliary collectors to

the positive or negative supply-voltage connection.

These precautions do not completely eliminate the

questionable thyristor.

However, the thyristors sensitivity is reduced to such an extent

that, under normal operating conditions, there should be little