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Kizilyalli, I., et al. "Channel Hot Electron Degradation-Delay in MOS Transistors Due to Deuterium Anneal"The VLSI Handbook.

Ed. Wai-Kai Chen

Boca Raton: CRC Press LLC, 2000

© 2000 by CRC PRESS LLC

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13Channel Hot ElectronDegradation-Delay in

MOS Transistors Due toDeuterium Anneal

13.1 Introduction 13.2 Post-Metal Forming Gas Anneals

in Integrated Circuits13.3 Impact of Hot Electron Effects

on CMOS Development13.4 The Hydrogen/Deuterium Isotope

Effect and CMOS Manufacturing13.5 Summary

13.1 Introduction

Hydrogen-related degradation by hot electrons in MOS transistors has been long known and is welldocumented.1 It has recently been discovered that the degradation exhibits a giant isotope effect if hydrogen is substituted by deuterium.2–4 The isotope effect can delay the channel hot-electron degradationby factors of 10 to 100 and, with the current definition of lifetime, even much beyond that. It thereforemust be an effect different to the known kinetic isotope effect and the standard changes in reactionvelocity of a factor of three or so when hydrogen is substituted by deuterium.

Deuterium is a stable and abundantly available isotope of hydrogen. It is contained at a level largerthan 10–4 in all natural water sources. Its mass is roughly twice that of hydrogen, while all its electronic

energy levels and the related chemistry are identical to that of hydrogen.The difference in channel hot-electron degradation and lifetime must therefore be due to the mass

difference. There are several possible explanations of the giant isotope effect in degradation.4 Themost probable explanation at low supply voltages (VDD < 3.3 V) is the one first advanced in Ref. 5.This explanation concerns the dynamics of hydrogen (deuterium) desorption from an Si-H (Si-D)bond at the silicon–silicon dioxide interface under extreme non-equilibrium conditions — which isthe central cause of the particular degradation discussed here. There are other forms of degradationknown that show no, or a much lesser, isotope effect and are not discussed here. According to Ref 5,the heated electrons (with a typical energy of several electron volts) excite local vibrations of theSi–H bond. These vibrations have a very long lifetime of the order of nanoseconds or longer because

the vibrational energy of the Si–H is mismatched to the bulk vibrations in both silicon and silicondioxide. Therefore, a high probability exists that other hot electrons will collide with the Si–H andcause further vibrational excitation until, finally, desorption is accomplished. One vibrational mode

Isik C. KizilyalliLucent Bell Laboratories

Karl HessUniversity of Illinois at Urbana-

Champaign

Joseph W. LydingUniversity of Illinois at Urbana-

Champaign

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of Si–D, on the other hand, virtually matches a bulk silicon vibrational energy. Therefore, the localSi–D vibrations are short lived and it is much less likely that Si–D is excited so much that deuteriumwill desorb. The basic science of these processes has meanwhile been investigated (e.g., by scanningtunneling microscopy) and is consistent with the above description.4 Similar desorption processesare known from photochemistry, where the energy is provided by photons, and the new aspect hereis only the energy supply by the channel electrons and the extent of the isotope effect due to thespecial interface properties. While these considerations apply only under extreme nonequilibriumconditions, there are also in-equilibrium isotopic differences between the Si–H and Si–D bond, againdue to their vibrational differences.

The question that appears under the initial equilibrium conditions, before the degradation occurs, isthe following. Since many processing steps in MOS technology introduce hydrogen in one form oranother, and since hydrogen densities in the silicon dioxide will be of the order of 10 18 cm–3 whetherdesired or not, how can the hydrogen be effectively replaced by deuterium? An elementary proof 6 showsthat the equilibrium population of the silicon bond by H or D also depends on the vibrational properties.Because of the higher vibrational energy of some of the Si-H vibrational modes (compared to deuterium),

hydrogen is less likely to saturate the bond. In fact, if H and D are present at the same density at theinterface, then (around the usual anneal temperature of 425°C) the deuterium is about 10 times morelikely to populate the silicon bond than hydrogen.6

From these facts, it is evident that a relatively simple substitution of hydrogen by deuterium can leadto very beneficial delays of hot-electron degradation. In the following, we first describe the necessity toanneal the silicon–silicon dioxide interface with H or D; then we describe the advantages of D for hotelectron degradation and the introduction of D by post-metal anneal procedures. Finally, we describeconfirmations and extensions to more complex introductions of D.

13.2 Post-Metal Forming Gas Anneals in Integrated Circuits

Low-temperature post-metal anneals (350–450°C) in hydrogen ambients have been successfully used inMOS fabrication technologies to passivate the silicon dangling bonds and consequently to reduce theSi/SiO2 interface trap charge density.7–11 This treatment is imperative from a fabrication standpoint sincesilicon dangling bonds at the Si/SiO2 interface are electrically active and lead to the reduction of channelconductance and also result in deviations from the ideal capacitance–voltage characteristics. Electronspin resonance (ESR) measurements performed in conjunction with deep-level transient spectroscopy (DLTS) and capacitance–voltage (C-V) measurements have elucidated the role of hydrogen in this defectannihilation process. The passivation process is described by the equation

Pb + H2 " PbH + H (13.1)

where PbH is the passivated dangling bond. These measurements indicate that for the oxides grown onSi-<111>, the density of the interface trap states in the middle of the forbidden gap decreases from1011–1012 cm–2 eV–1 to about 1010 cm–2 eV–1 after the post-metal anneal process step. The Si-<100>/SiO2

material system, which is technologically more significant, exhibits the same qualitative behavior. Thenecessity of post-metallization anneal processing for CMOS technologies is demonstrated in Figs. 13.1and 13.2 where the measured NMOS threshold voltage (Vth) and transconductance (g sub m) distribu-tions of a wafer annealed in forming gas (10% H2) is compared with an untreated wafer. The high meanvalue and variation of the threshold voltage and reduced channel mobility across the untreated wafer isa clear indication of the unacceptable levels of interface trap density for CMOS circuit operation andstability. As described above, MOS transistors under bias can degrade as a result of channel hot (largekinetic energy) carriers (electrons and holes) stimulating the desorption of the hydrogen that is passi-vating the dangling bonds at the Si/SiO2 interface. These concerns are exacerbated with the ever-ongoingscaling efforts for high-performance transistors and added dielectric/metallization (and hence plasmaprocess damage) layers in integrated circuits.

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FIGURE 13.1 Histogram demonstrating the effects of hydrogen anneals on the threshold voltage V th of NMOStransistors.

FIGURE 13.2 Same as Fig. 13.1 but for the transconductance gm.

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13.3 Impact of Hot Electron Effects on CMOS Development

The current industry practice for evaluating the intrinsic hot carrier related reliability of a MOS transistorinvolves two distinct accelerated electrical stress test methodologies (including certain intermediatemethodologies). Although it is unlikely that the physical mechanisms responsible for gate oxide wear-out are identical in each of these cases, hydrogen appears to play some role in both modes of degradation.In the first stress configuration, the Si/SiO2 system is degraded via large electrical fields across the gateoxide (e.g., |VG|>>VD).12 Threshold voltage shifts in MOS capacitor structures are observed. The damageinduced in this degradation mode is due to both charge trapping within the oxide and the creation of Si/SiO2 interface trap states. Our initial studies have not identified a clear isotope effect for this mode of stress test. In this article, only the second stress configuration, namely the channel hot carrier aging of

NMOS transistors, where we have discovered the large isotope effect, is discussed . In this mode of accelerated stress, threshold voltage instability and channel transconductance degradation in MOStransistors13 is induced with the aid of hot carriers (electrons and holes with large kinetic energy) usingthe source-drain electric field. That is, the Si/SiO2 interface is degraded by hot carriers that are traversing

the device while they gain kinetic energy from the source-drain electric field. The device is biased tomaximize the substrate current (e.g., VG # 1/2VD). The transistor aging is accelerated by stressing thedevice using a drain voltage (VD) which is much larger than the intended operating voltage. The hotcarrier lifetime of the transistor is estimated by extrapolating the accelerated stress test results to operatingvoltage (peak substrate current specification) conditions. DC, AC, or pulsed DC waveforms are mostcommonly used. This mode of accelerated stress tests performed on NMOS transistors typically resultsin localized oxide damage, which has been identified as Si/SiO2 interface trap states.14,15 The asymmetry of the current–voltage characteristics under source-drain reversal indicates that the damaged region islocated near the drain end of the transistor where the electric fields are the largest due to the the pinch-off effect. Moreover, it has been suggested that the generation of the interface trap states is due to hotcarrier-stimulated hydrogen desorption and depassivation of the silicon dangling bonds. Channel hot-carrier degradation in MOS transistors manifests itself in the form of threshold voltage (V th)) instability,transconductance (gm = dIDS/dVGS) degradation, and a change in the subthreshold slope (S I = d lnIDS

/dVGS at VGS < Vth) over time.Various technological advances have been made to address the problem of MOS transistor degradation

due to channel hot carriers. Most significant and lasting progress in fabrication technology to alleviate thechannel hot carrier problem has been the development of lightly doped source-drain (LDD) and gatesidewall spacer processes.15–17 The lightly doped drain region is used to reduce the strength of the electricfield at the gate-end of the drain. Such advances have been integrated in all submicron CMOS technologiesat the cost of added process complexity and intricate device design.18 Unfortunately, processing requirementsfor good short channel behavior and high performance, namely, shallow source-drain junctions, reduced

overlap capacitance, and low source-access resistance, are all at odds with hot carrier immune device design.A reasonable argument (now it appears that this was merely wishful thinking) had been that the hot

carrier degradation effect can be scaled away by reducing the supply voltage (constant field scaling).However, this does not appear to be the case since device feature size scaling accompanies supply voltagescaling in VLSI CMOS technologies to achieve improved performance and increased packing density.Gate oxide thickness is also reduced to maintain the device current density at low supply voltage operation.Takeda et al. have observed device degradation in a no-LDD NMOS transistor structure with gate lengthsof 0.3 $m at 2.5 V.19 Chung et al. observed hot carrier degradation for a 0.15-$m gate length transistor(with no LDD regions) at 1.8 V.20 Current state-of-the-art high-performance 1.5- and 1.8-V sub-0.18-$m CMOS technology with good quality gate oxide exhibits hot carrier degradation effects and requiresprecise drain engineering.21,22 Circuit solutions to alleviate hot carrier degradation effects in transistors,although proposed, involve further circuit design and layout complications.23 Hot carrier-induced tran-sistor degradation will continue to be a major roadblock for satisfying market demand for high-perfor-mance CMOS circuits such as the Lucent-DSP shown in Fig. 13.3 with transistor gate lengths phase-shifted down to 0.1 $m and operated at a large range of supply voltages (1.0 to 1.8 V).

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FIGURE 13.3 High-performance CMOS circuit with 0.1-$m gate length operated in a range of 1.0 V to 1.8 V of supply vo

© 2000 by CRC Press LLC

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13.4 The Hydrogen/Deuterium Isotope Effect and CMOSManufacturing

As noted above, the major reliability limitation for the miniaturization CMOS technologies is the NMOS

transistor hot carrier lifetime. A breakthrough in integrated circuit manufacturing is needed where reliableCMOS scaling is enabled by eliminating the undesirable effects of channel hot carriers. The gianthydrogen/deuterium isotope effect that has been discovered and reported by Lyding, Hess, and Kizilyalli2,3

in NMOS transistors is the extremely significant increase in time-dependent channel hot carrier transistor(reliability) lifetime in devices that have been annealed with deuterium instead of hydrogen, as shownin Figs. 13.4 and 13.5. In the fabrication sequence, deuterium is introduced, instead of hydrogen, to theSi/SiO2 interface via a low-temperature (400–450°C) post-metallization anneal process. Figure 13.6 showsthe transfer characteristics of uncapped NMOS and PMOS transistors annealed in deuterium and hydro-gen ambients at 400°C and 1 hour. Prior to hot electron stress, transistors annealed in either ambientare electrically identical. This results in indistinguishable device function prior to hot carrier stress.Indistinguishable device function prior to hot carrier stress is also demonstrated in two experiments

shown in Table 13.1. This is an expected result since the chemistry of deuterium and hydrogen is virtually identical. These results prove that deuterium and hydrogen are equally effective in reducing the interfacetrap charge density which results in equivalent device function. Deuterium can be substituted for hydro-gen (at least in post-metal anneal processes) in semiconductor manufacturing.

Although devices annealed either in deuterium or hydrogen appear to be identical in pre-stresselectrical tests, they exhibit markedly different degradation dynamics. The observed improvement in thedegradation rates (lifetimes) in the transistors is a result of the large difference in the desorption ratesof the two isotopes, as described in the introduction and in detail in Refs. 4 and 5.

FIGURE 13.4 Transconductance channel hot-electron accelerated stress degradation with hydrogen and deuteriumanneal and a significant degradation delay due to the presence of deuterium.

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FIGURE 13.5 Same as Fig. 13.4 but for the threshold voltage.

FIGURE 13.6 Subthreshold current IDS as a function of gate voltage VG for both hydrogen and deuterium annealbefore degradation. No difference is shown within the experimental accuracy.

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The large hydrogen/deuterium isotope effect in NMOS transistors has been subsequently observedand verified by other laboratories.24–27 Studies also indicate that transistors annealed in deuterium aremuch more resilient against plasma process-induced damage (as quantified by Si/SiO2 interface trapgeneration and gate oxide leakage).28 Furthermore, stability of PMOS transistors;29 hydrogenated (deu-terated) amorphous silicon-based solar cells and TFTs;30–32 hydrogen (deuterium) terminated, porous-silicon light-emitting devices;33 and ultra-thin oxides for non-volatile memory devices34 have been foundto improve with the isotopic substitution against degradation due to light and field exposure.

For reasons outlined above, there is a strong motivation to introduce the deuterium anneal process

to CMOS manufacturing. However, two further obstacles need to be removed for transfer of process tothe factory floor. First, all modern CMOS technologies require a minimum of three levels of dielec-tric/metal interconnect process. Anneal processes that are found to be effective for improving channelhot carrier reliability in one-level of metal/dielectric structures (e.g., 400°C for 0.5 hr and 10% D2/90% N2) may be ineffective for multi-level metal/dielectric structures. The deuterium anneal processneeds to be (and in some cases has been) optimized for multi-level interconnect. Second, the benefits of the deuterium anneal should be still evident subsequent to the final SiN cap wafer passivation process.

The test vehicle used for the experiments to surmount these challenges is a development version of Lucent Technologies 0.35 $m 3.3 V transistors with a 65 Å gate oxide, very shallow arsenic implantedMDD regions, TEOS spacers, and three dielectric (doped and undoped plasma enhanced TEOS) andmetal levels (Ti/TiN/AlCuSi/TiN).35 The deuterium (5–100% D

2) anneal process was performed after the

third layer of metal had been patterned. The deuterium anneal temperatures vary between 400 to 450°Cand anneal times of 1/2 to 5 hours are considered. Accelerated hot carrier DC stress experiments areperformed on NMOS transistors at peak substrate current conditions. In Fig. 13.7, the time-dependentdeviation of Vth is shown with the deuterium anneal conditions as a parameter. Table 13.2 summarizesthe results of all stress experiments (VDS = 5 V and VGS = 2 V), assuming a degradation criteria of %Vth

= 200 mV. The degradation dynamics of Si and ID,SAT are plotted in Figs. 13.8 and 13.9. Degradation inthe transistor I–V characteristics is accompanied by an increase in the interface trap density (D it) asextracted (Fig. 13.10) from charge-pump current measurements. Figure 13.11 shows hot electron deg-radation lifetime versus substrate current with 20% gm (transconductance) degradation as the lifetimecriteria. For a peak substrate current specification of ISUB = 2000 nA/$m, the extrapolated lifetime for

the hydrogen and deuterium annealed device is 0.06 years and 4 years, respectively. The hot carrierlifetime (reliability) of transistors increases continuously and dramatically with increases in deuteriumanneal times and temperatures. Negligible improvement is observed for short (1/2 hour) and low con-centration (<10% D2) anneal conditions. The 400°C, 2-hour process results in a four-fold improvementin lifetime over the standard hydrogen process, while the 450°C, 3-hour deuterium anneal process yieldsnearly a factor of 50 improvement. Hence, whenever the deuterium content in the wafer is increased,large corresponding improvements in transistor lifetimes are measured. For longer (450°C, and 5-hour)anneals, the lifetime improvement asymptotically reaches a factor of about 80 to 100 over the standardprocess, corresponding to similar findings in basic experiments using scanning tunneling microscopy.4

In Fig. 13.12, it is demonstrated that the benefits of the deuterium anneal are still observed even if thepost-metal anneal is followed by an SiN caps process. Similar findings for higher levels of metallizationwere made by other groups (see Ref. 27). For ultimate stability against further processing, and to avoidthe complicated diffusion through many layers of metallization, it may be necessary to introduce thedeuterium in a layer close to the device that can act as a reservoir and is activated in any temperatureincrease (anneal). A convincing proof of this possibility has been given. 36

TABLE 13.1 Anneal Process and Threshold Voltage

Process Vth,N &-Vth,N Vth,P &-Vth,P

10%-H2 0.51V 2.7 mV 0.983 V 2.8 mV50%-D2 0.51V 2.4 mV 0.986 V 4.5 mV

100%-D2 0.51V 1.7 mV 0.987 V 1.1 mV

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Figure 13.13 shows a hydrogen and deuterium profile as measured by surface ion mass spectroscopy for a successfully treated transistor. A deuterium peak concentration at the interface is a typical necessity for successful anneal. The absolute concentrations may vary according to experimental conditions.

These experiments prove that one can substitute deuterium for hydrogen in a CMOS manufacturingprocess with no penalty, yet with a 50 to 100-fold improvement in channel hot carrier lifetime. For

completeness, other transistor structures with varying design considerations have been evaluated andsummarized elsewhere.37,38 Transistor parameters that were explored include: (1) gate oxide thickness t ox

= 50–115 Å, (2) LDD implant species arsenic and phosphorus and (3) gate stack structure of n +-polysilicon and polycide (n+-polysilicon/WSi), and (4) an experimental 0.25-$m 3.3-V CMOS39 process

FIGURE 13.7 Degradation improvements by deuterium anneal after three levels of metallization for various tem-

peratures and times. Only one hydrogen curve is shown; annealing with hydrogen gives identical results over wideranges of temperature and time.

TABLE 13.2 Relative Hot Carrier Reliability (Lifetime) Improvement and D2 Anneals

Temperature Time Ambient N2 Pre-anneal Lifetime425°C 2 hr 10%H2/90%N2 No 1.0400°C 1/2 hr 5%D2/95%N2 No 1.0400°C 1 hr 5%D2/95%N2 No 1.0400°C 1 hr 10%D2/90%N2 No 1.0400°C 2 hr 100%D2 Yes 3.8400°C 3 hr 100%D2 No 5.5

425°C 3 hr 100%D2 No 12.5450°C 2 hr 100%D2 Yes 36.0450°C 3 hr 20%D2/80%N2 No 37.5450°C 3 hr 100%D2 No 62.5450°C 5 hr 100%D2 No 80.0

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FIGURE 13.8 Degradation dynamics as in Fig. 13.7 but for SI .

FIGURE 13.9 Degradation dynamics as in Fig. 13.7 but for ION .

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FIGURE 13.10 Interface trap density Dit extracted from charge-pump current measurements vs. stress time withhydrogen and deuterium anneal as indicated.

FIGURE 13.11 Channel hot electron lifetime (20% gm degradation as lifetime limit) vs. substrate current for bothhydrogen and deuterium anneal with extrapolations to actual operating conditions (dashed vertical line).

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with 4 levels of metal. In all cases, the large isotope effect is observed. Clearly, the hydrogen/deuteriumisotope effect is a general property of the semiconductor device wear-out.

It is important to correlate the observed improved hot carrier reliability to the location and quantity of deuterium in the wafer. Secondary ion mass spectroscopy (SIMS) analysis through the first interleveloxide and silicon was performed on two uncapped (it is well known that Six N y is a barrier for deuterium)samples as shown in Fig. 13.13. The first wafer was annealed in forming gas (10% molecular hydrogen),while the other sample was annealed in forming gas comprising 10% molecular deuterium. A Cameca

IMS-2f system with oxygen primary beam 60 $m2

was used for analysis.18

0+

was monitored to locatethe SiO2/Si interface. The 2D+ concentration is inferred from the difference between the 2H+ profiles forwafers annealed in deuterium and hydrogen. Deuterium was not detected under large areas of (200 times200 $m2) polysilicon in wafers that were annealed in deuterium and were not capped with Six N y . Thisindicates the finite lateral diffusion length of deuterium in the transistor gate oxide and channel region.Deuterium is detected in the interlevel oxide at concentrations of 1019 cm–3 and was found to accumulateat Si/SiO2 interfaces with a surface concentration of 1014 cm–2. This SIMS study suggests that deuteriumdiffuses rapidly through the interlevel oxides and the gate sidewall spacers to passivate the interface statesin the transistor channel region. However, the exact lateral spread (reach) of diffused deuterium in thetransistor-channel and gate-oxide region is not certain.

The question still remains regarding the purity, specification limits, as well as cost for the imple-

menting deuterium gas in semiconductor manufacturing. Deuterium is a stable isotope of hydrogenand is present as D2O. Deuterium gas is produced by electrolysis of pure D2O. Tritium is a radioactiveisotope of hydrogen and has a lifetime of 12.3 years. Because of the nature of the electrolysis, the molarconcentration of tritium in the gas will be essentially the same as the feed heavy water with the tritium

FIGURE 13.12 As in Fig. 13.11 but after final SiN cap process.

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gas being in the form of DT rather than pure T2. If the tritium content in the feed water is 50 nCi/kg,the expected concentration in the gas would be about 45 pCi/L (1.65 Bq/L). The tritium content inheavy water varies from 5 nCi/kg (virgin heavy water) to 50 Ci/kg (heavy water used in nuclear reactors).The limit of tritium in deuterium gas suitable for CMOS manufacturing is estimated as follows. When1014 deuterium atoms are placed in a single chip, 3 ' 10–9 Bq/L of tritium are also incorporated. Thisimplies that one tritium decay event would occur approximately every 370 days, much below the rateof other radioactive events occurring in chip technology and operation. In addition, this is only a (-decay with usually negligible consequences. Since it is very difficult to measure tritium gas at these

low concentrations, specifications should be placed on the tritium content for the heavy water usedin the electrolytic production process (which is straightforward). A suggested upper limit could be6000 nCi/kg that results in 1 tritium event/month per chip.40 The substitution of deuterium forhydrogen adds 0.1% to the total wafer cost.

13.5 Summary

It has been demonstrated that the replacement of hydrogen by deuterium in CMOS technology can leadto significant delays in channel hot electron degradation. Increases in hot electron lifetime of a factor of 10 to 100 and beyond have been shown by simple post-metal anneals in deuterium atmosphere for severallevels of metallization. Deuterium has also been proven beneficial for the reliability of other devices suchas deuterated amorphous thin-film silicon devices of various kinds. Since deuterium and hydrogen havethe same electronic energy levels, deuterium- and hydrogen-treated devices are indistinguishable in termsof their normal pre-stress electronic characteristics. Deuterium only delays degradation due to its highermass and different vibrational properties.

FIGURE 13.13

Typical results for hydrogen and deuterium concentrations measured after anneals by secondary ion mass spectroscopy (SIMS).

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Acknowledgments

K. H. and J. W. Lyding acknowledge financial support from the Office of Naval Research under theMURI program.

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