vlsi 使用 之硬體語言設計...
TRANSCRIPT
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VLSI之硬體語言設計-使用Verilog
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重要參考書籍:Verilog HDLA Guide to Digital Design and Synthesisby Samir PalnitkarSunSoft Press (全華圖書代理)
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重要 FTP Site(1) ftp.cray.com /pub/comp.lang.verilog
(a) newsgroup(b) FAQ(c) Verilog parsers(d) Verilog-to-VHDL Translators(e) Speedup notes(f) Verilog modes for GNU Emacs
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(2) Verilog Simulators(a) iii.net /pub/pub-site/wellspring/(b) ftp.netcom.com /pub/el/eli
** The public domain simulator is not restricted for sources files under 1000 lines.
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重要Web Site(a) http://www.syncad.com/vlg_form.htmfor evaluation simulator(b)
http://www.altera.com/html/tools/baseline.htmlfor simulator
(c) http://www.e2w3.com/ivcconf.htmlfor IVC(d) http://www.cadence.com(e) http://www.synopsys.com
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Web Site for Verilog FAQ
http://www.angelfire.com/in/verilogfaq/index.html
Tom Coonan’s Home Page
http://www.mindspring.com/~tcoonan/
Chiang’s Home Page for Verilog related
http://www.te.tku.edu.tw/~chiang/verilog/verilog.htm
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• Overview of Digital System Design with Verilog HDL• Verilog Data Types and Expressions• Structural Level Modeling• The Verilog Simulator• Data Flow (Assignment) Modeling• Behavioral Modeling• Hierachical Design (State Machine Design)• Register Transfer Level (RTL)• Modeling Memories• Physical Designs and UDP, Tasks, Function• Timing and Delays and Final Exam
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第一章 VERILOG HDL 語言簡介
�設計流程
� Verilog HDL 歷史
� Verilog HDL 特性
� Verilog HDL 模擬器
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Idea
Verilog Behavior Model
Verilog -XL Verification
Synopsys LogicSynthesis
Verilog Structural Model（Gate level netlist）
Verilog-XL Verification
Physical Design
Cell Libraries
● 設計流程
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● Verilog HDL歷史
1985年: Gateway Automation研發。
1989年: Cadence Design System買下Gateway
Automation。
1990年: Verilog HDL 語法定義公開化。
1990年: OVI（Open Verilog International）成立。
1995年: IEEE standard 1364。
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● Verilog HDL 特性
♦ 作設計、測試、模擬所用的語法皆相同。
♦ 可將不同 Level 的 View 合併在一起作模擬，如 Logic Level，
Switch Level，Behavior Level 等。
♦ 提供了如同C語言的流程控制指令，如if-else，case，loop等。
♦ 提供了arithmetic，logical，bit-wise等運算表示式。
♦ 內定完整的 combinational primitives 如and，or，xor等，不需
再自行定義。
♦ 支援primitives gate delay 和 primitive gate output strength。
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GraphicalOutput
Circuit Descriptionmodule fadder(s, co, a, b, ci) ... ... end module
Test Pattern Descriptionmodule test; reg a, b; ... end module
Verilog Simulator
Verilog-XL, VCS, NC-Verilog ...
0ns ci = 0 s = 0 5ns ci = 0 s = 1 10ns ci = 1 s = 1 .....
Textoutput
● Verilog 模擬器
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第二章 Verilog HDL 的基本架構
●以全加器為例
● Verilog Module
● Structure Description 和 Behavior
Description
● Testing System File 功能圖
●完整的Test File
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a sum b cin cout
(a) Truth Table
a b cin sum cout 0 0 0 0 0 1 0 1 0 0 1 1
0 0 1 0 1 0 0 1
Full Adder
A full adder
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(b) Gate Level
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Whenever a or b or cin changes its
logic state, evaluate sum and cout by
using the equations:
sum = a⊕b⊕c
cout = ab+bc+ca
(c) Behavior Level
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Verilog module
module module_name (port_name);
Port宣告
Data Type宣告
電路描述
endmodule
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Port Declaration:
module <module_name> （<I/O pin name>)；
input [<msb>：<lsb>] <input pin>；
output [<msb>：<lsb>] <output pin>；
inout [<msb>：<lsb>] <inout pin>；
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● Structure Description 和 Behavior Description
◆ Structure Description
module fadder (sum, cout, a, b, cin);//----------- port declarationoutput sum, cout；input a, b, cin；
// ----------- gate connectionxor U0（sum, a, b, cin）;and U1（net1, a, b）；and U2（net2, a, cin）；and U3（net3, b, cin）；or U4（cout, net1, net2, net3）；
endmodule
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◆ Behavior Description
module fadder (sum, cout, a, b, cin);// -------- port declaration
output sum, cout；input a, b, cin；
// -------- data type delcarationreg sum, cout；
// -------- behavior descriptionalways @（a or b or cin）
beginsum = a^b^cin；cout = (a&b)|(b&cin)|(cin&a)；
endendmodule
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● Testing System File 功能圖
a sum b cin cout
Test Pattern送入
Full adder讀取結果
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Data type宣告
呼叫受測元件
產生test pattern
觀察電路輸出結果
module test_file
endmodule
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完整的Test File
module testing_file；//data type declarationreg a, b, cin；//Instance modulesfadder U0 (sum,cout,a,b,cin);//Applying Stimulusinitial begina = 0；b = 0；cin = 0；#5 cin = 1；#5 cin = 0；b = 1；#5 cin = 1；#5 a = 1；b = 0；cin = 0；#5 cin = 1；
#5 cin =0；b = 1；#5 cin = 1；#10 $finish；endendmodule
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第三章 相關字元、特殊字元與資料型別
● 相關字元
● 特殊字元
● 資料型別
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●相關字元
○ operators
○ white space
○ comment
○ number
○ string
○ identifier
○ keyword
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Arithmetic Operators +, -, *, /, % Relational Operators <, <=, >, >= Equality Operators ==, !=, ===, !== Logical Operators !, &&, || Bitwise and Unary Reduction Operators
~, &, |, ^, ~^
Shift Operators >>, << Conditional Operators ?: Concatenations { } Replication {{ }}
▲ operators
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▲ white space與commentwhite space : 空白鍵（space bar），TAB 鍵，return鍵註解註解註解註解 (Comment) : “//”或“/*, */”。
/* 2-to-1 multiplexer； out = a when sel = 0；out = b when sel = 1；*/module MUX_2（out, a, b, sel）； output out； input a, b, sel；
//netlist not（sel_, sel）； and（a1, a, sel_）,（b1, b, sel）； or（out, a1, a2）；
endmodule
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▲ Number
整數（integer），實數（real number）。
<size> '<base> <value>
<size>：指定integer的size有多大，以bit為單位。
<base>：指定integer的基底，可以是b（binary）二進位，
o（octal）八進位，d（decimal）十進位，或h
（hexadecimal）十六進位。
<value>:指定integer的值。
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Integer:17 //size, base沒寫會採default值 (32bit十進位)8’d32 //8-bit十進位值為328’h128’h1A8’b0001_1100 /* ”_”無特別意義，只是為了方便二進位數易讀 */8’o3732’bx // ”x”表unknown4’b0??? // ”?”表High impedance
real：7.21.8e-49.5E6
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▲ Strings
reg [8*17] stringvar；
initial begin
stringvar = “This is a string!”； //共17個字
end
Verilog 的字串同時也支援如同 C 語言中的normal
escaped characters例如：
\n（換行），\t（TAB），\\（代表\），\”（代表”），
%%（代表%）
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▲ Identifier
Identifier必須是由a-z, A-Z, 0-9, - , $這些字元組成。並且第一個字元不可以是數字或$，而Identifier最長只能到1024個字元。若Identifier中必須用到先前所提以外的非法字元時，我們可以在identifier所取的非法名稱前加上Backslash（\），並在名稱結尾加上空白鍵（space bar），這樣就可以用任何可印出的ASCII字元來當作Identifier的名稱了；而backslash和space bar不會被視為Identifier的一部分。
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module MUX_2（out, a, b, sel）；output out；input a, b, sel；
not U0（sel_, sel）；and U1（a1, a sel_）,
U2（b1, b, sel）；or U3（out, a1, a2）；
endmodule
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使用非法字元的 Identifier
module \2:1MUX (out, a, b, sel)；output out；input a, b, sel；
not not1 (\~sel , sel)；and and1 (a1, a \~sel ),
and2 (b1, b, sel)；or or1 (out, a1, a2)；
endmodule
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▲ keywordskeywords是指一些事先定義好的合法 identifier，主要是用
來定義語言的架構，並且所有的keyword都是用小寫表示。
module, endmodule
input, output, inout
reg, integer, real
not, and, or, xor, nor
begin, end
...
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●特殊字元
$，#，’。
▲ $$time：傳回目前的模擬時間$display：顯示出信號的值$stop：停止模擬
▲ #not #3 not1(sel_, sel)；// instance delay#5 a = 0；b = 0；cin = 1； // procedural statement delay
▲ ``define，`include，`timescale
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■ `define`define <name> <macro_text>
EX:`define ADD 3’h0`define SUB 3’h1
....case（opcode）`ADD：....`SUB：.....
end case
■ `includeEX:`include “user_define_task.v”■ `timescale`timescale <time unit>/<time precision>
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EX:`timescale 10ns / 1psmodule MUX2（out, a, b, sel）；output out；input a, b, sel；not #3 not1（sel_, sel）； // delay 3個10ns
...endmodule
EX:`timescale 10ns / 1nsmodule MUX2（out, a, b, sel）；output out；input a, b, sel；not #2.63 not1（sel_, sel）； /* 2.63*10ns = 26.3ns ... 四捨五入→26ns.
delay 26ns */endmodule
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●資料型別
‘0’ (Logic Low)
‘1’ (Logic High)
‘x’ ( Unknown)
‘Z’ ( High impedance)
Nets, Registers, Parameters。
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▲ Nets
net
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Net 的型式和功能
Net Types Functionwire, tri
wor, trior
wand,triand
triregtri1tri0supply1supply0
For standard interconnection wire（default）For multiple drivers that areWired-ORFor multiple drivers that areWired-ANDFor nets with capacitive storageFor nets with weak pull up deviceFor nets with weak pull down devicePower netGround net
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EX:wire out；
if en = 1, out = i；if en = 0, out = high impedance；
trireg out；
if en = 1, out = i；if en = 0, out = its last value；
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tri0 out；
if en = 1, out = i；if en = 0, out = 0；
tri1 out；
if en = 1, out = i；if en = 0, out = 1；
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當沒指定 net 是何種 type 時，Verilog 會以 default 值來設定，default 為 wire，例如：
module inverter_chain（out, in）；output out；input in；trireg net 1； // in, out, net 0 沒指定會被視為wire。not not1（net0, in）；not not2（net1, net0）；not not3（out, net1）；
endmodule
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兩個 cell 的 output 相連接時:wire/Tri y
ba 0 1 X Z 0 1 X Z
0 X X 0 X 1 X 1 X X X X 0 1 X Z
wand/Triand y ba 0 1 X Z 0 1 X Z
0 0 0 0 0 1 X 1 0 X X X 0 1 X Z
wor/Trior y ba 0 1 X Z 0 1 X Z
0 1 X 0 1 1 1 1 X 1 X X 0 1 X Z
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Net的格式：
<net type> <[msb：lsb]> <delay> <net name> <, <net name>>*；
EX：
wire net1；
wand net2；
tri [15：0] bus_in；
wand [0：31] bus_a, bus_b；
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▲Registers
Register 的型式和功能：
RegisterTypes
Function
reginteger
realtime
Unsigned integer variable of varying bit widthSigned integer variable, 32-bit wide. Arithmeticoperations produce 2’s complement result.Signed floating-point variable, double precision.Unsigned integer variable, 64-bit wide (Verilog-XL stores simulation time as a 64-bit positivevalue).
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Register 的格式:<reg type> <[msb:lsb]> <name of variable> <,<name of variable>>*；
EX:
reg a；
reg [7:0] a；
reg [31:0] a, b；
reg [0:7] b；
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在使用Data type 要注意下列幾點：
(1)一個 input port 可以用 net 或 reg 來驅動，而進到電路
內部這個 input port 只能去驅動另一個 net，不可去驅動
register。
(2)在電路內部一個 output port 可以用 net 或 register 來
驅動，而這個 output port 只能去驅動另一個 net，不可去
驅動 register。
(3)一個 inout port只能由 net 驅動，也只能去驅動 net。
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示意圖
netnet
net netinput port output port
reg or net reg or net
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▲parameters
module var_mux (out, a, b, sel)；
parameter width = 8, delay = 3；
output [width-1:0] out；
input [width-1:0] a, b；
input sel;
assign #delay out = sel ? a : b；
endmodule
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更改 parameter 的值有兩種方法：法一：利用 defparam 及 hierarchical 的名字來更改，格式如下：
defparam <hierarchical name> = <new value><,<hierachicalname> = <new_value>>*
Ex:module top；......wire [1:0] outa, a0, a1；wire [3:0] outb, b0, b1；var_mux mux0(outa, a0, a1, sel)；var_mux mux1(outb, b0, b1, sel)；defparam mux0.width=4, mux1.delay=6；......endmodule
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法二：利用呼叫 instance 時直接給定，將會依原本
instance中所定義 parameter 的次序更新。
module top；
.......
wire [1:0] outa, a0, a1；
wire [3:0] outb, bo, b1；
var_mux #(2, 3) mux0(outa, a0, a1, sel)；
var_mux #(4, 2) mux1(outb, b0, b1, sel)；
.......
endmodule
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第四章 Structural 架構
●半加器為例
● Primitive Cell
● Instance Module
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半加器為例
module half_adder (sum, cout, a, b)；output sum, cout;input a, b;xor U0(sum, a, b);and U1(cout, a, b);
endmoudle
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● Primitive Cell
Primitive Name Function and or not buf xor nand nor xnor bufif1 bufif0 notif1 notif0
Logical ANDLogical ORInverterBufferLogical Exclusive ORLogical AND InverteredLogical OR InverteredLogical Exclusive OR InverteredConditional buffer with logic 1 as enable inputConditional buffer with logic 0 as enable inputConditional inverter with logic 1 as enable inputConditional inverter with logic 0 as enable input
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primitive cell格式：<pimitive cell name> <delay> <instance name> <connection list>；
Ex：
and (out, a, b);
or (out, in1, in2, in3); // a primitive instance without // instance name
buf U0 (out, in); // specify the instance namenotif0 #5 n0(out, in, enable); // specify the delay
注意 connection list 次序為先 output 再 input。
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primitive cell 的 propagation delay 表示法：
10
10
t
t
in
out not #10 (out, in)；
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(rise, fall, turn-off) delay 之表示法
0, x, or Z to 1
1, x, or Z to 0
0 or 1 to Z
t_rise
t_fall
t_turnoff
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and #(3, 2) (out, in1, in2);
in1
in2
out
3 2
t
t
t
1
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bufif1 #(3, 4, 7) (out, in ctrl);
in1
ctrl
out
t
t
tZ
3 4 3 7
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（minimum, typical, maximum）的 delay 表示：
and # (3：4：6) U0(out, in1, in2);
bufif1 # (3：3.5：4，4：4.5：5，7：7.5：8) (out, in, ctrl)；
在執行時，只要在command line加上+mindelays、
+typdelays、+maxdelays即可，例如：
unix> verilog +mindelays HW1.v
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●Instance Module
top
MUX
counter module top()....MUX U0()counter U1()...........endmodule
module MUX().........................endmodule
module counter()...............
endmodule
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Connection by ordered list vs. connection by port name
Ex：module DEF(q, qb, din, clk)；output q, qb；input din, clk；
....endmodulemodule port_map；DEF U0(q1, qb1, din_1, clock)；//port order mappingDEF U1(.din(D[0]), .clk(clock),.q(O[0]),.qb(_O[0]))；
//name_mappingDEF U2(Q, , DIN, clock)；//one port left unconnected DEF U3(.din(A), .clk(B), .qb(c), );
endmodule
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Signal Strength Value SystemStrength Name Strength Element Modeled Declaration Printed
Level Abbreviation Abbreviation (%V)
Su
St
Pu
La
We
Me
Sm
Hi
Supply Drive
Strong Drive
Pull Drive
Large Capacitor
Weak Drive
Medium Capacitor
Small Capacitor
High Impedance
7
6
5
4
3
2
1
0
Power supply connection
Gate and assign output strength(default)
Gate and assign output strength
Size of trireg net capacitor
Gate of trireg net capacitor
Size of trireg net capacitor
Size of trireg net capacitor
Not applicable
supply
strong
pull
large
weak
medium
small
highZ
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當兩個 driven strength不同的 net 相連時，會以 strength
level 較高的 net 輸出為結果，例如：
Pull 1
Strong 0
Supply 1
Large 1
Strong 0
Supply 1
當Strength model沒有使用時，Verilog的Default值是Strong Drive
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Strength Model宣告格式：<Gate type> <0-strength, 1-strength> <delay> <instance>；
或
assign <0-strength, 1-strength> <delay> <assignment>；
EX：
not(strong0, weak1) (Y, A)；not(strong0, strong1) (Y, B)；
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第五章 模擬器支援功能
● Reading simulation time
● Text output
● File output
● Graphic output
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● Reading simulation time
$time : 傳回一個 64-bit 的 integer。
$stime : 傳回一個 32-bit 的 integer。
$realtime : 傳回一個實數。
通常我們會利用$timeformat這個system task和%t這個format來將$time, $stime, $realtime所傳回的值作一格式化，成為我們所習慣的時間單位。
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$timeformat格式如下：格式如下：格式如下：格式如下：
$timeformat (<unit>, <precision>, <suffix>, <width>)；；；；
Ex：`timescale 10ns/10psmodule timeformat_test；initial begin$timeformat (-9, 2, "ns", 20)；#10 $display ($time,,,, "This shows the time without %%t specifier.")；$display ("%t This shows the time with %%t specifier.",$time)；end
endmodule
輸出結果為：
10 This shows the time without %t specifier. 10.00ns This shows the time with %t specifier.
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• 使用$timeformat時要注意到必須配合`timescale一起使用，並且$timeformat中所指定的unit不可比`timescale中所指定的precision小。
`timescale 1ns/10psmodule time_test；reg in1；not #9.49 n1(o1, in1)；initial begin$display (" time realtime stime \t in1 \t o1")；$monitor("%d %t %d\t %b \t %b", $time, $realtime, $stime, in1,
o1)；$timeformat(-9, 2, "ns", 10)；in1=0；#10 in1=1；end
endmodule
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輸出結果為：
time realtime stime in1 o10 0.00ns 0 0 X9 9.49ns 9 0 110 10.00ns 10 1 119 19.49ns 19 1 0
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● Text Output
$display
$write
$strobe
$monitor
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▲ $display
$display會列出所指定信號的值，例如：
$display (signal1, signal2, signal3, signal4)；；；；
$display ($time, "%b \t %h \t %d \t %o", a, b, c, d)；；；；
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$display 的 Format Specification 和 Escaped Character：
Format Specification Escaped character
%h or %H display in hexadecimal format
%d or %D display in decimal format
%o or %O display in octal format
%b or %B display in binary format
%c or %C display in ASCII format
%v or %V display net signal strength
%m or %M display hierarchical name
%s or %S display as a string
%t or %T display in current time format
\n is the new line character
\t is the tab character
\\ is the backslash character
\” is the “ character
\o 1-3 digits octal number
%% is the percent character
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$display支援以不同基底為格式輸出：$displayb：binary base$displayo：octal base$displayh：hexadecimal base
Ex:module display_test；reg [3:0] data；
initial begindata = 4’b1100；$display("from display, data = ", data)；$displayb("from displayb, data = ", data)；$displayh("from displayh, data = ", data)；
endendmodule
輸出結果為：from display, data = 12from displayb, data = 1100from displayh, data = C
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• $write和$display的功能都相同，唯一不同點在$display列印到最後會自動換行，而$write不會換行。
• $strobe和$display的功能亦類似，不同在於$strobe會列印出信號已stable的值。而$display則只要執行，不論信號是否stable都會印出。
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▲ $write, $strobemodule strobe_test；
reg [31:0] data；initial begin#10 $strobe ("From strobe, data = %d", data)；
//(1)data = 10；$display ("From display, data = %d", data)； //(2)data = 30；
endendmodule
輸出結果為：From display, data = 10From strobe, data = 30
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$write ($time, " % b \t %h \t %d \t %o", a, b, c, d)；
$strobe ($time, " % b \t %h \t %d \t %o", a, b, c, d)；
$writeb (signal1, signal2, signal3)； //binary base
$writeo (signal1, signal2, signal3)； // octal base
$writeh (signal1, signal2, signal3)； // hexadecimal base
$strobeb (signal1, signal2, signal3)； // binary base
$strobeo (signal1, signal2, signal3)； //octal base
$strobeh (signal1, signal2, signal3)； // hexadecimal base
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▲ $monitor
Ex:module monitor_test；reg in; wire out；not #1 U0(out, in)；initial
$monitor($time, "out = % in = %b", out, in)；initial beginin = 0；# 10 in = 1；# 10 in = 0；endendmodule
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輸出結果為：
0 out = x in = 0
1 out = 1 in = 0
10 out = 1 in = 1
11 out = 0 in = 1
20 out = 0 in = 0
21 out = 1 in = 0
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Ex:module monitor_test；
reg in；wire out；not #1 U0(out, in)；
initial$display($time, "out = %b in = %b", out, in)；
initial beginin = 0；#10 in = 1；#10 in = 0；
endendmodule
輸出結果為：out = x in = x
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● File output
$fdisplay (<multi channel descriptor>, P1, P2, ..., Pn)；
$fwrite (<multi channel descriptor>, P1, P2, ..., Pn)；
$fmonitor (<multi channel descriptor>, P1, P2, ..., Pn)；
$fstrobe (<multi channel descriptor>, P1, P2, ..., Pn)；
<multi channel descriptor>：
<multi channel descriptor>=$fopen("file name")；
$fclose (<multi channel descriptor>)；
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EX：........integer alu_chann；initial beginalu_chann = $fopen("alu.dat")；if (alu_chann==0) $finish；endalways @(posedge clock)$fdisplay(alu_chann, "acc = %h f = %h a = %h", acc, f, a)；
............
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● Graphic outputEx:module testfixture；......initial begin$shm_open ("adder.shm")； //open waveform database
// "adder.shm".$shm_probe("A")； //save the state of all nodes in current
//scope.#1 $stop；end
endmodule
啟動 cwaves 的方法如下：unix> cwaves &
85
第六章 Assignments
● Continuous Assignments
● Procedural Assignment
86
基本格式：
< left_hand_side > = < right_hand_side >
Assignments Left_hand_side Right_hand_sidecontinuous
procedural
netwire, triregister
reg, integer, real
expression, value, other net
expression, value, other net
87
• The left hand side of an assignment must always be a scalar or vector net.
• Continuous assignments are always active. The assignment expression is evaluated as soon as one of the left-hand-side operands changes.
• The operands on the right hand side can be registers or nets of function calls.
• Delay values can be specified for assignments in terms of time unit.
88
Continuous Assignments assign out = in； assign #2 out = in；
t
t
in
out
t
out
in
t
2
89
Continuous assignment
module inv_array（out, in);
output [31：0] out；
input [31：0] in；
assign out = ~in；
endmodule
Gate level modeling
module inv_array（out, in);
output [31：0] out；
input [31：0] in；
not G0（out[0], in[0]）；
....
not G31（out[31], in[31]）；
endmodule
90
■ expression assign and_out = i1&i2；■ value
assign net_1 = 1；■ other net
assign net_a = net_b；
91
宣告 continuous assignment 方式:
法一：
<NETTYPE > <drive_strength> <range> <delay>
<list_of_assignment>；
Ex：
wire inv_out = ~in；
92
wand #10 inv_out = ~in；
wire(strong0, pull1) and_out = a&b；
93
法二格式如下：
assign <drive_strength> <delay> <list_of_assignment>；
Ex：
module inv_array (out, in)；
output [31：0] out；
input [31：0] in；
assign out =~ in；
endmodule
94
■ arithmetic operator
operator operation+-*/
%
arithmetic additionarithmetic substractionarithmetic multiplicationarithmetic divisionarithmetic modulus
Ex：-10 % 3 = -114 % -3 = 2
95
■ Unary operator
operator operation & ~& | ~| ^ ~^
unary reduction ANDunary reduction NANDunary reduction OR
unary reduction NOR unary reduction XOR unary reduction XNOR
Ex：opa = 0010
&opa ⇒ 0 & 0 & 1 & 0 = 0
96
■ bit-wise operatorsEx：opa = 0010opb = 1100
opa & opb = 0010 &1100=0000
~opa = 1101
97
■ Logical operatorsEx：opa = 0010opb = 1100opc = 0000opa && opb && opc = 0 ⇐ opa = 0010 → true
opb = 1100 → trueopc = 0000 → falsetrue & true & false = false
opa && opb = 1 ⇐ opa = 0010 → trueopb = 1100 → true true & true = true
!opa = 0 ⇐ opa = 0010 → truetrue inverted = false
98
◆ identity operator
=== 0 1 x z 0 1 x z
1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1
◆ equality operator
== 0 1 x z 0 1 x z
1 0 x x 0 1 x x x x x x x x x x
99
■ Shift operator
operator operation
>>
<<
logical shift right
logical shift left
Ex：reg_in = 6 ‘b011100reg_in << 3 → 100000reg_in >>3 → 000011
100
■ Conditional operatoroperator operation
?： conditional
Ex：assign out = sel ? i1：i0； ⇐ 當 sel 為 true時，out = i1
sel 為 false時，out = i0
101
Ex：module MU4_1（out, i0, i1, i2, i3, sel）；output [3：0] out；input [3：0] i0, i1, i2, i3；input [1：0] sel；assign out =
（sel == 2’b00）? i0：（sel == 2’b01）? i1：（sel == 2’b10）? i2：（sel == 2’b11）? i3：4’bx；
endmodule
4out
i0i1i2i3
sel2
4
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■ Concatenation OperatorEx：module add_32（co, sum, a, b, ci）；
output co；output [31：0] sum；input [31：0] a, b；input ci；assign #50{co, sum } = a + b + ci；
endmodule
103
■ Replication Operator
Ex：assign byte = { 4 {2’b0l }} byte = 01 01 01 01
Ex：assign word = {{8{byte[7]}}, byte}；
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● Procedural Assignment
1.Procedural Assignment會將指定的值drive到register
2.Procedural assignment和Continuous Assignment不同的地方，第一是LHS被update的時間不同，第二是在程式中assignment statement放置的地方不同。
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• 在Continuous assignment，LHS是隨RHS改變而改變，也就是assign的動作是連續不斷地在發生。而Procedural assignment，LHS則是在assign這個statement被執行到時，RHS的值才會被update到LHS。
• Procedural assignment statement必須放在Procedural block 中（Procedural block會在下一章說明），而Continuous assignment statement一定不可以放在Procedural block中。
106
■ update的時間不同Ex：module assignment_test；reg [3：0] r1, r2；reg [4：0] sum2；wire [4：0] sum1；assign sum1 = r1+r2；//continuous assignmentinitial beginr1 = 4’b0010； r2 = 4’b1001；sum2 = r1+r2； //procedural assignment$display （"r1 r2 sum1 sum2"）；$monitorb（r1, r2, sum1, sum2）；#10 r1 = 4’b0011；endendmodule
107
Result：r1 r2 sum1 sum20010 1001 01011 010110011 1001 01100 01011
108
■ assignment statement 放置的地方不同Ex：
module assignment_test；reg [3：0] r1; r2；reg [4：0] sum2；wire [4：0] sum1；assign sum1 = r1+r2；
initial begin //procedural blockr1 = 4`b0010；r2 = 4`b1001；sum = r1+r2；$display（"r1 r2 sum1 sum2"）；$monitorb（r1, r2, sum1, sum2）；#10 r1 = 4`b0011；endendmodule
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// Module 4-to-1 mux using data flowmodule mux4_to_1 (out, i0, i1, i2, i3, s1, s0);// port declarationoutput out;input i0, i1, i2, i3;input s1, s0;// logic equation for outassign out = (~s1 & ~s0 & i0) | (~s1 & s0 & i1) |
(s1 & ~s0 & i2) | (s1 & s0 & i3);endmodule
110
// Module 4-to-1 mux using conditional opeartormodule mux4_to_1 (out, i0, i1, i2, i3, s1, s0);// port declarationoutput out;input i0, i1, i2, i3;input s1, s0;// use nested conditional operatorassign out = s1 ? (s0 ? i3 : i2) : ( s0 ? i1 : i0);endmodule
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// 4-bit full addermodule fulladd4 (sum, c_out, a , b, c_in);// I/O portoutput [3: 0] sum;output c_out;input [3: 0] a, b;input c_in;// the function of a full adderassign {c_out, sum} = a + b + c_in;endmodule
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Carry Lookahead Adder
method 1 method 2
G[i] = A[i] ⋅ B[i] G[i] = A[i] ⋅ B[i]P[i] = A[i] ⊕ B[i] P[i] = A[i] + B[i]C[i] = G[i] + P[i] ⋅ C[i-1] C[i] = G[i] + P[i] ⋅ C[i-1]S[i] = P[i] ⊕ C[i-1] S[i] = A[i] ⊕ B[i] ⊕ C[i-1]
C[1] = G[1] + P[1] ⋅ C[0]= G[1] + P[1] ⋅(G[0] + P[1] ⋅ C[-1])= G[1] + P[1] ⋅ G[0]
C[2] = G[2] + P[2] ⋅ G[1] + P[2] ⋅ P[1] ⋅ G[0] ,C[3] = G[3] + P[2] ⋅ G[2] + P[2] ⋅ P[1] ⋅ G[1] + P[3] ⋅ P[2] ⋅ P[1] ⋅
G[0]
113
// 4-bit full adder with carry lookaheadmodule fulladd4 (sum, c_out, a , b, c_in);//I/O portoutput [3: 0] sum;output c_out;input [3: 0] a, b;input c_in;//internal wireswire p0, g0, p1, g1, p2, g2, p3, g3;wire c4, c3, c2, c1;// compute the p for each stageassign p0 = a[0] ^ b[0],
p1 = a[1] ^ b[1],p2 = a[2] ^ b[2],p3 = a[3] ^ b[3];
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// compute the g for each stageassign g0 = a[0] & b[0],
g1 = a[1] & b[1],g2 = a[2] & b[2],g3 = a[3] & b[3];
// carry lookahead computationassign c1 = g0 | (p0 & c_in),
c2 = g1 | (p1 & g0) | (p1 & p0 & c_in),c3 = g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 & p0 & c_in),c4 = g3 | (p3 & g2) | (p3 & p2 & g1) | (p3 & p2 & p1 & g0) |
(p3 & p2 & p1 & p0 & c_in);//compute sumassign sum[0] = p0 ^ c_in,
sum[1] = p1^ c1;sum[2] = p2^ c2;
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sum[3] = p3^ c3;
//assign carry outputassign c_out = c4;
endmodule
116
// edge-triggered D flipflopmodule edge_dff (q, qbar, d, clk, clear);//inputs and outputsoutput q, qbar;input d, clk, clear;//internal variableswire s, sbar, r, rbar, cbar;// create a complement of signal clearassign cbar = ~ clear;// input latchesassign sbar = ~ ( rbar & s),
s = ~(sbar & cbar & ~clk),r = ~(rbar & ~clk & s),rbar = ~(r & cbar & d);
//output latchassign q = ~(s & qbar),
qbar = ~(q & r & cbar);endmodule
117
第七章 Behavior架構
● D_flip_flop為例
● Procedural block
● Procedural Continuous Assignment
● Timing Control
● Intra-Assignment Timing Control
● Control Statements
118
• D_flip_flop為例
PRESET behavior of DFF
CLEAR
1. At every positive edge of CLOCK if
PRESET and CLEAR are not low, then
set Q to the value of D.
2. Whenever PRESET goes low,
set Q to logic 1.
3. Whenever CLEAR goes low,
set Q to logic 0.
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在作Behavior modeling時要知道幾件事：
1.要先知道電路的行為
如果電路有多種行為，我們也要知道如何分開描
述它們。
2.時間控制所謂時間控制包括：
(a)什麼時間做什麼事，例如：經過多少個clock就要做什麼事。
(b)什麼狀況做什麼事，例如：某一控制信號進來就要做什麼事。
120
在Verilog HDL中有下列幾種結構可以來幫助我們描述電路的行為。
● Procedural block● Procedural assignment● Timing control● Control statement
121
● Procedural block
“initial”和 “always” procedural block
initial CCCCC
always CCCCC
122
module clock_gen (phi1, phi2); phi1 output phi1, phi2; reg phi1, phi2; phi2 100 These procedural blocks are activated and executed at
always #100 phi1 = ~phi1; simulation time 0.
This procedural block is activated at simulation time 0 but executed at positive edge of phi1.
endmodule
initial begin phi1 = 0; phi2 = 0; end
always @ (posedge phi1) begin phi2 = 1; #50 phi2 = 0; #50 phi2 = 1; #50 phi2 = 0; end
EX:
123
“sequential block” and “parallel block”
initial CbeginC .......C .......end
initial CforkC .......C .......join
always CbeginC .......C .......end
always CforkC .......C .......join
124
begin# 10 r = 'h35;# 10 r = 'hE2;# 10 r = 'h00;end
fork# 10 r = 'h35;# 20 r = 'hE2;# 30 r = 'h00;join
125
● Procedural Continuous Assignment使用procedural continuous assignment必須注意下列幾點：
1. procedural statement 仍必須放在 procedural block中。
2. 所 drive 的對象是 reg 而非 net。
3. 當 procedural continuous assignment 和 procedural
assignment 同時發生時，procedural continuous
assignment override procedural assignment。
4. 必須使用 deassign來結束一個 procedural continuous
assignment。
126
語法：語法：語法：語法：
assign <LHS> = <RHS>；；；；deassign <LHS>；；；；Ex：module dff（q, d, clear, preset, clock）；
output q；input d, clear, preset, clock；reg q；
always @（clear or preset）if （!clear）
assign q = 0； //procedural continuous assignmentelse if （!preset）
assign q=1； // procedural continuous assignmentelse
deassign q；always @（posedge clock）
q = d； //procedural assignmentendmodule
127
● Timing ControlTiming control 可分為三類：
♦ simple delay controlEx： #100 clk =~ clk；
♦ event controlEx：
@（a or b or ci）sum = a+b+ci；@（posedge clock）q=d；@（negedge clear）assign q=0；注意：當括弧內的值有任何改變時，就稱為event。
128
module level_latch（q, d, clk）；output q；input d, clock； clkreg q；always begin dwait（clock）assign q=d；wait（!clock）deassign q； qendendmodule
♦ level sensitive event control
d
129
Intra-Assignment Timing Control
Intra-Assignment Timing Control 是指將 timing control 寫到 assignment 的中間，例如：
Timing control
# 100 clk = ~clk
@(posedge clock)
Intra-assignment timing control
clk = # 100 ~clk;
q = @(posedge clock) d;
130
intra-assignment procedural assignment
a = #5b; begin
temp = b;#5 a = temp;
end a = @(posedge clk) b;
begintemp = b;
@(posedge clk) a=temp; end
a = repeat(3)@(posedge clk) b;begin
temp = b;@(posedge clk);@(posedge clk);
@(posedge clk) a=temp; end
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Intra-Assignment 在 model 電路上的應用：
■ Data Swapforka = #5 b；b = #5 a；join注意：若是
fork#5 a = b；#5 b = a；join則 a, b 會有 race 的現象。
132
■ Data Shift
forka = @（posedge clk）b；b = @（posedge clk）c；join
133
■ pipelinemodule data_pipe（out, a, b, c）；output [7：0] out；reg [7：0] out；input [7：0] a, b, c；reg [7：0] opa, opb, opc, opc2, sum；always @（posedge clk）forkopa = @（negedge clk）a；opb = @（negedge clk）b；opc = @（negedge clk）c；sum = @（negedge clk）opa+opb；opc2 = @（negedge clk）opc；out = @（negedge clk）opc2*sum；joinendmodule
134
● Control Statementsif, if-else, case, repeat loops, while loops, for loops
■ if，if-else語法如下：
if（expression）statement
elsestatement
或
135
if（expression）statement
else if（expression）statement
else if........elsestatement
136
Ex：if（rega >= regb）result = 1；elseresult = 0；
Ex：if（index > 0）if（rega > regb）result = regaelseresult = 0；else$display（”Warning!!”）；
137
■ case
Ex：'define pass_accum 4'b0000'define pass_data 4'b0001'define ADD 4'b0010........initialcase（opcode）'pass_accum：#3.5 alu_out = accum；'pass_data：#3.5 alu_out = data；'ADD：#3.5 alu_out = accum+data；'AND：#3.5 alu_out = accum&data；'XOR：#3.5 alu_out = accum^data；default：#3.5 alu_out = 8’bx；endcase
138
■ repeat loopsEx：module multiplier（result, op_a, op_b）；.......reg shift_opa, shift_opb；parameter size = 8；initial beginresult = 0；shift_opa = op_a；shift_opb = op_b；repeat（size）
begin //default repeat 8 times#10 if（shift_opb[0]）
result = result + shift_opa；shift_opa = shift_opa << 1；shift_opb = shift_opb >> 1；end endendmodule
139
■ while loops
Ex：initialbeginreg [7：0] tempreg；count = 0；tempreg = rega；while（tempreg）
beginif（tempreg[0]）count = count + 1；tempreg = tempreg >> 1；end
end
140
結果:
rega = 101;
tempreg count101 1010 101 2
141
■ for loops
Ex：parameter size = 8, longsize = 16；reg [size：1] opa, opb；reg [longsize：1] result；initialbegin
integer bindex；result = 0；for（bindex = 1；bindex <= size；bindex = bindex+1）if（opb[bindex]）
result = result +（opa << (bindex-1））；end
142
Ex：initialbeginreg [7：0] tempreg；count = 0；for（tempreg = rega；tempreg；tempreg = tempreg>>1）if（tempreg[0] ）count = count+1；end
143
Example: Traffic Signal Controller
A highway and a country road
Main Highway
Traffic signal
144
• The main highway signal remains green by default.
• Occasionally, cars from the country road arrive at the traffic signal. The signal of the country road turns green for a fixed period.
• As soon as there are no cars on the country road, the country road signal turns yellow and then red, then the signal in the main highway turns green.
• There is a sensor to detect cars waiting on the country road. The sensor sends a signal X = 1 if there are cars on the country road; otherwise X = 0.
• There are delays on transitions from S1 to S2, from S2 to S3, and from S4 to S0. The delay must be controllable.
145
State SignalsS0 Hwy=G Cntry=RS1 Hwy=Y Cntry=RS2 Hwy=R Cntry=RS3 Hwy=R Cntry=GS4 Hwy=R Cntry=Y S0
S1
S2S3
S4
X=0
X=1
X=1X=0
146
‘define TRUE 1’b1‘define FALSE 1’b0‘define RED 2’d0‘define YELLOW 2’d1‘define GREEN 2’d2
//State Definition HWY CNTRY‘define S0 3’d0 // GREEN RED‘define S1 3’d1 // YELLOW RED‘define S2 3’d2 // RED RED‘define S3 3’d3 // RED GREEN‘define S4 3’d4 // RED YELLOW
//Delays‘define Y2RDELAY 3 // Yellow to red delay‘define R2GDELAY 2 // Red to green delay
147
module sig_control (hwy, cntry, X, clock, clear);//I/O portsoutput [1:0] hwy, cntry;
// 2-bit output for 3 states of signal GREEN, YELLOW, RED;reg [1:0] hwy, cntry;
// declared output signals are registersinput X; // if TRUE, indicates that there is a car on the country road, otherwise
// FALSEinput clock, clear;// Internal state variablesreg [2:0] state;reg [2:0] next_state;
// Signal controller starts in S0initialbegin
state = ‘S0;
148
next_state = ‘S0;hwy = ‘GREEN;cntry = ‘RED;
end
// State changes only at positive edge of clockalways @(posedge clock)
state = next_state;
// Compute values of main signal and country signalalways @(state)begin
case(state)‘S0: begin
hwy =‘GREEN;cntry = ‘RED;
end
149
‘S1: beginhwy = ‘YELLOW;cntry = ‘RED;
end‘S2: begin
hwy = ‘RED;cntry = ‘RED;
end‘S3: begin
hwy = ‘RED;cntry = ‘GREEN;
end‘S4: begin
hwy = ‘RED;cntry = ‘YELLOW;
enddefault: begin
hwy = ‘GREEN;cntry = ‘REDend
endcaseend
150
// State machine using case statementalways @(state or clear or X)begin
if (clear)next_state = ‘S0;
elsecase (state)
‘S0: if (X)next_state = ‘S1;
elsenext_state = ‘S0;
‘S1: begin // delay some positive edges of clockrepeat (‘Y2RDELAY) @ (posedge clock)next_state = ‘S2;
end‘S2: begin // delay some positive edges of clock
repeat (‘R2GDELAY) @ (posedge clock)
151
next_state = ‘S3;end
‘S3: if (X)next_state = ‘S3;
elsenext_state = ‘S4;
‘S4: begin // delay some positive edges of clockrepeat (‘Y2RDELAY) @ (posedge clock);next_state = ‘S0;
enddefault: next_state = ‘S0;
endcaseend
endmodule
152
// Stimulus Modulemodule stimulus
wire [1:0] MAIN_SIG, CNTRY_SIG;reg CAR_ON_CNTRY_RD;// if TRUE, indicates that there is a car on the country roadreg CLOCK, CLEAR;sig_control (MAIN_SIG, CNTRY_SIG, CAR_ON_CNTRY_RD, CLOCK, CLEAR);//Iinstantiate signal controllerinitial
$monitor ($time, “Main Sig = %b Country Sig = %b Car_on_cntry = %b”,MAIN_SIG, CNTRY_SIG, CAR_ON_CNTRY_RD) ;
//Set up clockinitialbegin
CLOCK = ‘FALSE;
153
forever #5 CLOCK = ~CLOCK;end
//control clear signalinitial begin
CLEAR = ‘TRUE;repeat (5) @ (negedge CLOCK);CLEAR = ‘FALSE;
end// apply stimulusinitialbegin
CAR_ON_CNTRY_RD = ‘FALSE;
#200 CAR_ON_CNTRY_RD = ‘TRUE;#100 CAR_ON_CNTRY_RD = ‘FALSE;
154
#200 CAR_ON_CNTRY_RD = ‘TRUE;#100 CAR_ON_CNTRY_RD = ‘FALSE;
#200 CAR_ON_CNTRY_RD = ‘TRUE;#100 CAR_ON_CNTRY_RD = ‘FALSE;
#100 $STOPendendmodule
155
第八章第八章第八章第八章 Introduction to Finite State Machine (FSM)
Logic Circuits: (1) Combinational Logic(2) Sequential Logic
156
Combinational Logic:
It is memoryless; i.e., without states.
Combinational Circuits
Input
Output
157
Design Procedures
1. Construct the truth table
2. Based on the truth table(a) Simplify the logic and implement the CKT by
(i) random logic gates(ii) multiplexers(iii) PLA’s or PAL’s
(b) Implement the CKT by ROM’s
158
Sequential Logic(A) Synchronous CKTs(B) Asynchronous CKTs
External inputs and states as the inputs
Combinational circuits
External Inputs
States
Outputs
159
• Due to the time delay problems (races, hazards, … etc.) people rarely design sequential circuits in asynchronous approach.
• Synchronous circuits need a system clock to strobe the whole system. It is easier to control the inputs and states.
• The speed may be slower in the synchronous circuits.
160
Two types of synchronous circuits:(1) Moore machine(2) Mealy machine
X: inputsY: statesZ: outputs
Moore machine: Z = f (Y)Mealy machine: Z = f (X, Y)
161
Moore machine
Z = f (Y)
FFCombinational LogicY
y
X Z
CLK
162
Mealy machine
Z = f (X, y)Y = f (X, y)
X
y
Combinational Circuits
FF
CLK
Z
Y
163
Six Design-Step Processes for FSM
1. Understand the statement of the specification2. Obtain an abstract specification of the FSM3. Perform a state minimization4. Perform state assignment5. Choose FF types to implement FSM state
register6. Implement the FSM
164
Example: Vending Machine FSMGeneral Machine Concept:
1. deliver a package of gum after 15 cents deposited
2. single coin slot for dimes and nickels3. no change
Step 1. Understand the problem:Draw a picture!
Block DiagramN
D
ResetClk
VendingMachineFSM
CoinSensor
Open GumReleaserMechanism
165
Step 2. Map into more suitable abstract representation
Tabulate typical input sequences:three nickelsnickel, dimedime, nickeltwo dimestwo nickels, dime
166
Draw state diagram:Inputs: N, D, resetOutput: open
S0
N D
S1 S2
N DS3 S4
[open] [open] [open]
[open][open]
S5 S6
S7 S8
Reset
167
Step 3: State Minimization
Present Inputs Next OutputState D N State Open
0 0 0 0 00 1 5 01 0 10 01 1 - -
5 0 0 5 00 1 10 01 0 15 01 1 - -
10 0 0 10 00 1 15 01 0 15 01 1 - -
15 - - 15 1Symbolic State Table
168
State DiagramReset
0¢
5¢
10¢
15¢[open]
N
N
N, D
D
D
169
Step 4: State Encoding
Present State Inputs Next State OutputQ1 Q2 D N D1 D0 Open
0 0 0 0 0 0 00 1 0 1 01 0 1 0 01 1 - - -
0 1 0 0 0 1 00 1 1 0 01 0 1 1 01 1 - - -
1 0 0 0 1 0 00 1 1 1 01 0 1 1 01 1 - - -
1 1 0 0 1 1 10 1 1 1 11 0 1 1 11 1 - - -
170
Step 5. Choosing FF for implementation(1) D FF
D1 = Q1 + D + Q0 ND0 = N(Q0)' + Q0(N) ' + Q1 N + Q1 Dopen = Q1 Q0
(2) J-K FFJ1 = D + Q0 NK1 = 0J0 = (Q0) ' N + Q1 DK0 = (Q1) ' Nopen = Q1 Q0
171
Moore and Mealy MachinesMoore Machine Reset
0¢
[0]
5¢
[0]
10¢
[0]
15¢
[1]
N'D' + Reset
ResetN'D'
D
N
N
N+D
(Reset)'
DN'D'
172
Mealy MachineReset/0
0¢
5¢
10¢
15¢
(N'D' + Reset)/0
N'D'/0
D/0
N/0
N/0
(N+D)/1
(Reset)'/1
D/1
N'D'/0
Reset/0
173
RTL
• Data Path• Control• Connectivity
174
Statement<Control>: <Transfer>
For example,State_1: ……P1*CK: ……
175
P0*CK: B ← A, D ← C,P1 ← 1, P0 ← 0;
P1*CK: C ← B,P2 ← 1, P1 ← 0;
P2*CK: A ← D,P0 ← 1, P2 ← 0;
A, B, C, and D are 8-bit registers
176
Use the 4-bit register (74LS173) to implement the 8-bit resister.
1. M, N = H, H ⇒ Output is high impedance.2. G1, G2 = L, L ⇒ Q ← D;3. Clr = H ⇒ clear;
D
74LS173
Q
4
4
Clr
MN
G1
G2
177
8-bit register
ClrDH DL
QH QL
M
N
G1
G2
74LS173 74LS173
178
Control signalsP0 = P2P1 = P0P2 = P1
D D
D
Q Q
Q
P0 P1
P2
CK
179
Data Path and Connectivity(Clock signals are omitted.)
B ← A, C ← B, D ← C, A ← D;
AQ
Q Q
Q
D D
D D
C
B D
Clr
Clr
Clr
ClrM
M M
M
N
N
N
N
G1
G1
G1
G1
G2
G2
G2
G2
0
0
0
0
0
0
0
0
P2'
P0'
P1'
P0'
8
8
8
8 8
8
180
P0*CK : If Test = 1Then P2 ← 1, P0 ← 0;Else P1 ← 1, P0 ← 0;
P1*CK : If This = 0Then P0 ← 1, P1 ← 0;
P2*CK : P0 ← 1, P2 ← 0;
181
Control SignalsP0 = P1 * (This) ' + P2P1 = P0 * (Test) ' + P1* ThisP2 = P0 * Test
(This)'
(Test)'
This
TestP0
P1
P2
182
2’s Complement SubtractorZ ← A - BZ = A - BZ = A + B' + 1
RTL
P0*CK : B ← B', P1 ← 1, P0 ← 0;P1*CK : INCR(B), P2 ← 1, P1 ← 0;P2*CK : Z ← A + B, P2 ← 0;
183
4-bit Adder (74LS283)
4 4
4
A B
SUM
C0C4 74LS283Carry out Carry in
184
Counter (74LS163)
(Load)' = 0 ⇒ QD-QA ← D-A(CLR)' = 0 ⇒ clearT,P = H, H ⇒ countCK : Rising edge triggerWhen QD-QA = 1111 ⇒ RCO ← 1
4 (Load)'
Ripple carry out
QD-QA
Input enable {
CK D-A LDRCO
CLR4
163
(CLR)'
TP
185
up/down Counter (74LS169)
U/D'=1 ⇒ up count, U/D' = 0 ⇒ down countT, P = L, L ⇒ countWhen U/D'=1 and QD-QA = 1111 ⇒ (RCO) '= 0. When U/D'=0 and QD-QA = 0000 ⇒(RCO) ' = 0.
4 (Load)'
Ripple carry out
QD-QA
Input enable {
CK D-A LDRCO
CLR4
169
(CLR)'
U/DTP
186
For 163TP
TPRCO
A
(P0)'
163
P1
PT
LD
283
Z (P2)'G1G2
187
Method 2P1*CK : Incr(A), P2 ← 1, P1 ← 0;P2*CK : Z ← A + (B)';
Z
P1 TP A (P2)' M
N
283
G1G2 P2
B
188
Method 3P0 : A+ (B)' + 1;
C0 1
BA
Sum
Cn
189
Design the input enable (EN-IN) control line for a Reed-Solomon decoder
xxxx 31 K-1 31 K-1EN-IN
190
If RESET Then P0 ← 1, P1 ← 0, P2 ← 0;P0*CK : If GO=1 Then A ← 31, P0 ← 0, P1 ← 1;P1*CK : EN-IN ← 1
If A=0 Then A ← “K-1”,P1 ← 0, P2 ← 1;
Else Decr(A);P2*CK : EN-IN ← 0
If A=0 Then A ← 31,P2 ← 0, P1 ← 1;
Else Decr(A);
191
Control : P0 = P0*(GO)'P1 = P0*GO + P1*(A = 0) ' + P2*(A=0)P2 = P1*(A = 0) + P2*(A = 0) '
4 4
4
A B
O/P
257 (MUX)G SOutputControl
1. S=0 selects A2. S=1 selects B3. (G)'=1 ⇒ O/P=Z
192
Data path0 1
K-1 31
257
RCO 169LD
PT
S P0 + P2
U/D'
A B
(A=0)'
A=0
0
0
[P0*GO+P1*(A=0)+P2*(A=0)]'
193
Control Signals
(LD) ' = [P0*GO + P1*(A=0) ' + P2*(A=0)] 'P ', T ' = [P1*(A=0) ' + P2*(A=0) '] 'U/(D) ' = 0S = (P1) ' (or P0+P2)(OC) ' = 0
194
Time delayP0: B ← AP1: C ← B
P0 P1t
tprop
B
C
tsu
P0 P1
t ≥ tprop_B + tsu_C
195
P0: B ← AP1: C ← A + B
t
tprop_B
B
P0 P1P0 P1
tsu_C
tprop_adder
t ≥ tprop_B + tprop_adder + tsu_C
196
74LS283 4 4
4C0C4
4 4
4C0C4
4 4
4C0C4
4 4
424ns24ns 17ns22ns24ns22ns
tprop283 = f(#chips)
# chips = 1 tprop283 = 24ns2 tprop283 = (17+24) = 41ns3 tprop283 = 41+22 = 63ns
………………..n tprop283 = [41+22(n-2)]ns
197
Counter (163)
PT
RCOPT
RCOPT
RCOT
14ns 14ns 27ns35ns
tprop163 = f(#chips)
# chips = 1 tprop163 = 27ns2 tprop163 = 35+14 = 49ns3 tprop163 = 35+14*2 = 63ns
………………..n tprop163 = [35+14(n-1)]ns
198
EX:
P0 : If GO Then B ← A, C ← A, P1 ← 1, P0 ← 0;P1 : If B=0 Then D ← A+C, P2 ← 1, P1 ← 0;
Else D ← A+B, P3 ← 1, P1 ← 0;P2 : Incr(D), P3 ← 1, P2 ← 0;P3 : E ← D+B, P0 ← 1, P3 ← 0;
199
Data path
A
B C
257 #1 #2257
+ 283
D E
200
Control signals to the components
A (173) m, n = 0; cl=0B (169) (LD) ' = (P0) ’ ; P ', T’ = 1 ; U/D ' = 0C (173) (G1) ', (G2) ' = (P0) ' ; cl = 0 ; m, n = 0D (169) (LD) ' = (P1) ' ; P ', T ' = (P2) ' ; U/D '= 1E (173) (G1) ', (G2) ' = (P3) ' ; cl = 0; m, n =0257 #1 S=P1257 #2 S= (B=0)
201
Delay time:P0-P1: prop B, C
prop 257prop 283su 169
P1-P2: prop Dsetup incr on 169
202
P2-P3 P1-P3prop D prop Dprop 257 prop 257prop 283 prop 283su 173 su 173
203
74LS198 Shift Registera. cl = 0 ⇒ clearb. S1 S0
1 1 ⇒ Synchronous parallel loading0 1 ⇒ Shift right1 0 ⇒ Shift left0 0 ⇒ nothing
c. R: Shift right serial inputd. L: Shift left serial input cl L I/P
O/P
8
8
RCKS1
S0198
204
MultiplierC ← A × BA: a 16-bit shift registerB: a 8-bit shift registershift right : A[6, 0] ← A[7, 1]
A[7] ← rightshift left : A[7, 1] ← A[6, 0]
A[0] ← leftNotation:Shift L (A,0): shift A left 1 bit and put 0 into A[0]Shift R (A,1): shift A right 1 bit and put 1 into A[7]
205
Methodology of the multiplication
1011× 1010
00001011
000010111101110
1011 x 0 10101011 x 1 101
10110 x 0 10101100 x 1 1110111
1101110
A B
206
VARA 16-bit shift register, 198B 8-bit shift register, 198C 16-bit shift register, 198Count 4-bit up/down counterGO Hand shake inputRDY Hand shake outputP[0:2] Control states
XY
GORDY
ANS
Multiply
207
P0 : If GO Then A[15:8] ← 0 , A[7:0] ← X , B ← Y,Count ← 7, C ← 0, RDY ← 1,P1 ← 1, P0 ← 0;
P1 : If B[0] = 1 Then C ← A+C;Decr(Count), Shift L(A,0), Shift R (B,0);If Count = 0 Then P2 ← 1, P1 ← 0;
P2: If GO = 0 Then RDY ← 0, P0 ← 1, P2 ← 0;
208
Divider: 16-bit dividerAssume positive numbers. The operation is Quot ← A/Bby long division
11111100 ) 10110101
110010101110010010110011011100
1
209
VARA: 16-bit register 173B, C, Quot: 16-bit shift register 198
XY
GORDY
Quot
Division
210
P0 : If GO Then A ← X, B ← Y, Quot ← 0, RDY ← 1, C ← 1, P1 ← 1, P0 ← 0;
P1: If (A-B)>0 Then Shift L(B, 0), Shift L(C, 0);Else P2 ← 1, P1 ← 0;
P2: If C[0] Then P4 ← 1, P2 ← 0;Else P3 ← 1, P2 ← 0;
P3: Shift R(B, 0), Shift R(C, 0);If (A-B)≥0 Then A ← A-B, Shift L(Quot, 1);
Else Shift L(Quot, 0);P2 ← 1, P3 ← 0;
P4: If GO=0 Then RDY ← 0, P1 ← 1, P4 ← 0;
211
EX:Based on the multiplier and divider we designed previously. Let’s design a machine that finds the equation of a line through 2 points.Y = mx + b(x1, y1) and (x2, y2), , b= y1- m x1m
y y
x x= −
−1 2
1 2
Mul AMul B
GO
RDY Prod
MULNumDenGO
RDY Quot
DIV
212
1. Asynchronous
P0: If Div_rdy = 0 Then Num ← y1+(y2)'+1, Den ← x1+(x2) ' +1,Go_div ← 1, P1 ← 1, P0 ← 0;
P1: If Div_rdy = 1, Then Go_div ← 0, P2 ← 1, P1 ← 0;P2: If (Div_rdy) '(Mult_rdy) ' Then Mult_A ← Quot, Mult_B ← X1,
Go_mult ← 1, P3 ← 1, P2 ← 0;P3: If Mult_rdy Then Go_mult ← 0, P4 ← 1, P3 ← 0;P4: If (Mult_rdy) ' Then b ← y1+(prod) '+1, m ← Quot, Done ← 1
P4 ← 0, P0 ← 1;
213
2. Synchronous(1) For the synchronous operation, we need to know how many clock pulses both the divider and multiplier take.
(2) Say that the multiplication can be done in 16 clock pulses and the division can be done in 30 clock pulses.
(3) Therefore, there need no handshaking signals (GO and RDY).
214
P0: If Start Then Count ← 0, Num ← y1+(y2) ' +1Den ← x1+(x2) ' +1, div0 ← 1P1 ← 1, P0 ← 0;
P1: Incr(Count);If Count=30 Then Mult_A ← Quot,
Mult_B ← X1, mult0 ← 1;If Count=46 Then b ← (prod) ' +y1+1,
m ← Quot, Start ← 0, P1 ← 0, P0 ← 1;
215
Design a candy machine defined below. The machine will take one of three inputs, N for nickel, D for dime, and Q for quarter. The other two inputs change for change return and candy for getting candy out. The candy costs for 30 cents. When the candy is selected, the machine returns the current amount of change in nickels. You do not need to worry about the machine operating without enough changes. Let the buyer beware!Remarks! 1 quarter = 25 cents
1 nickel = 5 cents1 dime = 10 cents
216
VARMoney: Counter of type 169
P0: If N Then P5 ← 1, P0 ← 0;If D Then P4 ← 1, P0 ← 0;If Q Then P1 ← 1, P0 ← 0;If Candy Then P6 ← 1, P0 ← 0;If Change Then P7 ← 1, P0 ← 0;
P1: Incr(Money), P2 ← 1, P1 ← 0;P2: Incr(Money), P3 ← 1, P2 ← 0;P3: Incr(Money), P4 ← 1, P3 ← 0;P4: Incr(Money), P5 ← 1, P4 ← 0;P5: Incr(Money), P0 ← 1, P5 ← 0;P6: If Money>5 Then Return_Candy ← 1, Money ← Money-6,
P7 ← 1, P6 ← 0;Else P0 ← 1, P6 ← 0;
P7: If Money=0 Then P0 ← 1, P7 ← 0;Else Return_Nickel, Decr(Money);
217
The second approachVARMoney: 4-bit register
P0: If N Then Money ← Money +1;If D Then Money ← Money + 2;If Q Then Money ← Money + 5;If Change Then P1 ← 1, P0 ← 0;If Candy Then P2 ← 1, P0 ← 0;
P1: If Money = 0 Then P0 ← 1, P1 ← 0;Else Money ← Money - 1, Return_Nickel ← 1;
P2: If Money > 5 Then Return_Candy ← 1, Money ← Money - 6;P1 ← 1, P2 ← 0;
218
// Method 1 for the vending machine
// State Definition 'define P0 2'd0'define P1 2'd1'define P2 2'd2
module vending_machine (Return_Candy, Return_Nickel, N, D, Q, Change, Candy, reset, clock)
// I/O Portsoutput Return_Candy, Return_Nickel;input N, D, Q, Change, Candy;input reset, clock;reg Return_Candy, Return_Nickel;reg [2:0] Money;reg [1:0] State, next_state; // State: Present State
// next_state: Next State
219
always @(reset)begin
State = 'P0;next_state = 'P0;Money = 0; Return_Candy=0, Return_Nickel=0;
end
// State changes only at positive edge of clockalways @(posedge clock)
State = next_state;
always @(State or N or D or Q or Change or Candy)begin
case (State)'P0: begin
if (N) Money = Money + 1;if (D) Money = Money + 2; if (Q) Money = Money + 5;if (Change) then next_state = 'P1;
else if (Candy) then next_state = 'P2;else next_state = ‘P0;
end
220
'P1: beginif (Money = 0)
then next_state = 'P0;else begin
Money = Money - 1;Return_Nickel = 1;next_state = ‘P1
end'P2: begin
if ( Money > 5)begin
Return_Candy = 1;Money = Money - 6;
endnext_state = 'P1;
default: next_state = 'P0;end
endcaseendendmodule
221
// Method 2 for the vending machine
//State Definition 'define P0 2'd0'define P1 2'd1'define P2 2'd2
module vending_machine (Return_Candy, Return_Nickel, N, D, Q, Change, Candy, reset, clock)
// I/O Portsoutput Return_Candy, Return_Nickel;input N, D, Q, Change, Candy;input reset, clock;reg Return_Candy, Return_Nickel;reg [2:0] Money;reg [1:0] State, next_state; // State: Present State
// next_state: Next State// State changes only at positive edge of clockalways @(posedge clock)
State = next_state;
222
// Compute the output signals, Return_Candy and Return_Nickelalways @(state)
begincase (state)'P0: begin
Return_Candy = 0;Return_Nickel = 0;
end'P1: if (Money) Return_Nickel = 1;'P2: if (Money > 5) Return_Candy = 1;default : begin
Return_Candy = 0;Return_Nickel = 0;
endendcase
end// State machine using case statementalways @(state or reset or N or D or Q or Change or Candy)begin
223
if (reset)beginnext_state = 'P0; Money = 0; end
elsecase (state)
'P0: if (N) Money = Money+1;
if (D) Money = Money+2;
if (Q) Money = Money+5;
if (Change) thennext_state = 'P1;else if (Candy) then
next_state = 'P2;else next_state = ‘P0;
'P1: if !(Money) thennext_state = 'P0;
else next_state = ‘P1;
224
'P2: begin if (Money > 5)
Money = Money - 6;next_state = P1;
enddefault: next_state = 'P0;
endcaseendendmodule
225
第九章 Modeling Memories
●陣列暫存器
● Modeling a ROM
● Modeling a RAM
226
●陣列暫存器
宣告方式：
reg [7：0] mema [0：255]； //256x8 bit memory arrayreg [7：0] PLA [`hFFFE：`hFFFF]；//2x8 bit memory array
parameter wordsize = 16，memsize = 256；reg [wordsize - 1：0] mem_word，
mem_array [memsize-1:0]；
227
15 14 0mem_word
mem_array
256
16
228
Ex：......reg [8：1] mem_word, mema [0：255];......// assign a value to memory elementmema [0] = 8’b0010_0011;........//display the content of the 6th memory element$displayb（mema[5]）;..........// display the msb of the 6th memory elementmem_word = mema[5];$displayb（mem_word[8]）;
229
● Modeling a ROM
Ex：module ROM（DOUT, ADDR, CLK）；output [5：0] DOUT；input CLK；input [3：0] ADDR；reg [5：0] DOUT, rom_core [15：0]；initial beginrom_core [0] = 6`b001100；......... //specify the ROM code.rom_core [15] = 6`b100100；
endalways @（posedge clk）DOUT = rom_core [ADDR]； //addressing the ROMendmodule
230
$readmem <base>（"<file_name>"，<mem_name>，<start>，<finish>）；
Ex：reg [7：0] mem[1：256];initial $readmemh（”mem.data”, mem）；initial $readmemb（”mem.data”, mem, 16）；initial $readmemh（”mem.data”, mem, 128, 156）；檔案內容寫法如下：.....reg [0：7] mem[0：1023]；......$readmemb（”memfile.txt”, mem）；
231
memfile.txt：
0000_00000110_0001 0011_0010//addresses 3 to 255 are not defined@1001111_1100//address 257 to 1022 are not defined@3FF1110_0010
Memory contents 00000000 0 01100001 1
11111100 256
11100010 1023
232
● Modeling a RAM
以asynchronous RAM為例：
ADDR RAM DATA
writeread
read write RAM mode DATA1 0 read mode RAM[ADDR]0 1 write mode write data0 0 disable high Z1 1 ERROR ERROR
233
Ex：module ram2*4（DATA, ADDR, read, write）；inout [1：0] DATA；input [1：0] ADDR；
input read, write；reg [1：0] intBUS, ram_core [3：0]；wire [1：0] data_wr；
bufif1（DATA[0], intBUS [0], read）；bufif1（DATA[1], intBUS [1], read）；bufif1（dara_wr[0], DATA [0], write）；bufif1（data_wr[1], DATA [1], write）；always @（posedge read）//read modeassign intBUS = ram_core [ADDR]；always @（posedge write）//write moderam_core [ADDR] = data_wr；endmodule
read int Bus
ram_core DATA
data_wr write
234
Ex：module ram2*2 (DATA, ADDR, read, write)；inout [1：0] DATA；input [1：0] ADDR；input read, write；reg [1：0] ram_core [3：0]；assign DATA [1：0] = (read==1) ? ram_core [ADDR]：2’bz；
always @（posedge write）ram_core [ADDR] = DATA；endmodule
235
第十章 Tasks, Functions, and UDP
● User defined tasks and function
● User defined event
● User Defined Primitives
236
● User defined tasks and function
• 執行特定的procedure，如計算方程式
• 可使source code更架構化
• 使source code易於閱讀與除錯
237
• 差異點
Functions TasksA function cannot have timingcontrol.
A task can contain delay.
A function cannot enable atask.
A task can enable other tasksand functions.
A function must have at leastone input argument.
A task can have zero or morearguments of any types.
A function returns a singlevalue.
A task does not return a value
238
• Specifications of a CPU Interface
CPUINTERFACE
read_request
read_grant
address 16
data 16
Sys_clk
module cpu_interface(<port>);<port_declaration>;
reg [15:0] IR, PC, address;
always @(posedge sys_clk)begin
if (read_request==1)//call the read task//call function to swap bits//call named eventend//abort readendmodule
239
� CPU asserts read_request and waits for read_grant.
� When read_grant is asserted , the CPU places the address on the address bus and reads the data.
� After reading the data , CPU deasserts the read_request and drives the address to high impedance.
� The bits of the data need to be swapped.
� If read_grant is deasserted while read_request is asserted ,abort the read.
240
• Verilog Task…..always @(posedge sys_clk)beginif(read_request == 1)beginread_mem(IR,PC);
//Event and function callsend
end
task read_mem;output [15:0] data_in;input [15:0] addr;always @(posedge read_grant)
beginADDRESS = addr;#15 data_in = data;
endendtask…….
241
• Verilog Function
always @(posedge sys_clk)begin…..IR = swap_bits(IR);…..end
function [15:0] swap_bits;input [15:0] in_vec;reg [15:0] temp_reg;integer i;beginfor (I = 15; I >= 0; I = I-1)
temp_reg[15-i] = in_vec[i];swap_bits = temp_reg;
endendfunctioin
242
● User defined event
• Named Event
event read_complete;…..always @(posedge sys_clk)beginif(read_request == 1)begin//task and function calls-> read_complete;end
endalways @(read_complete)beginread_request = 1’b0;ADDRESS = 16’bZ;$display(“Data received, read is complete”);
end
243
• Disabling Named Blocks and Tasks…..always @(posedge sys_clk)beginif (read_request == 1)read_mem(IR,PC);
end…..
always @(negedge read_grant)if (read_request == 1)
disable read_mem;…..task read_mem;…...-> read_complete;
endtask…...
244
• User-Defined Function Example
function [31:0] power_2;input [31:0] operand;integer i;
beginpower_2 = 1;for (i =0; I < operand; i = i+1)
power_2 = 2*power_2;end
endfunction
245
Blocking and Non-Blocking Procedural Assignments
= and <= assignment operators
• The blocking assignment statement (= operator) acts much like in traditional programming languages. The whole statement is done before control passes on to the next statement.
• The non-blocking ( <= operator) evaluates all the right-hand sides for the current time unit and assigns the left-hand sides at the end of the time unit.
246
// testing blocking and non-blocking assignmentmodule blocking;reg [0:7] A, B;initial begin: init1
A = 3;#1 A = A + 1; // blocking procedural assignment
B = A + 1;$display("Blocking: A= %b B= %b", A, B );A = 3;
#1 A <= A + 1; // non-blocking procedural assignmentB <= A + 1;
$display("Non-blocking: A= %b B= %b", A, B ); endendmodule
247
Produces the following output:
Blocking: A= 00000100 B= 00000101Non-blocking: A= 00000100 B= 00000100
248
● User Defined Primitives
• User Defined Primitives (UDPs) provide a way to let users define their own primitive elements.
• The behavior of UDPs is described in a truth table.
• UDPs can represent sequential as well as combinational elements.
249
• UDP Features
� UDPs can have only one output.
� The state of UDP’s output can be 0, 1, or X. Z logic value is not supported.
� Combinational UDPs can have 1 to 10 inputs.
� Sequential UDPs can have 1 to 9 inputs.
� All ports must be scalar.
� UDPs does not support bidirectional ports.
� The memory requirements increase dramatically as the number of inputs increase.
250
• Declaration of UDP
� The syntax of UDP definition is as follows:
primitive <UDP_name> (<port_name_list>);<port_declaration>;
table<table_definition>
endtableendprimitive
<input_compostion_1>:<out_value_1><input_compostion_2>:<out_value_2><input_compostion_3>:<out_value_3>……..
table definition
251
• Combinational UDP Example
2 to 1 multiplexer
primitive MUX_2_1(o, a, b, s);output o;input a, b, s;table//a b s : o0 ? 1 : 0;1 ? 1 : 1;? 0 0 : 0;? 1 0 : 1;0 0 x : 0;1 1 x : 1;
endtableendprimitive
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• Level-Sensitive Sequential UDPs
level-sensitive latch
primitive latch (q, clock, data);output q;reg q;input clock, data;initial q = 1’b1;table//clock data q q+
0 1 : ? : 1;0 0 : ? : 0;1 ? : ? : -;
endtableendprimitive
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• Edge -Sensitive Sequential UDPs
edge-sensitive D flip-flop
primitive d_edge-ff(q, clock, data);output q;intput clock, dadta;reg q;
table// clock data q q+
(01) 0 : ? : o;(01) 1 : ? : 1;(0x) 1 : 1 : 1;(0x) 0 : 0 : 0;
// ignore negative edge of clock(x0) ? : ? : -;
// ignore data changes on steady clock? (??): ? : -;
endtableendprimitive
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• Instantiate an UDP
module dff(q, qb, clk, d);output q, qb;input clk, d;
d_edge_ff G0(qi, clk, d);buf #3 G1(q, qi);not #5 G2(qb, qi);
endmodulemodule dff
d
clk
UDP d_edge_ff
data
clockq
q
qb
qi
delay=3
delay=5
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第十一章 Timing and Delays
Types of Delay Models:
1. Distributed delay
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2. Lumped delays
3. Path (pin-to-pin) delays
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Path Delay Modeling• Use specify blocks
Format
specify
endspecify
• Assign pin-to-pin timing delays across module paths.
• Set up timing checks in the circuits.
• Define specparam constants.
• Does not appear in any other blocks such as initial or always.
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Example:
// pin-to-pin delays
module M (out, a, b, c , d);
output out;
input a, b, c, d;
wire e, f;
// specify block with path delay statements
specify
( a => out ) = 9;
( b => out ) = 9;
( c => out ) = 9;
( d => out ) = 9;
endspecify
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// continued// gate instructionsand a1 ( e, a, b);and a2 ( f, c, d);and a3 ( out, e, f );endmodule
Parallel connection ( => )format:( <source_field> => <destination_field> ) = <delay_value>;
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// bit-to-bit connection. Both a and out are single-bit( a => out ) = 9;//vector connection. Both a and out are 4-bit vectors a[3:0], out[3:0]// a is source field, out is destination field(a => out ) = 9;// the above statement is shorthand notation for 4 bit-to-bit connection// statements( a [0] => out [0] ) = 9;( a [1] => out [1] ) = 9;( a [2] => out [2] ) = 9;( a [3] => out [3] ) = 9;// illegal connection. a[4:0] is a five-bit vector, out[3:0] is 4-bit.// Mismatch between bit width of the source and destination fields( a => out ) = 9; // bit width does not match
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• If the source fields and destination fields are vectors, they must have the same number of bits
Full connection
Format:
( <source_field> *> <destination_field> ) = <delay_value>;
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//Full connectionmodule M (out, a, b, c , d);output out;input a, b, c, d;wire e, f;// full connectionspecify
( a , b *> out ) = 9;( c, d *> out ) = 11;
endspecify
and a1 ( e, a, b);and a2 ( f, c, d);and a3 ( out, e, f );endmodule
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• The full connection is particularly useful for specifying a delay between each bit of an input vector and every bit in the output vector when bit width of the vector is large.
// a[31:0] is a 32-bit vector and out[15:0] is a 16-bit vector
// Delay of 9 between each bit of a and every bit out
specify
( a *> out ) = 9; // you would need 32 x 16 = 352 parallel connection
// statements to accomplish the same result!
endspecify
specparam statements
• Special parameters can be declared for use inside a specify block.
• They are declared by the keyword specparam.
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// Specify parameters using specparam statement
specify
// define parameters inside the specify block
specparam d_to_q = 9;
specparam clk_to_q = 11;
( d => q ) = d_to_q;
(clk => q ) = clk_to_q;
endspecify
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Conditional path delays• Based on the states of input signals to a circuit, the pin-to-pin delays might change.
Use if statement to accomplish it.
• There is no else statement in the specify blocks.
Example:
// Conditional Path Delaysmodule M (out, a, b, c , d);output out;input a, b, c, d;wire e, f;// specify block with conditional pin-to-pin timing
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specify// different pin-to-pin timing based on state of signal a.if (a) ( a => out ) = 9;if (~a) ( a => out ) = 10;// Conditional expression contains two signals b and c.// If b&c is true, delay = 9, otherwise delay = 13.If ( b&c ) (b => out ) = 9;If (~ ( b&c )) (b => out ) = 13;// Use concatenation operator.// Use full conncectionif ( {c, d} == 2’b01 )
( c, d *> out ) = 11;if ( {c, d} != 2’b01 )
( c, d *> out ) = 13;endspecifyand a1 ( e, a, b);and a2 ( f, c, d);and a3 ( out, e, f );endmodule
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Rise, fall, and turn-off delays• One, two, three, six, or twelve delay values can be specified for any path.
Example://Specify one delay only. Used for all transitions.specparam t_delay = 11;(clk => q) = t_delay;
//Specify two delays, rise and fall// Rise used for transitions 0-> 1, 0 -> z, z -> 1// Fall used for transitions 1 -> 0, 1 -> z, z -> 0specparam t_rise = 9, t_fall = 13;(clk => q) = (t_rise, t_fall);
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// Specify 3 delays, rise, fall, and turn-off// Rise used for transitions 0 -> 1, z -> 1// Fall used for transitions 1 -> 0, z -> 0// Turn-off used for transitions 0 -> z, 1 -> zspecparam t_rise = 9, t_fall = 13, t_turn_off = 11;( clk => q ) = ( t_rise, t_fall, t_turn_off );
// Specify 6 delays.// Delays are specified in order// for transitions 0 -> 1, 1 -> 0, 0 -> z, z -> 1, 1 -> z, z -> 0. // Order must be followed strictly.specparam t_01 = 9, t_10 = 13, t_0z = 11;specparam t_z1 = 9, t_1z = 11, t_z0 = 13;(clk => q ) = ( t_01, t_10, t_0z, t_z1, t_1z, t_z0);
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// Specify 12 delays
// Delays are specified in order
// for transitions 0 -> 1, 1 -> 0, 0 -> z, z -> 1, 1 -> z, z -> 0
// 0 -> x, x -> 1, 1 -> x, x -> 0, x -> z, z -> x.
// order must be followed strictly.specparam t_01 = 9, t_10 = 13, t_0z = 11;specparam t_z1 = 9, t_1z = 11, t_z0 = 13;specparam t_0x = 4, t_x1 = 13, t_1x = 5;specparam t_x_0 = 9, t_xz = 11, t_zx = 7;(clk => q ) = ( t_01, t_10, t_0z, t_z1, t_1z, t_z0,
t_0x, t_x1, t_1x, t_x0, t_xz, t_zx);
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Min, max, and typical delays// Specify three delays, rise , fall, and turn-off
//Each delay has a min: typ: max value
specparam t_rise = 8:9:10, t_fall = 12:13:14, t_turn_off = 10:11:12;
(clk => q) = (t_rise, t_fall, t_turn_off);
• use +mindelays, +typdelays, or +maxdelays
Handling x transitions• Transitions from x to a known state should take maximum possible time.
• Transition from known state to x should take minimum possible time.
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// Six delays specified.
// for transitions 0 -> 1, 1 -> 0, 0 -> z, z -> 1, 1 -> z, z -> 0.
specparam t_01 = 9, t_10 = 13, t_0z = 11;
specparam t_z1 = 9, t_1z = 11, t_z0 = 13;
( clk => q ) = ( t_01, t_10, t_0z, t_z1, t_1z, t_z0);
results:
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Timing Checks
clock
data
setup time
hold time
$setup taskformat: $setup (data_event, reference_event, limit);data_event signal that is monitored for violationsreference_event signal that establishes a reference for monitoring
the data_event signallimit minimum time requirement for setup of data event
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• Violation is reported if (Treference_event-Tdata_event) < limit
Example:
// Setup check is set.
// clock is the reference
// data is being checked for violations
// Violation reported if Treference_event-Tdata_event < 3
specify
$setup (data, posedge clock, 3);
endspecify
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$hold task
format:
$hold (reference_event, data_event, limit);
reference_event signal that establishes a reference for monitoring the data_event signal
data_event signal that is monitored for violations
limit minimum time requirement for hold of data event
• Violation is reported if (Tdata_event - Treference_event) < limit
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Example:
// Hold check is set.
// clock is the reference
// data is being checked for violations
// Violation reported if Tdata_event - Treference_event < 5
specify
$hold (posedge clear, data, 5);
endspecify
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$width check
format:
$width (reference_event, limit);
reference_event Edge-triggered event (edge transition of a signal)
limit Minimum width of the pulse
• Violation is reported if (Tdata_event - Treference_event ) < limit
// width check is set
// posedge of clear is the clear reference_event
// the next negedge of clear is the data_event
// Violation reported if Tdata_event - Treference_event < 6
specify
$width (posedge clock, 6);
endspecify
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Width of the pulse (min=6)
clear
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Delay Back-Annotation
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// **** Here's a simple, sequential multiplier. Very simple, unsigned..// Not very well tested, play with testbench, use at your own risk, blah // blah blah..//
//// Unsigned 16-bit multiply (multiply two 16-bit inputs to get a 32-bit // output)//// Present data and assert start synchronous with clk.// Assert start for ONLY one cycle.// Wait N cycles for answer (at most). Answer will remain stable until // next start.// You may use DONE signal as handshake.//
//
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// Written by Tom Coonan
module mult16 (clk, resetb, start, done, ain, bin, yout);parameter N = 16;input clk;input resetb;input start; // Register the ain and bin inputs (they can
// change afterwards)input [N-1:0] ain;input [N-1:0] bin;output [2*N-1:0] yout;output done;reg [2*N-1:0] a;reg [N-1:0] b;reg [2*N-1:0] yout;
reg done;
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always @(posedge clk or negedge resetb) beginif (~resetb) begin
a <= 0;b <= 0;yout <= 0;done <= 1'b1;
endelse begin
// Load will register the input and clear the counter.if (start) begin
a <= ain;b <= bin;yout <= 0;done <= 0;
end
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else begin// Go until b is zeroif (~done) begin
if (b != 0) begin// If '1' then add a to sumif (b[0]) begin
yout <= yout + a;endb <= b >> 1;a <= a << 1;//$display ("a = %b, b = %b, yout = %b", a,b,yout);
endelse begin
done <= 1'b1;end
endend
endendendmodule
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module div16 (clk, resetb, start, a, b, q, r, done);
parameter N = 16; // a/b = q remainder r, where all operands are N wide.
input clk;input resetb; // Asynchronous, active low reset.input start; // Pulse this to start the division.input [N-1:0] a; // This is the number we are dividing (the
// dividend)input [N-1:0] b; // This is the 'divisor'output [N-1:0] q; // This is the 'quotient'output [N-1:0] r; // Here is the remainder.output done; // Will be asserted when q and r are available.
// Registered qreg [N-1:0] q;reg done;
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// Power is the current 2^n bit we are considering. Power is a shifting// '1' that starts at the highest power of 2 and goes all the way down// to ...00001 Shift this until it is zero at which point we stop.//reg [N-1:0] power;
// This is the accumulator. We are start with the accumulator set to 'a' // (the dividend).// For each (divisor*2^N) term, we see if we can subtract (divisor*2^N) // from the accumulator.// We subtract these terms as long as adding in the term doesn't cause the // accumulator// to exceed a. When we are done, whatever is left in the accumulator is // the remainder.//reg [N-1:0] accum;
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// This is the divisor*2^N term. Essentually, we are taking the divisor // ('b'), initially// shifting it all the way to the left, and shifting it 1 bit at a time to the // right.//reg [(2*N-1):0] bpower;
// Remainder will be whatever is left in the accumulator.assign r = accum;
// Do this addition here for resource sharing. // ** Note that 'accum' is N bits wide, but bpower is 2*N-1 bits wide **//wire [2*N-1:0] accum_minus_bpower = accum - bpower;
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// Power is the current 2^n bit we are considering. Power is a shifting// '1' that starts at the highest power of 2 and goes all the way down// to ...00001 Shift this until it is zero at which point we stop.//reg [N-1:0] power;
// This is the accumulator. We are start with the accumulator set to 'a' // (the dividend).// For each (divisor*2^N) term, we see if we can subtract (divisor*2^N) // from the accumulator.// We subtract these terms as long as adding in the term doesn't cause the // accumulator// to exceed a. When we are done, whatever is left in the accumulator is // the remainder.//reg [N-1:0] accum;
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else begin// Go until power is zero.//if (power != 0) begin//// Can we add this divisor*2^(power) to the accumulator without going // negative?// Just test the MSB of the subtraction. If it is '1', then it must be // negative.//if ( ~accum_minus_bpower[2*N-1]) begin// Yes! Set this power of 2 in the quotieny and// then actually comitt to the subtraction from our accumulator.//q <= q | power;accum <= accum_minus_bpower;end
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// Regardless, always go to next lower power of 2.//
power <= power >> 1;bpower <= bpower >> 1;
endelse begin
// We're done. Set done flag.done <= 1;
endend
endendendmodule
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// An 8 bit x 8 synchronous FIFO
// AUTHOR: Celia Clause
//
module fifo (data_out, fifo_full, fifo_he, fifo_hf, fifo_empty, clk, reset,write, read, data_in);
parameter FIFO_WIDTH = 8;parameter FIFO_DEPTH = 8;parameter FIFO_PTR_WDTH = 3;
output [FIFO_WIDTH - 1:0] data_out; // The output dataoutput fifo_full; // The fifo full flagoutput fifo_he; // The fifo half empty flagoutput fifo_hf; // The fifo half full flagoutput fifo_empty; // The fifo empty flag
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input clk; // The input clockinput reset; // The fifo resetinput write; // The syncronous write strobeinput read; // The syncronous read strobeinput [FIFO_WIDTH - 1:0] data_in; // The input data
reg [FIFO_WIDTH - 1:0] fifo_ram[0:FIFO_DEPTH -1];reg [FIFO_PTR_WDTH - 1:0] wr_ptr, rd_ptr;reg [FIFO_PTR_WDTH:0] fifo_count;wire fifo_full, fifo_empty;wire fifo_he, fifo_hf;reg [FIFO_WIDTH - 1:0] data_out;
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/***********************************************If this is a read get the data that is inthe location pointed to by the read pointerand put it onto the output bus************************************************/always @ (posedge clk)begin if (read) begin data_out <= fifo_ram[rd_ptr];
endend
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/************************************************Increment the write pointer on every write and the read pointer on every read************************************************/always @ (posedge clk)
if (reset)wr_ptr <= 0;
elsewr_ptr <= (write) ? wr_ptr + 1 : wr_ptr;
always @ (posedge clk)if (reset)
rd_ptr <= 0;else
rd_ptr <= (read) ? rd_ptr + 1 : rd_ptr;
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/*********************************************The fifo counter increment on every write and decrement on every read **********************************************/
always @ (posedge clk)beginif (reset) beginfifo_count <= 0;
endelse begin case ({write, read})2'b00: fifo_count <= fifo_count;2'b01: fifo_count <= (fifo_count == 0) ? FIFO_DEPTH:fifo_count - 1;2'b10: fifo_count <= (fifo_count == FIFO_DEPTH) ? 0:fifo_count + 1;2'b11: fifo_count <= fifo_count;endcase
endend
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assign fifo_hf = (fifo_count >= 4);assign fifo_he = (fifo_count <= 4);assign fifo_empty = (fifo_count == 0);assign fifo_full = (fifo_count >= FIFO_DEPTH);
endmodule //of fifo
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// // Just a little demo of some FSM techniques, including One-Hot and// using 'default' settings and the case statements to selectively// update registers (sort of like J-K flip-flops).//// tom coonan, 12/98.//module onehot (clk, resetb, a, b, x, y);
input clk;input resetb;input [7:0] a;input [7:0] b;output [7:0] x;output [7:0] y;
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// Use One-Hot encoding. There will be 16 states.//reg [15:0] state, next_state;
// These are working registers. Declare the register itself (e.g. 'x') and then// the input bus used to load in a new value (e.g. 'x_in'). The 'x_in' bus will// physically be a wire bus and 'x' will be the flip-flop register ('x_in' must// be declared 'reg' because it's used in an always block.//reg [7:0] x, x_in;reg [7:0] y, y_in;
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// Update state. 'state' is the actual flip-flop register and next_state is the combinatorial// bus used to update 'state''s value. Check for the ZERO state which means an unexpected// next state was computed. If this occurs, jump to our initialization state; state[0].// // It is considered good practice by many designers to seperate the combinatorial// and sequential aspects of state registers, and often registers in general.//always @(posedge clk or negedge resetb) begin
if (~resetb) state <= 0;else begin
if (next_state == 0) beginstate <= 16'h0001;
endelse begin
state <= next_state;end
endend
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// Implement the X flip-flop register. Always load the input bus into the register.// Reset to zero.//always @(posedge clk or negedge resetb) begin
if (~resetb) x <= 0;else x <= x_in;
end
// Implement the Y flip-flop register. Always load the input bus into the register.// Reset to zero.//always @(posedge clk or negedge resetb) begin
if (~resetb) y <= 0;else y <= y_in;
end
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// Generate the next_state function. Also, based on the current state, generate// any new values for X and Y.//always @(state or a or b or x or y) begin
// *** Establish defaults.
// Working registers by default retain their current value. If any particular
// state does NOT need to change a register, then it doesn't have to reference
// the register at all. In these cases, the default below takes affect. This// turns out to be a pretty succinct way to control stuff from the FSM.//x_in <= x;y_in <= y;
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// State by default will be cleared. If we somehow ever got into an unknown
// state, then the default would throw state machine back to zero. Look// at the sequential 'always' block for state to see how this is handled.//next_state <= 0;
// One-Hot State Machine Encoding.//// *** Using a 1'b1 in the case statement is the trick to doing One-Hot...// DON'T include a 'default' clause within the case because we want
to// establish the defaults above. ***//case (1'b1) // synopsys parallel_case
// Initialization state. Set X and Y register to some interesting starting values.
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state[0]:begin
x_in <= 8'd20;y_in <= 8'd100;next_state[1] <= 1'b1;
end
// Just for fun.. Jump through states.. state[1]: next_state[2] <= 1'b1;state[2]: next_state[3] <= 1'b1;state[3]: next_state[4] <= 1'b1;state[4]: next_state[5] <= 1'b1;state[5]: next_state[6] <= 1'b1;state[6]: next_state[7] <= 1'b1;
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// Conditionally decrement Y register.state[7]:
beginif (a == 1) begin
y_in <= y - 1;next_state[1] <= 1'b1;
endelse begin
next_state[8] <= 1'b1;end
end
// Just for fun.. Jump through states.. state[8]: next_state[9] <= 1'b1;state[9]: next_state[10] <= 1'b1;state[10]: next_state[11] <= 1'b1;
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// Conditionally increment X register.state[11]:
beginif (b == 1) begin
x_in <= x + 1;next_state[1] <= 1'b1;
endelse begin
next_state[12] <= 1'b1;end
end// Just for fun.. Jump through states..
state[12]: next_state[13] <= 1'b1;state[13]: next_state[14] <= 1'b1;state[14]: next_state[15] <= 1'b1;state[15]: next_state[1] <= 1'b1; // Don't go back to our initialization state,
but state following that one.endcase
endendmodule
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// synopsys translate_offmodule test_onehot;reg clk, resetb;reg [7:0] a;reg [7:0] b;wire [7:0] x;wire [7:0] y;
// Instantiate module.//onehot onehot (
.clk(clk),
.resetb(resetb),
.a(a),
.b(b),
.x(x),
.y(y));
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// Generate clock.//initial begin
clk = 0;forever begin
#10 clk = ~clk;end
end
// Reset..//initial begin
resetb = 0;#33 resetb = 1;
end
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// Here's the test.// Should see X and Y get initially loaded with their starting values.// As long as a and b are zero, nothing should change.// When a is asserted, Y should slowly decrement. When b is asserted, X should// slowly increment. That's it.//initial begin
a = 0;b = 0;repeat (64) @(posedge clk);#1
// Y should be decremented..a = 1;b = 0;repeat (256) @(posedge clk);#1
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// X should be incremented..a = 0;b = 1;repeat (256) @(posedge clk);
$finish;end// Monitor the module.//initial begin
forever begin@(posedge clk);#1;$display ("a = %b, b = %b, x = %0d, y = %0d", a,b,x,y);
endend
endmodule
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Appendix A
Verilog Syntax