visio-dramロードマップ最新 - pc watchddr3 800-1600(2133)mtps dram roadmap 100mhz 1ghz...

1

DDR3 800-1600(2133)Mtps DRAM Roadmap 100MHz 1GHz 200MHz 300MHz 400MHz 500MHz 600MHz 700MHz 800MHz 900MHz 1.1GHz 10GHz 2GHz 3GHz 4GHz 5GHz 6GHz 7GHz 8GHz 9GHz 1.2GHz 1.3GHz 1.4GHz 1.5GHz 1.6GHz 1.7GHz 1.8GHz 1.9GHz 2.5GHz 3.5GHz 4.5GHz 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 1996 1997 1998 1999 DDR 200-400Mtps DDR2 400-800(1067)Mtps DDR3 800-1600(2133)Mtps NGM Diff ? 4.x?-6.4Gtps DDR4 1.6-3.2Gtps SDRAM 66-133Mtps DRDRAM 600-1066(1333)Mtps 100MHz 1GHz 200MHz 300MHz 400MHz 500MHz 600MHz 700MHz 800MHz 900MHz 1.1GHz 10GHz 2GHz 3GHz 4GHz 5GHz 6GHz 7GHz 8GHz 9GHz 1.2GHz 1.3GHz 1.4GHz 1.5GHz 1.6GHz 1.7GHz 1.8GHz 1.9GHz 2.5GHz 3.5GHz 4.5GHz Micron Technologyのロードマップでは2009年頃にNGM Diffが登場? 実際にはもう少し後ろか Samsung Electronicsのロードマップでは2011年頃にDDR4が登場 XDR DRAM 3.2-6.4Gbps

Upload: others

Post on 22-Apr-2020

3 views

Category:

Documents

0 download

Report

Download

Embed Size (px):

TRANSCRIPT

Page 1: VISIO-DRAMロードマップ最新 - PC WatchDDR3 800-1600(2133)Mtps DRAM Roadmap 100MHz 1GHz 200MHz 300MHz 400MHz 500MHz 600MHz 700MHz 800MHz 900MHz 1.1GHz 10GHz 2GHz 3GHz 4GHz 5GHz

DDR3800-1600(2133)Mtps

DRAM Roadmap

100MHz

1GHz

200MHz

300MHz

400MHz

500MHz

600MHz

700MHz

800MHz

900MHz

1.1GHz

10GHz

2GHz

3GHz

4GHz

5GHz

6GHz

7GHz

8GHz

9GHz

1.2GHz1.3GHz1.4GHz1.5GHz1.6GHz1.7GHz1.8GHz1.9GHz

2.5GHz

3.5GHz

4.5GHz

2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 20131996 1997 1998 1999

DDR200-400Mtps

DDR2400-800(1067)Mtps

DDR3800-1600(2133)Mtps

NGM Diff ?4.x?-6.4Gtps

DDR41.6-3.2Gtps

SDRAM66-133Mtps

DRDRAM600-1066(1333)Mtps

100MHz

1GHz

200MHz

300MHz

400MHz

500MHz

600MHz

700MHz

800MHz

900MHz

1.1GHz

10GHz

2GHz

3GHz

4GHz

5GHz

6GHz

7GHz

8GHz

9GHz

1.2GHz1.3GHz1.4GHz1.5GHz1.6GHz1.7GHz1.8GHz1.9GHz

2.5GHz

3.5GHz

4.5GHz

Micron Technologyのロードマップでは2009年頃にNGM Diffが登場?実際にはもう少し後ろか

Samsung Electronicsのロードマップでは2011年頃にDDR4が登場

XDR DRAM3.2-6.4Gbps

Gather-Scatter DRAM: In-DRAM Address ranslationT …omutlu/pub/GSDRAM-gather...Gather-Scatter DRAM: In-DRAM Address ranslationT to Improve the Spatial Locality of Non-unit Strided

Memory Scaling : A Systems Architecture PerspectiveSolution 1: Tolerate DRAM ! Overcome DRAM shortcomings with " System-DRAM co-design " Novel DRAM architectures, interface, functions

CAT 6 600MHz Outdoor Solid Direct Burial Shielded …...CAT 6 600MHz Outdoor Solid Direct Burial Shielded Bulk Cable Rev. 02/22/16 PrimusCable.com - (951) 824-1571 Category 6 Outdoor

HY425 Lecture 15: DRAM Technology - University of Cretehy425/2012f/lectures/lecture15...DRAM basics Advanced DRAM technology Virtual memory HY425 Lecture 15: DRAM Technology Dimitrios

US 600MHz Incentive Auction Forward and Reverse Auction …€¦ · US 600MHz Incentive Auction Forward and Reverse Auction Rules By Richard Marsden and Jonathan Pike The “Incentive

Solar-DRAM: Reducing DRAM Access Latency by Exploiting …...reads to DRAM cache lines containing “weak” or “strong” cells, and 2) writes to all of DRAM. We evaluate Solar-DRAM

AHM - DSL Ltd€¦ · AHM-6058 AHM-6088 AHM-6108 AHM-6128 System Processor Intel ® Atom ™ Z510 1.1GHz CPU Default, upgrade to Z530 1.6GHz CPU System Memory 1GB DDR2 400MHz DRAM

DRAM Technology

KTD-00774-F · KTUS15/mITX 1.1GHz Basic + 2 + KTUS15/mITX 1.1GHz Std + + + 4 + KTUS15/mITX 1.6GHz Std + + + + 2 + KTUS15/mITX 1.6GHz Plus + + + + + 4 + Use of this manual implies

1 Multi-Core Systems CORE 0CORE 1CORE 2CORE 3 L2 CACHE L2 CACHE L2 CACHE L2 CACHE DRAM MEMORY CONTROLLER DRAM Bank 0 DRAM Bank 1 DRAM Bank 2 DRAM Bank

ARCHITECTURAL TECHNIQUES TO ENHANCE DRAM …research.ece.cmu.edu/safari/thesis/ykim_defense_slides.pdfCO-DESIGN: CPU & DRAM CPU Memory Management DRAM Controller DRAM Arch & Interface

VRL-DRAM: Improving DRAM Performance via Variable Refresh ... · VRL-DRAM: Improving DRAM Performance via Variable Refresh Latency Anup Das Drexel University Philadelphia, PA, USA

DDR3 Synchronous DRAM Memory - … · DDR3 Synchronous DRAM Memory ... Read/Write leveling . DDR3 Synchronous DRAM 3 8-bit prefetch/burst length . DDR3 Synchronous DRAM 4 Commands

Gather-Scatter DRAM: In-DRAM Address ranslationT …people.inf.ethz.ch/omutlu/pub/GSDRAM-gather-scatter-dram...Gather-Scatter DRAM: In-DRAM Address ranslationT to Improve the Spatial

IDTF0502NLGI F0552NBGI Sampling IF Receiver 600MHz to

ADVANTECH DRAM Memory Module Portfolio Introductionags.advantech.com/PTDFiles/ADVANTECH DRAM Memory...ADVANTECH DRAM Memory Module Portfolio Introduction PAPS Product Management Q3

DRAM Memory Controllerscs7810/pres/dram-cs7810-mem-ctlr-x2.pdf · DRAM Memory Controllers Reference: “Memory Systems: Cache, DRAM, Disk Bruce Jacob, Spencer Ng, & David Wang Today’s

High Speed DRAM Interface - Hanyangiclab.hanyang.ac.kr/research/data/High-speed DRAM interface.pdf · High Speed DRAM Interface Changsik Yoo DRAM Design 3 Samsung Electronics. [email protected]@ieee.org

etrij.etri.re.kr · rule -x SRAM 04K SRAM DRAM a 0 16K SRAM 64K DRAM oa 256K DRAM 64K SRAM 1M DRAM 256K SRAM 4M DRAM SRAM 88 16M DRAM SRAM 10 10 10 10 10 0.8 0.6 70 4K DRAM 72 01K

US 600MHz Incentive Auction Forward and Reverse …...29 October 2014 US 600MHz Incentive Auction Forward and Reverse Auction Rules By Richard Marsden and Jonathan Pike The “Incentive

Staged-Reads : Mitigating the Impact of DRAM Writes on DRAM Reads

Adaptive-Latency DRAM: Optimizing DRAM Timing …users.ece.cmu.edu/~omutlu/pub/adaptive-latency-dram_hpca15.pdf · Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common

Scalable Many-Core Memory Systems Lecture 1, Topic 1: DRAM ...users.ece.cmu.edu/.../onur-ACACES2013-Lecture1-dram... · Solution 1: Tolerate DRAM ! Overcome DRAM shortcomings with

ettrends.etri.re.kr · rule -x SRAM 04K SRAM DRAM a 0 16K SRAM 64K DRAM oa 256K DRAM 64K SRAM 1M DRAM 256K SRAM 4M DRAM SRAM 88 16M DRAM SRAM 10 10 10 10 10 0.8 0.6 70 4K DRAM 72

Co-Architecting Controllers and DRAM to Enhance DRAM ...camelab.org/uploads/Main/Co-Architecting Controllers and DRAM to... · Co-Architecting Controllers and DRAM to Enhance DRAM

ProactiveDRAM: A DRAM-initiated Retention Management ......DRAM cell DRAM row sense amp DRAM bank subarray wordline bitline Fig. 2. DRAM internal bank architecture. banks. A rank can

QNP Accessory for BLAXH300/100 200-600MHz