10/25/05 ELEC 5970-001/6970-001 Lecture 15 1

ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic Circuits

Pseudo-nMOS, Dynamic CMOSand Domino CMOS Logic

Vishwani D. AgrawalJames J. Danaher Professor

Department of Electrical and Computer EngineeringAuburn University

http://www.eng.auburn.edu/~vagrawalvagrawal@eng.auburn.edu

10/25/05 ELEC 5970-001/6970-001 Lecture 15 2

Why Not Static CMOS?

• Advantages: Static (robust) operation, low power, scalable with technology.

• Disadvantages:– Large size: An N input gate requires 2N transistors.– Large capacitance: Each fanout must drive two

devices.

• Alternatives: Pass-transistor logic (PTL), pseudo-nMOS, dynamic CMOS, domino CMOS.

10/25/05 ELEC 5970-001/6970-001 Lecture 15 3

A Pseudo-nMOS Gate

PUN

PDN

VDD

CMOS Gate

PDN

VDD

Pseudo-nMOS Gate

Output

Inp

uts

Inp

uts

Output

10/25/05 ELEC 5970-001/6970-001 Lecture 15 4

A Pseudo-nMOS Inverter

W/Lp = 4

W/Lp = 2

W/Lp = 0.25

W/Lp

= 0.5W/Lp

= 1

0.0 0.5 1.0 1.5 2.0 2.5

Input voltage, V

Ou

tpu

t vo

ltag

e, V

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Nominal device: W 0.5μ── = ──── = 2 Ln 0.25μ

10/25/05 ELEC 5970-001/6970-001 Lecture 15 5

Performance of Pseudo-nMOSSize, W/Lp Logic 0 voltage

Logic 0 static power

Delay

0 → 1

4 0.693 V 564 μW 14 ps

2 0.273 V 298 μW 56 ps

1 0.133 V 160 μW 123 ps

0.5 0.064 V 80 μW 268 ps

0.25 0.031 V 41 μW 569 ps

J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital IntegratedCircuits, Upper Saddle River, New Jersey: Pearson Education, 2003.

10/25/05 ELEC 5970-001/6970-001 Lecture 15 6

Negative Aspects of Pseudo-nMOS

• Output 0 state is ratioed logic.

• Faster gates mean higher static power.

• Low static power means slow gates.

10/25/05 ELEC 5970-001/6970-001 Lecture 15 7

A Dynamic CMOS Gate

PDN

VDD

Inp

uts

Output

CK

CL

10/25/05 ELEC 5970-001/6970-001 Lecture 15 8

Two-Phase Operation in a Vector Period

Phase CK Inputs Output

Precharge low don’t care high

Evaluation high Valid inputs Valid outputs

10/25/05 ELEC 5970-001/6970-001 Lecture 15 9

4-Input NAND Dynamic CMOS Gate

Output= CK’ + (ABCD)’∙ CK

CL

CK

A

B

C

D

CK

VDD

tL→H ≈ 0

10/25/05 ELEC 5970-001/6970-001 Lecture 15 10

Characteristics of Dynamic CMOS

• Nonratioed logic – sizing of pMOS transistor is not important for output levels.

• Larger precharge transistor reduces output fall time, but increases precharge power. Faster switching due to smaller capacitance.

• Static power – negligible.• Short-circuit power – none.• Dynamic power

– no glitches – following precharge, signals can either make transitions only in one direction, 1→0, or no transition, 1→1.

– only logic transitions – all nodes at logic 0 are charged to VDD during precharge phase.

10/25/05 ELEC 5970-001/6970-001 Lecture 15 11

Logic Activity• Probability of 0 → 1 transition:

– Static CMOS, p0 p1 = p0(1 – p0)– Dynamic CMOS, p0

• Example: 2-input NOR gate– Static CMOS, Pdyn = 0.1875 CLVDD

2fCK

– Dynamic CMOS, Pdyn = 0.75 CLVDD2fCK

p1=0.5

p1=0.5

p1=0.25 p0=0.75

10/25/05 ELEC 5970-001/6970-001 Lecture 15 12

Charge Leakage

OutputA’

CL

CK

A=0

CK

VDD

CK

A’

TimeP

rech

arg

e

Eva

luat

e

IdealActual

J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital IntegratedCircuits, Upper Saddle River, New Jersey: Pearson Education, 2003.

10/25/05 ELEC 5970-001/6970-001 Lecture 15 13

Bleeder Transistor

Output

CL

CK

A

B

C

D

CK

VDD

Output

CL

CK

A

B

C

D

CK

VDD

10/25/05 ELEC 5970-001/6970-001 Lecture 15 14

A Problems With Dynamic CMOS

CK

A=0→1

CK

VDDCK

A

B

C

B

J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital IntegratedCircuits, Upper Saddle River, New Jersey: Pearson Education, 2003.

CK

CK

VDD

C

prech. evaluate

10/25/05 ELEC 5970-001/6970-001 Lecture 15 15

Domino CMOS

CK

A=0→1

CK

VDD

CK

A

B

C

B

R. H. Krambeck, C. M. Lee and H.-F. S. Law, “High-Speed Compact Circuits with CMOS,” IEEE J. Solid-State Circuits, vol. SC-17, no. 3, pp. 614-619, June 1982.

CK

CK

VDD

C

prech. evaluate

10/25/05 ELEC 5970-001/6970-001 Lecture 15 16

Bleeder in Domino CMOS

Output

CL

CK

A

B

C

D

CK

VDD

10/25/05 ELEC 5970-001/6970-001 Lecture 15 17

Logic Mapping for Noninverting Gates

A

B

C

D

E

FG

H

ABC

G+H

AND

OR AND/OR

X

Y

Y

ABC

D

E

F

G+H

10/25/05 ELEC 5970-001/6970-001 Lecture 15 18

Selecting a Logic Style• Static CMOS: most reliable and predictable,

reasonable in power and speed, voltage scaling and device sizing are well understood.

• Pass-transistor logic: beneficial for multiplexer and XOR dominated circuits like adders, etc.

• For large fanin gates, static CMOS is inefficient; a choice can be made between pseudo-nMOS, dynamic CMOS and domino CMOS.