ECE 6420 – Final Design Project – Group 7

Abstract – In this paper, we describe the design and implementation of a CMOS WiMAX Power Amplifier implemented using a two-stage cascade topology. Multiple stages have been combined utilizing power-combination transformer techniques. Simulation results show a power gain of 29 dB with a P1dB of 30.71 dBm and an EVM of 3% @ 23.5 dBm with a PAE of 21.5%. The PA was tested with IEEE 802.11a (WLAN) 54-Mbps OFDM signals at 2.4-Ghz. It is proved that the PA fulfils the requirements of both WLAN and WiMAX standards. Additionally, a 3.5 Ghz version was developed and the two PAs combined.

Index Terms—CMOS, Class-AB, Power Amplifiers, WiMAX, transformer power combination, cascode, EVM, mask.

I. INTRODUCTION

HE growing demand of wireless communication using digital modulation has driven the adoption of orthogonal

frequency division multiplexing (OFDM) schemes which provides high data-rate transmission. This makes linearity of the transmitter a stringent requirement. The linearity of the whole transmitter is a strong function of the linearity of PA and it is also a major parameter in determining the quality of the transmitter.

T

In the case of cellular applications, output power usually reaches watt-levels. For example, most PA products for GSM applications generate more than 2W. Hence, when using CMOS processes which are known for low power-driving capabilities, it is necessary to have an additional function, i.e. a power combiner, to combine several power cells unit to generate the required output power. One of the most popular combining techniques is based on a Wilkinson-type combiner, which requires quarter-wavelength transmission lines and it is therefore difficult to integrate in systems for typical cellular applications frequency bands.

Recently, there have been several successful efforts to realize the function of power combination and impedance transformation at the same time by using transformer-based networks. They can be categorized as series-combining transformers (SCTs) and parallel-combining transformers (PCTs) depending on how the voltage and the current are effectively combined at the output stage.

In this work, we decided to investigate a transformer-based parallel-combining technique to deliver a high output power while using CMOS technology. Section II presents the market analysis for a WiMAX PA, section III describes the PA structure and design methodologies, section IV describes the peripheral circuitry associated with the PA. In section V package considerations are presented, while results are provided in section VI and limitations of the design in section VII.

II.MARKET ANALYSIS

A. WiMAX ResearchRF PA products are targeted at mobile phones and other 3G

wireless devices, such as datacards, netbooks and technology products compatible with new standards like WiMAX. Mobile phones and wireless products today use power amplifiers mainly based on Gallium Arsenide (GaAs) or Silicon Germanium (SiGe) semiconductor technology. Replacing GaAs or SiGe with CMOS silicon technology would improve manufacturing yield and cost, but the efficiency could decrease, even though latest studies suggest that a high PAE can be obtained. However, research is still required for CMOS to be able to meet modern performance, battery life, and call quality requirements. Over time, CMOS has replaced GaAs technology in many other applications from audio chips to DVD decoders. However, CMOS does not lend itself easily to use in power amplifiers, so that a novel architecture may be required.

The importance of this market is easily understood by considering that 3G mobile phones typically employ more power amplifier units than 2G or 2.5G phones. As an example, the iPhone, a 2.5G phone, integrates one cellular power amplifier package while the iPhone 3G integrates five cellular power amplifier packages. New products compatible with 4G (WiMAX) are expected to require more of these packages. WiMAX products are predicted to hold a value of $1.7 billion with an 80% market penetration in the upcoming future.

WiMAX penetration in December 2010 can be considered significant. The number of people covered by WiMAX service providers is more than 621 million, while the total number of deployed networks is shown in table I (i.e. included base stations that are being deployed, but there are few subscribers yet).

TABLE IWIMAX PENETRATION

Total Deployments tracked 592

Countries with WiMAX Deployments

149

Eastern Europe 86Western Europe 76Africa 117Middle East 29North America 57Asia/Pacific 109CALA 118WiMAX is compatible with multiple frequency bands,

depending on the market and the geographical region of interest. For this reason, a PA which is multi-standard compatible could have a worldwide application and a wider market penetration. Table II shows the number of deployments divided by frequency bands. A PA compatible with the 2.3 – 2.7 GHz band and at the

Design of a CMOS WiMAX Power Amplifier using Power Combining Techniques

Michele Piccardi, Jason Pinto,Akshil Shah and Pritham Raja

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ECE 6420 – Final Design Project – Group 7same time compatible with the 3.5 GHz band would have a potentially high market diffusion.

TABLE IIWIMAX FREQUENCY DEPLOYEMENT

Freq. Range BW Deployement #2.3 GHz 5/10 MHz 552.5 GHz 5/10 MHz 1553.3 GHz 5/7 MHz 93.5 GHz 5/7 MHz 3095+ GHz 10 MHz 21

The following maps show how different WiMAX bands are geographically distributed. Figure I shows the 2.3-2.5 GHz band penetration, while Figure II the 3.5 GHz band penetration.

Fig. 1 2.4 GHz worldwide diffusion

Fig. 2 3.5 GHz worldwide diffusion

Fig. 3 Other bands combined worldwide diffusionDeveloping a PA targeted at the dual band 2.4 GHz and 3.5

GHz seems consequently reasonable. Few companies providing CMOS solutions for the PA exist in the market. Blacksand Technologies is an Austin based company with no available products. Javelin Semiconductors also based in Austin has a

CMOS PA, JAV5001, with a selling price of $1.45 @ 10k. Skyworks solutions is another company developing a CMOS PA. Industry stalwarts like RFMD, TI, Analog devices, Anadigics, FairChild Semiconductors, Triquint Semiconductors and so on have PAs available but in different technologies such as InGaP HBT, GaAs HBT, and SiGe HBT. The next table shows the performance and features of the products present on the market and at the research level.

TABLE IIIWIMAX PRODUCTS AND PROTOYPES

MarketFreq

(GHz)Gain (dB)

P1dBdBm EVM Supply PAE(%) Tech

Analog Devices

2.5-2.7 29 29 3%@25 dBm 3.2 21 GaAs

Anagidics2.3-2.4 30 30 3%@25 dBm 3 or 5 20

InGaP

SiGe Semicon.

2.5-2.7 34 - 3%@25.5dBm

2.9 - 4.2 20 SiGe

RFMD3.3-3.8 33 33.5 2.5%@26dBm 3 or 6 14.5

InGaP

TriQuint2.3-2.8 - 29.8 2.5%@23dBm 5 -

InGaP

Skyworks2.3-2.5 - - 27.5dBm linear 6 -

InGaP

Research              Laskar at

al. 2.4 32 31 20 db @25 dBm 3.3 27 cmosMobility Wireless Group

2.3-2.7 18 32 30 db @25 dBm 3.3 48 cmos

Chowdury at al. 2.4 28 30 25 db @25 dBm 3.3 33 cmosRF

Systems Labs 2.3 22.4 24.7   3.3 22.6 cmos

Liu and Haldi 2.4 10 24

4.48%@14.5dBm 1.2 32 cmos

CMOS technology has been already used in WiFi applications, where the required highly linear output power is around 24 dBm, and in GSM-GPRS applications, where the output power can be as high as 1 W, but the linearity requirements are less stringent and operation in saturation is still admitted. WiMAX incorporated the challenges of both worlds.The requirements for a CMOS PA are pretty strict. Since the minimum output power (Pout) at the antenna is 23dBm, the power amplifier needs to deliver at least 25dBm linear power to account for the loss between the PA output and the antenna. A typical transmitter chip can only provide -5dBm linear power at its baseband output. In addition, there may be a filter between the TX chip and power amplifier for noise reduction purposes and the typical filter loss is around 2 to 3dB. Consequently, to achieve 25dBm of output power, around 33dB gain is required from the power amplifier. To address mobile unit application, the power amplifier is to be used in handheld devices and typical available supply voltage is most likely 3.3V. Also, the amplifier has to have sufficiently high efficiency so that the device be able to operate for a longer time. The allocated frequency band is anywhere between 100MHz to 500MHz, operation band of the amplifier should be designed as broad as possible. An EVM of less than 3% at Pout of 25dBm is required.

WiMAX requires to respect a specified spectral mask for the output signal, in order to reduce the risk of out of band transmission of interferers which could disturb adjacent channels. The spectral requirements are shown in fig.4:

Fig. 4 WiMAX PA spectral mask

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ECE 6420 – Final Design Project – Group 7

Based on the above mentioned research we decided to implement a highly linear system with a high gain and a high P1db compression point with a good EVM result and a good efficiency. Clearly these requirements are stringent. Our aim is to try offering a product which can be comparable to market’s products as far as gain, P1dB, EVM and PAE are concerned, but implementing it using CMOS technology, in order to reduce the associated production costs and being able to aggressively compete in the market.

B. Justification of StrategySince there are no commercial products available in CMOS

technology, our strategy may take advantage of the high integration capability of the CMOS industry, while would enable an easy integration of wide devices, while guaranteeing a low production cost. In the cellular device market, an important concern is the battery life, so that PAE should be considered when taking decisions in impedance matching problems.

III. POWER AMPLIFIER DESIGN

A. Design CriteriaWiMAX requires a good compromise between linearity and

efficiency. The power amplifier design unit consists of a driver stage and a power stage in cascade. Three of these units are then connected in parallel, to provide high output power with good linearity. The driver stage is designed to have a gain of approximately 20 dB, while the power stage adds approximately 8 dB. By power combination using transformers, the PA manages to obtain approximately 30 dBm P1dB when lossy inductors and capacitors are taken into account. We decided to use the cascode topology for every elementary stage, since this topology provides a good output power for realistic biasing conditions without pushing any transistor into breakdown.

B. Design choices for the driver stage (2.4GHz)The driver stage is chosen to be a differential stage. The

differential stage has a very good common mode noise rejection capability as compared to other topologies. Another advantage of the differential topology is the reduction of even harmonics at the output, improving linearity. The power supply chosen is 3.2 V, which is standard in CMOS Power Amplifier cascode designs. From the literature, common biasing conditions for a cascode

stage are 0.6 V at the lower stage and 2.5 V at the upper stage. From this starting point, we perform loadline analysis using baluns at the input and output to transform the signal from single ended to differential then back to single ended again. We decide to bias for a tradeoff between linearity and efficiency in class AB, with resulting optimal biases of 0.54V and 2.2V. Loadline analysis is performed according to:

Ropt=(Vds|max−Vknee ) /Ids∨maxPout=¿¿

Iterative loadpull and sourcepull measurements lead to:

Zload=3.7+ j∗20.618Zsource=10+ j∗69.5

Fig. 5 shows the driver stage. The devices sizes are L=0.18 µm and W=1000 µm. Frequency traps are used to extract the third harmonics from the output. A 0.3nH inductor with a Q of 50 is used at the source connection to ground to take into account bondwire degeneration effects. RF chokes of a value of 1 µH are used at the drains to provide isolation between DC and AC components and the appropriate 3.2V bias. A transformer based balun is used to convert the signal from single ended to differential while and to partially transform the impedance seen from the input of the driver stage.

Fig. 5 Schematic of driver stage

C. Design choice for power stage (2.4GHz) The power stage consists of a parallel combination of cascode structures with the lower transistor sized at L=0.18 µm, W= 4000 µm, while the upper stage at W=4000 µm, L=0.35 µm. This increases the robustness and reliability of the system, since the outer stage can now withstand voltage sweeps up to 7V. The cascode structure also provides relative input/output independence in load/source impedance matching since the Miller capacitor that usually connects input and output of a common source stage is now connected to a common gate stage.Loadline analysis is performed according to:

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ECE 6420 – Final Design Project – Group 7

Ropt=(Vds|max−Vknee ) /Ids∨maxPout=¿¿

Iterative loadpull and sourcepull measurements lead to:

Zload=28.86− j∗1.65Zsource=4− j∗18.3

A degeneration 0.3nH inductor with a Q of 50 models bondwires degeneration effects. From the image, we notice that the required bias is provided using resistors: this choice is used only during simulations, but in the final product a separate bias network will provide the necessary bias.Since three stages are connected in parallel, transformers are used for power combining. The transformers can also be used for impedance matching of the real part of the impedance. Fig. 6 shows the schematic of the power stage. A balun is used at the input to convert the differential output of the driver stage to two single ended inputs, to be given to the two parallel cascode stages.

Fig. 6 Schematic of the power stage

D. Design StepsThe main steps used in the design process of the power amplifier were loadline analysis, and iterative load and source pull simulations. Agilent ADS was used for the optimization of the design. These steps are partially performed for each block of the power amplifier, as well as for the entire power amplifier. In particular, from loadpull and sourcepull measurements we obtain that the optimal load impedance for the driver stage and the optimal source impedance for the power stage could be made one the complex conjugate of the other with less than 2 dBm loss at the cascaded output. This enables us not to implement any interstage matching network and connect the two stages directly, for the sake of design and implementation simplicity. We based this choice on loadpull and sourcepull measurements without having the time to actually implement lossy matching networks and compare the results for the two cases.Overall, the results given by the loadpull and sourcepull measurements are taken as a starting point for the design and parameters tuning is necessary to achieve best linearity with the best output power. Matching of the real part of the load and the

source can be partially done using the power combining transformers, as shown in fig.7.

Fig.7 Balun

The impedance transformation from the double branch to the single branch follows the following (the opposite holds in the other direction):

ZoutZin

=( NsecNprim )

2

For example, as the single branch has a fixed number of turns equal to 1, setting the number of turns for the double branch equal to 2 will result in upsizing the seen impedance by a factor of 4. A downsizing is possible by by reducing the number of the double branch windings.This reduces the need for sharp integrated components. Fig. 5 shows the entire power amplifier design, with input and output matching networks. The matching networks are implemented using non ideal components (inductors with Q of 15 and capacitors with Q of 100). Introduction of non ideal components makes the matching trickier as non convergence issues are experienced during H1B and H2B tone simulations.

Fig. 8 The 2.4 GHz PA with matching networks

E. Additional 3.5 GHz Power AmplifierAn additional 3.5 GHz Power amplifier is designed using the same architecture to implement dual band functionality. The schematic is shown in Fig. 9. Frequency traps are used to filter out the third harmonics so as to improve the linearity. Load line analysis is performed followed by iterative load and source pull simulations. Matching networks are then designed for maximum power transfer and stability. The same procedure is followed for this design, which represents an addendum to the PA to improve versatility. The new PA is not able to behave equally well in comparison with the 2.4 GHz version, possibly due to lack of time for its design optimization.

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ECE 6420 – Final Design Project – Group 7

Fig. 9 Schematic for the 3.5 GHz Power amplifier with source and load matching networks

IV. ADDITIONAL CIRCUITS

A. Bias circuitsBias networks are an important part of the RF circuit design. A

good bias network is capable of providing stable sub voltages by utilizing a single input power supply, thus reducing the pin count and the package size.The bias network determines the amplifier performance over temperature as well as the RF drive. The DC bias condition is usually determined independently of the RF design. Power efficiency, stability, noise, thermal runway, and ease to use are the main concerns when selecting a bias configuration.A transistor amplifier must possess a DC biasing circuit for a couple of reasons. We would require two separate voltage supplies to furnish the desired class of bias for both the common gate and the base gate voltages. This is in fact still done in certain applications, but biasing was introduced so that these separate voltages could be obtained from a single supply voltage. Transistors are remarkably temperature sensitive, their threshold voltage changing with temperature: this causes an undesirable change at the drain and source of the MOSFET from which we get the desired bias voltages, unless the amplifier is temperature stabilized to nullify this effect.The schematic of the bias circuit is shown in fig.10. A passive bias circuit approach using resistors can load the amplifier creating extra losses and add source or emitter inductance. The best practice is to directly ground the source for microwave amplifiers. But, grounding the source leaves the devices wide open to DC bias problems such as temperature drift of the bias point for FETs. So, an active feedback circuit as shown below is used. A simple approach utilizing a PMOS transistor is frequently more efficient. The equations governing the bias network are the following:

V g=V DD( R 2R 1+R 2 )−V d1

V d 1=¿ V th¿

V out 1=V DD( R 2R 1+R 2 )

V out 2=I ds∗R 4

The above equations are used to calculate the values of the resistors employed in the biasing circuit. Also a RFC choke comprising of an inductor of value 4nH in series and a capacitor in parallel connected to ground is used to provide an isolation for the biasing circuits from the RF circuits.

As can be seen from the schematic, there is a diode connected MOSFET used in the circuit. This is used for providing temperature compensation. As seen in the equations above if there is a change in temperature (which causes an equal change in the threshold voltage) the forward active voltage of the diode connected MOSFET will reduce or try to cancel this deviation, giving an almost constant stable output voltage. The precision of this voltage in temperature cannot be compared to the precision offered by voltage references, but still can be considered a first implementation for our chip.

Fig. 10 Schematic for the bias networks

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ECE 6420 – Final Design Project – Group 7Fig. 11 Transient Response results for the bias circuit

Fig. 12 DC response of the system vs. a temperature sweep

B. Combining CircuitThis design implements power combination using both parallel combination (PCT) and series combination (SCT). In the power stage, the two stages are combined using PCT, which has a power combination ratio that depends on windings, load impedance and source/load series resistances R1 and R2 by:

PCR=M 2(N 1

N 2 )2

Rload

R 1+M ( N 1N 2 )

2

( R 2+Rload )

where M is the number of combined stages. On the other hand, the three sub-Pas are globally combined using SCT, which power combination ratio is:

PCR=( N 1

N 2 )2

Rload

R 1+( 1M

)( N 1N 2 )

2

(R 2+Rload )

At the inter-stage level, a secondary number of turns equal to 2 is chosen in order not to modify the impedance seen by the two stages, as discusses in the previous sections. At the source level and at the load level, the number of windings is chosen based on simulation data during loadpull and sourcepull as well as H1B tone simulations results, in order to maximize to maximum linear output power.Additionally, LC-lattice type balun combiners were investigated to combine the output power of the three sub-stages. Following the equations:

Po=V o

2

Rload

ωo2= 1

(L¿¿m Cm)¿

we implemented the combiner, but we experienced difficulties in using the LC-balun combiner together with the input/output matching networks during the simulations. Hence, the design was implemented using transformers. We set the coupling efficiency K to 1 but we wanted to limit to inductance of the transformer to 2 nH, as this is the common upper limit for integrated transformers in planar CMOS technology (i.e. if no MEMS are used).

Fig. 13 Investigated combining networks

C. Switching CircuitSince a dual-band power amplifier was implemented, a switch

is required to switch between the power amplifiers depending on the selected transmission frequency band. Figure 14 below shows the switching circuit implemented in this design.

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ECE 6420 – Final Design Project – Group 7

Fig. 14 Switching circuit

A binary input signal is received from the local logic processor. The input signal is 0V if the communication frequency is 2.4 GHz, and 3.2V if the communication frequency is 3.5 GHz. Therefore the PMOS is turned ON for the 2.4 GHz communication frequency and the NMOS is turned ON for the 3.5 GHz communication frequency. A current controlled voltage source is connected to the drain of the PMOS and another to the source of the NMOS. Therefore, when a particular MOSFET is turned ON, the current controlled voltage source connected to the MOSFET will have 3.2V across it. This voltage source behaves as the VDD to the power amplifiers. Therefore if the 2.4 GHz communication frequency is selected, the VDD for the 2400PA would be 3.2V while the VDD for the 3500PA would be 0V. Implementing this design using power mosfets would be a possible design improvement.

V. PACKAGING

Amkor FlipChip technology is used in this design because of its high quality properties. This package family is specifically targeted for RF applications and the mobile handsets market, due to its low thermal resistance and low bondwire inductance added to each I/O pin. The PA is then expected to work very similarly to the original design even after packaging. Since bondwires add to the inductance as a function of their length and diameter thickness, by using the flipchip fcCSP1 their impact is reduced. Flipchip does not involve interconnection between the die and the package carrier using bond wires. Instead, the connection is made through a conductive bump that is placed directly on the die surface. The bumped die is then flipped over and placed face down, with the bumps connecting to the carrier directly. A bump is typically 70-100 μm high, and 90-125 μm in diameter. The advantages of Flip Chip over bond wires are reduced signal inductance, high signal density, die shrink and reduced package footprint. The identified package is 8mm by 8mm in size and can accommodate a maximum die size of 7 by 7 mm, which is compatible with this design. As far as thermal power dissipation considerations are concerned, the 2.4 GHz power amplifier dissipates around 3W (worst case condition in linear regime) while 4.5W (worst case condition in linear regime) are dissipated by the 3.5 GHz power amplifier. Amkor’s fcCSP1 has a thermal resistance (Rt) of 21.3˚C/W.

By following the next equation:

Rt=Tj−TaPdis

Tj = Junction temperature, limited to 125 °CTa = Ambient temperature (we have considered a temperature

range from 0 to 85 ˚C)Pdis = Power dissipated

This give a power dissipation range of 2W to 5.8W (assuming that the PCB is an ideal heat sink). To operate in complete reliability, the maximum ambient temperature for which the PA can transmit at full power at 2.4 GHz is 61.1 °C, which reduces to 29 °C for the 3.5 GHz model. However, if we consider the maximum output power for which the 3% EVM condition is satisfied, there are no constraints since the PA have now a limited output power and the dissipation is much lower (reliable operation from 0 to 85 °C).As far as floor plan and die considerations are concerned, a rough die size can be estimated with the assumption of multi-finger transistor layout. The driver stage has transistors with W/L of 1000µm/0.18µm. The power stage has transistors with sizes W/L of 4000µm/0.18µm and W/L = 4000µm/0.35µm. The estimated size of the die is 3mm x 3mm, as shown in Fig. 15.In the driver stage, each transistor can be designed with 40 fingers each 25 µm wide 0.18 µm long, so that a driver stage would approximately occupy an area of 60 µm by 20 µm. Since we have 3 drivers, the total driver area would be 60 by 60 µm. For the power stage, each transistor would occupy a 100 by 20 µm area using 40 fingers layout (worst case).The three power stages would then account for an approximate area of 250 by 150 µm. Assuming a similar reasoning for the 2.4 and the 3.5 GHz PAs, and estimating an output transformer size of 1mm by 400 µm, an input transformer size of 250 by 400 µm and accounting for on size matching networks and a shared bias circuitry for both PAs, the total area estimation would be around 1600 µm by 800 µm. By adding guard rings, bond pads for I/O pins and by letting some isolation space between critical sections, the worst case die size is estimated to be 3 by 3 mm.

Fig. 15 Estimated die aspect, size and floor plan

Our design needs at most three pin types: ground, 3.2V Vdd, RF input, RF output. At this high level the pin schematic is simple,

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ECE 6420 – Final Design Project – Group 7but electromagnetic and thermal simulations and considerations would be necessary in order to decide where to distribute the pins in a multiple fashion. Ground and Vdd would be distributed using multiple pins, to increase voltage distribution uniformity and reduce the amount of current flowing through every single pin/pad. RF input and output signal would require a single pad, due to signal integrity considerations. The 3.2V bias should be provided to the chip from the exterior using off chip power inductors, like the MDT2012-CR from Toko, which has the required inductance (1 µH) and can withstand currents up to 1.55 A (our PAs require about 1 A in linear region).

VI. RESULTS

Results are schematically shown in table IV and they are compared to two PAs present on the market from Anagidics and Triquint. Some specifications are missing for the market products, but the comparison holds. The designed PA can compete against these products, at least on a schematic simulation level. However, the produced chip is expected to have worse performances. The linearity of the 2.4 GHz model is quite good and EVM at 3% is obtained for an output power level of 23.5 dBm, which is less than expected. The 3.5 GHz model only reaches 12 dBm output power with EVM at 3%. The reason for this results is the phase shift introduced on the output signal: this design has a very good gain compression for both bands, but the AM-PM distortion is high. We could not improve this parameter no matter our efforts. One possible reason is the NMOS capacitance Cgs primarily at the input of the power stage. This capacitance is a function of the bias point, which is variable for class AB amplifiers. The biggest change in the capacitance takes place for the transistor changing from saturation to triode region and could be counterbalanced by using a varactor-connected PMOS.

TABLE IVResults comparison

2.4 GhZ PA

3.5 GHz PA Triquint Anagidics

Current P1dB 1.4 A 1.855 A - -

Current B 0.9 A 1.4 A - -

Current Idle 0.75 A 0.7 A - -

PAE B 21.5 % 18% 20% -

PAE B-5dB 9% 9.5% - -

PAE B-10dB 3% 4% - - Absolute

Gain 29 dB 22.5 dB - 30 dB

Δ Gain -3dB -3.9 dB - -Linear Output

Power (-0.25m) 28.15 dBm 29.74 dBm - -

P1dB 30.71 dBm 30.53 dBm 29.8 dBm 30 dBm

EVM 3% 23 dBm 12 dBm 23 dBm 25 dBm

Stability K>100 K>100 Stable Stable

Bias 3.2 V 3.2 V 5 V 3-5 V

Band2.3 – 2.5

GHz3.4-3.6 GHz

2.3-2.4 GHz

2.3-2.5 GHz

A. Results (2.4GHz)Results for the PA are shown in detail in the provided attachment. Here we show just the most significative plots. The waveform at the output is shown in fig.16. Note that the voltage swing goes from -12 V to 12 V with the input test signal and a gain of 29 dB, but the output voltage is derived from the combination of three stages, that share the swing equally. Moreover, each sub-PA consists of two output power stages in parallel, with the last transistor 0.35 µm thick in length. The operation is then safe.AM-AM distortion is very small, but it can be seen that a phase shift is present on the output waveform.

Fig. 16 Output voltage waveform

Fig. 17 Gain

Gain is very linear up to an output power of approximately 30 dBm. The third harmonic and the first harmonic behavior are shown next.

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ECE 6420 – Final Design Project – Group 7

Fig. 18 Principal harmonic content

Gain compression and phase distortion are shown in the next images. EVM is also plotted against a custom power index and reaches 3% at about -8 dBm, which corresponds to approximately 23 dBm output power. Any additional detail about H1Btone simulation and H2Btone simulation, matching networks details and EVM testing can be found in the addendum and in the provided zap files.The 2.4 GHz PA is also tested for compliance with the WiMAX spectrum mask and the result is shown in fig 18. According to fig. 1, the PA respects the spectrum limitations for WiMAX, since the attenuation of the adjacent channels are sufficiently high enough.

Fig. 19 Gain compression

Fig. 20 Phase distortion

The EVM variation as an indirect function of input power is shown in the next figure:

Fig. 21 EVM degeneration

The 2.4 GHz PA can be considered our main design, while the 3.5 GHz an application to see if the same structure could have been used for a different band, with the necessary tuning. Due to lack of time, we cannot say if the structure could be successfully adapted for the 3.5 GHz band, since as it is now, it is not employable as a WiMAX product. The output power at which the EVM is 3% or less is too low, and doesn’t satisfy the requirements for WiMAX at the antenna.

PAE also is too low at those conditions.

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ECE 6420 – Final Design Project – Group 7

Fig. 22 WiMAX mask compliance

B. Results (3.5GHz)Detailed results for this PA can be found in the provided .zap files.

VII. LIMITATIONS AND POSSIBLE IMPROVEMENTS

The linearity of the PA can be improved and techniques to reduce the phase distortion should be introduced and implemented. As mentioned, the PMOS exhibits an opposite behavior of its Cgs capacitance as a function of gate voltage and could be used to counterbalance the Cgs variation of the input NMOS of the power stage.Additionally, the non idealities of the transformers should be better implemented, since a coupling factor K=1 was used in the design. Each transformer should include a series resistance of a few Ohms and a capacitance of a few fF to ground, for taking into account the parasitic effects to the substrate. Moreover, several coupling capacitors and additional resistances should be included. Finally, we would like to optimize the dual band aspect of the PA by improving and optimizing the design of the 3.5 GHz version, also trying different topologies and improved linearization techniques. Especially considering the market analysis, a product compatible with the two most widespread bands would have a much greater chance to gain market share.In conclusion, we would like to remark that we did try to include a linearization system to improve the overall performances of the PA, specifically digital predistortion. However, by using the ADS template, we encountered major difficulties for convergence and the required time for simulations was too high.

VIII.CONCLUSION

We successfully implemented a dual band CMOS PA with a two stage cascode amplifier topology and have met the requirements for the 2.4 GHz band, while missing the requirements in the 3.5 GHz band.

REFERENCES

[1] Ping Li, ”Overview of WiMAX system and related power amplifier deisgn”, ICSICT 2008

[2] Kyu Hwan, “Power-Combining Transformer Techniques for Fully-Integrated CMOS Power Amplifiers, IEEE JSSC 2008

[3] Kyu Hwan An, “A 2.4GHz Fully Integrated Linear CMOS Power Amplifier With Discrete Power Control”

[4] B. Smith, “An approach to graphs of linear forms (Unpublished work style),” unpublished.

[5] Bias Circuit Design for Microwave Amplifiers, UCSB ECE[6] ……

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