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TRANSCRIPT
AUTOMATIC INTELLIGENT ROOM
LIGHT CONTROLLER USING 89S52
MICROCONTROLLER WITH AUTO
DOOR OPENING/CLOSING
1
CONTENTS
DESCRIPTION PAGE NO.1. CERTIFICATE
2. ABSTRACT 53. TECHNICAL SPECIFICATIONS 7
4. LIST OF FIGURES 9
5. LIST OF TABLES 9
6. BLOCK DIAGRAM OF 89S52 10
7. BLOCK DIAGRAM OF POWER SUPPLY 10
CHAPTER1: INTRODUCTION 12
CHAPTER2: POWER SUPPLY 15
2.1 Transformer 15
2.2 Rectifier 16
2.3 Filter 16
2.4 Voltage Regulator 16
CHAPTER 3: MICRO CONTROLLER 17
3.1 Features of AT89S52 19
3.2 Description 19
3.3 Pin Diagram 20
3.4 Pin Description 20
3.5 Machine Cycle for 8051 21
CHAPTER 4: SOFTWARE COMPONENTS 24
4.1 Keil Compiler
4.2 Proload
CHAPTER 5: IR SECTION 26
2
5.1 What is an Infrared
27
5.2 IR in Electronics 28
5.3 IR Generator 28
5.4 Rc-5 30
5.5 IR Receiver 31
5.5.1 Description
5.5.2 Features
5.5.3 Suitable Data Format
CHAPTER 6: ULN 2003 CURRENT DRIVER 35
CHAPER 7: STEPPER MOTOR 38
7.1 Advantages 40
7.2 Disadvantages 41
7.3 Open Loop Operation 41
7.4 Stepper Motor Types 41
7.5 Variable Reluctance (Vr) 41
7.6 Permanent Magnet 42
7.7 Hybrid (Hb) 43
7.8 When to Use Stepper Motor 43
7.9 Rotating Magnetic Field 44
7.10 Torque Generation 45
7.11 Step Angle Accuracy 45
7.12 Torque versus Speed Characteristics 46
7.13 Single Step Response and Resonance 46
7.14 Few Definitions of Stepper Motor 47
7.15 Stepper Motor Interfacing with Microcontroller 48
3
CHAPTER 8: RELAYS 49
8.1 Operation 50
8.2 Driving a Relay 52
8.3 Relay Interfacing with Microcontroller 53
CHAPTER 9 DISPLAY COMPONENTS 54
9.1 Light Dependent Resistor 55
9.2 Liquid Crystal Device 55
9.2.1 Pin Function
9.2.2 LCD Screen
9.2.3 LCD Basic Commands
9.2.4 LCD Connections
9.2.5 LCD Initialization
9.2.6 LCD Interfacing with Microcontroller
CHAPTER 10: SWITCH & LED INTERFACING WITH 63
MICROCONTROLLER
10.1 Switch Interfacing 64
10.2 LCD Interfacing 65
CHAPTER 11: WORKING PROCEDURE OF PROJECT 68
CHAPTER 12: ALGORITHM 71
CHAPTER 13: FLOWCHART 73
CHAPTER 14: PROGRAM 75
CHAPTER 15: ADVANTAGES & APPLICATIONS 88
CONCLUSION 91
RESULTS 93
REFERENCES 95
4
5
ABSTRACT
6
ABSTRACT
In this competitive world and busy schedule human cannot spare time to perform
his daily activities manually. The most common thing that he forgets to do is switching
OFF the lights wherever they are not required. This project is a standalone automatic
room light controller with auto door opening and closing. The main aim of the project is
to control the lighting in a room depending upon lighting that is present in the room. Use
of embedded technology makes this closed loop feedback control system efficient and
reliable. Micro controller (AT89S52) allows dynamic and faster control. Liquid crystal
display (LCD) makes the system user-friendly. AT89S52 micro controller is the heart of
the circuit as it controls all the functions.
The system comprises of two IR Transmitter-Receiver pairs, one of which is
located in front of the door outside the room. The other pair is located inside the room.
LDR is placed outside the room and is used to identify whether it is day or night time.
Initially the light is switched off in the room. Whenever a person tries to enter into the
room, the receiver of first IR pair identifies the person. Then the microcontroller opens
the door by rotating the stepper motor. After the person had entered into the room
completely, the door will be closed automatically.
The light is switched off even if anyone is present inside the room during the day
time. Similarly, the light is switched off if no one is there inside the room or if it is night
times. Thus, depending on the intensity of light and the surrounding temperature, the
required action is performed by the microcontroller. LCD displays the number of persons
present inside the room.
This project uses regulated 5V, 500mA power supply. 7805 three terminal voltage
regulator is used for voltage regulation. Bridge type full wave rectifier is used to rectify
the ac out put of secondary of 230/12V step down transformer.
7
TECHNICAL SPECIFICATIONS
8
TECHNICAL SPECIFICATIONS
Title of the project : Automatic Intelligent Room Light Controller using
89S52 MCU with auto door opening/closing
Domain : Embedded Systems Design
Software : Embedded C, Keil, Proload
Microcontroller : AT89S52
Power Supply : +5V, 500mA Regulated Power Supply
Display : LCD
LCD : HD44780 16-character, 2-line (16X2)
LED : 5mm
Crystal : 11.0592MHz
Sensor : IR Sensors
9
LIST OF FIGURES
DESCRIPTION PAGE NO 1. BLOCK DIAGRAM OF 89S52 8
2. BLOCK DIAGRAM OF POWER SUPPLY 8
3. POWER SUPPLY 10
4. PIN DIAGRAM OF 8051 14
5. BLOCK DIAGRAM OF IR RECEIVER 24
6. APPLICATION CIRCUIT FOR IR receiver 24
7. DIP 16 PACKAGE 26
8. PIN CONNECTION OF ULN2003 27
9. STEPPER MOTOR 28
10. STEPPER MOTOR OPERATION 29
11. CROSS SECTION OF VARIABLE RELUCTANCE MOTOR 31
12. PM STEPPER MOTOR PRINCIPLE 32
13. CROSS SCETION OF HYBRID STEPPER MOTOR 32
14. MAGNETIC FLUX PATH TO A 2POLE STEPPER MOTOR WITH LAG 33
BETWEEN ROTOR &STATOR
15. POSITIONAL ACCURACY OF STEPPER MOTOR 35
16. TORQUE VS SPEED CHARACTERISTICS 35
17. SINGLE STEP RESPONSE VS TIME 36
18. CIRCUIT SYMBOL OF A RELAY 38
19. RELAY OPERATION &USE OF PROTECTION DIODES 39
20. PROCEDURE ON 8BIT INITIALIZATION 48
21. INTERFACING SWITCH WITH MICROCONTROLLER 50
22. LED INTERFACING WITH MICRO CONTROLLER 52
23. SCHEMATIC DIAGRAM 54
LIST OF TABLES
1. PORT3 ALTERNATE FUNCTION 17
10
2. STEPPER MOTOR STEP ANGLE 36
3. LIST COMMANDS WHICH LCD RECOGNISES 45
BLOCK DIAGRAM
11
BLOCK DIAGRAM OF 89S52
Fig1: Block Diagram Of Automatic room light control
BLOCK DIAGRAM OF POWER SUPPLY:
12
EXIT SENSOR IR
89S52
STEPPER
MOTOR 1
ULN 2003
Step down T/F
Bridge Rectifier
Filter Circuit Regulator
CRYSTAL
RESETCIRCUIT
STEPPER MOTOR 2
ENTRY SENSOR IR
LDR
LCD
Fig2: Block Diagram Of Power Supply
CHAPTER -1
13
Power supply to all sections
INTRODUCTION
An embedded system is a combination of software and hardware to perform a dedicated
task.
Some of the main devices used in embedded products are Microprocessors and
Microcontrollers.
Microprocessors are commonly referred to as general purpose processors as they simply
accept the inputs, process it and give the output.
In contrast, a microcontroller not only accepts the data as inputs but also manipulates it,
interfaces the data with various devices, controls the data and thus finally gives the result.
As everyone in this competitive world prefer to make the things easy and simple to
handle, this project sets an example to some extent.
In this busy and competitive world, human cannot spare time to do the things
manually. He tries to atomize the things around him up to a maximum extent. There are
many techniques to automize the things around at the best level. One of the efficient
techniques to automize the things in an easy way is through this project.
14
CHAPTER-2
15
POWER SUPPLY
The input to the circuit is applied from the regulated power supply. The a.c. input i.e.,
230V from the mains supply is step down by the transformer to 12V and is fed to a
rectifier. The output obtained from the rectifier is a pulsating d.c voltage. So in order to
get a pure d.c voltage, the output voltage from the rectifier is fed to a filter to remove any
a.c components present even after rectification. Now, this voltage is given to a voltage
regulator to obtain a pure constant dc voltage.
Fig3:Power Supply
2.1Transformer:
Usually, DC voltages are required to operate various electronic equipment and
these voltages are 5V, 9V or 12V. But these voltages cannot be obtained directly. Thus
the a.c input available at the mains supply i.e., 230V is to be brought down to the
16
RegulatorFilter
Bridge
Rectifier
Step down
transformer
D.C
Output
230V AC 50Hz
required voltage level. This is done by a transformer. Thus, a step down transformer is
employed to decrease the voltage to a required level.
2.2Rectifier:
The output from the transformer is fed to the rectifier. It converts A.C. into
pulsating D.C. The rectifier may be a half wave or a full wave rectifier. In this project, a
bridge rectifier is used because of its merits like good stability and full wave rectification.
2.3Filter:
Capacitive filter is used in this project. It removes the ripples from the output of
rectifier and smoothens the D.C. Output received from this filter is constant until the
mains voltage and load is maintained constant. However, if either of the two is varied,
D.C. voltage received at this point changes. Therefore a regulator is applied at the output
stage.
2.4Voltage regulator:
As the name itself implies, it regulates the input applied to it. A voltage
regulator is an electrical regulator designed to automatically maintain a constant voltage
level. In this project, power supply of 5V and 12V are required. In order to obtain these
voltage levels, 7805 and 7812 voltage regulators are to be used. The first number 78
represents positive supply and the numbers 05, 12 represent the required output voltage
levels.
17
CHAPTER-3
18
MICROCONTROLLERS
Microprocessors and microcontrollers are widely used in embedded
systems products. Microcontroller is a programmable device. A microcontroller has a
CPU in addition to a fixed amount of RAM, ROM, I/O ports and a timer embedded all on
a single chip. The fixed amount of on-chip ROM, RAM and number of I/O ports in
microcontrollers makes them ideal for many applications in which cost and space are
critical.
The Intel 8051 is a Harvard architecture, single chip microcontroller (µC) which
was developed by Intel in 1980 for use in embedded systems. It was popular in the 1980s
and early 1990s, but today it has largely been superseded by a vast range of enhanced
devices with 8051-compatible processor cores that are manufactured by more than 20
independent manufacturers including Atmel, Infineon Technologies and Maxim
Integrated Products.
8051 is an 8-bit processor, meaning that the CPU can work on only 8 bits
of data at a time. Data larger than 8 bits has to be broken into 8-bit pieces to be processed
by the CPU. 8051 is available in different memory types such as UV-EPROM, Flash and
NV-RAM.
The microcontroller used in this project is AT89S52. Atmel Corporation
introduced this 89S52 microcontroller. This microcontroller belongs to 8051 family. This
microcontroller had 128 bytes of RAM, 4K bytes of on-chip ROM, two timers, one serial
port and four ports (each 8-bits wide) all on a single chip. AT89S52 is Flash type 8051.
The present project is implemented on Keil Uvision. In order to program the
device, Proload tool has been used to burn the program onto the microcontroller.
19
The features, pin description of the microcontroller and the software tools used
are discussed in the following sections.
3.1 FEATURES OF AT89S52:
4K Bytes of Re-programmable Flash Memory.
RAM is 128 bytes.
2.7V to 6V Operating Range.
Fully Static Operation: 0 Hz to 24 MHz.
Two-level Program Memory Lock.
128 x 8-bit Internal RAM.
32 Programmable I/O Lines.
Two 16-bit Timer/Counters.
Six Interrupt Sources.
Programmable Serial UART Channel.
Low-power Idle and Power-down Modes.
3.2Description:
The AT89S52 is a low-voltage, high-performance CMOS 8-bit microcomputer
with 4K bytes of Flash programmable memory. The device is manufactured using
Atmel’s high-density nonvolatile memory technology and is compatible with the
industry-standard MCS-51 instruction set. By combining a versatile 8-bit CPU with Flash
20
on a monolithic chip, the Atmel AT89S52 is a powerful microcomputer, which provides
a highly flexible and cost-effective solution to many embedded control applications.
In addition, the AT89S52 is designed with static logic for operation down to zero
frequency and supports two software selectable power saving modes. The Idle Mode
stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system
to continue functioning. The power-down mode saves the RAM contents but freezes the
oscillator disabling all other chip functions until the next hardware reset.
3.3PIN DIAGRAM:
Fig4: Pin diagram of 8051
21
3.4PIN DESCRIPTION:
Vcc:
Pin 40 provides supply voltage to the chip. The voltage source is +5V.
GND:
Pin 20 is the ground.
XTAL1 and XTAL2:
The 8051 has an on-chip oscillator but requires an external clock to run it.
Usually, a quartz crystal oscillator is connected to inputs XTAL1 (pin19) and XTAL2
(pin18).
There are various speeds of 8051 family. Speed refers to the maximum oscillator
frequency connected to XTAL. When the 8051 is connected to a crystal oscillator and is
powered up, the frequency can be observed on the XTAL2 pin using the oscilloscope.
RESET:
Pin9 is the reset pin. It is an input and is active high. Upon applying a high pulse
to this pin, the microcontroller will reset and terminate all the activities. This is often
referred to as a power-on reset.
EA (External access):
Pin 31 is EA. It is an active low signal. It is an input pin and must be connected to
either Vcc or GND but it cannot be left unconnected.
22
The 8051 family members all come with on-chip ROM to store programs. In
such cases, the EA pin is connected to Vcc. If the code is stored on an external ROM, the
EA pin must be connected to GND to indicate that the code is stored externally.
PSEN (Program store enable):
This is an output pin.
ALE (Address latch enable):
This is an output pin and is active high.
Ports 0, 1, 2 and 3:
The four ports P0, P1, P2 and P3 each use 8 pins, making them 8-bit ports. All
the ports upon RESET are configured as input, since P0-P3 have value FFH on them.
Port 0(P0):
Port 0 is also designated as AD0-AD7, allowing it to be used for both address and
data. ALE indicates if P0 has address or data. When ALE=0, it provides data D0-D7, but
when ALE=1, it has address A0-A7. Therefore, ALE is used for demultiplexing address
and data with the help of an internal latch.
When there is no external memory connection, the pins of P0 must be connected
to a 10K-ohm pull-up resistor. This is due to the fact that P0 is an open drain. With
external pull-up resistors connected to P0, it can be used as a simple I/O, just like P1 and
P2. But the ports P1, P2 and P3 do not need any pull-up resistors since they already have
pull-up resistors internally. Upon reset, ports P1, P2 and P3 are configured as input ports.
Port 1 and Port 2:
23
With no external memory connection, both P1 and P2 are used as simple I/O.
With external memory connections, port 2 must be used along with P0 to provide the 16-
bit address for the external memory. Port 2 is designated as A8-A15 indicating its dual
function. While P0 provides the lower 8 bits via A0-A7, it is the job of P2 to provide bits
A8-A15 of the address.
Port 3:
Port 3 occupies a total of 8 pins, pins 10 through 17. It can be used as input or
output. P3 does not need any pull-up resistors, the same as port 1 and port 2. Port 3 has an
additional function of providing some extremely important signals such as interrupts.
Table1: Port 3 Alternate Functions
3.5Machine cycle for the 8051:
24
The CPU takes a certain number of clock cycles to execute an instruction. In the
8051 family, these clock cycles are referred to as machine cycles. The length of the
machine cycle depends on the frequency of the crystal oscillator. The crystal oscillator,
along with on-chip circuitry, provides the clock source for the 8051 CPU.
The frequency can vary from 4 MHz to 30 MHz, depending upon the chip rating
and manufacturer. But the exact frequency of 11.0592 MHz crystal oscillator is used to
make the 8051 based system compatible with the serial port of the IBM PC.
In the original version of 8051, one machine cycle lasts 12 oscillator periods.
Therefore, to calculate the machine cycle for the 8051, the calculation is made as 1/12 of
the crystal frequency and its inverse is taken.
CHAPTER-4
25
Software components
4.1KEIL COMPILER:
Keil compiler is a software used where the machine language code is written and
compiled. After compilation, the machine source code is converted into hex code which
is to be dumped into the microcontroller for further processing. Keil compiler also
supports C language code.
4.2PROLOAD:
Proload is a software which accepts only hex files. Once the machine code is
converted into hex code, that hex code has to be dumped into the microcontroller and this
is done by the Proload. Proload is a programmer which itself contains a microcontroller
in it other than the one which is to be programmed. This microcontroller has a program in
it written in such a way that it accepts the hex file from the keil compiler and dumps this
hex file into the microcontroller which is to be programmed. As the proload programmer
kit requires power supply to be operated, this power supply is given from the power
supply circuit designed above. It should be noted that this programmer kit contains a
power supply section in the board itself but in order to switch on that power supply, a
source is required. Thus this is accomplished from the power supply board with an output
of 12volts.
26
CHAPTER-5
27
IR SECTION
5.1 WHAT IS INFRARED?
Infrared is a energy radiation with a frequency below our eyes sensitivity, so we
cannot see it.
Even that we can not "see" sound frequencies, we know that it exist, we can listen
them.
Even that we can not see or hear infrared, we can feel it at our skin temperature
sensors.
When you approach your hand to fire or warm element, you will "feel" the heat, but you
can't see it. You can see the fire because it emits other types of radiation, visible to your
eyes, but it also emits lots of infrared that you can only feel in your skin.
5.2 INFRARED IN ELECTRONICS
Infra-Red is interesting, because it is easily generated and doesn't suffer
electromagnetic interference, so it is nicely used to communication and control, but it is
not perfect, some other light emissions could contains infrared as well, and that can
interfere in this communication. The sun is an example, since it emits a wide spectrum or
radiation.
28
The adventure of using lots of infra-red in TV/VCR remote controls and other
applications, brought infra-red diodes (emitter and receivers) at very low cost at the
market.
From now on you should think as infrared as just a "red" light. This light can
means something to the receiver, the "on or off" radiation can transmit different
meanings. Lots of things can generate infrared, anything that radiate heat do it, including
out body, lamps, stove, oven, friction your hands together, even the hot water at the
faucet.
To allow a good communication using infra-red, and avoid those "fake" signals, it
is imperative to use a "key" that can tell the receiver what is the real data transmitted and
what is fake. As an analogy, looking eye naked to the night sky you can see hundreds of
stars, but you can spot easily a far away airplane just by its flashing strobe light. That
strobe light is the "key", the "coding" element that alerts us.
Similar to the airplane at the night sky, our TV room may have hundreds of tinny
IR sources, our body, and the lamps around, even the hot cup of tea. A way to avoid all
those other sources, is generating a key, like the flashing airplane. So, remote controls use
to pulsate its infrared in a certain frequency. The IR receiver module at the TV, VCR or
stereo "tunes" to this certain frequency and ignores all other IR received. The best
frequency for the job is between 30 and 60kHz, the most used is around 36kHz
5.3 IR GENERATION
To generate a 36kHz pulsating infrared is quite easy, more difficult is to receive
and identify this frequency. This is why some companies produce infrared receives, that
contains the filters, decoding circuits and the output shaper, that delivers a square wave,
meaning the existence or not of the 36kHz incoming pulsating infrared.
29
It means that those 3 dollars small units, have an output pin that goes high
(+5V) when there is a pulsating 36kHz infrared in front of it, and zero volts when there is
not this radiation.
A square wave of approximately 27uS (microseconds) injected at the base of a
transistor, can drive an infrared LED to transmit this pulsating light wave. Upon its
presence, the commercial receiver will switch its output to high level (+5V).If you can
turn on and off this frequency at the transmitter, your receiver's output will indicate when
the transmitter is on or off.
Those IR demodulators have inverted logic at its output, when a burst of IR is
sensed it drives its output to low level, meaning logic level = 1.
The TV, VCR, and Audio equipment manufacturers for long use infra-red at their
remote controls. To avoid a Philips remote control to change channels in a Panasonic
TV, they use different codification at the infrared, even that all of them use basically the
30
same transmitted frequency, from 36 to 50kHz. So, all of them use a different
combination of bits or how to code the transmitted data to avoid interference.
5.4 RC-5:
Various remote control systems are used in electronic equipment today. The RC5
control protocol is one of the most popular and is widely used to control numerous home
appliances, entertainment systems and some industrial applications including utility
consumption remote meter reading, contact-less apparatus control, telemetry data
transmission, and car security systems. Philips originally invented this protocol and
virtually all Philips’ remotes use this protocol. Following is a description of the RC5.
When the user pushes a button on the hand-held remote, the device is activated and sends
modulated infrared light to transmit the command. The remote separates command data
into packets. Each data packet consists of a 14-bit data word, which is repeated if the user
continues to push the remote button. The data packet structure is as follows:
2 start bits
1 control bit
5 address bits
6 command bits.
The start bits are always logic ‘1’ and intended to calibrate the optical receiver
automatic gain control loop. Next, is the control bit. This bit is inverted each time the
user releases the remote button and is intended to differentiate situations when the user
continues to hold the same button or presses it again. The next 5 bits are the address bits
and select the destination device. A number of devices can use RC5 at the same time. To
exclude possible interference, each must use a different address. The 6 command bits
describe the actual command. As a result, a RC5 transmitter can send the 2048 unique
commands. The transmitter shifts the data word, applies Manchester encoding and passes
the created one-bit sequence to a control carrier frequency signal amplitude modulator.
The amplitude modulated carrier signal is sent to the optical transmitter, which radiates
31
the infrared light. In RC5 systems the carrier frequency has been set to 36 kHz. Figure
below displays the RC5 protocol.
The receiver performs the reverse function. The photo detector converts optical
transmission into electric signals, filters it and executes amplitude demodulation. The
receiver output bit stream can be used to decode the RC5 data word. This operation is
done by the microprocessor typically, but complete hardware implementations are
present on the market as well. Single-die optical receivers are being mass produced by a
number of companies such as Siemens, Temic, Sharp, Xiamen Hualian, Japanese Electric
and others. Please note that the receiver output is inverted (log. 1 corresponds to
illumination absence).
5.5 IR RECEIVER
5.5.1 Description:The TSOP17.. – series are miniaturized receivers for infrared remote control
systems. PIN diode and preamplifier are assembled on lead frame, the epoxy package is
designed as IR filter.
The demodulated output signal can directly be decoded by a microprocessor.
TSOP17.. is the standard IR remote control receiver series, supporting all major
transmission codes.
5.5.2 Features: Photo detector and preamplifier in one package
Internal filter for PCM frequency
Improved shielding against electrical field disturbance
TTL and CMOS compatibility
Output active low
Low power consumption
High immunity against ambient light
Continuous data transmission possible (up to 2400 bps)
Suitable burst length .10 cycles/burst
32
Fig5: Block Diagram For IR Receiver
Fig6: Application Circuit For IR Receiver
5.5.3 Suitable Data Format
The circuit of the TSOP17 is designed in that way that unexpected output pulses
due to noise or disturbance signals are avoided. A bandpassfilter, an integrator stage and
an automatic gain control are used to suppress such disturbances. The distinguishing
mark between data signal and disturbance signal are carrier frequency, burst length and
duty cycle. The data signal should fulfill the following condition:
Carrier frequency should be close to center frequency of the bandpass (e.g.
38kHz).
Burst length should be 10 cycles/burst or longer.
33
After each burst which is between 10 cycles and 70 cycles a gap time of at least
14 cycles is necessary.
For each burst which is longer than 1.8ms a corresponding gap time is necessary
at some time in the data stream. This gap time should have at least same length as
the burst.
Up to 1400 short bursts per second can be received continuously.
Some examples for suitable data format are: NEC Code, Toshiba Micom
Format, Sharp Code, RC5 Code, RC6 Code, R–2000 Code, Sony Format (SIRCS). When
a disturbance signal is applied to the TSOP17.. it can still receive the data signal.
However the sensitivity is reduced to that level that no unexpected pulses will occur.
Some examples for such disturbance signals which are suppressed by the TSOP17 are:
DC light (e.g. from tungsten bulb or sunlight)
Continuous signal at 38 kHz or at any other frequency
Signals from fluorescent lamps with electronic ballast (an example of the
signal modulation is in the figure below).
34
Fig7: DIP 16 Package
35
CHAPTER-6
36
ULN2003 CURRENT DRIVER
The ULN2003 current driver is a high voltage, high current Darlington arrays
each containing seven open collector Darlington pairs with common emitters. Each
channel is rated at 500mA and can withstand peak currents of 600mA. Suppression
diodes are included for inductive load driving and the inputs are pinned opposite the
outputs to simplify board layout.
These versatile devices are useful for driving a wide range of loads including
solenoids, relays DC motors, LED displays filament lamps, thermal print heads and high
power buffers. This chip is supplied in 16 pin plastic DIP packages with a copper lead
frame to reduce thermal resistance.
37
Fig8: Pin Connection of ULN 2003
This ULN2003 driver can drive seven relays at a time. The pins 8 and 9 provide
ground and Vcc respectively.
The working of ULN driver is as follows:
It can accept seven inputs at a time and produces seven corresponding outputs. If
the input to any one of the seven input pins is high, then the value at its corresponding
output pin will be low, for example if the input at pin 6 is high, then the value at the
corresponding output i.e., output at pin 11 will be low. Similarly if the input at a
particular pin is low, then the corresponding output will be high.
38
CHAPTER -7
39
STEPPER MOTOR:
Fig9: Stepper motor
A stepper motor is a widely used device that translates electrical pulses into
mechanical movement. The stepper motor is used for position control in applications
such as disk drives, dot matrix printers and robotics.
Stepper motors commonly have a permanent magnet rotor surrounded by a stator.
The most common stepper motors have four stator windings that are paired with a center-
tapped common. This type of stepper motor is commonly referred to as a four-phase or
unipolar stepper motor. The center tap allows a change of current direction in each of the
two coils when a winding is grounded, thereby resulting in a polarity change of the stator.
The direction of the rotation is dictated by the stator poles. The stator poles are
determined by the current sent through the wire coils. As the direction of the current is
changed, the polarity is also changed causing the reverse motion of the rotor.
It should be noted that while a conventional motor shaft runs freely, the stepper
motor shaft moves in a fixed repeatable increment, which allows one to move it to a
precise position. Thus, the stepper motor moves one step when the direction of current
40
flow in the field coil(s) changes, reversing the magnetic field of the stator poles. The
difference between unipolar and bipolar motors lies in the may that this reversal is
achieved.
Fig10: Stepper motor operation
7.1 Advantages:
1. The rotation angle of the motor is proportional to the input pulse.
2. The motor has full torque at standstill (if the windings are energized)
3. Precise positioning and repeatability of movement since good stepper motors have an
accuracy of 3 – 5% of a step and this error is non cumulative from one step to the next.
4. Excellent response to starting/ stopping/reversing.
5. Very reliable since there are no contact brushes in the motor. Therefore the life of the
motor is simply dependant on the life of the bearing.
6. The motors response to digital input pulses provides open-loop control, making the
motor simpler and less costly to control.
7. It is possible to achieve very low speed synchronous rotation with a load that is
directly coupled to the shaft.
41
8. A wide range of rotational speeds can be realized as the speed is proportional to the
frequency of the input pulses.
7.2 Disadvantages:
1. Resonances can occur if not properly controlled.
2. Not easy to operate at extremely high speeds.
7.3 Open Loop Operation:
One of the most significant advantages of a stepper motor is its ability to be
accurately controlled in an open loop system. Open loop control means no feedback
information about position is needed. This type of control eliminates the need for
expensive sensing and feedback devices such as optical encoders.
7.4 Stepper Motor Types:
There are three basic stepper motor types. They are:
• Variable-reluctance
• Permanent-magnet
• Hybrid
7.5 Variable-reluctance (VR):
This type of stepper motor has been around for a long time. It is probably the
easiest to understand from a structural point of view. This type of motor consists of a soft
iron multi-toothed rotor and a wound stator. When the stator windings are energized with
DC current, the poles become magnetized. Rotation occurs when the rotor teeth are
attracted to the energized stator poles.
42
Fig 11: Cross-section of a variable reluctance (VR) motor.
7.6 Permanent Magnet (PM)
The permanent magnet step motor is a low cost and low resolution type motor
with typical step angles of 7.5° to 15°. (48 – 24 steps/revolution) PM motors as the name
implies have permanent magnets added to the motor structure. In this type of motor, the
rotor does not have teeth . Instead the rotor is magnetized with alternating north and south
poles situated in a straight line parallel to the rotor shaft. These magnetized rotor poles
provide an increased magnetic flux intensity and because of this the PM motor exhibits
improved torque characteristics when compared with the VR type.
43
Fig12: PM stepper motor principle Fig13: Cross section of a hybrid stepper motor
7.7 Hybrid (HB):
The hybrid stepper motor is more expensive than the PM stepper motor but
provides better performance with respect to step resolution, torque and speed. Typical
step angles for the HB stepper motor range from 3.6° to 0.9° (100 – 400 steps per
revolution).
The hybrid stepper motor combines the best features of both the PM and VR type
stepper motors. The rotor is multi-toothed like the VR motor and contains an axially
magnetized concentric magnet around its shaft. The teeth on the rotor provide an even
better path which helps guide the magnetic flux to preferred locations in the air gap. This
further increases the detent, holding and dynamic torque characteristics of the motor
when compared with both the VR and PM types. This motor type has some advantages
such as very low inertia and a optimized magnetic flow path with no coupling between
the two stator windings. These qualities are essential in some applications.
7.8 When to Use a Stepper Motor:
A stepper motor can be a good choice whenever controlled movement is required.
They can be used to advantage in applications where you need to control rotation angle,
speed, position and synchronism. Because of the inherent advantages listed previously,
stepper motors have found their place in many different applications.
7.9 The Rotating Magnetic Field:
When a phase winding of a stepper motor is energized with current a magnetic
flux is developed in the stator. The direction of this flux is determined by the “Right
Hand Rule” which states:
“If the coil is grasped in the right hand with the fingers pointing in the direction of
the current in the winding (the thumb is extended at a 90° angle to the fingers), then the
thumb will point in the direction of the magnetic field.”
44
The below figure shows the magnetic flux path developed when phase B is
energized with winding current in the direction shown. The rotor then aligns itself so that
the flux opposition is minimized. In this case the motor would rotate clockwise so that its
south pole aligns with the north pole of the stator B at position 2 and its north pole aligns
with the south pole of stator B at position 6. To get the motor to rotate we can now see
that we must provide a sequence of energizing the stator windings in such a fashion that
provides a rotating magnetic flux field which the rotor follows due to magnetic attraction.
Fig14: Magnetic flux path through a two-pole stepper motor with a lag between the
rotor and stator.
7.10 Torque Generation:
The torque produced by a stepper motor depends on several factors.
• The step rate
• The drive current in the windings
• The drive design or type
In a stepper motor, a torque will be developed when the magnetic fluxes of the
rotor and stator are displaced from each other. The stator is made up of a high
permeability magnetic material. The presence of this high permeability material causes
the magnetic flux to be confined for the most part to the paths defined by the stator
45
structure. This serves to concentrate the flux at the stator poles. The torque output
produced by the motor is proportional to the intensity of the magnetic flux generated
when the winding is energized.
The basic relationship which defines the intensity of the magnetic flux is defined by:
H = (N * i) / l
where
N = The number of winding turns
i = current
H = Magnetic field intensity
l = Magnetic flux path length
This relationship shows that the magnetic flux intensity and consequently the
torque is proportional to the number of winding turns and the current and inversely
proportional to the length of the magnetic flux path. Thus from this basic relationship it is
concluded that the same frame size stepper motor could have very different torque output
capabilities simply by changing the winding parameters.
7.11 Step Angle Accuracy:
The main reason that the stepper motor gained such popularity as a positioning
device is for its accuracy and repeatability. Typically stepper motors will have a step
angle accuracy of 3 – 5% of one step. This error is also non cumulative from step to step.
The accuracy of the stepper motor is mainly a function of the mechanical precision of its
parts and assembly.
46
Fig15: Positional accuracy of a stepper motor
7.12 Torque versus Speed Characteristics:
The torque versus speed characteristics are the key to selecting the right motor
and drive method for a specific application. These characteristics are dependent upon
(change with)the motor, excitation mode and type of driver or drive method.
Fig16: Torque versus speed characteristics
7.13 Single Step Response and Resonances:
Stepper motors can often exhibit a phenomena referred to as resonance at certain
step rates. This can be seen as a sudden loss or drop in torque at certain speeds which can
result in missed steps or loss of synchronism. It occurs when the input step pulse rate
coincides with the natural oscillation frequency of the rotor. Often there is a resonance
area around the 100 – 200 pps region and also one in the high step pulse rate region. The
47
resonance phenomena of a stepper motor comes from its basic construction and therefore
it is not possible to eliminate it completely. It is also dependent upon the load conditions.
It can be reduced by driving the motor in half or micro stepping modes.
Fig17: Single step response versus time
7.14 Definitions related to stepper motor:
1. Step angle:
Step angle is associated with the internal construction of the motor, in particular
the number of teeth on the stator and the rotor.
The step angle is the minimum degree of rotation associated with a single step.
Step angle Steps per Revolution
0.72 500
1.8 200
2.0 180
2.5 144
5.0 72
7.5 48
15 24
Table 2: Stepper motor step angles
48
2. Steps per second and rpm relation:
The relation between rpm (revolutions per minute), steps per revolution and steps
per second is as follows:
Steps per second = (rpm*steps per revolution)/60
3. Motor speed:
The motor speed, measured in steps per second (steps/sec) is a function of the
switching rate.
4. Holding torque:
The amount of torque, from an external source, required to break away the shaft from its
holding position with the motor shaft standstill or zero rpm condition.
7.15 STEPPER MOTOR INTERFACING WITH MICROCONTROLLER:
BLOCK DIAGRAM:
49
1 U 16 2 L 153 N 144 2 135 0 126 0 117 3 108 9
STEPPER MOTOR
GroundVcc
AT 89C51
P1.0 P1.1 P1.2 P1.3
CHAPTER-8
50
RELAYS
A relay is an electrically controllable switch widely used in industrial controls,
automobiles and appliances.
The relay allows the isolation of two separate sections of a system with two different
voltage sources i.e., a small amount of voltage/current on one side can handle a large
amount of voltage/current on the other side but there is no chance that these two voltages
mix up.
Fig18: Circuit symbol of a relay
8.1 Operation:
When current flows through the coil, a magnetic field is created around the coil
i.e., the coil is energized. This causes the armature to be attracted to the coil. The
armature’s contact acts like a switch and closes or opens the circuit. When the coil is not
energized, a spring pulls the armature to its normal state of open or closed. There are all
types of relays for all kinds of applications.
51
Fig19: Relay Operation and use of protection diodes
Transistors and ICs must be protected from the brief high voltage 'spike' produced
when the relay coil is switched off. The above diagram shows how a signal diode (eg
1N4148) is connected across the relay coil to provide this protection. The diode is
connected 'backwards' so that it will normally not conduct. Conduction occurs only when
the relay coil is switched off, at this moment the current tries to flow continuously
through the coil and it is safely diverted through the diode. Without the diode no current
could flow and the coil would produce a damaging high voltage 'spike' in its attempt to
keep the current flowing.
In choosing a relay, the following characteristics need to be considered:
1. The contacts can be normally open (NO) or normally closed (NC). In the NC type, the
contacts are closed when the coil is not energized. In the NO type, the contacts are closed
when the coil is energized.
2. There can be one or more contacts. i.e., different types like SPST (single pole single
throw), SPDT (single pole double throw) and DPDT (double pole double throw) relays.
3. The voltage and current required to energize the coil. The voltage can vary from a few
volts to 50 volts, while the current can be from a few milliamps to 20milliamps. The relay
52
has a minimum voltage, below which the coil will not be energized. This minimum
voltage is called the “pull-in” voltage.
4. The minimum DC/AC voltage and current that can be handled by the contacts. This is
in the range of a few volts to hundreds of volts, while the current can be from a few amps
to 40A or more, depending on the relay.
8.2 DRIVING A RELAY:
. In order to operate more than one relay, ULN2003 can be connected between An
SPDT relay consists of five pins, two for the magnetic coil, one as the common terminal
and the last pins as normally connected pin and normally closed pin. When the current
flows through this coil, the coil gets energized. Initially when the coil is not energized,
there will be a connection between the common terminal and normally closed pin. But
when the coil is energized, this connection breaks and a new connection between the
common terminal and normally open pin will be established. Thus when there is an input
from the microcontroller to the relay, the relay will be switched on. Thus when the relay
is on, it can drive the loads connected between the common terminal and normally open
pin. Therefore, the relay takes 5V from the microcontroller and drives the loads which
consume high currents. Thus the relay acts as an isolation device.
Digital systems and microcontroller pins lack sufficient current to drive the relay.
While the relay’s coil needs around 10milli amps to be energized, the microcontroller’s
pin can provide a maximum of 1-2milli amps current. For this reason, a driver such as
ULN2003 or a power transistor is placed in between the microcontroller and the
relayrelay and microcontroller.
53
8.3RELAY INTERFACING WITH THE MICROCONTROLLER:
BLOCK DIAGRAM:
54
1 U 16 2 L 153 N 144 2 135 0 126 0 117 3 108 9
RELAY LOAD
Gnd Vcc
AT 89C51
P1.0
CHAPTER-9
55
DISPLAY COMPONENTS
9.1 LIGHT DEPENDENT RESISTOR:
LDRs or Light Dependent Resistors are very useful especially in light/dark sensor
circuits. Normally the resistance of an LDR is very high, sometimes as high as 1,000,000
ohms, but when they are illuminated with light, the resistance drops dramatically.
Thus in this project, LDR plays an important role in controlling the electrical
appliances based on the intensity of light i.e., if the intensity of light is more (during
daytime) the loads will be in off condition. And if the intensity of light is less (during
nights), the loads will be switched on.
9.2 LIQUID CRYSTAL DISPLAY:
LCD stands for Liquid Crystal Display. LCD is finding wide spread use replacing
LEDs (seven segment LEDs or other multi segment LEDs) because of the following
reasons:
1. The declining prices of LCDs.
2. The ability to display numbers, characters and graphics. This is in contrast to
LEDs, which are limited to numbers and a few characters.
3. Incorporation of a refreshing controller into the LCD, thereby relieving the CPU
of the task of refreshing the LCD. In contrast, the LED must be refreshed by the
CPU to keep displaying the data.
4. Ease of programming for characters and graphics.
These components are “specialized” for being used with the microcontrollers,
which means that they cannot be activated by standard IC circuits. They are used for
writing different messages on a miniature LCD.
56
Function Pin Number Name Logic
State Description
Ground 1 Vss - 0VPower supply 2 Vdd - +5V
Contrast 3 Vee - 0 - Vdd
Control of operating
4 RS 01
D0 – D7 are interpreted as commands
D0 – D7 are interpreted as data
5 R/W 01
Write data (from controller to LCD)
Read data (from LCD to controller)
6 E
01
From 1 to 0
Access to LCD disabledNormal operating
Data/commands are transferred to LCD
Data / commands
7 D0 0/1 Bit 0 LSB8 D1 0/1 Bit 19 D2 0/1 Bit 210 D3 0/1 Bit 311 D4 0/1 Bit 412 D5 0/1 Bit 513 D6 0/1 Bit 614 D7 0/1 Bit 7 MSB
A model described here is for its low price and great possibilities most frequently
used in practice. It is based on the HD44780 microcontroller (Hitachi) and can display
57
messages in two lines with 16 characters each . It displays all the alphabets, Greek letters,
punctuation marks, mathematical symbols etc. In addition, it is possible to display
symbols that user makes up on its own. Automatic shifting message on display (shift left
and right), appearance of the pointer, backlight etc. are considered as useful
characteristics.
9.2.1 Pins Functions
There are pins along one side of the small printed board used for connection to the
microcontroller. There are total of 14 pins marked with numbers (16 in case the
background light is built in). Their function is described in the table below:
9.2.2 LCD screen:
LCD screen consists of two lines with 16 characters each. Each character consists
of 5x7 dot matrix. Contrast on display depends on the power supply voltage and whether
messages are displayed in one or two lines. For that reason, variable voltage 0-Vdd is
applied on pin marked as Vee. Trimmer potentiometer is usually used for that purpose.
Some versions of displays have built in backlight (blue or green diodes). When used
during operating, a resistor for current limitation should be used (like with any LE diode).
9.2.3 LCD Basic Commands:
All data transferred to LCD through outputs D0-D7 will be interpreted as
commands or as data, which depends on logic state on pin RS:
RS = 1 - Bits D0 - D7 are addresses of characters that should be displayed. Built
in processor addresses built in “map of characters” and displays corresponding symbols.
Displaying position is determined by DDRAM address. This address is either previously
defined or the address of previously transferred character is automatically incremented.
RS = 0 - Bits D0 - D7 are commands which determine display mode. List of
commands which LCD recognizes are given in the table below:
58
Command RS RW D7 D6 D5 D4 D3 D2 D1 D0 Execution Time
Clear display 0 0 0 0 0 0 0 0 0 1 1.64mSCursor home 0 0 0 0 0 0 0 0 1 x 1.64mSEntry mode set 0 0 0 0 0 0 0 1 I/D S 40uSDisplay on/off control 0 0 0 0 0 0 1 D U B 40uSCursor/Display Shift 0 0 0 0 0 1 D/C R/L x x 40uSFunction set 0 0 0 0 1 DL N F x x 40uSSet CGRAM address 0 0 0 1 CGRAM address 40uS
Set DDRAM address 0 0 1 DDRAM address 40uS
Read “BUSY” flag (BF) 0 1 BF DDRAM address -
Write to CGRAM or DDRAM 1 0 D7 D6 D5 D4 D3 D2 D1 D0 40uS
Read from CGRAM or DDRAM 1 1 D7 D6 D5 D4 D3 D2 D1 D0 40uS
Table3: List of commands which LCD recognizes
I/D 1 = Increment (by 1) R/L 1 = Shift right
0 = Decrement (by 1) 0 = Shift left
S 1 = Display shift on DL 1 = 8-bit interface
0 = Display shift off 0 = 4-bit interface
D 1 = Display on N 1 = Display in two lines
0 = Display off 0 = Display in one line
U 1 = Cursor on F 1 = Character format 5x10 dots
59
0 = Cursor off 0 = Character format 5x7 dots
B 1 = Cursor blink on D/C 1 = Display shift
0 = Cursor blink off 0 = Cursor shift
9.2.4 LCD Connection:
Depending on how many lines are used for connection to the microcontroller,
there are 8-bit and 4-bit LCD modes. The appropriate mode is determined at the
beginning of the process in a phase called “initialization”. In the first case, the data are
transferred through outputs D0-D7 as it has been already explained. In case of 4-bit LED
mode, for the sake of saving valuable I/O pins of the microcontroller, there are only 4
higher bits (D4-D7) used for communication, while other may be left unconnected.
Consequently, each data is sent to LCD in two steps: four higher bits are sent first
(that normally would be sent through lines D4-D7), four lower bits are sent afterwards.
With the help of initialization, LCD will correctly connect and interpret each data
received. Besides, with regards to the fact that data are rarely read from LCD (data
mainly are transferred from microcontroller to LCD) one more I/O pin may be saved by
simple connecting R/W pin to the Ground. Such saving has its price. Even though
message displaying will be normally performed, it will not be possible to read from busy
flag since it is not possible to read from display.
9.2.5 LCD Initialization:
Once the power supply is turned on, LCD is automatically cleared. This process
lasts for approximately 15mS. After that, display is ready to operate. The mode of
operating is set by default. This means that:
1. Display is cleared
2. Mode
DL = 1 Communication through 8-bit interface
N = 0 Messages are displayed in one line
F = 0 Character font 5 x 8 dots
60
3. Display/Cursor on/off
D = 0 Display off
U = 0 Cursor off
B = 0 Cursor blink off
4. Character entry
ID = 1 Addresses on display are automatically incremented by 1
S = 0 Display shift off
Automatic reset is mainly performed without any problems. Mainly but not
always! If for any reason power supply voltage does not reach full value in the course of
10mS, display will start perform completely unpredictably. If voltage supply unit can not
meet this condition or if it is needed to provide completely safe operating, the process of
initialization by which a new reset enabling display to operate normally must be applied.
Algorithm according to the initialization is being performed depends on whether
connection to the microcontroller is through 4- or 8-bit interface. All left over to be done
after that is to give basic commands and of course- to display messages.
61
Fig 20: Procedure on 8-bit initialization.
62
9.2.6 LCD INTERFACING WITH THE MICROCONTROLLER:
BLOCK DIAGRAM:
63
Vcc
Gnd
PRESET(CONTRAST CONTROL)
Vcc FOR BACKLIGHT PURPOSE
P2.0 P2.1 P2.2
89C51 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
4 (RS) 15 (R/W) 26(EN) 3
LCD
D0 D1D2D3D4D5 15D6 16D7
Gnd
CHAPTER-10
64
SWITCH AND LED INTERFACING WITH THE
MICROCONTROLLER:
Switches and LEDs are the most widely used input/output devices of the 8051.
10.1 SWITCH INTERFACING:
CPU accesses the switches through ports. Therefore these switches are connected
to a microcontroller. This switch is connected between the supply and ground terminals.
A single microcontroller (consisting of a microprocessor, RAM and EEPROM and
several ports all on a single chip) takes care of hardware and software interfacing of the
switch.
These switches are connected to an input port. When no switch is pressed, reading
the input port will yield 1s since they are all connected to high (Vcc). But if any switch is
pressed, one of the input port pins will have 0 since the switch pressed provides the path
to ground. It is the function of the microcontroller to scan the switches continuously to
detect and identify the switch pressed.
The switches that we are using in our project are 4 leg micro switches of
momentary type.
Vcc
R
65
P2.0
Fig21: Interfacing switch with the microcontroller
Thus now the two conditions are to be remembered:
1. When the switch is open, the total supply i.e., Vcc appears at the port pin P2.0
P2.0 = 1
2. When the switch is closed i.e., when it is pressed, the total supply path is
provided to ground. Thus the voltage value at the port pin P2.0 will be zero.
P2.0 = 0
By reading the pin status, the microcontroller identifies whether the switch is
pressed or not. When the switch is pressed, the corresponding related to this switch press
written in the program will be executed.
10.2 LED INTERFACING:
LED stands for Light Emitting Diode.
Microcontroller port pins cannot drive these LEDs as these require high currents
to switch on. Thus the positive terminal of LED is directly connected to Vcc, power
supply and the negative terminal is connected to port pin through a current limiting
resistor.
This current limiting resistor is connected to protect the port pins from sudden
flow of high currents from the power supply.
Thus in order to glow the LED, first there should be a current flow through the
LED. In order to have a current flow, a voltage difference should exist between the LED
terminals. To ensure the voltage difference between the terminals and as the positive
terminal of LED is connected to power supply Vcc, the negative terminal has to be
connected to ground. Thus this ground value is provided by the microcontroller port pin.
This can be achieved by writing an instruction “CLR P1.0”. With this, the port pin P1.0 is
initialized to zero and thus now a voltage difference is established between the LED
terminals and accordingly, current flows and therefore the LED glows. LED and switches
can be connected to any one of the four port pins.
66
Fig22: LED Interfacing with the microcontroller
67
P1.0
Vcc
CHAPTER-11
68
Working Procedure
This project is useful in all applications where controlling the entry and exit into a
room is needed. In this project we also control the room light. Use of embedded
technology makes this closed loop feedback control system efficient and reliable. Micro
controller (AT89S52) allows dynamic and faster control. AT89S52 micro controller is the
heart of the circuit as it controls all the functions.
Two IR TX – RX pairs are used in this project to identify the entry or exit of the
person. These two IR TX – RX pairs are arranged each one on oneside of the door i.e.
one at the entry of the room and other inside the room. The TX and RX are arranged face
to face across the door so that the RX should get IR signal continuously.
Initially the door is closed. Whenever any person comes in front of the door, the
IR RX identifies it since the IR signal gets disturbed. Then the microcontroller opens the
entry door by rotating the stepper motor. After some delay, the door will be closed.
After the person finishes his task and wants to leave the room, he stands near the
door, the second IR pair placed on the other side of the door detects the person and then
opens the door for the person to leave. The microcontroller closes the door only after the
person exits out. And again the entry door sensor will be waiting for the person to enter.
For controlling the room light we use a LDR which is nothing but a light
dependent resistor. The principle of this component is its resistance is inversely
proportional to the intensity of light. Taking this as an advantage we use this component
in our project for controlling the room light. In day time as the intensity of the light will
be high, the resistance of the LDR will be low and hence the light will be in off condition.
But in night times or if the room is dark according to its principle and hardware
arrangement the light should glow, but in contrast to it the light will be in off condition.
69
The main reason for this action is as there is no one inside the room there is no
need of light. The response of the LDR is sent to the microcontroller and the
microcontroller will take care of the further action.
When a person enters into the room at night time, automatically the light will
glow and when the person leaves the room the light will be off.
70
CHAPTER-12
71
12.0 ALGORITHM
Step by step procedure of a program is known as a algorithm.
12.1 PROCEDURESTEP-1 : - Start.
STEP-2 :- LCD Initialization.
STEP-3:- LCD Initial Message Display.
STEP-4:- Checking Person Entry/Exit
ENTRY
Opening the gate for person entry.
EXIT
Closing the gate for person exit
STEP-5:- If person is inside the room.
STEP-6:- Count will be displaced on LCD.
STEP-7:- Count get incremented.
STEP-8:- Count get decremented.
STEP-9:- LDR will be activated /Deactivated.
STEP-10:- Light on/off.
72
CHAPTER-13
73
74
CHAPTER-14
75
14.0 PROGRAMSP3.6 AND P3.7 RECEIVERS OF ENTRY AND EXIT SENSORS RESP.
; P1.0,P1.1,P1.2 AND P1.3 STEPPER MOTOR A,B,C AND D COILS
; P2 LCD DATA PINS
; P3.0,P3.1 AND P3.2 ARE RS,R/W AND EN PINS OF LCD RESP.
; P3.4 LDR
ORG 00H
SETB P3.6 ; MAKING P3.6 AS I/P PIN
SETB P3.7 ; MAKING P3.7 AS I/P PIN
MOV R5,#0 ; NO.OF PERSONS IN THE ROOM
SETB P3.4 ; LDR
CLR P0.1 ; LIGHT (RELAY)
;******* LCD INITIALISATION ****************************
MOV DPTR,#COMM
BACK1 : CLR A
MOVC A,@A+DPTR
JZ NEXT
ACALL COMN
ACALL DELAY
INC DPTR
SJMP BACK1
;****** LCD INITIAL MESSAGE DISPLAY ********************
NEXT : MOV DPTR,#MESG4
ACALL BACK2
ACALL DELAY1
76
MOV A,#0C0H
ACALL COMN
ACALL DELAY
MOV DPTR,#MESG5
ACALL BACK2
ACALL FORDELAY
ACALL FORDELAY
MOV A,#01H
ACALL COMN
ACALL DELAY
MOV A,#80H
ACALL COMN
ACALL DELAY
MOV DPTR,#MESG6
ACALL BACK2
MOV A,#0C0H
ACALL COMN
ACALL DELAY
MOV DPTR,#MESG7
ACALL BACK2
ACALL FORDELAY
ACALL FORDELAY1
MOV A,#01H
ACALL COMN
ACALL DELAY
MOV A,#87H
ACALL COMN
ACALL DELAY
MOV DPTR,#MESG
77
ACALL BACK2
MOV A,#0C0H
ACALL COMN
ACALL DELAY
MOV DPTR,#MESG1
ACALL BACK2
MOV A,#82H
ACALL COMN
ACALL DELAY
MOV A,#'0'
ACALL DATAWRT
ACALL DELAY
MOV A,#'0'
ACALL DATAWRT
ACALL DELAY
MOV A,#'0'
ACALL DATAWRT
ACALL DELAY
;*********** CHECKING FOR VEHICLE ENTRY OR EXIT ********
BACK : JNB P3.6,ENTRY
JNB P3.7,EXIT
ACALL CHECK
SJMP BACK
;*********** OPENING THE GATE FOR VEHICLE ENTRY ********
78
ENTRY : MOV R7,#10
MOV A,#66
ACALL RUNACW
INC R5
MOV A,#82H
ACALL COMN
ACALL DELAY
CLR A
MOV A,R5 ; DISPLAYING CURRENT CAPACITY
MOV B,#10
DIV AB
MOV R1,B
MOV B,#10
DIV AB
ORL A,#30H
ACALL DATAWRT
ACALL DELAY
; MOV A,#83H
; ACALL COMN
; ACALL DELAY
MOV A,B
ORL A,#30H
ACALL DATAWRT
ACALL DELAY
; MOV A,#84H
; ACALL COMN
; ACALL DELAY
MOV A,R1
ORL A,#30H
ACALL DATAWRT
ACALL DELAY
79
STAY : JNB P3.6,STAY
ACALL DELAY1
ACALL DELAY1
STAY1 : JB P3.7,STAY1 ; FOR EXIT GATE HIGH TO LOW
STAY2 : JNB P3.7,STAY2
ACALL FORDELAY1
MOV R7,#10
MOV A,#66
ACALL RUNCW
ACALL CHECK
LJMP BACK
EXIT : MOV R7,#10
MOV A,#66
ACALL RUNACW
DEC R5
MOV A,#82H
ACALL COMN
ACALL DELAY
CLR A
MOV A,R5 ; DISPLAYING CURRENT CAPACITY
MOV B,#10
DIV AB
MOV R1,B
MOV B,#10
DIV AB
ORL A,#30H
ACALL DATAWRT
ACALL DELAY
; MOV A,#83H
80
; ACALL COMN
; ACALL DELAY
MOV A,B
ORL A,#30H
ACALL DATAWRT
ACALL DELAY
; MOV A,#84H
; ACALL COMN
; ACALL DELAY
MOV A,R1
ORL A,#30H
ACALL DATAWRT
ACALL DELAY
STAY3 : JNB P3.7,STAY3
ACALL DELAY1
STAY4 : JB P3.6,STAY4
STAY5 : JNB P3.6,STAY5
ACALL FORDELAY
MOV R7,#10
MOV A,#66
ACALL RUNCW
ACALL CHECK
LJMP BACK
CHECK : CJNE R5,#0,LIGHT
CLR P0.1
RET
81
LIGHT : JB P3.4,LIGHTOFF
SETB P0.1 ; LIGHT ON
RET
LIGHTOFF:CLR P0.1
RET
FORDELAY:ACALL DELAY2
ACALL DELAY2
ACALL DELAY2
ACALL DELAY2
ACALL DELAY2
ACALL DELAY2
ACALL DELAY2
ACALL DELAY2
ACALL DELAY2
ACALL DELAY2
ACALL DELAY2
RET
FORDELAY1:ACALL DELAY2
ACALL DELAY2
ACALL DELAY2
ACALL DELAY2
ACALL DELAY2
ACALL DELAY2
RET
RUNACW: CLR P1.0
SETB P1.1
SETB P1.2
82
CLR P1.3
ACALL DELAY1
CLR P3.0
SETB P3.1
SETB P3.2
CLR P3.3
ACALL DELAY1
SETB P1.0
SETB P1.1
CLR P1.2
CLR P1.3
ACALL DELAY1
SETB P3.0
SETB P3.1
CLR P3.2
CLR P3.3
ACALL DELAY1
SETB P1.0
CLR P1.1
CLR P1.2
SETB P1.3
ACALL DELAY1
SETB P3.0
CLR P3.1
CLR P3.2
83
SETB P3.3
ACALL DELAY1
CLR P1.0
CLR P1.1
SETB P1.2
SETB P1.3
ACALL DELAY1
CLR P3.0
CLR P3.1
SETB P3.2
SETB P3.3
ACALL DELAY1
DJNZ R7,RUNACW
RET
RUNCW: CLR P1.0
SETB P1.1
SETB P1.2
CLR P1.3
ACALL DELAY1
CLR P3.0
SETB P3.1
SETB P3.2
CLR P3.3
ACALL DELAY1
CLR P1.0
84
CLR P1.1
SETB P1.2
SETB P1.3
ACALL DELAY1
CLR P3.0
CLR P3.1
SETB P3.2
SETB P3.3
ACALL DELAY1
SETB P1.0
CLR P1.1
CLR P1.2
SETB P1.3
ACALL DELAY1
SETB P3.0
CLR P3.1
CLR P3.2
SETB P3.3
ACALL DELAY1
SETB P1.0
SETB P1.1
CLR P1.2
CLR P1.3
ACALL DELAY1
SETB P3.0
SETB P3.1
85
CLR P3.2
CLR P3.3
ACALL DELAY1
; MOV P1,A
; RR A
; ACALL DELAY1
DJNZ R7,RUNCW
RET
COMN : MOV P2,A
CLR P1.7
CLR P1.6
SETB P1.5
ACALL DELAY
CLR P1.5
RET
DATAWRT:MOV P2,A
SETB P1.7
CLR P1.6
SETB P1.5
ACALL DELAY
CLR P1.5
RET
BACK2 : CLR A
MOVC A,@A+DPTR
JZ NEXT1
ACALL DATAWRT
ACALL DELAY
INC DPTR
86
SJMP BACK2
NEXT1 : RET
DELAY : MOV R2,#20
HERE1 : MOV R3,#255
HERE2 : DJNZ R3,HERE2
DJNZ R2,HERE1
RET
DELAY1: MOV R2,#30
HERE3 : MOV R3,#255
HERE4 : DJNZ R3,HERE4
DJNZ R2,HERE3
RET
DELAY2: MOV R2,#255
HERE5 : MOV R3,#255
HERE6 : DJNZ R3,HERE6
DJNZ R2,HERE5
RET
COMM : DB 38H,0CH,01,06,84H,00
MESG4 : DB "WIN KIT",0
MESG5 : DB "LEARNING IS FUN",0
MESG6 : DB "INTELLIGENT ROOM",0
MESG7 : DB "LIGHT CONTROLLER",0
MESG : DB "PERSONS",0
MESG1 : DB "INSIDE THE ROOM",0
END
87
CHAPTER-15
88
14.0 ADVANTAGES
1. Reliability
2. Ease of Operation
3. As we can enhance security by implementing it.
4. No need of human supervision
5. The number of people in the seminar hall can be monitored.
6. Automatic device ON/OFF
7. No need of manual supervision.
8. Power can be saved.
14.0 APPLICATION
Seminar Halls
Colleges
Banks
Offices
Public Places.
89
90
Fig23: Schematic diagram
CONCLUSION
91
CONCLUSIONOur project is a standalone automatic room light controller with auto door
opening and closing to control the lighting in a room depending upon lighting that is
present in the room. Use of embedded technology makes this closed loop feedback
control system efficient and reliable. Micro controller (AT89S52) allows dynamic and
faster control. Liquid crystal display (LCD) makes the system user-friendly. AT89S52
micro controller is the heart of the circuit as it controls all the functions.
92
RESULTS
93
RESULT
LDR is placed outside the room and is used to identify whether it is day or night
time. Whenever a person tries to enter into the room, the receiver of first IR pair
identifies the person. Then the microcontroller opens the door by rotating the stepper
motor. After the person had entered into the room completely, the door will be closed
automatically. The light is switched off even if anyone is present inside the room during
the day time. The light is switched off even if anyone is present inside the room during
the day time. Similarly, the light is switched off if no one is there inside the room or if it
is night times. Thus, depending on the intensity of light and the surrounding temperature,
the required action is performed by the microcontroller. LCD displays the number of
persons present inside the room.
94
REFERENCES
95
REFERENCES:
1. “Embedded System” By Raj Kamal
2. “8052 Microcontroller And Embedded Systems” By Mazzidi
3. “Embedded real time systems” By Dr. K.V.K.K.Prasad
4. “8086 micro processor interfacing” By A.K.Roy
96
APPENDIX
97
98
Features• Compatible with MCS-51 Products®
8K Bytes of In-System Programmable (ISP) Flash Memory– Endurance: 1000 Write/Erase Cycles
4.0V to 5.5V Operating Range Fully Static Operation: 0 Hz to 33 MHz Three-level Program Memory Lock 256 x 8-bit Internal RAM 32 Programmable I/O Lines Three 16-bit Timer/Counters Eight Interrupt Sources Full Duplex UART Serial Channel Low-power Idle and Power-down Modes Interrupt Recovery from Power-down Mode Watchdog Timer Dual Data Pointer Power-off Flag
DescriptionThe AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8Kbytes of in-system programmable Flash memory. The device is manufactured usingAtmel’s high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pinout. The on-chip Flash allows the programmemory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer. By combining a versatile 8-bit CPU with in-system programmable Flash ona monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides ahighly-flexible and cost-effective solution to many embedded control applications.The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytesof RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, asix-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,and clock circuitry. In addition, the AT89S52 is designed with static logic for operationdown to zero frequency and supports two software selectable power saving modes.The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, andinterrupt system to continue functioning. The Power-down mode saves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next interruptor hardware reset.
Rev. 1919A-07/01
8-bitMicrocontrollerwith 8K BytesIn-SystemProgrammable Flash
AT89S52
99
100AT89S52
QFP
1234567891011
3332313029282726252423
44 43 42 41 40 39 38 37 36 35 34
12 13 14 15 16 17 18 19 20 21 22
(MOSI) P1.5(MISO) P1.6(SCK) P1.7
RST(RXD) P3.0
NC(TXD) P3.1(INT0) P3.2(INT1) P3.3
(T0) P3.4(T1) P3.5
P0.4 (AD4)P0.5 (AD5)P0.6 (AD6)P0.7 (AD7)EA/VPPNCALE/PROGPSENP2.7 (A15)P2.6 (A14)P2.5 (A13)
P1.4P1.3P1.2
P1.1 (T2 EX)
P1.0 (T2)
NCVCC
P0.0 (AD0)P0.1 (AD1)P0.2 (AD2)P0.3 (AD3)
(WR) P3.6(RD) P3.7XTAL2XTAL1GNDGND(A8) P2.0(A9) P2.1(A10) P2.2(A11) P2.3(A12) P2.4
PLCC
7891011121314151617
3938373635343332313029
(MOSI) P1.5(MISO) P1.6(SCK) P1.7
RST(RXD) P3.0
NC(TXD) P3.1(INT0) P3.2(INT1) P3.3
(T0) P3.4(T1) P3.5
P0.4 (AD4)P0.5 (AD5)P0.6 (AD6)P0.7 (AD7)EA/VPPNCALE/PROGPSENP2.7 (A15)P2.6 (A14)P2.5 (A13)
6 5 4 3 2 1 44 43 42 41 40
18 19 20 21 22 23 24 25 26 27 28
(WR) P3.6(RD) P3.7XTAL2XTAL1GNDNC(A8) P2.0(A9) P2.1(A10) P2.2(A11) P2.3(A12) P2.4
P1.4P1.3P1.2
P1.1 (T2 EX)
P1.0 (T2)
NCVCC
P0.0 (AD0)P0.1 (AD1)P0.2 (AD2)P0.3 (AD3)
Pin ConfigurationsPDIP
1234567891011121314151617181920
4039383736353433323130292827262524232221
(T2) P1.0(T2 EX) P1.1
P1.2P1.3P1.4
(MOSI) P1.5(MISO) P1.6(SCK) P1.7
RST(RXD) P3.0(TXD) P3.1(INT0) P3.2(INT1) P3.3
(T0) P3.4(T1) P3.5
(WR) P3.6(RD) P3.7
XTAL2XTAL1
GND
VCCP0.0 (AD0)P0.1 (AD1)P0.2 (AD2)P0.3 (AD3)P0.4 (AD4)P0.5 (AD5)P0.6 (AD6)P0.7 (AD7)EA/VPPALE/PROGPSENP2.7 (A15)P2.6 (A14)P2.5 (A13)P2.4 (A12)P2.3 (A11)P2.2 (A10)P2.1 (A9)P2.0 (A8)
101
AT89S52
Block Diagram
PORT 2 DRIVERS
PORT 2LATCH
P2.0 - P2.7
FLASHPORT 0LATCHRAM
PROGRAMADDRESSREGISTER
BUFFER
PCINCREMENTER
PROGRAMCOUNTER
DUAL DPTRINSTRUCTIONREGISTER
BREGISTER
INTERRUPT, SERIAL PORT,AND TIMER BLOCKS
STACKPOINTERACC
TMP2 TMP1
ALU
PSW
TIMINGAND
CONTROL
PORT 1 DRIVERS
P1.0 - P1.7
PORT 3LATCH
PORT 3 DRIVERS
P3.0 - P3.7
OSC
GND
VCC
PSEN
ALE/PROG
EA / V PP
RST
RAM ADDR.REGISTER
PORT 0 DRIVERS
P0.0 - P0.7
PORT 1LATCH
WATCHDOG
ISPPORT
PROGRAMLOGIC
102
103AT89S52
Pin DescriptionVCCSupply voltage.
GNDGround.
Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As anoutput port, each pin can sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as high-impedance inputs.Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to externalprogram and data memory. In this mode, P0 has internalpullups.Port 0 also receives the code bytes during Flash program-ming and outputs the code bytes during program verifica-tion. External pullups are required during programverification.
Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will sourcecurrent (I ) because of the internal pullups.IL
In addition, P1.0 and P1.1 can be configured to be thetimer/counter 2 external count input (P1.0/T2) and thetimer/counter 2 trigger input (P1.1/T2EX), respectively, asshown in the following table.Port 1 also receives the low-order address bytes duringFlash programming and verification.
Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will sourcecurrent (I ) because of the internal pullups.IL
Port 2 emits the high-order address byte during fetchesfrom external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @DPTR). In this application, Port 2 uses strong internal pul-lups when emitting 1s. During accesses to external datamemory that use 8-bit addresses (MOVX @ RI), Port 2emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and somecontrol signals during Flash programming and verification.
Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will sourcecurrent (I ) because of the pullups.IL
Port 3 also serves the functions of various special featuresof the AT89S52, as shown in the following table.Port 3 also receives some control signals for Flash pro-gramming and verification.
RSTReset input. A high on this pin for two machine cycles whilethe oscillator is running resets the device. This pin drivesHigh for 96 oscillator periods after the Watchdog times out.The DISRTO bit in SFR AUXR (address 8EH) can be usedto disable this feature. In the default state of bit DISRTO,the RESET HIGH out feature is enabled.
ALE/PROGAddress Latch Enable (ALE) is an output pulse for latchingthe low byte of the address during accesses to externalmemory. This pin is also the program pulse input (PROG)during Flash programming.In normal operation, ALE is emitted at a constant rate of1/6 the oscillator frequency and may be used for externaltiming or clocking purposes. Note, however, that oneALE pulse is skipped during each access to external datamemory.If desired, ALE operation can be disabled by setting bit 0 ofSFR location 8EH. With the bit set, ALE is active only dur-ing a MOVX or MOVC instruction. Otherwise, the pin is
Port Pin Alternate Functions
P1.0 T2 (external count input to Timer/Counter 2),clock-out
P1.1 T2EX (Timer/Counter 2 capture/reload triggerand direction control)
P1.5 MOSI (used for In-System Programming)
P1.6 MISO (used for In-System Programming)
P1.7 SCK (used for In-System Programming)
Port Pin Alternate Functions
P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0 (external interrupt 0)
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR (external data memory write strobe)
P3.7 RD (external data memory read strobe)
104
AT89S52
weakly pulled high. Setting the ALE-disable bit has noeffect if the microcontroller is in external execution mode.
PSEN Program Store Enable (PSEN) is the read strobe to exter-nal program memory.When the AT89S52 is executing code from external pro-gram memory, PSEN is activated twice each machinecycle, except that two PSEN activations are skipped duringeach access to external data memory.
EA/VPPExternal Access Enable. EA must be strapped to GND inorder to enable the device to fetch code from external pro-gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will beinternally latched on reset.EA should be strapped to V CC for internal program execu-tions.This pin also receives the 12-volt programming enable volt-age (VPP) during Flash programming.
XTAL1Input to the inverting oscillator amplifier and input to theinternal clock operating circuit.
XTAL2Output from the inverting oscillator amplifier.
Table 1. AT89S52 SFR Map and Reset Values
0F8H 0FFH
0F0H B00000000 0F7H
0E8H 0EFH
0E0H ACC00000000 0E7H
0D8H 0DFH
0D0H PSW00000000 0D7H
0C8H T2CON00000000
T2MODXXXXXX00
RCAP2L00000000
RCAP2H00000000
TL200000000
TH200000000 0CFH
0C0H 0C7H
0B8H IPXX000000 0BFH
0B0H P311111111 0B7H
0A8H IE0X000000 0AFH
0A0H P211111111
AUXR1XXXXXXX0
WDTRSTXXXXXXXX 0A7H
98H SCON00000000
SBUFXXXXXXXX 9FH
90H P111111111 97H
88H TCON00000000
TMOD00000000
TL000000000
TL100000000
TH000000000
TH100000000
AUXRXXX00XX0 8FH
80H P011111111
SP00000111
DP0L00000000
DP0H00000000
DP1L00000000
DP1H00000000
PCON0XXX0000 87H
105
106AT89S52
Special Function RegistersA map of the on-chip memory area called the Special Func-tion Register (SFR) space is shown in Table 1.Note that not all of the addresses are occupied, and unoc-cupied addresses may not be implemented on the chip.Read accesses to these addresses will in general returnrandom data, and write accesses will have an indetermi-nate effect.User software should not write 1s to these unlisted loca-tions, since they may be used in future products to invoke
new features. In that case, the reset or inactive values ofthe new bits will always be 0.Timer 2 Registers: Control and status bits are contained inregisters T2CON (shown in Table 2) and T2MOD (shown inTable 3) for Timer 2. The register pair (RCAP2H, RCAP2L)are the Capture/Reload registers for Timer 2 in 16-bit cap-ture mode or 16-bit auto-reload mode.Interrupt Registers: The individual interrupt enable bitsare in the IE register. Two priorities can be set for each ofthe six interrupt sources in the IP register.
Table 2. T2CON – Timer/Counter 2 Control Register
T2CON Address = 0C8H Reset Value = 0000 0000B
Bit Addressable
Bit TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
7 6 5 4 3 2 1 0
Symbol Function
TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1
EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine.
EXF2 must be Cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
TCLK Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/T2 Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered).
CP/RL2Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0
causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When
either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
107
AT89S52
Dual Data Pointer Registers: To facilitate accessing bothinternal and external data memory, two banks of 16-bitData Pointer Registers are provided: DP0 at SFR addresslocations 82H-83H and DP1 at 84H-85H. Bit DPS = 0in SFR AUXR1 selects DP0 and DPS = 1 selects DP1.The user should always initialize the DPS bit to the
appropriate value before accessing the respective DataPointer Register.Power Off Flag: The Power Off Flag (POF) is located at bit4 (PCON.4) in the PCON SFR. POF is set to “1” duringpower up. It can be set and rest under software control andis not affected by reset.
Table 3a. AUXR: Auxiliary Register
AUXR Address = 8EH Reset Value = XXX00XX0B
Not Bit Addressable
– – – WDIDLE DISRTO – – DISALE
Bit 7 6 5 4 3 2 1 0
– Reserved for future expansion
DISALE Disable/Enable ALE
DISALE Operating Mode
0 ALE is emitted at a constant rate of 1/6 the oscillator frequency
1 ALE is active only during a MOVX or MOVC instruction
DISRTO Disable/Enable Reset out
DISRTO
0 Reset pin is driven High after WDT times out
1 Reset pin is input only
WDIDLE Disable/Enable WDT in IDLE mode
WDIDLE
0 WDT continues to count in IDLE mode
1 WDT halts counting in IDLE mode
Table 3b. AUXR1: Auxiliary Register 1
AUXR1 Address = A2H Reset Value = XXXXXXX0B
Not Bit Addressable
––– – – – – DPS
Bit 7 6 5 4 3 2 1 0
– Reserved for future expansion
DPS Data Pointer Register Select
DPS
0 Selects DPTR Registers DP0L, DP0H
1 Selects DPTR Registers DP1L, DP1H
108AT89S52
Memory OrganizationMCS-51 devices have a separate address space for Pro-gram and Data Memory. Up to 64K bytes each of externalProgram and Data Memory can be addressed.
Program MemoryIf the EA pin is connected to GND, all program fetches are directed to external memory.On the AT89S52, if EA is connected to V CC, programfetches to addresses 0000H through 1FFFH are directed tointernal memory and fetches to addresses 2000H throughFFFFH are to external memory.
Data MemoryThe AT89S52 implements 256 bytes of on-chip RAM. Theupper 128 bytes occupy a parallel address space to theSpecial Function Registers. This means that the upper 128bytes have the same addresses as the SFR space but arephysically separate from SFR space.
When an instruction accesses an internal location aboveaddress 7FH, the address mode used in the instructionspecifies whether the CPU accesses the upper 128 bytesof RAM or the SFR space. Instructions which use directaddressing access of the SFR space.For example, the following direct addressing instructionaccesses the SFR at location 0A0H (which is P2).
MOV 0A0H, #data
Instructions that use indirect addressing access the upper128 bytes of RAM. For example, the following indirectaddressing instruction, where R0 contains 0A0H, accessesthe data byte at address 0A0H, rather than P2 (whoseaddress is 0A0H).
MOV @R0, #data
Note that stack operations are examples of indirectaddressing, so the upper 128 bytes of data RAM are avail-able as stack space.
109
AT89S52
Watchdog Timer(One-time Enabled with Reset-out)The WDT is intended as a recovery method in situationswhere the CPU may be subjected to software upsets. TheWDT consists of a 13-bit counter and the Watchdog TimerReset (WDTRST) SFR. The WDT is defaulted to disablefrom exiting reset. To enable the WDT, a user must write01EH and 0E1H in sequence to the WDTRST register(SFR location 0A6H). When the WDT is enabled, it willincrement every machine cycle while the oscillator is run-ning. The WDT timeout period is dependent on the externalclock frequency. There is no way to disable the WDTexcept through reset (either hardware reset or WDT over-flow reset). When WDT overflows, it will drive an outputRESET HIGH pulse at the RST pin.
Using the WDTTo enable the WDT, a user must write 01EH and 0E1H insequence to the WDTRST register (SFR location 0A6H).When the WDT is enabled, the user needs to service it bywriting 01EH and 0E1H to WDTRST to avoid a WDT over-flow. The 13-bit counter overflows when it reaches 8191(1FFFH), and this will reset the device. When the WDT isenabled, it will increment every machine cycle while theoscillator is running. This means the user must reset theWDT at least every 8191 machine cycles. To reset theWDT the user must write 01EH and 0E1H to WDTRST.WDTRST is a write-only register. The WDT counter cannotbe read or written. When WDT overflows, it will generate anoutput RESET pulse at the RST pin. The RESET pulseduration is 96xTOSC, where TOSC=1/FOSC. To make thebest use of the WDT, it should be serviced in those sec-tions of code that will periodically be executed within thetime required to prevent a WDT reset.
WDT During Power-down and IdleIn Power-down mode the oscillator stops, which means theWDT also stops. While in Power-down mode, the userdoes not need to service the WDT. There are two methodsof exiting Power-down mode: by a hardware reset or via alevel-activated external interrupt which is enabled prior toentering Power-down mode. When Power-down is exitedwith hardware reset, servicing the WDT should occur as itnormally does whenever the AT89S52 is reset. ExitingPower-down with an interrupt is significantly different. Theinterrupt is held low long enough for the oscillator to stabi-lize. When the interrupt is brought high, the interrupt isserviced. To prevent the WDT from resetting the devicewhile the interrupt pin is held low, the WDT is not starteduntil the interrupt is pulled high. It is suggested that theWDT be reset during the interrupt service for the interruptused to exit Power-down mode.
To ensure that the WDT does not overflow within a fewstates of exiting Power-down, it is best to reset the WDTjust before entering Power-down mode.Before going into the IDLE mode, the WDIDLE bit in SFRAUXR is used to determine whether the WDT continues tocount if enabled. The WDT keeps counting during IDLE(WDIDLE bit = 0) as the default state. To prevent the WDTfrom resetting the AT89S52 while in IDLE mode, the usershould always set up a timer that will periodically exit IDLE,service the WDT, and reenter IDLE mode.With WDIDLE bit enabled, the WDT will stop to count inIDLE mode and resumes the count upon exit from IDLE.
UARTThe UART in the AT89S52 operates the same way as theUART in the AT89C51 and AT89C52. For further informa-tion on the UART operation, refer to the ATMEL Web site(http://www.atmel.com). From the home page, select ‘Prod-ucts’, then ‘8051-Architecture Flash Microcontroller’, then‘Product Overview’.
Timer 0 and 1Timer 0 and Timer 1 in the AT89S52 operate the same wayas Timer 0 and Timer 1 in the AT89C51 and AT89C52. Forfurther information on the timers’ operation, refer to theATMEL Web site (http://www.atmel.com). From the homepage, select ‘Products’, then ‘8051-Architecture FlashMicrocontroller’, then ‘Product Overview’.
Timer 2Timer 2 is a 16-bit Timer/Counter that can operate as eithera timer or an event counter. The type of operation isselected by bit C/T2 in the SFR T2CON (shown in Table 2).Timer 2 has three operating modes: capture, auto-reload(up or down counting), and baud rate generator. Themodes are selected by bits in T2CON, as shown in Table 3.Timer 2 consists of two 8-bit registers, TH2 and TL2. In theTimer function, the TL2 register is incremented everymachine cycle. Since a machine cycle consists of 12 oscil-lator periods, the count rate is 1/12 of the oscillatorfrequency.
Table 3. Timer 2 Operating Modes
110
111AT89S52
In the Counter function, the register is incremented inresponse to a 1-to-0 transition at its corresponding externalinput pin, T2. In this function, the external input is sampledduring S5P2 of every machine cycle. When the samplesshow a high in one cycle and a low in the next cycle, thecount is incremented. The new count value appears in theregister during S3P1 of the cycle following the one in whichthe transition was detected. Since two machine cycles (24oscillator periods) are required to recognize a 1-to-0 transi-tion, the maximum count rate is 1/24 of the oscillator fre-quency. To ensure that a given level is sampled at leastonce before it changes, the level should be held for at leastone full machine cycle.
Capture ModeIn the capture mode, two options are selected by bitEXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timeror counter which upon overflow sets bit TF2 in T2CON.
This bit can then be used to generate an interrupt. IfEXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transition at external input T2EX also causes thecurrent value in TH2 and TL2 to be captured into RCAP2Hand RCAP2L, respectively. In addition, the transition atT2EX causes bit EXF2 in T2CON to be set. The EXF2 bit,like TF2, can generate an interrupt. The capture mode isillustrated in Figure 5.
Auto-reload (Up or Down Counter)Timer 2 can be programmed to count up or down whenconfigured in its 16-bit auto-reload mode. This feature isinvoked by the DCEN (Down Counter Enable) bit located inthe SFR T2MOD (see Table 4). Upon reset, the DCEN bitis set to 0 so that timer 2 will default to count up. WhenDCEN is set, Timer 2 can count up or down, depending onthe value of the T2EX pin.
Figure 5. Timer in Capture Mode
Figure 6 shows Timer 2 automatically counting up whenDCEN=0. In this mode, two options are selected by bitEXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to0FFFFH and then sets the TF2 bit upon overflow. Theoverflow also causes the timer registers to be reloaded withthe 16-bit value in RCAP2H and RCAP2L. The values inTimer in Capture ModeRCAP2H and RCAP2L are presetby software. If EXEN2 = 1, a 16-bit reload can be triggeredeither by an overflow or by a 1-to-0 transition at externalinput T2EX. This transition also sets the EXF2 bit. Both theTF2 and EXF2 bits can generate an interrupt if enabled.Setting the DCEN bit enables Timer 2 to count up or down,as shown in Figure 6. In this mode, the T2EX pin controls
the direction of the count. A logic 1 at T2EX makes Timer 2count up. The timer will overflow at 0FFFFH and set theTF2 bit. This overflow also causes the 16-bit value inRCAP2H and RCAP2L to be reloaded into the timer regis-ters, TH2 and TL2, respectively.A logic 0 at T2EX makes Timer 2 count down. The timerunderflows when TH2 and TL2 equal the values stored inRCAP2H and RCAP2L. The underflow sets the TF2 bit andcauses 0FFFFH to be reloaded into the timer registers.The EXF2 bit toggles whenever Timer 2 overflows orunderflows and can be used as a 17th bit of resolution. Inthis operating mode, EXF2 does not flag an interrupt.
OSC
EXF2T2EX PIN
T2 PIN
TR2
EXEN2
C/T2 = 0
C/T2 = 1
CONTROL
CAPTURE
OVERFLOW
CONTROL
TRANSITIONDETECTOR TIMER 2
INTERRUPT
÷12
RCAP2LRCAP2H
TH2 TL2 TF2
112
AT89S52
Figure 6. Timer 2 Auto Reload Mode (DCEN = 0)
Table 4. T2MOD – Timer 2 Mode Control Register
OSC
EXF2
TF2
T2EX PIN
T2 PIN
TR2
EXEN2
C/T2 = 0
C/T2 = 1
CONTROL
RELOAD
CONTROL
TRANSITIONDETECTOR
TIMER 2INTERRUPT
÷12
RCAP2LRCAP2H
TH2 TL2
OVERFLOW
T2MOD Address = 0C9H Reset Value = XXXX XX00B
Not Bit Addressable
––––––T2OE DCEN
Bit 7 6 5 4 3 2 1 0
Symbol Function
– Not implemented, reserved for future
T2OE Timer 2 Output Enable bit
DCEN When set, this bit allows Timer 2 to be configured as an up/down counter
113
114AT89S52
Figure 7. Timer 2 Auto Reload Mode (DCEN = 1)
Figure 8. Timer 2 in Baud Rate Generator Mode
OSC
EXF2
TF2
T2EX PIN
COUNTDIRECTION1=UP0=DOWN
T2 PIN
TR2CONTROL
OVERFLOW
TOGGLE
TIMER 2INTERRUPT
12
RCAP2LRCAP2H
0FFH0FFH
TH2 TL2
C/T2 = 0
C/T2 = 1
÷
(DOWN COUNTING RELOAD VALUE)
(UP COUNTING RELOAD VALUE)
OSC
SMOD1
RCLK
TCLK
RxCLOCK
TxCLOCK
T2EX PIN
T2 PIN
TR2CONTROL
"1"
"1"
"1"
"0"
"0"
"0"
TIMER 1 OVERFLOW
NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12
TIMER 2INTERRUPT
2
2
16
16
RCAP2LRCAP2H
TH2 TL2
C/T2 = 0
C/T2 = 1
EXF2
CONTROL
TRANSITIONDETECTOR
EXEN2
÷
÷
÷
÷
115
AT89S52
Baud Rate GeneratorTimer 2 is selected as the baud rate generator by settingTCLK and/or RCLK in T2CON (Table 2). Note that thebaud rates for transmit and receive can be different if Timer2 is used for the receiver or transmitter and Timer 1 is usedfor the other function. Setting RCLK and/or TCLK putsTimer 2 into its baud rate generator mode, as shown in Fig-ure 8.The baud rate generator mode is similar to the auto-reloadmode, in that a rollover in TH2 causes the Timer 2 registersto be reloaded with the 16-bit value in registers RCAP2Hand RCAP2L, which are preset by software.The baud rates in Modes 1 and 3 are determined by Timer2’s overflow rate according to the following equation.
The Timer can be configured for either timer or counteroperation. In most applications, it is configured for timeroperation (CP/T2 = 0). The timer operation is different forTimer 2 when it is used as a baud rate generator. Normally,as a timer, it increments every machine cycle (at 1/12 theoscillator frequency). As a baud rate generator, however, it
increments every state time (at 1/2 the oscillator fre-quency). The baud rate formula is given below.
where (RCAP2H, RCAP2L) is the content of RCAP2H andRCAP2L taken as a 16-bit unsigned integer.Timer 2 as a baud rate generator is shown in Figure 8. Thisfigure is valid only if RCLK or TCLK = 1 in T2CON. Notethat a rollover in TH2 does not set TF2 and will not gener-ate an interrupt. Note too, that if EXEN2 is set, a 1-to-0transition in T2EX will set EXF2 but will not cause a reloadfrom (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer2 is in use as a baud rate generator, T2EX can be used asan extra external interrupt.Note that when Timer 2 is running (TR2 = 1) as a timer inthe baud rate generator mode, TH2 or TL2 should not beread from or written to. Under these conditions, the Timer isincremented every state time, and the results of a read orwrite may not be accurate. The RCAP2 registers may beread but should not be written to, because a write mightoverlap a reload and cause write and/or reload errors. Thetimer should be turned off (clear TR2) before accessing theTimer 2 or RCAP2 registers.
Figure 9. Timer 2 in Clock-Out Mode
Modes 1 and 3 Baud Rates Timer 2 Overflow Rate16
------------------------------------------------------------=
Modes 1 and 3Baud Rate
--------------------------------------- Oscillator Frequency32 x [65536-RCAP2H,RCAP2L)]--------------------------------------------------------------------------------------=
OSC
EXF2
P1.0(T2)
P1.1(T2EX)
TR2
EXEN2
C/T2 BIT
TRANSITIONDETECTOR
TIMER 2INTERRUPT
T2OE (T2MOD.1)
÷2 TL2(8-BITS)
RCAP2L RCAP2H
TH2(8-BITS)
÷2
116
117AT89S52
Programmable Clock OutA 50% duty cycle clock can be programmed to come out onP1.0, as shown in Figure 9. This pin, besides being a regu-lar I/O pin, has two alternate functions. It can be pro-grammed to input the external clock for Timer/Counter 2 orto output a 50% duty cycle clock ranging from 61 Hz to 4MHz at a 16 MHz operating frequency.To configure the Timer/Counter 2 as a clock generator, bitC/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer.The clock-out frequency depends on the oscillator fre-quency and the reload value of Timer 2 capture registers(RCAP2H, RCAP2L), as shown in the following equation.
In the clock-out mode, Timer 2 roll-overs will not generatean interrupt. This behavior is similar to when Timer 2 isused as a baud-rate generator. It is possible to use Timer 2as a baud-rate generator and a clock generator simulta-neously. Note, however, that the baud-rate and clock-outfrequencies cannot be determined independently from oneanother since they both use RCAP2H and RCAP2L.
InterruptsThe AT89S52 has a total of six interrupt vectors: two exter-nal interrupts (INT0 and INT1), three timer interrupts (Tim-ers 0, 1, and 2), and the serial port interrupt. Theseinterrupts are all shown in Figure 10.Each of these interrupt sources can be individually enabledor disabled by setting or clearing a bit in Special FunctionRegister IE. IE also contains a global disable bit, EA, whichdisables all interrupts at once.Note that Table 5 shows that bit position IE.6 is unimple-mented. In the AT89S52, bit position IE.5 is also unimple-mented. User software should not write 1s to these bitpositions, since they may be used in future AT89 products.Timer 2 interrupt is generated by the logical OR of bits TF2and EXF2 in register T2CON. Neither of these flags iscleared by hardware when the service routine is vectoredto. In fact, the service routine may have to determinewhether it was TF2 or EXF2 that generated the interrupt,and that bit will have to be cleared in software.The Timer 0 and Timer 1 flags, TF0 and TF1, are set atS5P2 of the cycle in which the timers overflow. The valuesare then polled by the circuitry in the next cycle. However,the Timer 2 flag, TF2, is set at S2P2 and is polled in thesame cycle in which the timer overflows.
Table 5. Interrupt Enable (IE) Register
Figure 10. Interrupt Sources
Clock-Out Frequency Oscillator Frequency4 x [65536-(RCAP2H,RCAP2L)]-------------------------------------------------------------------------------------=
(MSB) (LSB)
EA – ET2 ES ET1 EX1 ET0 EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.
Symbol Position Function
EA IE.7 Disables all interrupts. If EA = 0,no interrupt is acknowledged. IfEA = 1, each interrupt source isindividually enabled or disabledby setting or clearing its enablebit.
– IE.6 Reserved.
ET2 IE.5 Timer 2 interrupt enable bit.
ES IE.4 Serial Port interrupt enable bit.
ET1 IE.3 Timer 1 interrupt enable bit.
EX1 IE.2 External interrupt 1 enable bit.
ET0 IE.1 Timer 0 interrupt enable bit.
EX0 IE.0 External interrupt 0 enable bit.
User software should never write 1s to unimplemented bits,because they may be used in future AT89 products.
IE1
IE0
1
1
0
0
TF1
TF0
INT1
INT0
TIRI
TF2EXF2
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AT89S52
Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier that can be configured for use asan on-chip oscillator, as shown in Figure 11. Either a quartzcrystal or ceramic resonator may be used. To drive thedevice from an external clock source, XTAL2 should be leftunconnected while XTAL1 is driven, as shown in Figure 12.There are no requirements on the duty cycle of the externalclock signal, since the input to the internal clocking circuitryis through a divide-by-two flip-flop, but minimum and maxi-mum voltage high and low time specifications must beobserved.
Idle ModeIn idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked bysoftware. The content of the on-chip RAM and all the spe-cial functions registers remain unchanged during thismode. The idle mode can be terminated by any enabledinterrupt or by a hardware reset.Note that when idle mode is terminated by a hardwarereset, the device normally resumes program executionfrom where it left off, up to two machine cycles before theinternal reset algorithm takes control. On-chip hardwareinhibits access to internal RAM in this event, but access tothe port pins is not inhibited. To eliminate the possibility ofan unexpected write to a port pin when idle mode is termi-nated by a reset, the instruction following the one thatinvokes idle mode should not write to a port pin or to exter-nal memory.
Power-down ModeIn the Power-down mode, the oscillator is stopped, and theinstruction that invokes Power-down is the last instructionexecuted. The on-chip RAM and Special Function Regis-ters retain their values until the Power-down mode is termi-nated. Exit from Power-down mode can be initiated eitherby a hardware reset or by an enabled external interrupt.Reset redefines the SFRs but does not change the on-chipRAM. The reset should not be activated before V CC isrestored to its normal operating level and must be held
active long enough to allow the oscillator to restartand stabilize.
Figure 11. Oscillator Connections
Note: C1, C2 = 30 pF 10 pF for Crystals= 40 pF 10 pF for Ceramic Resonators
Figure 12. External Clock Drive Configuration
C2XTAL2
GND
XTAL1C1
XTAL2
XTAL1
GND
NC
EXTERNALOSCILLATOR
SIGNAL
Table 6. Status of External Pins During Idle and Power-down Modes
Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power-down Internal 0 0 Data Data Data Data
Power-down External 0 0 Float Data Data Data
119
120AT89S52
Program Memory Lock BitsThe AT89S52 has three lock bits that can be left unpro-grammed (U) or can be programmed (P) to obtain the addi-tional features listed in the following table.
When lock bit 1 is programmed, the logic level at the EA pinis sampled and latched during reset. If the device is pow-ered up without a reset, the latch initializes to a randomvalue and holds that value until reset is activated. Thelatched value of EA must agree with the current logic levelat that pin in order for the device to function properly.
Programming the Flash – Parallel ModeThe AT89S52 is shipped with the on-chip Flash memoryarray ready to be programmed. The programming interfaceneeds a high-voltage (12-volt) program enable signal andis compatible with conventional third-party Flash orEPROM programmers.The AT89S52 code memory array is programmed byte-by-byte.Programming Algorithm: Before programming theAT89S52, the address, data, and control signals should beset up according to the Flash programming mode table andFigures 13 and 14. To program the AT89S52, take the fol-lowing steps:1. Input the desired memory location on the address
lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V.5. Pulse ALE/PROG once to program a byte in the
Flash array or the lock bits. The byte-write cycle isself-timed and typically takes no more than 50 µs.
Repeat steps 1 through 5, changing the addressand data for the entire array or until the end of theobject file is reached.
Data Polling: The AT89S52 features Data Polling to indi-cate the end of a byte write cycle. During a write cycle, anattempted read of the last byte written will result in the com-plement of the written data on P0.7. Once the write cyclehas been completed, true data is valid on all outputs, andthe next cycle may begin. Data Polling may begin any timeafter a write cycle has been initiated.Ready/Busy : The progress of byte programming can alsobe monitored by the RDY/BSY output signal. P3.0 is pulledlow after ALE goes high during programming to indicateBUSY . P3.0 is pulled high again when programming isdone to indicate READY.Program Verify: If lock bits LB1 and LB2 have not beenprogrammed, the programmed code data can be read backvia the address and data lines for verification. The status ofthe individual lock bits can be verified directly by readingthem back.Reading the Signature Bytes: The signature bytes areread by the same procedure as a normal verification oflocations 000H, 100H, and 200H, except that P3.6 andP3.7 must be pulled to a logic low. The values returned areas follows.
(000H) = 1EH indicates manufactured by Atmel(100H) = 52H indicates 89S52(200H) = 06H
Chip Erase: In the parallel programming mode, a chiperase operation is initiated by using the proper combinationof control signals and by pulsing ALE/PROG low for a dura-tion of 200 ns - 500 ns.In the serial programming mode, a chip erase operation isinitiated by issuing the Chip Erase instruction. In this mode,chip erase is self-timed and takes about 500 ms.During chip erase, a serial read from any address locationwill return 00H at the data output.
Programming the Flash – Serial ModeThe Code memory array can be programmed using theserial ISP interface while RST is pulled to V CC. The serialinterface consists of pins SCK, MOSI (input) and MISO(output). After RST is set high, the Programming Enableinstruction needs to be executed first before other opera-tions can be executed. Before a reprogramming sequencecan occur, a Chip Erase operation is required.The Chip Erase operation turns the content of every mem-ory location in the Code array into FFH.Either an external system clock can be supplied at pinXTAL1 or a crystal needs to be connected across pinsXTAL1 and XTAL2. The maximum serial clock (SCK)
Table 7. Lock Bit Protection Modes
Program Lock Bits
LB1 LB2 LB3 Protection Type
1 U U U No program lock features
2 P U U MOVC instructions executedfrom external programmemory are disabled fromfetching code bytes frominternal memory, EA is sampled and latched on reset,and further programming ofthe Flash memory is disabled
3 P P U Same as mode 2, but verify isalso disabled
4 P P P Same as mode 3, but externalexecution is also disabled
121
AT89S52
frequency should be less than 1/16 of the crystal fre-quency. With a 33 MHz oscillator clock, the maximum SCKfrequency is 2 MHz.
Serial Programming AlgorithmTo program and verify the AT89S52 in the serial program-ming mode, the following sequence is recommended:1. Power-up sequence:
Apply power between VCC and GND pins.Set RST pin to “H”.If a crystal is not connected across pins XTAL1 andXTAL2, apply a 3 MHz to 33 MHz clock to XTAL1 pinand wait for at least 10 milliseconds.
2. Enable serial programming by sending the Pro-gramming Enable serial instruction to pinMOSI/P1.5. The frequency of the shift clock sup-plied at pin SCK/P1.7 needs to be less than theCPU clock at XTAL1 divided by 16.
3. The Code array is programmed one byte at a timeby supplying the address and data together with the
appropriate Write instruction. The write cycle is self-timed and typically takes less than 1 ms at 5V.
4. Any memory location can be verified by using theRead instruction which returns the content at theselected address at serial output MISO/P1.6.
5. At the end of a programming session, RST can beset low to commence normal device operation.
Power-off sequence (if needed):Set XTAL1 to “L” (if a crystal is not used).Set RST to “L”.Turn VCC power off.
Data Polling: The Data Polling feature is also available inthe serial mode. In this mode, during a write cycle anattempted read of the last byte written will result in the com-plement of the MSB of the serial output byte on MISO.
Serial Programming Instruction SetThe Instruction Set for Serial Programming follows a 4-byteprotocol and is shown in Table 10.
122
123AT89S52
Programming Interface – Parallel ModeEvery code byte in the Flash array can be programmed byusing the appropriate combination of control signals. Thewrite operation cycle is self-timed and once initiated, willautomatically time itself to completion.
All major programming vendors offer worldwide support forthe Atmel microcontroller series. Please contact your localprogramming vendor for the appropriate software revision.
Notes: 1. Each PROG pulse is 200 ns - 500 ns for Chip Erase.2. Each PROG pulse is 200 ns - 500 ns for Write Code Data.3. Each PROG pulse is 200 ns - 500 ns for Write Lock Bits.4. RDY/BSY signal is output on P3.0 during programming. 5. X = don’t care.
Figure 13. Programming the Flash Memory(Parallel Mode)
Figure 14. Verifying the Flash Memory (Parallel Mode)
Table 8. Flash Programming Modes
Mode VCC RST PSENALE/
PROGEA/VPP P2.6 P2.7 P3.3 P3.6 P3.7
P0.7-0Data
P2.4-0 P1.7-0
Address
Write Code Data 5V H L(2)
12V L HHHH D IN A12-8 A7-0
Read Code Data 5V H L H H L L L H H DOUT A12-8 A7-0
Write Lock Bit 1 5V H L(3)
12V H H H H H X X X
Write Lock Bit 2 5V H L(3)
12V H H H L L X X X
Write Lock Bit 3 5V H L(3)
12V H L H H L X X X
Read Lock Bits1, 2, 3
5V H L H H H H L H LP0.2,P0.3,P0.4
X X
Chip Erase 5V H L(1)
12V H L H L L X X X
Read Atmel ID 5V H L H H LLLLL1EH X 0000 00H
Read Device ID 5V H L H H LLLLL 52H X 0001 00H
Read Device ID 5V H L H H LLLLL 06H X 001000H
P1.0-P1.7
P2.6
P3.6
P2.0 - P2.4
A0 - A7ADDR.
0000H/1FFFH
SEE FLASHPROGRAMMINGMODES TABLE
3-33 MHz
P0
V
P2.7
PGMDATA
PROG
V/VIH PP
VIH
ALE
P3.7
XTAL2 EA
RST
PSEN
XTAL1
GND
VCC
AT89S52
P3.3
P3.0 RDY/BSY
A8 - A12
CC
P1.0-P1.7
P2.6
P3.6
P2.0 - P2.4
A0 - A7ADDR.
0000H/1FFFH
SEE FLASHPROGRAMMINGMODES TABLE
3-33 MHz
P0
P2.7
PGM DATA(USE 10KPULLUPS)
VIH
VIH
ALE
P3.7
XTAL2 EA
RST
PSEN
XTAL1
GND
VCC
AT89S52
P3.3
A8 - A12
VCC
124
AT89S52
Figure 15. Flash Programming and Verification Waveforms – Parallel Mode
Flash Programming and Verification Characteristics (Parallel Mode)T = 20°C to 30°C, VA CC = 4.5 to 5.5V
Symbol Parameter Min Max Units
VPP Programming Supply Voltage 11.5 12.5 V
IPP Programming Supply Current 10 mA
ICC VCC Supply Current 30 mA
1/tCLCL Oscillator Frequency 3 33 MHz
tAVGL Address Setup to PROG Low 48tCLCL
tGHAX Address Hold After PROG 48tCLCL
tDVGL Data Setup to PROG Low 48tCLCL
tGHDX Data Hold After PROG 48tCLCL
tEHSH P2.7 (ENABLE) High to VPP 48tCLCL
tSHGL VPP Setup to PROG Low 10 µs
tGHSL VPP Hold After PROG 10 µs
tGLGH PROG Width 0.2 1 µs
tAVQV Address to Data Valid 48tCLCL
tELQV ENABLE Low to Data Valid 48tCLCL
tEHQZ Data Float After ENABLE 0 48tCLCL
tGHBL PROG High to BUSY Low 1.0 µs
tWC Byte Write Cycle Time 50µs
tGLGHtGHSL
tAVGL
tSHGL
tDVGLtGHAX
tAVQV
tGHDX
tEHSH tELQV
tWC
BUSY READY
tGHBL
tEHQZ
P1.0 - P1.7P2.0 - P2.5
P3.4
ALE/PROG
PORT 0
LOGIC 1LOGIC 0EA/VPP
VPP
P2.7(ENABLE)
P3.0(RDY/BSY)
PROGRAMMINGADDRESS
VERIFICATIONADDRESS
DATA IN DATA OUT
125
126AT89S52
Figure 16. Flash Memory Serial Downloading
Flash Programming and Verification Waveforms – Serial Mode
Figure 17. Serial Programming Waveforms
P1.7/SCK
DATA OUTPUT
INSTRUCTIONINPUT
CLOCK IN
3-33 MHz
P1.5/MOSI
VIH
XTAL2
RSTXTAL1
GND
VCC
AT89S52
P1.6/MISO
VCC
7 6 5 4 3 2 1 0
127
AT89S52
Notes: 1. The signature bytes are not readable in Lock Bit Modes 3 and 4.2. B1 = 0, B2 = 0 ---> Mode 1, no lock protection
B1 = 0, B2 = 1 ---> Mode 2, lock bit 1 activatedB1 = 1, B2 = 0 ---> Mode 3, lock bit 2 activatedB1 = 1, B1 = 1 ---> Mode 4, lock bit 3 activated
After Reset signal is high, SCK should be low for at least 64system clocks before it goes high to clock in the enabledata bytes. No pulsing of Reset signal is necessary. SCKshould be no faster than 1/16 of the system clock atXTAL1.
For Page Read/Write, the data always starts from byte 0 to255. After the command byte and upper address byte arelatched, each byte thereafter is treated as data until all 256bytes are shifted in/out. Then the next instruction will beready to be decoded.
Table 9. Serial Programming Instruction Set
Instruction
InstructionFormat
OperationByte 1 Byte 2 Byte 3 Byte 4
Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx0110 1001(Output)
Enable Serial Programmingwhile RST is high
Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase Flash memoryarray
Read Program Memory(Byte Mode)
0010 0000 xxx Read data from Programmemory in the byte mode
Write Program Memory(Byte Mode)
0100 0000 xxx Write data to Programmemory in the byte mode
Write Lock Bits(2) 1010 1100 1110 00 xxxx xxxx xxxx xxxx Write Lock bits. See Note (2).
Read Lock Bits 0010 0100 xxxx xxxx xxxx xxxx xx xx Read back current status ofthe lock bits (a programmedlock bit reads back as a ‘1’)
Read Signature Bytes(1) 0010 1000 xxx xxx xxxx Signature Byte Read Signature Byte
Read Program Memory(Page Mode)
0011 0000 xxx Byte 0 Byte 1...Byte 255
Read data from Programmemory in the Page Mode(256 bytes)
Write Program Memory(Page Mode)
0101 0000 xxx Byte 0 Byte 1...Byte 255
Write data to Programmemory in the Page Mode(256 bytes)
D7D6D5D4D3D2D1D0A7A6A5A4A3A2A1A0A12 A11A10A9A8
B2B1
A12 A11A10 A9A8 A7A6A5A4A3A2A1A0 D7D6D5D4D3D2D1D0
LB3LB2LB1
A5A4A3A2A1A0
A12 A11A10A9A8
A12 A11A10A9A8
Each of the lock bits needs to be activated sequentially beforeMode 4 can be executed.
128
129AT89S52
Serial Programming Characteristics
Figure 18. Serial Programming Timing
MOSI
MISO
SCK
tOVSH
tSHSL
tSLSHtSHOX
tSLIV
Table 10. Serial Programming Characteristics, T = -40A C to 85 C, VCC = 4.0 - 5.5V (Unless otherwise noted)
Symbol Parameter Min Typ Max Units
1/tCLCL Oscillator Frequency 0 33 MHz
tCLCL Oscillator Period 30 ns
tSHSL SCK Pulse Width High 2 tCLCL ns
tSLSH SCK Pulse Width Low 2 tCLCL ns
tOVSH MOSI Setup to SCK High tCLCL ns
tSHOX MOSI Hold after SCK High 2 tCLCL ns
tSLIV SCK Low to MISO Valid 10 16 32 ns
tERASE Chip Erase Instruction Cycle Time 500 ms
tSWC Serial Byte Write Cycle Time 64 tCLCL + 400 µs
130
AT89S52
Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:Maximum IOL per port pin: 10 mAMaximum IOL per 8-bit port:Port 0: 26 mA Ports 1, 2, 3: 15 mAMaximum total IOL for all output pins: 71 mAIf IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greaterthan the listed test conditions.
2. Minimum VCC for Power-down is 2V.
Absolute Maximum Ratings*Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only andfunctional operation of the device at these or anyother conditions beyond those indicated in theoperational sections of this specification is notimplied. Exposure to absolute maximum ratingconditions for extended periods may affectdevice reliability.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pinwith Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage ............................................ 6.6V
DC Output Current...................................................... 15.0 mA
DC CharacteristicsThe values shown in this table are valid for T = -40°C to 85°C and VA CC = 4.0V to 5.5V, unless otherwise noted.
Symbol Parameter Condition Min Max Units
VIL Input Low Voltage ( E x c e p t E A ) - 0 . 50.2 VCC-0.1 V
VIL1 I n p u t L o w V o l t a g e ( E A ) - 0 . 5
0.2 VCC-0.3 V
VIH Input High Voltage (Except XTAL1, RST) 0.2 VCC+0.9 VCC+0.5 V
VIH1 Input High Voltage (XTAL1, RST) 0.7 VCC VCC+0.5 V
VOL Output Low Voltage(1) (Ports 1,2,3) IOL = 1.6 mA 0.45 V
VOL1Output Low Voltage(1)
(Port 0, ALE, PSEN ) IOL = 3.2 mA 0.45 V
VOHOutput High Voltage(Ports 1,2,3, ALE, PSEN)
IOH = -60 µA, VCC = 5V 10% 2.4 V
IOH = -25 µA 0.75 VCC V
IOH = -10 µA 0.9 VCC V
VOH1Output High Voltage(Port 0 in External Bus Mode)
IOH = -800 µA, VCC = 5V 10% 2.4 V
IOH = -300 µA 0.75 VCC V
IOH = -80 µA 0.9 VCC V
IIL Logical 0 Input Current (Ports 1,2,3) VIN = 0.45V -50 µA
ITLLogical 1 to 0 Transition Current(Ports 1,2,3) VIN = 2V, VCC = 5V 10% -650 µA
ILI Input Leakage Current (Port 0, EA) 0.45 < VIN < VCC10 µA
RRST Reset Pulldown Resistor 10 30 KΩ
CIO Pin Capacitance Test Freq. = 1 MHz, T = 25°CA 10 pF
ICC
Power Supply CurrentActive Mode, 12 MHz 25 mA
Idle Mode, 12 MHz 6.5 mA
Power-down Mode(1) VCC = 5.5V 50 µA
131
132AT89S52
AC CharacteristicsUnder operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF.
External Program and Data Memory Characteristics
Symbol Parameter
12 MHz Oscillator Variable Oscillator
UnitsMin Max Min Max
1/tCLCL Oscillator Frequency 0 33 MHz
tLHLL ALE Pulse Width 127 2tCLCL-40 ns
tAVLL Address Valid to ALE Low 43 tCLCL-25 ns
tLLAX Address Hold After ALE Low 48 tCLCL-25 ns
tLLIV ALE Low to Valid Instruction In 233 4tCLCL-65 ns
tLLPL ALE Low to PSEN Low 43 tCLCL-25 ns
tPLPH PSEN Pulse Width 205 3tCLCL-45 ns
tPLIV PSEN Low to Valid Instruction In 145 3tCLCL-60 ns
tPXIX Input Instruction Hold After PSEN 0 0 ns
tPXIZ Input Instruction Float After PSEN 59 tCLCL-25 ns
tPXAV PSEN to Address Valid 75 tCLCL-8 ns
tAVIV Address to Valid Instruction In 312 5tCLCL-80 ns
tPLAZ PSEN Low to Address Float 10 10 ns
tRLRH RD Pulse Width 400 6tCLCL-100 ns
tWLWH WR Pulse Width 400 6tCLCL-100 ns
tRLDV RD Low to Valid Data In 252 5tCLCL-90 ns
tRHDX Data Hold After RD 0 0 ns
tRHDZ Data Float After RD 97 2tCLCL-28 ns
tLLDV ALE Low to Valid Data In 517 8tCLCL-150 ns
tAVDV Address to Valid Data In 585 9tCLCL-165 ns
tLLWL ALE Low to RD or WR Low 200 300 3tCLCL-50 3tCLCL+50 ns
tAVWL Address to RD or WR Low 203 4tCLCL-75 ns
tQVWX Data Valid to WR Transition 23 tCLCL-30 ns
tQVWH Data Valid to WR High 433 7tCLCL-130 ns
tWHQX Data Hold After WR 33 tCLCL-25 ns
tRLAZ RD Low to Address Float 0 0 ns
tWHLH RD or WR High to ALE High 43 123 tCLCL-25 tCLCL+25ns
133
AT89S52
External Program Memory Read Cycle
External Data Memory Read Cycle
tLHLL
tLLIV
tPLIV
tLLAXtPXIZ
tPLPH
tPLAZtPXAV
tAVLL tLLPL
tAVIV
tPXIX
ALE
PSEN
PORT 0
PORT 2 A8 - A15
A0 - A7 A0 - A7
A8 - A15
INSTR IN
tLHLL
tLLDV
tLLWL
tLLAX
tWHLH
tAVLL
tRLRH
tAVDV
tAVWL
tRLAZ tRHDX
tRLDV tRHDZ
A0 - A7 FROM RI OR DPL
ALE
PSEN
RD
PORT 0
PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH
A0 - A7 FROM PCL
A8 - A15 FROM PCH
DATA IN INSTR IN
134
135AT89S52
External Data Memory Write Cycle
External Clock Drive Waveforms
tLHLL
tLLWL
tLLAX
tWHLH
tAVLL
tWLWH
tAVWL
tQVWXtQVWH
tWHQX
A0 - A7 FROM RI OR DPL
ALE
PSEN
WR
PORT 0
PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH
A0 - A7 FROM PCL
A8 - A15 FROM PCH
DATA OUT INSTR IN
tCHCXtCHCX
tCLCX
tCLCL
tCHCLtCLCH V - 0.5VCC
0.45V 0.2 V - 0.1VCC
0.7 VCC
External Clock DriveSymbol Parameter Min Max Units
1/tCLCL Oscillator Frequency 0 33 MHz
tCLCL Clock Period 30 ns
tCHCX High Time 12 ns
tCLCX Low Time 12 ns
tCLCH Rise Time 5 ns
tCHCL Fall Time 5 ns
136
AT89S52
Shift Register Mode Timing Waveforms
AC Testing Input/Output Waveforms (1)
Note: 1. AC Inputs during testing are driven at V CC - 0.5Vfor a logic 1 and 0.45V for a logic 0. Timing mea-surements are made at VIH min. for a logic 1 and VILmax. for a logic 0.
Float Waveforms (1)
Note: 1. For timing purposes, a port pin is no longer floatingwhen a 100 mV change from load voltage occurs. Aport pin begins to float when a 100 mV change fromthe loaded VOH/VOL level occurs.
Serial Port Timing: Shift Register Mode Test ConditionsThe values in this table are valid for V CC = 4.0V to 5.5V and Load Capacitance = 80 pF.
Symbol Parameter
12 MHz Osc Variable Oscillator
UnitsMin Max Min Max
tXLXL Serial Port Clock Cycle Time 1.0 12tCLCLs
tQVXH Output Data Setup to Clock Rising Edge 700 10tCLCL-133 ns
tXHQX Output Data Hold After Clock Rising Edge 50 2tCLCL-80 ns
tXHDX Input Data Hold After Clock Rising Edge 0 0 ns
tXHDV Clock Rising Edge to Input Data Valid 700 10tCLCL-133ns
tXHDV
tQVXH
tXLXL
tXHDX
tXHQX
ALE
INPUT DATA
CLEAR RIOUTPUT DATA
WRITE TO SBUF
INSTRUCTION
CLOCK
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
SET TI
SET RI
8
VALID VALIDVALID VALIDVALID VALIDVALID VALID
0.45V
TEST POINTS
V - 0.5VCC 0.2 V + 0.9VCC
0.2 V - 0.1VCC
VLOAD+ 0.1V
Timing ReferencePoints
V
LOAD- 0.1V
LOAD
V VOL+ 0.1V
VOL- 0.1V
137
138AT89S52
Ordering Information
*Controlling dimension: millimeters
1.20(0.047) MAX
10.10(0.394)9.90(0.386) SQ
12.21(0.478)11.75(0.458) SQ
0.75(0.030)0.45(0.018)
0.15(0.006)0.05(0.002)
0.20(.008)0.09(.003)
07
0.80(0.031) BSC
PIN 1 ID
0.45(0.018)0.30(0.012)
.045(1.14) X 45° PIN NO. 1IDENTIFY
.045(1.14) X 30° - 45° .012(.305).008(.203)
.021(.533)
.013(.330)
.630(16.0)
.590(15.0)
.043(1.09)
.020(.508)
.120(3.05)
.090(2.29).180(4.57).165(4.19)
.500(12.7) REF SQ
.032(.813)
.026(.660)
.050(1.27) TYP
.022(.559) X 45° MAX (3X)
.656(16.7)
.650(16.5)
.695(17.7)
.685(17.4)SQ
SQ
2.07(52.6)2.04(51.8) PIN
1
.566(14.4)
.530(13.5)
.090(2.29)MAX
.005(.127)MIN
.065(1.65)
.015(.381) .022(.559).014(.356) .065(1.65)
.041(1.04)
015
REF
.690(17.5)
.610(15.5)
.630(16.0)
.590(15.0)
.012(.305)
.008(.203)
.110(2.79)
.090(2.29)
.161(4.09)
.125(3.18)
SEATINGPLANE
.220(5.59)MAX
1.900(48.26) REF
Flat Package (TQFP)Dimensions in Millimeters and (Inches)*
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)Dimensions in Inches and (Millimeters)
40P6, 40-pin, 0.600" Wide, Plastic Dual InlinePackage (PDIP)Dimensions in Inches and (Millimeters)JEDEC STANDARD MS-011 AC
44A, 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad