vhdl write user.s and reference manual

8/14/2019 VHDL Write User.s and Reference Manual

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VHDLwriteUsers and Reference Manual

Software Version 8.6_4

Copyright 1994 - 1999 Mentor Graphics Corporation. All rights reserved.

This document contains information that is proprietary to Mentor Graphics Corporation and may beduplicated in whole or in part by the original recipient for internal business purposes only, provided that this

entire notice appears in all copies. In accepting this document, the recipient agrees to make everyreasonable effort to prevent the unauthorized use of this information.


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This document is for information and instruction purposes. Mentor Graphics reserves the right to makechanges in specifications and other information contained in this publication without prior notice, and thereader should, in all cases, consult Mentor Graphics to determine whether any changes have beenmade.

The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth inwritten agreements between Mentor Graphics and its customers. No representation or other affirmationof fact contained in this publication shall be deemed to be a warranty or give rise to any liability of MentorGraphics whatsoever.

MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIALINCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OR MERCHANTABILITY ANDFITNESS FOR A PARTICULAR PURPOSE.

MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR

CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS)ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT,EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OFSUCH DAMAGES.

RESTRICTED RIGHTS LEGEND 03/97

U.S. Government Restricted Rights. The SOFTWARE and documentation have been developedentirely at private expense and are commercial computer software provided with restricted rights. Use,duplication or disclosure by the U.S. Government or a U.S. Government subcontractor is subject to therestrictions set forth in the license agreement provided with the software pursuant to DFARS 227.7202-3(a) or as set forth in subparagraph (c)(1) and (2) of the Commercial Computer Software - Restricted

Rights clause at FAR 52.227-19, as applicable.

Contractor/manufacturer is:Mentor Graphics Corporation

8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.

A complete list of trademark names appears in a separate Trademark Information document.

This is an unpublished work of Mentor Graphics Corporation.
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Table of Contents

VHDLwrite User's and Reference Manual, V8.6_4 iii

About This Manual ................................................................................................xi

On-line Documentation .........................................................................................xiYear 2000 Ready ..................................................................................................xii

Chapter 1VHDLwrite Overview ......................................................................................... 1-1

Introduction......................................................................................................... 1-1VHDL Export Procedure .................................................................................... 1-2Exporting VHDL to a Source Directory............................................................. 1-4

Modifying the Export Options............................................................................ 1-6Miscellaneous Options........................................................................................ 1-8Libraries and Packages Options........................................................................ 1-10Types Options................................................................................................... 1-12Generics Options .............................................................................................. 1-14Primitive Control Options................................................................................. 1-16Archs and Configs Options............................................................................... 1-18Name Mapping Options.................................................................................... 1-20Compilation Options......................................................................................... 1-22Options File Example ....................................................................................... 1-24Adding VHDL Information to a Symbol.......................................................... 1-26Adding VHDL Information to Schematic ........................................................ 1-28Overriding the Arch or Config Name............................................................... 1-30Invoking VHDLwrite from a Shell................................................................... 1-32Compiling Source Files for ModelSim............................................................. 1-34Frame Example (review) .................................................................................. 1-36Design Viewpoint (conceptual review) ............................................................ 1-38Generating a Symbol from an Entity ................................................................ 1-40Symbol Generation Example............................................................................ 1-42

Importing VHDL Info to a Symbol .................................................................. 1-44Chapter 2The VHDL Generation Process .......................................................................... 2-1

Adding VHDL Info to a Symbol ........................................................................ 2-1

TABLE OF CONTENTS


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TABLE OF CONTENTS [continued]

Table of Contents

VHDLwrite User's and Reference Manual, V8.6_4vi

Pin Names Referencing a Bus........................................................................ 4-27Schematic Properties Mapped to VHDL .......................................................... 4-28

Chapter 5Function Dictionary ............................................................................................ 5-1

Introduction......................................................................................................... 5-1Function Descriptions......................................................................................... 5-2

$delete_all_hdl_entity_generics() .................................................................. 5-15$delete_default_architecture_name()............................................................. 5-16$delete_default_pin_hdl_type() ..................................................................... 5-17$delete_hdl_entity_constants() ...................................................................... 5-18$delete_hdl_entity_generic().......................................................................... 5-19$delete_hdl_entity_libraries() ........................................................................ 5-20$delete_hdl_entity_packages()....................................................................... 5-21$delete_hdl_entity_statements() .................................................................... 5-22$delete_instance_architecture_name()........................................................... 5-23$delete_net_hdl_type()................................................................................... 5-24$delete_pin_hdl_mode() ................................................................................ 5-25$delete_pin_hdl_type() .................................................................................. 5-26

$delete_schematic_architecture_name() ........................................................ 5-27$dx__import_entity_info() ............................................................................. 5-28$export_vhdl()................................................................................................ 5-30$generate_symbol()........................................................................................ 5-33$get_default_architecture_name().................................................................. 5-39$get_default_pin_hdl_type() .......................................................................... 5-40$get_hdl_entity_constants() ........................................................................... 5-41$get_hdl_entity_generics()............................................................................. 5-42$get_hdl_entity_libraries() ............................................................................. 5-43$get_hdl_entity_packages() ........................................................................... 5-44$get_hdl_entity_statements() ......................................................................... 5-45$get_instance_architecture_name()................................................................ 5-46$get_net_hdl_type() ....................................................................................... 5-47$get_pin_hdl_mode() ..................................................................................... 5-48$get_pin_hdl_type() ....................................................................................... 5-49$get_schematic_architecture_name()............................................................. 5-50


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TABLE OF CONTENTS [continued]

Table of Contents

VHDLwrite User's and Reference Manual, V8.6_4 vii

$set_default_architecture_name() .................................................................. 5-51$set_default_pin_hdl_type() .......................................................................... 5-53$set_hdl_entity_constants()............................................................................ 5-54$set_hdl_entity_generics() ............................................................................. 5-55$set_hdl_entity_info() .................................................................................... 5-56$set_hdl_entity_libraries() ............................................................................. 5-58$set_hdl_entity_packages()............................................................................ 5-59$set_hdl_entity_statements().......................................................................... 5-60$set_instance_architecture_name() ................................................................ 5-61$set_net_hdl_type()........................................................................................ 5-62

$set_pin_hdl_mode()...................................................................................... 5-64$set_pin_hdl_type()........................................................................................ 5-65$set_schematic_architecture_name() ............................................................. 5-66

Chapter 6Shell Command Dictionary ................................................................................ 6-1

Introduction......................................................................................................... 6-1vhdlwrite .......................................................................................................... 6-2

Index


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Table of Contents

VHDLwrite User's and Reference Manual, V8.6_4viii

Figure 4-1. Overriding the Architecture or Configuration Name...................... 4-4Figure 4-2. Handling Pins of Mode OUT........................................................ 4-14Figure 4-3. Mapping Bus Rippers ................................................................... 4-16Figure 4-4. Mapping Parameterized Bus Rippers............................................ 4-17Figure 4-5. Schematic with Complex Bus Structures...................................... 4-18Figure 4-6. For Frame...................................................................................... 4-22Figure 4-7. Bus/Bundle Connections that Do Not Map .................................. 4-25Figure 4-8. Two Ports Shorted Together ......................................................... 4-25Figure 4-9. Unnamed Nets that Connect Two Wide Pins ............................... 4-26Figure 4-10. Global Net Ripped from a Bus.................................................... 4-26

Figure 4-11. Pin Names Referencing a Bus..................................................... 4-27

LIST OF FIGURES


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Table of Contents

VHDLwrite User's and Reference Manual, V8.6_4 ix

Table 2-1. Adding VHDL Information to a Symbol ......................................... 2-2Table 2-2. Adding VHDL Information to a Schematic ..................................... 2-4Table 2-3. Options File Keywords and Arguments ........................................... 2-8Table 2-4. String Length Restrictions .............................................................. 2-20Table 2-5. Naming Conventions for Output Files ........................................... 2-25Table 2-6. Keyword Substitution in Compilation Template ........................... 2-27Table 3-1. Symbol Properties Mapped to VHDL ............................................ 3-11Table 3-2. Symbol Body Properties Added to a Generated Symbol ............... 3-14Table 3-3. Properties Added to Generated Symbol Pins ................................ 3-14Table 4-1. Mapping Wide Pins to VHDL Text .............................................. 4-7

Table 4-2. Inferred Signal Width & Data Type for Bus-Ripped Signals ........ 4-10Table 4-3. Initial Default Scalar/Vector Data Type ......................................... 4-11Table 4-4. Mapping PINTYPE to VHDL Mode ............................................. 4-13Table 4-5. Mapping PIN Name to Signal Direction ........................................ 4-13Table 4-6. Schematic Properties Mapped to VHDL ........................................ 4-28Table 5-1. Summary of VHDLwrite Functions ................................................. 5-4

LIST OF TABLES


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VHDLwrite User's and Reference Manual, V8.6_4x


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VHDLwrite User's and Reference Manual, V8.6_4 xi

About This Manual

VHDLwrite is a product that provides the functionality to generate and exportVHDL source code from a specified Mentor Graphics component structure,design viewpoint, or EDDM single-object netlist. VHDLwrite is packaged as aDesign Architect(DA) Personality Module, an extension to the AutoLogic I andDesign Viewpoint Editor User Interface, or as a standalone batch utility. Wheninvoked from a Mentor Graphics application, the functionality appears as a tightlyintegrated part of the user interface.

This VHDLwrite User's and Reference Manual is part of a VHDLwrite Doc Setthat also contains VHDLwrite Release Notes . Training exercises using DesignArchitect, VHDLwrite and Model SimTM EE/PLUS* can be found in the GettingStarted with QuickSim Pro training workbook.

On-line DocumentationThis application uses Adobe Acrobat Exchange as its online documentation andhelp viewer. Online help requires installing the Mentor Graphics-suppliedAcrobat Exchange program with Mentor Graphics-specific plugins and alsorequires setting an environment variable. For more information, refer to thesection, Setting Up Online Manuals and Help in Using Mentor Graphics

Documentation with Acrobat Exchange .

___________________* Model Sim EE/PLUS is referred to as ModelSim from now on .

NTFor Microsoft Windows NT users, this symbol identifies uniqueinformation for using VHDLwrite on a Windows NT platform.
http://vhdlwrite_rn.pdf/http://qspro_gs.pdf/http://qspro_gs.pdf/http://mgc_acrobat_user.pdf/http://mgc_acrobat_user.pdf/http://qspro_gs.pdf/http://qspro_gs.pdf/http://vhdlwrite_rn.pdf/


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VHDLwrite User's and Reference Manual, V8.6_4xii

Year 2000 Ready About This Manual

Year 2000 ReadyVHDLwrite, as an internally developed product, has been rigorously reviewed,

thoroughly tested, and is fully certified as Year 2000 ready.

By the phrase Year 2000 ready, Mentor Graphics means this product will beable to function correctly within and between the 20th and 21st centuries,provided that all other computer products used with it exchange accurate dateinformation. Existing Mentor Graphics products will determine the proper centurybased upon the following convention:

A two-digit year of 00 through 68 will be interpreted as years 2000 through2068;

a two-digit year of 69 through 99 will be interpreted as years 1969 through1999.

Be aware that Mentor Graphics is not able to independently certify Year 2000readiness of software products from third-party vendors or of customer-generatedcode which links with this product at runtime.


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VHDLwrite User's and Reference Manual, V8.6_4 1-1

Chapter 1VHDLwrite Overview

IntroductionVHDLwrite is a tool that generates plain-text VHDL structural source code fromunevaluated design data (a Mentor Graphics component structure), evaluated

design data (a Mentor Graphics component structure as seen through a viewpoint)and from a single-object EDDM netlist. VHDLwrite can be added to DesignArchitect (DA) through a personality module, it can be invoked from theAutologic I or Design Viewpoint Editor User Interface, or it can be invoked inbatch mode from a Shell.

The design data can be represented by a schematic and symbol inside a newlycreated or previously created Mentor Graphics component structure. A VHDLentity source file is generated from the information on the symbol and a VHDLarchitecture source file is generated from the schematic. If the component

structure represents the top level of a hierarchical design, VHDLwrite generatesan entity and an architecture for each non-primitive (schematic-based) componentin the design hierarchy, unless specifically instructed not to do so.

Although you will generally provide VHDL export setup values and optionsbefore generating the source files, VHDLwrite does not require you to do so.Pre-set default values allow you to quickly generate the VHDL files provided theschematics and symbols have been successfully checked and do not containconstructs that violate the VHDL code generation rules.

A number of new functions are added to an applications user interface in order toprovide you with greater flexibility and control over the VHDL output. You canuse these functions in AMPLE scripts to automatically add VHDL-specificproperties to schematics and symbols before the code is generated or you can usethem interactively to add VHDL information to the design in the Schematic andSymbol editors.


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VHDLwrite User's and Reference Manual, V8.6_41-2

VHDL Export Procedure VHDLwrite Overview

VHDL Export Procedure

Default Path

Check and Save Each SymbolCheck and Save Each Schematic

Custom VHDL Informationto Symbols and Sheets

Add

Inspect the Design forIncompatible Constructs

(optional)

VHDL Export Options

(Modify Options)

Verify

ExecuteFile > VHDL Export > Check Only

(optional)

Inspect and VerifyVHDL Source Files

(optional)

ExecuteFile > Export VHDL

Options Path Customization Path


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VHDLwrite Overview VHDL Export Procedure


VHDL Export ProcedureThe basic procedure for generating VHDL source code is as follows:

1. (optional) Visually inspect each symbol and schematic in your designhierarchy for constructs that will not translate to VHDL. Remove or replacethese constructs with valid VHDL-compatible design objects. A partial listof these schematic constructs can be found on page 4-24.

2. (optional) Add VHDL information to Symbols and Schematics.

3. (optional, but highly recommended) Verify that each symbol in the designhas been checked without errors.

a. From the DA Symbol Editor, execute Check > Symbo l on uncheckedsymbols used in the design hierarchy.

b. Make corrections and repeat the process until no errors are reported.

c. Execute File > Save Symbol

4. (optional, but highly recommended) Verify that each schematic in thedesign has been checked without errors.

a. From the DA Schematic Editor, execute Check > Schematic on eachunchecked schematic in the design hierarchy.

b. Make corrections and repeat the process until no errors are reported.

c. Execute File > Save Schematic

5. (optional) Verify that the VHDL Export options are set as you desire.Execute Check > Export VHDL until no errors are reported.

6. Generate the code. Execute File > Export VHDL

7. (optional) Open the newly generated VHDL source files. Visually inspectand verify that the code reflects the intent of the schematic-based design.


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Exporting VHDL to a Source Directory VHDLwrite Overview

Exporting VHDL to a Source Directory

Export VHDLComponent/Viewpoint: $DESIGN/card_reader

Each Component

VHDL Units to Generate

Entity and Architecture

Navigator...

Model Label: schematic

Output to Path: $QSLAB/card_reader_src

Entity OnlyArchitecture Only

(Not used for viewpoint)

Output to: Directory

Messages

No notes

No warningsCheck Only

Options Control

Reset to Defaults Modify Options... Load from File...

Design Specified Here

card_reader_structural_archcard_reader_entcard_reader

$DESIGN $QSLAB/card_reader_src

add_convert_entanalog_ent

access_chk_entfreq_det_ent

schematic

$DESIGN/card_reader

viewpt1dvpt

part

card_reader

CancelResetOK

Target Source DirectorySpecified Here


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VHDLwrite Overview Exporting VHDL to a Source Directory


Exporting VHDL to a Source DirectoryThe illustration to the left shows how VHDL source files are generated from a

hierarchical design called $DESIGN/card_reader . The export operation has thefollowing characteristics:

The design may be the path to an mgc_component structure, a designviewpoint or a single-object EDDM netlist that is generated by AutoLogic.

The target source directory $QSLAB/card_reader_src specifies where theVHDL source files are to be placed. If the specified target directory doesnot exist, the directory is automatically created by VHDLwrite.

Both entity declarations and architecture bodies are generated forcard_reader.

Selecting the Load from File... button causes VHDLwrite to first reset all theoption settings to their default values, then load the options configuration asdefined in the specified options file .

!Caution

When VHDLwrite finds an error in the design source, an errormessage is issued to the transcript. VHDLwrite will generate asmuch VHDL as possible. You should always examine thetranscript after an export operation for possible error messagesand, if found, realize that the generated code may contain errors.

i References to the VHDLwrite options file (which can have any nameyou want), are shown in italic font to emphasize that these references areall to the same file.


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Modifying the Export Options VHDLwrite Overview

Modifying the Export Options

Modify Options

CancelReset

Reset to Defaults Save to File... Merge from File...

Name Mapping...

Archs/Configs... Types...

Libs/Pkgs...

Generics...

Compile... Primitives...

Misc Options...

OK

Merges the optionssettings from a specifiedfile to the options settingscurrently in memory

Resets the current optionssettings to system-defineddefault values

Saves the current optionsettings to a specified file


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VHDLwrite Overview Modifying the Export Options


Modifying the Export OptionsWhen you select the Modify Options... button on the File > Export VHDL

dialog box, the Modify Options dialog box appears as shown on the oppositepage. You may then change the options by selecting a category represented by oneof eight buttons. Additional dialog boxes pop up requesting information: Theseare explained on the pages that follow.

When VHDLwrite is invoked from Design Architect or the Design ViewpointEditor, the options you specify are held in memory even after the export operationis complete. This allows you to re-invoke VHDLwrite repeatedly without havingto specify the options each time. If you want to save a particular options setup,you must explicitly save the setup to an options file by selecting the Save to File...button.

You may import an options setup that was saved by selecting Load from File... inthe Export VHDL dialog box. All options specified in the file overwrite thecorresponding option setting that may currently be in memory.

Selecting the Merge from File... button merges the options settings from the fileyou specify with the option settings currently in memory. Option settings alreadyset manually through the User Interface are not overwritten by a correspondingoption specification statement that may be in the file.

Selecting the Reset to Defaults button returns all option settings to their systemdefined default values. See the Options File Example on page 1-24 .


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VHDLwrite Overview Miscellaneous Options


Miscellaneous Options(1) Component Decls . For components referenced by the map library options,

tells VHDLwrite to place the generated architecture (IN-LINE) or in apackage located in a separate file (IN-FILE). The NONE option suppressesthose component declarations. (Assumes that there is an existing packagewhich should be referenced with the default_libs and default_pkgs option.)

(2) Vector Direction . Changes all vectors to be ascending A(0:7) ordescending A(7:0) or as-is.

(3) Configurations . Tells VHDLwrite where to place configuration statements.(4) Replace Files . Gives VHDLwrite permission to overwrite an existing file of

the same name in the target source directory.(5) Single File Netlist . Yes tells VHDLwrite to place all generated entities

and architectures into a single source file.(6) QuickSim Port Mode . On tells VHDLwrite to use the first letter of the

pin name to determine the port mode(direction). See the sectionDetermining Port Mode (direction) on page 4-12 .

(7) Coalesce Wide Pins . On tells VHDLwrite to coalesce symbol pins of theform (Q(0), Q(0)...Q(7)) into a single VHDL vector Q with a rangeof (0 to 7).

(8) Alias Rippers . Off tells VHDLwrite not to create aliases for unnamed netsthat are ripped off a bus.

(9) Alias Netcon . Off tells VHDLwrite not to create aliases for unnamed netconbits.

(10) Asserts . Yes tells VHDLwrite to place Assert statements explainingVHDLwrite assumptions into the exported VHDL source code.

(11) Verbose . Yes tells VHDLwrite to output detailed messages describing theprogress of the VHDL code generation.

(12) Descend . Yes tells VHDLwrite to generate VHDL for all symbols andschematics in the design hierarchy. Any object marked primitive stops thedescent on that leg of the hierarchy. See Primitive Control Options onpage 1-16.

(13) Vital . Yes tells VHDLwrite to make the generated VHDL code compliantwith VITAL (VHDL Initiative Toward ASIC Libraries).

(14) LRM 87 identifiers are restricted to letters, digits and the underlinecharacter(_). LRM 93 identifiers may be any sequence of graphiccharacters enclosed in back slashes(\). If LRM 93 is used, also set thecompilation options to use the 93 switch. (See page 1-22.)


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Libraries and Packages Options VHDLwrite Overview

Libraries and Packages Options

Modify Options

CancelReset


Name Mapping...


Libs/Pkgs...

Generics...


Misc Options...

OKLibraries & Packages

Default Libraries (Valid VHDL)LIBRARY ieee;

CancelResetOK

Default Packages (Valid VHDL)USE ieee.std_logic_1164.ALL;

Tells VHDLwrite to include the specifiedLIBRARY statements in the entity source file

Tells VHDLwrite to include the specified USE statements in the entity source file

LIBRARY my_parts_lib;

USE my_parts_lib.my_package.ALL;


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VHDLwrite Overview Libraries and Packages Options


Libraries and Packages OptionsWhen you click the Libs/Pkgs... button, the Libraries & Packages dialog box

pops up as shown on the opposite page. The VHDL statements you enter into thelist boxes are directly inserted into the entity source code. Since VHDLwrite doesnot check the statements for valid VHDL syntax, invalid statements will causecompile errors when the entity source code is compiled.


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Types Options VHDLwrite Overview

Types Options

Modify Options

CancelReset


Name Mapping...


Lies/Pegs...

Generics...


Misc. Options...

OK Types Options

Default Scalar Type:

CancelResetOK

std_logic

Default Vector Type: std_logic_vector

Auto Type Conversion Table ( )

Scalar/Vector Table ( : )

bit:bit_vectorstd_logic:std_logic_vectorstd_ulogic:std_ulogic_vector


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VHDLwrite Overview Types Options


Types OptionsThe figure to the left further illustrates how to set the options for a VHDL export

operation. When you click the Types... button, the Types Options dialog boxpops up.

Scalar/Vector Table Sets the mapping between a scalar type on a scalar objectand a vector type on a vector object. VHDLwrite always expects to find a scalartype assigned to a wire and a vector type assigned to a bus. Therefore, if youunintentionally assign a vector type like std_ulogic_vecto r to a wire on aschematic (for example), or assign a scalar type like std_ulogic to a bus,VHDLwrite will issue an error message. See the discussion on page 4-11 .

Auto Type Conversion Table Allows you to specify two different type marksand the type conversion function needed to convert the first type mark into thesecond. For each pin to net connection, the first argument corresponds to the typemark of the driver and the second argument corresponds to the type mark of thereceiver.

The type conversion function will be inserted in the port map connecting the pinto the signal. The function name is specified as the third argument and should notinclude the function parentheses, because the parentheses get added automaticallywhen the conversion function is inserted in the port map. You must supply theconversion function in a package and make the package visible by adding thepackage to the design using the VHDLwrite default_libraries anddefault_packages option or the da_hdl_libraries and da_hdl_packagesproperty on the root symbol.


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Generics Options VHDLwrite Overview

Generics Options

Modify Options

CancelReset


Name Mapping...


Libs/Pkgs...

Generics...


Misc Options...

OKGenerics

Add:component $QSLAB/component_lib/card_reader delay1 time : = 5 ns

[conditional] component


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VHDLwrite Overview Generics Options


Generics OptionsThere are two ways to flag properties as generics in a design.

1. You can open the Design Architect Symbol Editor on a symbol and addgenerics to the symbol body using the popup menu item Set VHDL Info >Generics. You must then check and save the symbol, then update, check andsave any sheets that include instances of the symbol. Adding Genericinformation to a symbol is further explained on page 1-26.

2. You may also associate generic information with a component or with a libraryof components as shown on the opposite page. The advantage of this method isthat editing changes to the design are not required.

These two alternatives flag symbol/instance properties as VHDL generics. Eithermethod defines the generic statements which appear in the VHDL entity andcomponent declarations while the associated symbol/instance propertiesdetermine the value passed in the VHDL generic map. If you enter generics in theAdd Quoted: entry box rather than the Add: box, the value of the generic willalways be double quoted in the VHDL source code.

A detailed discussion of generics and more examples can be found in the sectionHandling Generics on page 3-6 .


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Primitive Control Options VHDLwrite Overview

Primitive Control Options

Modify Options

CancelReset


Name Mapping...


Libs/Pkgs...

Generics...


Misc Options...

OK Primitive Control

Libraries ()$MGC_GENLIB

CancelResetOK

$MGC_STDLIB

Schematics ()$QSLAB/component_lib/my_dff/schematic$QSLAB/component_lib/my_dff/schematic2

Components ()$QSLAB/component_lib/card_reader/access_chk$QSLAB/component_lib/card_reader/analog$QSLAB/component_lib/card_reader/freq_det

Netlists ()

ArchitecturePrimitive Units: Entity

This tells VHDLwriteto generate an entity,for the primitiveobjects specified below.

This tells VHDLwrite

to treat all componentsin these libraries asprimitive

This tells VHDLwrite totreat these specificcomponents as primitive

This tells VHDLwriteto treat these schematicobjects as primitive

This tells VHDLwrite togenerate a black box(empty) architecturebody, for the primitiveobjects specified below.


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VHDLwrite Overview Primitive Control Options


Primitive Control OptionsWhen you click the Primitives... button, the Primitive Control dialog box

appears. The callouts explain these options.

Remember that the term primitive means non-schematic. Therefore, whenVHDLwrite descends down a design hierarchy, it stops at every object labeledprimitive and descends no further, even though there may be a schematic modelunderneath. (See also the topic Overriding the Arch or Config Name onpage 1-30 for other ways to control the descent into the design hierarchy.

With the Primitive Units buttons set as shown in the illustration on the left, anentity declaration and a black box (empty) architecture body is generated for theobjects specified as primitive in the lower part of the form. If, for example,VHDLwrite descends into a schematic containing an instance of a componentlocated in libraries $MGC_GENLIB or $MGC_STDLIB, then an entitydeclaration and a black box architecture body is generated for that instance. If theArchitecture button is not set, then an architecture body is not generated for theinstance.

Suppressing All VHDL Code for Objects Declared Primitive If both theEntity and the Architecture buttons are clicked OFF in the Primitive Controldialog box, then all VHDL code is suppressed for all the objects specified asprimitive in the dialog box.

Using a Viewpoint to control Descent If VHDLwrite is invoked on a designthrough a Design Viewpoint, then descent of VHDLwrite down through thehierarchy may be controlled by the viewpoints Primitive Rule as well as throughthe VHDLwrite Primitive Control options. When VHDLwrite is invoked on adesign through a Design Viewpoint, the VHDLwrite Primitive Control optionsoverride the Primitive Rule in the Viewpoint. The concept of a Design Viewpointis summarized on page 1-38. The Design Viewpoint Editor Users and Reference

Manual has more in-depth information.

Note

VHDL code can also be suppressed for all schematic sheets belowthe root schematic on down by setting the descend option toOFF. See item (7) in the illustration on page 1-9.
http://dve_useref.pdf/http://dve_useref.pdf/http://dve_useref.pdf/http://dve_useref.pdf/


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Archs and Configs Options VHDLwrite Overview

Archs and Configs Options

Modify Options

CancelReset


Name Mapping...


Libs/Pkgs...

Generics...


Misc Options...

OK

Architectures & Configurations

Default Architectures ( )$QSLAB/component_lib behav1

CancelResetOK

Default Configurations ( )

$QSLAB/component_lib config1

If not specified elsewhere, this tells VHDLwrite touse the architecture name behav1 for all VHDLconfiguration specifications generated fromsymbols in the $QSLAB/component_lib MGCcomponent library.

If not specified elsewhere, this tells VHDLwrite to

use the configuration name config1 for allVHDL instances generated from symbols in the$QSLAB/component_lib MGC componentlibrary.


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Name Mapping Options VHDLwrite Overview

Name Mapping Options

Modify Options

CancelReset


Name Mapping...


Libs/Pkgs...

Generics...


Misc Options...

OK

Name Mapping Options

Map User Names

Yes

Map Entity Name:component $QSLAB/component_lib/my_dff \7474\

No

component { | }

CancelResetOK

Generate Mapping File

Yes

No

library

{ []}

Map Library: $QSLAB/component_lib my_parts_lib $QSLAB/my_parts_lib

Use the entity name \7474\ for allinstances of the component at pathname$QSLAB/component_lib/my_dff

For all VHDL instances generated from symbols in$QSLAB/component_lib use my_parts_lib as theVHDL logical library name instead of work. Thelogical library my_parts_lib is located at path$QSLAB/my_parts_lib.

library $LSLIB (COMP)

For all instances in the library$LSLIB, use the value of the COMPproperty as the entity name

Map invalid user-defined VHDLidentifiers to

valid VHDL

Generate a namemapping file foreach architecture


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VHDLwrite Overview Name Mapping Options


Name Mapping OptionsWhen you click the Name Mapping... button, the Name Mapping Options

dialog box pops up. The callouts explain the options.

Map User Names The Map User Names option has a different effect, dependingon the setting of the LRM option as shown on page 1-8.

If the LRM options is set to 87, then illegal characters are mapped to legalcharacters. See the section Rules for Name Mapping on page 3-2

If the LRM option is set to 93, then extended identifiers are generated. Refer to thesection Mapping Names on page 3-2 for details.


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Compilation Options VHDLwrite Overview

Compilation Options

Modify Options

CancelReset


Name Mapping...


Libs/Pkgs...

Generics...


Misc Options...

OK

Compilation Options

Compilation Script

CancelResetOK

Automatic Compilation

DefaultCompilation Template From: ModelSim Other Compiler

$LIBPATHWork Library:

Start Compiler at Line #:

Print VHDL Source line w/errors

No STD 1164

LRM

87

93

Load Standard Package

Range Checking

Explicit scoping

No Debug

Unbounded Component

Process without Wait Stmt

No Warnings for:

Null Range

No Space in TIme Literal

Multiple drivers on Unresolved Signal

1

4

2

3

5 8

7

6Yes

No

Yes

No


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VHDLwrite Overview Compilation Options


Compilation OptionsWhen you click the Compile... button, the Compilation Options dialog box pops

up. The paragraphs below explain the callouts on the left:

(1) Yes tells VHDLwrite to create a compile shell script for the generateddesign units.

(2) Click one of these buttons to specify which compiler to use. ModelSimcompile options are specified in the areas marked by the (5) and (8).

(3) This entry box specifies the path to the VHDL logical library where thecompiled code will be placed. The value of the compile template keyword

$LIBPATH is used as the default. If the keyword $LIBPATH is specified,the VHDL library name specified in the Map Library option is used as theworking library. See the section Compiling the VHDL Source on page 2-26.

(4) You may specify the line number in the source file where the compiler is tostart.

(5) This is the area where you specify ModelSim compiler options.

(6) Yes tells VHDLwrite to automatically execute the generated compilescript after the netlisting operation is complete. If errors are reported duringthe netlisting operation, the automatic execution of this script is suppressed.

(7) This option sets the LRM compile switch to either 87 or 93.

(8) These buttons allow you to turn off the specified warning messages duringthe ModelSim compile operation.

Note

Sometimes a Warning message similar to Warning: No defaultbinding for... is issued while the compilation script is running.This warning can be ignored. It occurs when the name of anarchitecture body, which has not yet been compiled, appears in aconfiguration statement.


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Options File Example VHDLwrite Overview

Options File Example# vhdlwrite options filedescend on

override_vectors as-isprimitive_units entitydefault_scalar_type std_ulogicdefault_vector_type std_ulogic_vectorscalar_vector_table resetscalar_vector_table bit:bit_vectorscalar_vector_table std_logic:std_logic_vectorscalar_vector_table std_ulogic:std_ulogic_vectorlrm 93map_user_names onmap_file on

configurations inlinecompilation_script onreplace_files allprimitive_library $MGC_GENLIBprimitive_component $QSLAB/component_lib/analogprimitive_component $QSLAB/component_lib/freq_detprimitive_component $QSLAB/component_lib/access_chkprimitive_schematic $QSLAB/component_lib/my_dff/schematicprimitive_schematic $QSLAB/component_lib/my_dff/schematic2default_libraries LIBRARY ieee;default_libraries LIBRARY my_parts_lib;

default_libraries LIBRARY card_reader_lib;default_packages USE ieee.arithematic.All;default_architecture $QSLAB/component_lib behav1asserts onverbose on#default_configuration $QSLAB/component_lib config1map_library $QSLAB/component_lib card_reader_lib$QSLAB/card_reader_libsingle_file_netlist offautomatic_compilation onvital_compliance off

compilation_template $MTI_HOME/bin/vcom -93 -work $LIBPATH-source -map card_reader_lib $QSLAB/card_reader_lib#add generic $QSLAB/component_lib/add2 MODEL string $hdl#delete_generic


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VHDLwrite Overview Options File Example


Options File ExampleAn ASCII text options file may be used to first hold and then load a particular set

of VHDLwrite options into memory. An options file may also be used to specifyoptions when VHDLwrite is invoked directly from a shell.

The figure to the left illustrates the actual contents of an options file . This file maybe overwritten from the File > Export VHDL > Modify Options... form or itmay be edited with any ASCII text editor. Notice the following characteristics:

Some keywords such as descend on may be overridden by invocationswitches like nodescend .

Only one argument may be specified in some statements likeprimitive_library , but the statement may be included any number of times to add libraries to the Primitive Libraries Table.

Arguments to keywords like default_libraries anddefault_packages are inserted directly into the code, so they must bevalid VHDL statements with an ending semicolon. A seconddefault_libraries keyword appends the second statement to the first.The same is true for the default_packages statements. The__da_hdl properties on the symbol override the default valuesspecified in this file.

When VHDLwrite is executed from a shell, it locates the options file by applyingthe following ordered list of rules:

1. Use the value of the options file pathname supplied with the -optionsswitch.

2. Look for a file named vhdlwrite.options in the current workingdirectory. (This working directory may be overridden by the value of theshell environment variable MGC_WD, if set.)

3. Look for a file at the location $HOME/mgc/vhdlwrite/options.

4. Look for the file $MGC_HOME/pkgs/vhdlwrite_da/doc/default_options.


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Adding VHDL Information to a Symbol VHDLwrite Overview

Adding VHDL Information to a Symbol

------------------------------------------------------------ VHDL object: Entity"card_reader"(component interface"$DESIGNS/card_reade-- Generated on : Wed Jan 12 16:03:11 1994-- Generated by: ellisc-- Source information: $DESIGNS/card_reader/part-- VHDLwrite version: v8.2_10.1 Fri Jan 7 19:00:03 PST 1994------------------------------------------------------------ LIBRARY STATEMENTLIBRARY ieee,my_vhdl_lib;--PACKAGE STATEMENTUSE ieee.std_logic_1164.all;use my_vhdl_lib.my_package.all;USE work.card_reader_global_signals.ALL;entity card_reader is -- GENERIC LIST generic ( green_led_fall : time := 10ns; green_led_rise : time := 5ns

); -- PORT LIST port ( GREEN_LED : inout bit; RED_LED : out bit; RF_IN : in std_ulogic ); --CONSTANTS constant pi:real:= 3.14; begin -- ENTITY STATEMENTS -- ENTITY STATEMENTS assert GREEN_LED_FALL > 15; REPORT FALL time exceeded;

RF_IN

CARD_READERRED_LED

GREEN_LED

schematic

LIBRARY ieee, my_vhdl_lib;

in

bit

24

out

USE ieee.std_logic_1164.all;USE my_vhdl_lib.my_package.all;

CONSTANT pi :real := 3.14;ASSERT GREEN_LED_FALL > 15;

outinout

bittime := 5 ns

time := 10 ns

(Logical Symbol Body Properties)

strucls_lib

card_reader

__da_hdl_statements __da_hdl_constant

__da_hdl_packages __da_hdl_libraries

__da_hdl_arch_name

__da_hdl_entity_name

__da_hdl_lib_nameMODEL

PINTYPE

PINTYPE __da_hdl_port_mode __da_hdl_port_type __da_generic_GREEN_LED_RISE __da_generic_GREEN_LED_FALL

__da_hdl_port_type

RED_LED_RISERED_LED_FALLPINTYPE

end card_reader;


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Adding VHDL Information to Schematic VHDLwrite Overview

Adding VHDL Information to Schematic

architecture structure of card_reader is -- TYPE DECLARATIONS -- SIGNAL DECLARATIONS

signal ABUS : std_ulogic_vector(15 to 0); signal ADDRESS_IN : std_ulogic; signal \N$10\ : std_ulogic; signal \N$6\ : std_ulogic;

.

-- COMPONENT DECLARATIONS component ANALOG port ( SERIAL_OUT : out std_ulogic; OSC : out std_ulogic; RF_IN : in std_ulogic; /_CLR/ : out std_ulogic ); end component;

.

-- INLINE CONFIGURATIONS

for \I$210\ : ACCESS_CHK use entity my_parts_lib.ACCESS_CHK(custom); for \I$211\ : ADD_CONVERT use entity card_reader_lib.ADD_CONVERT(struct for ANALOG1 : ANALOG use entity my_parts_lib.ANALOG(behav1);

.

-- COMPONENT INSTANTIATIONS ANALOG1 : ANALOG port map( SERIAL_OUT => ADDRESS_IN, OSC => \N$6\, RF_IN => RF_IN

RF_INRED_LED

GREEN_LED

FREQ_DET

OSC

_CLR

ADDRESS_IN

P U L S E

S T A R T

L A T C H

ADD_CONVERT

ADDRESS_IN

_CLR ACCESS(15:0)

P U L S E

S T A R T

L A T C H

GREEN_LED

RED_LEDACCESS_CHK

_CLR

DATA_BUS(15:0)

ANALOG

OSC

SERIAL_OUT

RF_IN _CLR

P U L S E

S T A R T

L A T C H

READ

READ

ANALOG1

ADDRESS_IN

ABUS(15:0)

custom

NET

INST NET

__da_hdl_arch_name

MODELschematic


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VHDLwrite Overview Adding VHDL Information to Schematic


Adding VHDL Information to SchematicVHDLwrite will generate valid VHDL code using net handles (like N$5) for

internal signal names and instance handles (like I$256) for componentinstantiation labels. This, however, makes it harder to debug the code in thesimulator because you may not remember the net handle of a particular wire. It isa good practice to assign NET properties to important internal nets and give themeasy-to-remember values. It is also a good practice to do the same with instancesby assigning instance-specific INST property values.

The illustration on the left shows how a NET property value is mapped to a VHDLsignal name and how an INST property value is mapped to a componentinstantiation label.

Architecture Name for Each Instance If an architecture name is specified for aninstance by attaching a __da_hdl_arch_name property, VHDLwrite treats theinstance as primitive and uses the architecture name in the binding indication forthat instance. This feature allows you to change a binding on an instance withoutediting the VHDL source file after it is generated. This is illustrated in the figureon the left with the ACCESS_CHK instance. The complete set of rules fordetermining the overriding architecture name for an instance is covered on thenext page.

Assigning a Net Type Typically, the net type of a particular net is assumed fromthe pin type assigned to the symbol pins to which the net is connected.VHDLwrite allows you to assign a net type to a net by attaching a__da_hdl_net_type property to the net, but this is not a common practice. Inaddition, the net type must match the pin type of the connected pins, or an errorresults.

Assigning a Pin Type A VHDL pin type property can only be assigned to symbolpins (on a symbol), not instance pins on a schematic. It is possible to attach a

__da_hdl_pin_type property to an instance pin by using the regular methods of adding properties, but VHDLwrite ignores a property like this.


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Invoking VHDLwrite from a Shell VHDLwrite Overview

Invoking VHDLwrite from a Shell$MGC_HOME/bin/vhdlwrite

Example 1

$MGC_HOME/bin/vhdlwrite $DESIGN/card_reader -entity_only -nodescend-output_to $DESIGN/card_reader_src

Example 2

vhdlwrite $DESIGN/card_reader -options_file $DESIGN/optionsfile -check_only -nonotes -nowarnings -nowrap

OptionalSwitches

SwitchArgument

-help

-model_label

-options_file

-option_summary

-check_only

-entity_only | -arch_only

-nodescend

-nonotes

-nowarnings

-nowrap

-replace [all | none | non_primitives]

-output_to [component | directory ]


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VHDLwrite Overview Invoking VHDLwrite from a Shell


Invoking VHDLwrite from a ShellThe vhdlwrite shell command invokes the VHDLwrite application in standalone

mode. If a switch is specified in this command (such as -nodescend ) and akeyword in the options file is set differently (such as descend on ), the shellcommand switch overrides the keyword in the options file . If the output_toswitch is not specified, then the generated VHDL source files are placed in thecurrent working directory. If the environmental variable $MGC_WD is definedfor the shell, the generated files are placed in the directory defined by the value of this variable (unless output_to is defined).

Example 1 Meaning : Generate VHDL source from the $DESIGN/card_reader component and place the code in the $DESIGN/card_reader_src directory. Usethe default component interface. Only generate an entity and do not descend thedesign hierarchy. Because -options is not specified, look for an options file calledvhdlwrite.options in the current working directory. If not found, look for anoptions file located at $HOME/mgc/vhdlwrite/options . If there is no options filethere, use the default options specified in $MGC_HOME/pkgs/vhdlwrite_da/doc/ default_options.

Example 2 Meaning : Perform all Export VHDL validity checks on the$DESIGN/card_reader component. Use the options file at the path$DESIGN/optionsfile . Only output Error Messages. Do not generate any VHDLsource files. Tell VHDLwrite that the display does not auto wrap lines. Use thedirectory $QSLAB/card_reader_work as the work directory.

Note

The vhdlwrite_server process stays active for several minutes afternetlisting finishes to speed up invocation time on a subsequent runof VHDLwrite. The following UNIX command shows this: $ ps -ef | grep vhdl 9309 9142 2 14:55:35 ttypb 0:00 grep vhdl 9292 1 0 14:50:14 ? 0:01 /pkgs/vhdlwrite_da/.lib/vhdlwrite_serverIf you want the process, vhdlwrite_server, to be terminated aftereach run of VHDLwrite, set the following environment variable: $ setenvMGC_VHDLWRITE_DISABLE_SERVER_REUSE XXXX


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Compiling Source Files for ModelSim VHDLwrite Overview

Compiling Source Files for ModelSim

Directory: $DESIGN/card_reader_vhdl_source

ACCESS_CHK_black_box_arch.vhdACCESS_CHK_ent.vhdADD_DET_ent.vhdADD_DET_structural_arch.vhdANALOG_black_box_arch.vhdANALOG_ent.vhd

FREQ_DET_black_box_arch.vhdFREQ_DET_ent.vhdcard_reader_cfg.vhdcard_reader_compile.shcard_reader_ent.vhdglobal_signals_card_reader.vhdcard_reader_structural_arch.vhdmakefilemy_dff.vhdmy_dff_structural_arch.vhd

compile shell script placed here

$ cd $DESIGN/card_reader_vhdl_source$ ls

$ vlib /tmp/worklib create a new working library

$ card_reader_compile.sh

execute the "compile" shell script


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VHDLwrite Overview Compiling Source Files for ModelSim


Compiling Source Files for ModelSimVHDLwrite optionally generates a Bourne shell script that compiles all the

generated VHDL source in the following order:

1. package declaring global signals

2. all entities

3. all architectures

4. configuration file (if present)

The figure to the left illustrates the contents of a directory containing VHDLsource files from the card_reader design. The following list describes a generalprocedure for compiling the VHDL source with the ModelSim compiler:

1. Identify a location for creating a new working library. For example /tmp/worklib . (The directory worklib must not currently exist at thislocation.)

2. Execute the following command: $vlib /tmp/worklib

This creates a new working library that will receive the compiled VHDL.3. Next, execute the following command:

$DESIGN/card_reader_source/card_reader_compile.sh

This line executes the card_reader_compile.sh shell script. All thecard_reader source files generated from VHDLwrite are compiled one-at-a-time and placed in the /tmp/worklib directory.

If references are made to architectures that exist outside the schematic-based

design, these architectures must be compiled separately and placed in the /tmp/worklib before ModelSim is invoked on the compiled design.


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Generating a Symbol from an Entity VHDLwrite Overview

Generating a Symbol from an Entity

Generate SymbolChoose Source Pinlist File

Directory: $QSLAB/component_lib

ModelSim InitFile: $QSLAB/modelsim.ini

Current Shape

Place Component In

CancelResetOK

EntitySchematic

Set Init File...

Shape Arguments: [2,2]

Choose Shape

Pin Spacing (in pin grids) 2

Activate symbol?

No

Yes

(Symbol must be saved)

Replace existing?

No

Yes

Sort Pins?NoYes

Library Logical Name: Choose Library...

Entity Name: card_reader Choose Entity...

Default Architecture: structure Choose Arch...

work

Choose a Symbol Shape

Shape: Box

CancelResetOK

Min Width: 3

Or Gate Xor Gate BufferAnd Gate AndOr OrAnd

Min Height: 2

6. Enter

1. Click

2

7. Click

9. Enter 10. Click

11. Click

3

4

5

8. Verify


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VHDLwrite Overview Generating a Symbol from an Entity


Generating a Symbol from an Entity

A symbol can be generated from a compiled entity by executing the DesignArchitect session pulldown menu as follows: File > Generate > Symbol. Fill outthe dialog box as shown on the left:(1) Click the Entity button.(2) Navigate to and select a valid modelsim.ini file. If an .ini file is not specified,

VHDLwrite uses: (a) the value of MODELSIM if set, (b) the modelsim.inifile located in the directory from which DA was invoked, or (c) themodelsim.ini file located in 1) the directory containing the ModelSimexecutables, or 2) the parent of the ModelSim executables directory.

(3) Click Choose Library... , then select a valid logical library name from the list.

(4) Click Choose Entity... , then select a valid entity name from the list.(5) (optional) Click Choose Arch... , then select a valid default architecture name

from the list. This will cause VHDLwrite to treat the symbol as a primitivewhen the symbol is instantiated on a sheet.

(6) Enter the pathname of a component library. If a component with the samename as the entity does not exist at that location, a new component structurewill be created. If a component structure with the same name as the entity doesexist at the specified location and Replace existing? is Yes , then the symbolwill be replaced with a new symbol.

(7) Choose the graphic characteristics of the new symbol.(8) Choose the shape (box in this case).(9) Specify the shape (make the width greater than the height in this case).(10) Execute the Choose a Symbol Shape dialog box.(11) Execute the Generate Symbol dialog box.

The new symbol is created, checked and saved to the specified location. Thesymbol editor is then opened for further editing on the symbol. The results of theGenerate Symbol dialog box are recorded on the next page. This function alsochecks to see if a PARTNER hdl model has been registered with the interface

for this symbol and that it is the only model with the label hdl. If it is notpresent, then a partner model is registered and labeled hdl. If any other modelhas the label hdl, then a non-fatal error message is issued.

For detailed information on how to use this dialog box, refer to the Section,Creating a Symbol for a Sheet in the Design Architect Users Manual.
http://da_user.pdf/http://da_user.pdf/http://da_user.pdf/http://da_user.pdf/


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Symbol Generation Example VHDLwrite Overview

Symbol Generation Example

RF_IN

hdl

card_reader

IN

structure

USE ieee.std_logic_1164.ALL;LIBRARY ieee;

work

__da_hdl_arch_name __da_hdl_entity_name

__da_hdl_packages

__da_hdl_lib_name

__da_hdl_librariesMODEL

------------------------------------------------------------ VHDL object: Entity"card_reader"(component interface"$QSLAB/component_lib/-- Generated on Wed Sep 2 16:03:11 1998-- Generated by: davidb-- Source from: $DESIGNS/card_reader/part-- Program: VHDLwrite v8.6_4.1 Fri Aug 21 19:00:03 PST 1998------------------------------------------------------------ LIBRARY STATEMENTLIBRARY ieee;--PACKAGE STATEMENTUSE ieee.std_logic_1164.ALL;entity card_reader is -- GENERIC LIST

-- PORT LIST

port ( RF_IN : in std_ulogict; GREEN_LED : out std_ulogic; RED_LED : out std_ulogic ); attribute original_name : string

end card_reader;

GREEN_LEDOUT

RED_LEDOUT

STD_ULOGIC STD_ULOGIC

STD_ULOGIC

entity __da_hdl_suppress_units

generic(delay : time := 2 ns)

delay : 2 ns

delay(type) : time __da_generic_delay

delay propertywith a value of 2 ns


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VHDLwrite Overview Symbol Generation Example


Symbol Generation Example

Information is taken from the specified Entity object and the Generate Symboldialog box to make the new symbol as shown on the left page.

(1) A pin is created for each port name specified in the Entity. A PIN property isattached to each pin with a value equivalent to its corresponding port name.

(2) A PINTYPE property is attached to each pin with a value equivalent to the portmode(direction) of the corresponding port.

(3) The port type, such as std_ulogic, is attached to the corresponding pin as the

value of a __da_hdl_port_type property.(4) The LIBRARY statement(s) in the entity are attached to the symbol as thevalue of a __da_hdl_libraries symbol body property.

(5) The USE statement(s) in the entity are attached to the symbol as the value of a__da_hdl_packages symbol body property.

(6) The entity name specified in the Generate Symbol dialog box is attached to thesymbol as the value of a __da_hdl_entity_name symbol body property.

(7) The default architecture name specified in the Generate Symbol dialog box isattached to the symbol as the value of a __da_hdl_arch_name symbol bodyproperty. (The presence of this property on the symbol will cause VHDLwrite tothink that the symbol is primitive the next time VHDL code is generated from aninstance of the symbol.)

(8) The logical library name specified in the Generate Symbol dialog box isattached to the symbol as the value of a __da_hdl_lib_name symbol bodyproperty.

(9) A __da_suppress_units property is attached to the symbol body with a valueof entity. This causes VHDLwrite to suppress the generation of entities frominstances of this symbol.


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VHDLwrite Overview Importing VHDL Info to a Symbol


Importing VHDL Info to a Symbol

The information contained in the properties on an existing symbol can be updatedto match the VHDL information in the specified compiled entity. The VHDLinformation from the entity is annotated on the symbol pins and symbol body sothat when VHDLwrite is used later to generate code from the symbol, thegenerated code will match the code of the original entity.

The VHDL information can be imported by opening a Symbol Editor window ona symbol, then executing the ADD popup menu item Set VHDL Info... > Importfrom Entity: The procedure for filling out the dialog box is shown on the left anddiscussed as follows:

(1) Click the Entity button.(2) Navigate to and select a valid modelsim.ini file.(3) Click Choose Library... , then select a valid logical library name from the list.(4) Click Choose Entity... , then select a valid entity name from the list.(5) (optional) Click Choose Arch... , then select a valid default architecture orconfiguration name from the list. This will cause VHDLwrite to treat the symbolas a primitive when the symbol is instantiated on a sheet, then netlisted later byVHDLwrite.

Before making any design changes to an existing symbol, VHDLwrite firstverifies that the pins on the symbol match the ports in the entity. If they do notmatch, an error message is issued and no edits are made. The properties added tothe symbol are listed in 3-2 and Table 3-3 starting on page 3-14.

This function also checks to see if a PARTNER hdl model has been registeredwith the interface for this symbol and that it is the only model with the label hdl.If it is not present, then a partner model is registered and labeled hdl. If anyother model has the label hdl, then a non-fatal error message is issued.


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Chapter 2The VHDL Generation Process

Although you will generally specify VHDL export setup values and optionsbefore generating the source files, VHDLwrite does not required you to do so.Pre-set default values allow you to quickly generate the VHDL provided theschematics and symbols do not contain constructs that violate the code generationrules and the default values are appropriate for you needs. If you are in a DAsession, a DVE session or an AutoLogic I session, just execute the menu selectionFile > Export VHDL and specify a directory path where you want the VHDLsource files placed.

A number of new functions are added to an applications user interface in order toprovide you with greater flexibility and control over the VHDL output. You canuse these functions in AMPLE scripts to automatically add VHDL-specificproperties to schematics and symbols before the code is generated or you can usethem interactively to add VHDL information to the design in the Schematic andSymbol editors.

Adding VHDL Info to a SymbolTable 2-1 provides a list of actions you might want to perform in the DA SymbolEditor to add VHDL information to a Symbol. The VHDL information is addedby attaching __da_hdl properties to the logical symbol body or to the selectedor specified symbol pin(s). The illustration on page 1-26 shows where theproperty values are inserted into the code when the entity source is generated.

Details on the meanings of the property values can be found in Table 3-2 startingon page 3-14.


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Adding VHDL Info to a Symbol The VHDL Generation Process

Table 2-1. Adding VHDL Information to a Symbol

Action to Perform Symbol Editor Menu PathSet the VHDL mode for the selected (orspecified) symbol pin(s) .

(Symbol Body & Pins Popup)VHDL Info > Set Pin Mode:

Set the VHDL data type for the selected(or specified) symbol pin(s) .

(Symbol Body & Pins Popup)VHDL Info > Set Pin Type:

Insert the following VHDLinformation into the entity source code.(Performs the same operation as the next

seven individual operations.)

(ADD Popup)Set VHDL Info...

Set the default VHDL data type that willbe assigned to newly created symbolpins on this symbol.

(ADD Popup)Set VHDL Info > Default Pin Type:

Set the default architecture name for thissymbol. Use this name in bindingindications for all instances of thissymbol.

(ADD Popup)Set VHDL Info > DefaultArchitecture:

Insert the following VHDL librarystatement into the entity source code.

(ADD Popup)Set VHDL Info > Libraries:

Insert the following VHDL usestatement into the entity source code.

(ADD Popup)Set VHDL Info > Packages:

Insert the following VHDL constantstatement into the entity source code.

(ADD Popup)Set VHDL Info > Constants:

Insert the following VHDL statementinto the entity source code.

(ADD Popup)Set VHDL Info > Statements:

Insert the following generics into theentity source code.

(ADD Popup)Set VHDL Info > Generics:

Import VHDL information from thespecified Entity source file.

(ADD Popup)Set VHDL Info > Import fromEntity:


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The VHDL Generation Process Adding VHDL Info to a Schematic


When you add __da_hdl properties to a symbol from the Design Architect user

interface, the properties are added as logical symbol properties and are non-graphic and not visible. You may see the properties by executing the Report >Object As Specified form. Select the Logical Symbol button, OK the form and areport window lists the properties. If you add generics to a symbol and want thevalues to be visible, you must add each __da_generic property using the (ADDpopup)Properties(Logical) menu pick.

Adding VHDL Info to a SchematicVHDL-specific information can also be added to a schematic in order tocustomize the generated architecture source code. Table 2-2 provides a list of actions you might want to perform in the Schematic Editor and the Menu Pathsrequired to perform the action. The VHDL information is included in the designdata by attaching __da_hdl properties to the schematic design object itself or todesign objects on the schematic sheets. The illustration on page 1-28 shows wherethe property values are inserted into the generated source code. Details on themeanings of the property values can be found starting on pages 4-28.

Check the validity of the VHDL sourcecode that will be generated from thisdesign. Report all Errors, Warnings, andNotes in the Transcript Window.

Check > Export VHDL...

Generate VHDL source code from thisdesign.

File > Export VHDL...

Table 2-1. Adding VHDL Information to a Symbol

Action to Perform Symbol Editor Menu Path


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Adding VHDL Info to a Schematic The VHDL Generation Process

Table 2-2. Adding VHDL Information to a Schematic

Action to Perform Schematic Editor Menu PathSet the VHDL signal name for theselected net.

(NET Popup) Name Nets:

Set the VHDL signal type for theselected (or specified) net(s).

(NET Popup) Set Net Type:

Set the VHDL instance name for theselected (or specified) instance.

(Instance Popup)Properties > Add > Add SingleProperty...

(Specify the value of the INSTproperty)

Set the architecture name or theconfiguration name for this instance.Use this name in the binding indicationfor the instance. If descend on and thename is $schematic, treat the instanceas non-primitive and generate anarchitecture from the default schematic.

(Instance Popup)Set Architecture Name:

Set the architecture name for thisschematic. Use this name for thearchitecture that is generated from thisschematic.

(ADD Popup)VHDL Info > Set SchematicArchitecture:

Set the default architecture name orconfiguration name for this schematic.Use this name in the binding indicationsfor all instances on this schematic.

(ADD Popup)VHDL Info > Set DefaultArchitecture:

Set the default VHDL data type that willbe assigned to newly created floatingsymbol pins on this schematic.

(ADD Popup)VHDL Info > Set Default Pin Type:


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The VHDL Generation Process Specifying VHDL Export Options


Specifying VHDL Export Options

Specifying Export Options from the DA User InterfaceVHDL Export Options are set from an applications user interface by selecting theModify Options... button on the File > Export VHDL dialog box. You maychange the options manually by selecting buttons as shown starting on page 1-6,or you may import pre-defined options from an options file by selecting the Loadfrom File... button. Selecting the Reset to Defaults button sets the options to thedefault values as defined in Table 2-3 on page 2-8. You may add pre-definedoptions from options you have already set manually by selecting the Merge fromFile... button. You may then save the entire options configuration by selecting theSave to File... button. Regardless of the method you use to specify the options, theoptions currently selected are held in memory and are used during the exportoperation when you click the OK button on the Export VHDL dialog box.

Set the VHDL data type for the selected(or specified) floating symbol pin(s)on this schematic.

(Draw Popup)VHDL Info > Set Pin Type:

Set the VHDL mode for the selected (orspecified) floating symbol pin(s) onthis schematic.

(Draw Popup)VHDL Info > Set Pin Mode:

Check the validity of the VHDL sourcecode that will be generated from thisdesign. Report all Errors, Warnings, and

Notes in the Transcript Window.

Check > Export VHDL

Generate VHDL source code from thisdesign.

File > Export VHDL

Table 2-2. Adding VHDL Information to a Schematic [continued]

Action to Perform Schematic Editor Menu Path


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Specifying VHDL Export Options The VHDL Generation Process

Specifying Export Options from a Shell Invocation

When VHDLwrite is executed from a shell, VHDLwrite locates the options byapplying the following ordered list of rules:

1. Use the value of the options file pathname supplied with the -optionsswitch.

2. Look for a file named vhdlwrite.options in the current working directory.(This working directory may be overridden by the value of the shellenvironment variable MGC_WD, if set.)

3. Look for a file at the location $HOME/mgc/vhdlwrite/options .

4. Look for the file$MGC_HOME/pkgs/vhdlwrite_da/doc/default_options .

Options File Format

A VHDLwrite options file contains lines of ASCII text, each starting with akeyword followed by arguments on the same line. Blank lines and lines startingwith a # are ignored; the maximum line length is twice the limitation imposedby the string length restrictions shown in Table 2-4 on page 2-20.


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The following table provides details on the meaning of the option file keywordsand arguments. (d) indicates the default value if the keyword is not specified orcommented out with the character #.

Table 2-3. Options File Keywords and Arguments

Keyword Argument(s) and Meaning

add_generic [conditional] componentcomponent[:interface_name] [:=]

[conditional] library [:=] Ensure that the entity description corresponding toeither the component[:interface_name] or anycomponent in the specified contains a generic declaration for .If the property __da_generic_ already exists in the component interface, the and specifications

in this statement override. If :interface_name isomitted, the default component interface is used asthe source for the entity.If the keyword conditional is present, the generic isadded only if the component interface has a propertywith the name .

add_quoted_generic This option has the same syntax as theadd_generic option but differs in that it forces thevalues of the specified generic to always be double-

quoted. This option has been added to support LMCSwift model libraries.


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alias_netcon off on (d)If off , do not create aliases in the generated VHDLfor unnamed netcon bits. If on , create aliases forunnamed netcon bits. Turning alias_netcon off canbe useful if, for example, aliases generated byVHDLwrite do not work in another vendors designflow.

alias_rippers off on (d)If off , do not create aliases in the generated VHDLfor unnamed nets that are ripped off a bus. If on ,create aliases for these unnamed nets. Turningalias_rippers off can be useful if, for example,aliases generated by VHDLwrite do not work inanother vendors design flow.

asserts onoff (d)If on , VHDLwrite includes assert statements in theVHDL source code that reflect assumptions whichare made about the design. VHDLwrite includesassert statements only when scanning unevaluateddesign data (data not looked at through a designviewpoint).

automatic_compilation onoff (d)If on , VHDLwrite automatically executes thecompilation script after the VHDL export operationis complete. If on , the compilation_script option isforced on.

Table 2-3. Options File Keywords and Arguments [continued]



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mapping_file off on (d)If off , a mapping file showing the mapping of schematic identifiers to VHDL identifiers is notgenerated. The file is named the same as thearchitecture file with a .vxt extension.

override_vectors todowntoas-is (d)If to is specified, override the bit order for vectors toascending on a global basis. If downto , override thebit order to descending on a global basis. If as-is ,leave the bit order for all vectors as-is.

primitive_component Treat the specified component as primitive. Thepathname may be a hard or soft pathname.

primitive_library Treat all the components in the specified library as

primitive. The path to the component must exactlymatch the given argument. For example, if $LIB/cmos/gen_lib is specified, the component$LIB/cmos/gen_lib/nand will be consideredprimitive, while $LIB/cmos/buffer will not.

primitive_netlist Treat the specified single-object EDDM-basednetlist as primitive.




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primitive_schematic Treat the specified schematic as primitive. Forexample, if $QSLAB/component_lib/add_convert/schematic is specified, VHDLwriteconsiders instances of add_convert to referenceBlack Box models and generates an entity and anull architecture (if specified).

primitive_units entityarchitecturenone (d)If entity is specified, only generate an entity forprimitive components. If architecture , only generatean architecture for primitive components. If none,don't generate anything. If primitive_units is notspecified, generate both an entity and a black boxarchitecture for primitive components.

replace_files allnonenon-primitives (d)If all is specified, overwrite all existing files by thesame name in the output_to directory. If none , don'toverwrite any already- existing files. If non-primitive , only overwrite existing files for non-primitive components. Already existing compilationscripts are replaced unless replace_files none isspecified. Already existing architectures are notreplaced if the architecture which would be written isa black box.




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Verifying the Design The VHDL Generation Process

Case-insensitivity

VHDLwrite checks whether any generated entity names would collide if considered case-insensitive. If a potential collision is detected, VHDLwrite issuesa warning message.

Identifiers

Identifiers which are names of instances, components, ports, signals, types,constants, packages, libraries, generics, entities, or architectures must conform tothe following rules:

Identifiers must not be a VHDL reserved word

Identifiers must not be expressions; for example (x+5)

Identifiers must not contain illegal characters. If they do and are user-defined, VHDLwrite will, based on the setting of the map_user_nameskeyword in the options file , either map the identifier to valid VHDL or issuean error message. If these identifiers are generated internally by the system,VHDLwrite always maps them to valid VHDL. Refer to the section titledMapping Names on page 3-2 for details.

Identifiers must not exceed the string length restrictions of any MentorGraphics tool. The tool list includes Design Architect, ModelSim, and theCUI and AMPLE subsystems of the Falcon Framework. Restrictions aresummarized in Table 2-4. Note that there are length restrictions for bothidentifiers and source lines:

Table 2-4. String Length Restrictions

Pattern Generated VHDL

Design Architect Property names must have less than 512 characters.

Property values have no character length restrictions.VHDLwrite Maximum identifier length is 1023 characters.

Maximum source line length is 1024 characters.

ModelSim Maximum identifier length is 1023 characters.No limitation on source line length.


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The VHDL Generation Process Verifying the Design


Types

How VHDLwrite determines the VHDL data type for pins and nets is described indetail starting on page 4-6. VHDLwrite verifies that:

every pin-to-net connection has the same type using a literal stringcompare

user-specified data types do not contain parentheses.

the range of an instance pin (if specified) is the same for the connected net(if specified). If both ranges are constants then VHDLwrite compares theactual widths; otherwise, the comparison is performed using a literal stringcompare

If VHDLwrite detects a mismatch, an error message is issued.

Auto Type Conversion

VHDLwrite has an option that allows one type to be converted to another throughthe use of a specified conversion function. The conversion function must beincluded in a package and made visible through a USE statement. The syntax of the options is:

auto_type_conv driver_type reader_type type_conversion_function

Example 1

Assume that an output pin has a port type of qsim_state and the connected net hasa type qsim_12state. A type mismatch will occur unless the following optionsstatement is included:

AMPLE Limited only by available virtual memory.

Common UserInterface

Limited only by available virtual memory.

Table 2-4. String Length Restrictions [continued]

Pattern Generated VHDL


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vhdl write user.s and reference manual

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