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1.HOW TO COMPILE AND SIMULATE THE MENTOR

GRAPHICS TOOL

Aim: To operate Mentor Graphics Tool (Compile and Simulation only)

Procedure:

I. 1. Go to START-All Programs2. Go to Modelsim SE 6.6bLicensing WizardUsertoolEdit Environment

Variables

[email protected] update it.

Go to MGLS License, enter the same value and update it. Close the window.

II. To create a folder in local drive:1. Go to Z drive(any local drive)2. Create a new folder with name VHDLOCT2011NAME

III. To compile a program using MODELSIM1. Go to STARTAll ProgramsModelsim SE6.6bModelsim window.

2. In Modelsim, go to NewProjectBrowse for the path where the folder is created inStep IIgive project name (combinational circuits) and click OK.

3. A new window pops up to provide the file name inside the folder specified in step 2.Eg:AND2GATE

4. Write program in editor window.library ieee;use ieee.std_logic_1164.all;

entity and2gate is

port(a,b : in std_logic;c: out std_logic);

end and2gate;

architecture andarc of and2gate is

begin

c

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V. Simulation of the programGo to SimulateStart Simulationselect the specified program(and2gate) entity typeinside WORK folder. Click OK

Now the object window appears where the input values are forced.

1. To give a forced inputWe have a and b as input signals. Right click on i/p signals and give FORCE option

and in the popped window give the value of corresponding signal.2. To add the signals into waveform

Go to ADDTo WaveSelected Signals(for single signal)

Signals in Region (for all signals)

Now the Wave window appears.

3. To obtain waveformsClick on RUN icon. Repeat for all combination of inputs to obtain the corresponding

i/p and o/p waveforms.

This is Forced Simulation.

Result:

Familiarized with compilation and simulation of Mentor Graphics Tool.

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2.HOW TO WRITE AND SIMULATE A TEST-BENCH

Aim:To write a test bench and simulate for a two input AND gate.

Procedure:

Test bench is used to simulate input samples continuously and check in the output.

library ieee;

use ieee.std_logic_1164.all;

entity and2gatetestbench is

end;

architecture testbenchandarc of and2gatetestbench is

component and2gateport(a,b : in std_logic;

c : out std_logic);

end component;signal s1,s2,s3:bit;

begin

L1:and2gate port map(s1,s2,s3);

s1

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Now select the SIMtestbenchprogramright clickADDTo WaveAll items in

region.

Wave window pops out. Click RUN icon. The waveform is obtained.

Result:

Familiarized to write a Test-Bench and simulate using VHDL program.

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q r

TRUTH TABLE

q r

0 1

1 0

Fig: Output waveform of not gate

nnotgate

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3.LOGIC GATES

Aim: To design all logic gates

3.1 NOT GATE

library ieee;


entity nnotgate is

port(q: in bit; r: out bit);

end nnotgate;

architecture nnotgate of nnotgate is

begin

r

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q

s

r

TRUTH TABLE

Fig: Out put waveform of And gate

q r s

0 0 0

0 1 0

1 0 0

1 1 1

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TRUTH TABLE

Fig: Output waveform of Nand gate

q r s

0 0 1

0 1 1

1 0 1

1 1 0

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3.3 NAND GATE

library ieee;


entity nand2gate is

port(q,r:in bit;s:out bit);

end nand2gate;

architecture nand2gate of nand2gate is

signal S1:bit;

begin

process(q,r)

begin

if q='0' and r='0' then

S1

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TRUTH TABLE

Fig:Out put waveform ofOR gate

O1 O2 O3

0 0 0

0 1 1

1 0 1

1 1 1

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3.4 OR GATE

library ieee;


entity or2gate t is


end or2gate;

architecture a_or2gate of or2gate is

begin

s

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TRUTH TABLE

Fig: Out put waveform of NOR gate

q r s

0 0 1

0 1 0

1 0 0

1 1 0

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3.5 NOR GATE

library ieee;


entity nor2gateis


end nor2gate;;

architecture NOR_2bit of nor2gate

signal S1:bit;

begin

process(q,r)

begin

if q='0' and r='0' then

S1

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TRUTH TABLE

Fig: Out put waveform of Xor gate

X1 X2 X3

0 0 0

0 1 1

1 0 1

1 1 0

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3.6 XOR GATE

library ieee;


entity xxor2gate is

port(q,r : in bit; s: out bit);

end xxor2gate;

architecture xor_2 of xxor2gate is

begin

process(q,r)

begin

if q='0' and r='0' then s

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TRUTH TABLE

Fig:Out put waveform ofXNOR gate

q r s

0 0 1

0 1 0

1 0 0

1 1 1

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3.7 XNOR GATE

library ieee;


entity xnor2gate is

port(q,r:in std_logic;s:out std_logic);

end xnor2gate;

architecture x nor2gate of x nor2gate is

begin

s

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Fig: output waveform of three input nand gate

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3.8 THREE INPUT NAND GATE

library ieee;


entity nand3gate isport(q,r,s:in std_logic;t:out std_logic);

end nand3gate;


begin

t

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Fig: output waveform of three input nor gate

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Fig: output waveform of four input nand gate

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3.10 FOUR INPUT NAND GATE

library ieee;


entity nand4gate isport(q,r,s,t:in std_logic;u:out std_logic);

end nand4gate;


begin

u

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Fig: output waveform of four input nor gate

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3.11 FOUR INPUT NOR GATE

library ieee;


entity nor4gate is

port(q,r,s,t:in std_logic;u:out std_logic);

end nor4gate;

architecture a_nor of nor4gate is

begin

u

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Fig: Out put waveform of test bench (and gate)

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3.12 TEST BENCH (AND GATE)

library ieee;


entity t_AND2bit is end;

architecture t_AND_2bit of t_AND2bit is

component AND2bit

port(A1,A2:in bit;A3:out bit);

end component;

signal S1,S2,S3:bit;

begin

B1:AND2bit port map(S1,S2,S3);

S1

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TRUTH TABLE

Fig: output waveform of half adder

q r s t

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

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4.ADDER AND SUBTRACTOR

Aim: To design full adder, half adder, full subtractor and half subtractor

4.1 HALF ADDER

library ieee;


entity ha is

port(q,r:in bit;s,t:out bit);

end ha;

architecture a_ha of ha is

begin

s

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TRUTH TABLE

Fig: Out put waveform of full adder

p q r s t

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

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4.2 FULL ADDER

library ieee;


entity fulladder is

port(p,q,r:in bit;s,t:out bit);

end fulladder;

architecture full_adder of fulladder is

component halfadder

port(a,b:in bit;s,c:out bit);

end component;

component OR2bit

port(O1,O2:in bit;O3:out bit);

end component;

signal s1,s2,s3:bit;

begin

a1:halfadder port map(p,q,s1,s2);

a2:halfadder port map(r,s1,s,s3);

a3:OR2bit port map(s3,s2,t);

end full_adder;

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TRUTH TABLE

Fig: Out put waveform of half subtractor

q r s t

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

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4.3 HALF SUBTRACTOR

library ieee;


entity hs isport(q,r:in bit;s,t:out bit);

end hs;

architecture hs of hs is

begin

s

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TRUTH TABLE

q r s t u

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 1 0 0 0

1 1 1 1 1

Fig:output wave form of full subtractor

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4.4 FULL SUBTRACTOR

library ieee;


entity fs is

port(q,r,s:in std_logic;t,u:out std_logic);

end fs;

architecture a_fs of fs is

begin

t

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Fig: output waveform of adder cum subtractor

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4.5 ADDER CUM SUBTRACTOR

library ieee;


entity acs is

port(Q1,R1:in bit_vector(3 downto 0);M:in bit; S1: out bit; T1: out bit_vector(3 downto 0));

end acs;

architecture a_acs of acs is

component fa

port(q,r,s:in bit;t,u:out bit);

end component;

component xxor2gate


end component;

signal a:bit_vector(3 downto 0);

signal b:bit_vector(2 downto 0);

begin

X1:xxor2gate PORT MAP(M,R1(0),a(0));



X4:xxor2gate PORT MAP (M,R1(3),a(3));

F1:fa PORT MAP(Q1(0),a(0),M,T1(0),b(0));

F2:fa PORT MAP(Q1(1),a(1),b(0),T1(1),b(1));

F3:fa PORT MAP(Q1(2),a(2),b(1),T1(2),b(2));

F4:fa PORT MAP(Q1(3),a(3),b(2),T1(3),s1);

end a_acs;

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Fig: output wave form of test bench (half adder)

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4.6 TEST BENCH(HALF ADDER)

library ieee;


entity t_halfadder is end;

architecture t_half_adder of t_halfadder is

component halfadder

port(a,b:in bit;s,c:out bit);

end component;

signal s1,s2,s3,s4:bit;

begin

b1:halfadder port map(s1,s2,s3,s4);

s1

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Fig:output waveform of ripplecarry adder

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5.2 CARRY LOOK AHEAD ADDER

library ieee;


entity cla isport(q,r:in bit_vector(3 downto 0);tin:in bit;tout:out bit;s:out bit_vector(3 downto 0));

end cla;

architecture cla of cla is

component fa


end component;

component or2gate


end component;

component xxor2gate


end component;

component and2gate


end component;

signal g:bit_vector(2 downto 0);

signal ge,pr,t:bit;

begin

x1:xxor2gate port map(q(0),r(0),pr);

x2:xxor2gate port map(pr,tin,s(0));

a1:and2gate port map(pr,ge,t);

a2:and2gate port map(q(0),r(0),ge);

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Fig: output waveform of carry save adder

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5.3 CARRY SAVE ADDER

library ieee;


entity csa is

port(q,r,s:in bit_vector(3 downto 0);t,m:out bit_vector(3 downto 0));

end csa;

architecture a_csa of csa is

component fa


end component;

begin

b1:fa port map(q(0),r(0),s(0),t(0),m(0));




end a_csa;

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Fig: output waveform of multiplier

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6. MULTIPLIER AND DIVIDER CIRCUIT

Aim: To write program for multiplier and divider

6.1 MULTIPLIER

library ieee;


entity mul is

port(q,r:in bit_vector(1 downto 0);s:out bit_vector(3 downto 0));

end mul;

architecture mul of mul is

component and2gate


end component;

component ha

port(q,r:in bit;s,t:out bit);

end component;

signal v:bit_vector(4 downto 1);

begin

a1:and2gate port map(q(0),r(0),s(0));

a2:and2gate port map(q(0),r(1),v(1));



h1:ha port map(v(1),v(2),s(1),v(4));

h2:ha port map(v(3),v(4),s(2),s(3));

end mul;

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0010(rem)

Fig: output waveform of divider

INDEX(i)

q-inp comp r-input s(qoutient) Operation on 1st

column

3 1011 < 0011000 0 none

2 1011 < 0001100 0 none

1 1011 > 0000110 1 q-input(i)-r-

input(i)

0 0101 > 0000011 1 q-input (i)-r-

input(i)

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6.2 DIVIDER

library ieee;


entity div4 isgeneric(n1:integer:=3);

port(q,r:in integer range 0 to 15; s:out std_logic_vector(3 downto 0);t:out integer range 0 to 15;

err:out std_logic);

end div4;

architecture div of div4 is

begin

process(q,r)

variable temp1,temp2:integer range 0 to 15;

begin

temp1:=q;

temp2:=r;

if (r=0)

then err

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6.3 MULTIPLIER TEST BENCH

library ieee;


entity mul_tb is

end;

architecture tb_mularc of mul_tb is

component mul

port(q,r:in bit_vector(1 downto 0);s:out bit_vector(3 downto 0));

end component;

signal a,b:bit_vector(1 downto 0);

signal c:bit_vector(3 downto 0);

begin

L1 : mul port map(a,b,c);

a(0)

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Fig: output waveform of magnitude comparator

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7 . MAGNITUDE COMPARATOR

Aim: To write program for magnitude comparator

PROGRAM

library ieee;


entity comparator is

generic(n:integer:=7);

port(q,r:in std_logic_vector(n downto 0);s1,s2,s3:out std_logic);

end comparator;

architecture acomp of comparator is

begin

s1r else '0';

s2

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TRUTH TABLE

Fig:output wave form of mux 2:1

s t

0 q

1 r

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8 MUX AND DMUX, DECODER AND ENCODER

Aim: To write programs for MUX and DMUX,DECODER and ENCODER

8.1 MUX 2:1

library ieee;


entity mux2to1 is

port(q,r,s : in bit; t : out bit);

end mux2to1;

architecture mux2to1 of mux2to1 is

begin

process(q,r,s)

begin

if s='0' then t

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TRUTH TABLE

Fig: Output waveform of 1:2 DMUX

r s t

0 q 0

1 0 q

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8.2 DMUX 1:2

library ieee;


entity demux1to2 isport(q,r:in std_logic;s,t:out std_logic);

end demux1to2;

architecture demux of demux1to2 is

begin

process(q,r)

begin

if r='0' then s

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8.3 MUX 4:1

library ieee;


entity mux4to1 isport(q,r,s,t,t1,t0:in std_logic;u:out std_logic);

end mux4to1;

architecture mux of mux4to1 is

begin

u

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CIRCUIT DIAGRAM

Fig: Output waveform of 1:4 DMUX

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8.4 DMUX 1:4

library ieee;


entity demux1to4 isport(q,r1,r0:in std_logic;s,t,u,v:out std_logic);

end demux1to4;

architecture demux of demux1to4 is

begin

s

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8.5 OCTAL TO BINARY ENCODER

library ieee;


entity encoder isport(q:in std_logic_vector(0 to 7);r:out std_logic_vector(2 downto 0));

end encoder;

architecture encoder of encoder is

begin

r(0)

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INPUT(q2 to q0) OUTPUT( r7 to r0)

000

001

010

011

100

101

110

111

00000001

00000010

00000100

00001000

00010000

00100000

01000000

10000000

Fig: Output waveform of 3 to 8 Decoder

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8.6 DECODER 3 TO 8

library ieee;


entity decoder is

port(q:in bit_vector(2 downto 0);r:out bit_vector(7 downto 0));

end decoder;

architecture decoder of decoder is

begin

r(0)

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Fig: Output waveform of testbench(MUX 2:1)

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8.7 TEST BENCH(MUX 2:1)

library ieee;


entity tb_mux2to1 is end;architecture tb_mux_2to1 of tb_mux2to1 is

component mux2to1

port(q,r,s : in bit; t : out bit);

end component;

signal s1,s2,s3,s4:bit;

begin

b1:mux2to1 port map(s1,s2,s3,s4);

s1

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BINARY GRAY

q3 q2 q1 q0 r3 r2 r1 r0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 1 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

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9 CODE CONVERTERS

Aim:To design and implement different code converters using VHDL.

i. Binary to gray code converterii. Gray code to binary converteriii. Binary to BCD converteriv. BCD to Excess3 converter

9.1 BINARY TO GRAY CODE CONVERTER

library ieee;


entity btog is

port(q:in std_logic_vector(3 downto 0);r:out std_logic_vector(3 downto 0));

end btog;

architecture btogarc of btog is

begin

r(3)

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Fig: Output waveform of binary to gray code converter

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GRAY BINARY

q3 q2 q1 q0 r3 r2 r1 r0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 0 0

0 1 1 1 1 1 0 1

1 0 0 0 1 1 1 1

1 0 0 1 1 1 1 0

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 0 1 0 1 1

1 1 1 1 1 0 1 0

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9.2 GRAY TO BINARY CODE CONVERTER

library ieee;


entity gb is

port(q:in std_logic_vector(3 downto 0);r:inout std_logic_vector(3 downto 0));

end gb;

architecture gbarc of gb is

begin

r(3)

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Fig: Out put waveform of gray to binary code converter

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BINARY BCD

q3 q2 q1 q0 r4 r3 r2 r1 r0

0 0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0 1

0 0 1 0 0 0 0 1 0

0 0 1 1 0 0 0 1 1

0 1 0 0 0 0 1 0 0

0 1 0 1 0 0 1 0 1

0 1 1 0 0 0 1 1 0

0 1 1 1 0 0 1 1 1

1 0 0 0 0 1 0 0 0

1 0 0 1 0 1 0 0 1

1 0 1 0 1 0 0 0 0

1 0 1 1 1 0 0 0 1

1 1 0 0 1 0 0 1 0

1 1 0 1 1 0 0 1 1

1 1 1 0 1 0 1 0 0

1 1 1 1 1 0 1 0 1

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9.3 BINARY TO BCD CODE CONVERTER

library ieee;


entity btob isport(q:in std_logic_vector(3 downto 0);r:inout std_logic_vector(4 downto 0));

end btob;

architecture btobarc of btob is

begin

r(4)

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r0=q0 r1=q3q2q1 +q3

r3=q3 q2 + q1

r4=q3q2+q2 q1

Fig: Out put waveform of binary to bcd code converter

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9.4 BCD TO EXCESS-3 CODE CONVERTER

library ieee;


entity bcdtoexcess3 isport(q,r,s,t:in bit;u,v,w,x:out bit);

end bcdtoexcess3;

architecture bcdfun of bcdtoexcess3 is

component and2gate

port (q,r:in bit;s:out bit);

end component;

component xor2gate


end component;

component or2gate


end component;

component not1gate

port (q:in bit;r:out bit);

end component;

signal a1,o1,x1:bit;

begin

G1:or2gate port map (q,a1,u);

G2:and2gate port map (r,o1,a1);

G3:or2gate port map (s,t,o1);

G4:xor2gate port map (o1,r,v);

G5:xor2gate port map (s,t,x1);

G6:not1gate port map (x1,w);

G7:not1gate port map (t,x); end bcdfun;

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9.5 TEST BENCH( BINARY TO GRAY CODE CONVERTER)

library ieee;


entity b2gtestbench isend;

architecture testbench of b2gtestbench is

component btog

port(q:in std_logic_vector(3 downto 0);

r:out std_logic_vector(3 downto 0));

end component;

signal s1,s2: std_logic_vector(3 downto 0);

begin

L1:B2G port map(s1,s2);

s1(0)

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s q

r qb

clk

TRUTH TABLE

S R Clk q qb

0

0

1

1

0

1

0

1

1

1

1

1

q

0

1

X

qb

1

0

X

Fig: Output waveform of SR FlipFlop

sr

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10 FLIP FLOPS

Aim:To design and implement the following flipflops using VHDL.

10.1 SR flipflops

library ieee;


entity sr is

port(s,r,clk,rst:in std_logic;q:inout std_logic;qb:out std_logic);

end sr;

architecture sr of sr is

begin

process(s,r,clk)

begin

if rst='1' then

q

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10.2 JK FLIP FLOP

library ieee;


entity jkff is

port(j,k,clk,rst:in std_logic;q,qb:out std_logic);

end jkff;

architecture jkff of jkff is

signal qt,qbt:std_logic;

begin

process(j,k,clk,rst,qt,qbt)

begin

if rst='1' then

qt

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d q

clk qbar

TRUTH TABLE

d Clk q qbar

0

1

1

1

0

1

1

0

Fig: Output waveform of D Flip Flop

dff

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10.3 D FLIP FLOP

library ieee;


entity dff isport(d,clk,rst:in std_logic;q,qbar:inout std_logic);

end dff;

architecture dff of dff is

begin

process(d,clk,rst)

begin

if rst='1' then

q

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T q

clk qbar

rst

TRUTH TABLE

T Clk rst q qbar

0

1

X

1

1

X

0

0

1

1

0

0

0

1

0

Fig: Output Waveform of T Flip Flop

tff

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10.4 T FLIP FLOP

library ieee;


entity tff isport(t,clk,rst:in std_logic;q,qbar:inout std_logic);

end tff;

architecture tff of tff is

begin

process(t,clk,rst)

begin

if rst='1' then

q

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t_dff

q t

r u

Fig: Output waveform of test bench (D Flip Flop)

d q

Clk qb

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10.5 TEST BENCH(D FLIP FLOP)

library ieee;


entity t_dff is end;architecture t_d_ff of t_dff is

component dff

port(d,clk,rst:in std_logic;q,qbar:inout std_logic);

end component;

signal q,r,s,t,u: std_logic;

begin

a1:dff port map(q,r,s,t,u);

q

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q(3)

q(2)

clk q(1)

q(0)

Clk Q3 Q2 Q1 Q0

1

2

34

5

1 0 0 0

0 1 0 0

0 0 1 00 0 0 1

1 0 0 0

Fig: Output waveform of Ring Counter

ring1

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11 SYNCHRONOUS COUNTER

Aim: To write program for Synchronous Counters

11.1 RING COUNTER

library ieee;


entity ring1 is

port(clk:in std_logic;q:inout std_logic_vector(3 downto 0));

end ring;

architecture ring1 of ring1 is

begin

process(clk)

variable r: std_logic_vector(3 downto 0):= "0001";

variable s: std_logic;

begin

if (clk'event and clk='1')then

s:=r(0);

r:=s & r(3 downto 1);

end if;

q

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q3

q2 q2

clk q1

q0

TRUTH TABLE

Clk Q3 Q2 Q1 Q0

1

2

3

4

5

1 0 0 0

1 1 0 0

1 1 1 0

1 1 1 1

0 1 1 1

Fig: Output waveform of Johnson Counter

johnson

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11.2 JOHNSON COUNTER

library ieee;


entity johnson isport(clk:in std_logic;q:out std_logic_vector(3 downto 0));

end johnson;

architecture johnson of johnson is

begin

process(clk)

variable r:std_logic;

variable s:std_logic_vector(3 downto 0):="0000";

begin

if(clk'event and clk='1') then

r:=not s(0);

s:=r& s(3 downto 1);

end if;

q

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Clk count

Clk Count

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Fig: Output waveform of Up- Counter

upcounter

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11.3 UP-COUNTER

library ieee;


use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;

entity upcounter is

port(clk:in std_logic;count:out std_logic_vector(3 downto 0));

end upcounter;

architecture behavioural of upcounter is

signal temp:std_logic_vector(3 downto 0):="0000";

begin

process(clk)

begin


temp

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clk Count

Clk Count

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

1111

1110

1101

1100

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

0000

Fig: Output waveform of Down Counter

downcounter

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11.4 DOWN COUNTER

library ieee;



entity downcounter is


end downcounter;

architecture behavioural of downcounter is


begin

process(clk)

begin


temp

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clk Count

clk Q3 Q2 Q1 Q0

1

2

3

4

5

6

7

8

9

0000

0001

0010

0011

0100

0101

0110

0111

1000

Fig: Output waveform of Decade Counter

decadecounter

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11.5 DECADE COUNTER

library ieee;



entity decadecounter is


end decadecounter;

architecture decadecounter of decadecounter is


begin

process(clk)

begin


temp

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tb_ring

ring1

r s

Fig: Output waveform of Test bench (Ring Counter)

Clk Count

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TRUTH TABLE

Fig: Output waveform of Up-Counter

clk q(0) q(1) q(2) q(3)

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

clk q(0) q(1) q(2) q(3)

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 114 1 1 1 0

15 1 1 1 1

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12 ASYNCHRONOUS COUNTER

Aim: To write program on Asynchronous Counter

i. Up counterii. Down counter

12.1 UP-COUNTER

library ieee;


entity a_upcounter is

port(clk,rst:in std_logic;q:inout std_logic_vector(3 downto 0));

end a_upcounter;

architecture a_upcounter of a_upcounter is

component tff

port(t,clk,rst:in std_logic;q,qbar:inout std_logic);

end component;

signal qbar:std_logic_vector(3 downto 0);

begin

s1:tff port map('1',clk,rst,q(0),qbar(0));

s2:tff port map('1',qbar(0),rst,q(1),qbar(1));



end a_upcounter;

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TRUTH TABLE

Fig: Output waveform of Down counter

clk q(0) q(1) q(2) q(3)

0 1 1 1 1

1 1 1 1 0

2 1 1 0 1

3 1 1 0 0

4 1 0 1 1

5 1 0 1 0

6 1 0 0 1

7 1 0 0 0

clk q(0) q(1) q(2) q(3)

8 0 1 1 1

9 0 1 1 0

10 0 1 0 1

11 0 1 0 0

12 0 0 1 1

13 0 0 1 014 0 0 0 1

15 0 0 0 0

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q1 q2

clk

Count_up/count_down

TRUTH TABLE count_up=1 count_down=1

Fig::Output waveform of Up-Down Counter

clk q2(0) q2(1) q2(2) q2(3)

0 1 1 1 1

1 1 1 1 0

2 1 1 0 13 1 1 0 0

4 1 0 1 1

5 1 0 1 0

6 1 0 0 1

7 1 0 0 0

8 0 1 1 1

9 0 1 1 0

10 0 1 0 111 0 1 0 0

12 0 0 1 1

13 0 0 1 0

14 0 0 0 1

15 0 0 0 0

clk q1(0) q1(1) q1(2) q1(3)

0 0 0 0 0

1 0 0 0 1

2 0 0 1 03 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 011 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1

a_upcounter

a_downcounter

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13 UP- DOWN COUNTER

Aim: To design asynchronous and synchronous up-down counters.

13.1 ASYNCHRONOUS UP- DOWN COUNTER

library ieee;


entity a_updowncounter is

port(clk,rst,count_up,count_down:in std_logic;q:inout std_logic_vector(3 downto 0));

end a_updowncounter;

architecture a_updowncounter of a_updowncounter is

component jkff

port(j,k,clk,rst:in std_logic;q,qb:inout std_logic);

end component;

component and2gate

port (q,r:in std_logic;s:out std_logic);

end component;

component or2gate

port (q,r:in std_logic;s:out std_logic);

end component;

signal qbar:std_logic_vector(3 downto 0);

signal t:std_logic_vector(8 downto 0);

begin

f1:jkff port map('1','1',clk,rst,q(0),qbar(0));

a1:and2gate port map(count_up,q(0),t(0));

a2:and2gate port map(count_down,qbar(0),t(1));

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o1:or2gate port map(t(0),t(1),t(2));

f2:jkff port map('1','1',t(2),rst,q(1),qbar(1));









end a_updowncounter;

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13.2 SYNCHRONOUS UP-DOWN COUNTER

library ieee;



entity updowncounter is

port(clk:in std_logic;drn: in std_logic;count:out std_logic_vector(3 downto 0));

end updowncounter;

architecture behavioural of updowncounter is


begin

process(clk,drn)

begin


if drn='1' then

temp

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clk SIPO

din q[3:0]

Fig: output waveform of sipo

SIPO

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clk PISO

dout

d[3:0]

Fig:output waveform of piso shift register

PISO

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14.2 PARALLEL IN SERIAL OUT SHIFT REGISTER

Library ieee;

Use ieee.std_logic_1164.all;

Entity piso is

Port(clk,din:in bit;d:in bit_vector( 3 downto 0) ;dout:out bit);

End piso;

Architecture a_piso of piso is

signal a:integer:= 3;

signal b:bit_vector(0 to 3);

begin

process(din,clk)

begin

If (clk'event and clk='1') then

dout

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clk PIPO

dout[3:0]

din[0:3]

CIRCUIT DIAGRAM

Fig: output waveform of PIPO register

PIPO

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14.3 PARALLEL IN PARALLEL OUT SHIFT REGISTER

Library ieee;


Entity pipo is

Port(clk:in bit;din:in bit_vector (0 to 3);dout:out bit_vector(0 to 3));

end pipo;

architecture a_pipo of pipo is

begin

Process(din,clk)

begin


Dout

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Fig: output waveform of left shift siso register

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14.4 LEFT SHIFT SERIAL IN SERIAL OUT SHIFT REGISTER

library ieee;


entity l_siso is

Port(d,clk:in bit;dout:out bit);

End l_siso;

architecture a_siso of l_siso is

begin

Process(d,clk)

Variable a:bit_vector(3 downto 0);

Variable b:bit;

begin


b:=d;

a:=a(2 downto 0) & b;

end if;

Dout

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Fig: output waveform of right shift siso

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14.5 RIGHT SHIFTSERIAL IN SERIAL OUT SHIFT REGISTER

library ieee;

Use ieee.std_logic_1164.all;entity r_siso is


End r_siso;

architecture a_siso of r_siso is

begin

Process(d,clk)

Variable a:bit_vector(0 to 3);

Variable b:bit;

begin


b:=d;

a:=b & a(0 to 2);

end if;

Dout

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14.6 TEST BENCH OF SISO-LEFT

library ieee;


entity t_lsiso is end;

architecture t_lsiso of t_lsiso is

component lsiso is


end component;

signal s1,s2,s3: bit;

begin

a1:l_siso port map(s1,s2,s3);

s1

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Q[3:0] BARREL-SHIFTER

R[1:0] S[3:0]

TRUTH TABLE

R1 R0 Q3 Q2 Q1 Q0 S3 S2 S1 S0

0 0 0 1 0 1 0 1 0 1

0 1 0 1 0 1 1 0 1 0

1 0 0 1 0 1 0 1 0 1

1 1 0 1 0 1 1 0 1 0

Fig :output waveform of barrel shifter

BARREL-SHIFTER

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15. BARREL SHIFTER

Aim: To design a barrel shifter .

PROGRAM

library ieee;


entity barrel_shifter is

port(q:in bit_vector(3 downto 0); r:in bit_vector(1 downto 0);s:out bit_vector(3 downto 0));

end barrel_shifter;

architecture barrel_shifter of barrel_shifter is

begin

process(q,r)

begin

case r is

when "00"=> s s(3)

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STATE DIAGRAM

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16.TRAFFIC LIGHT CONTOL USING FSM

Aim:To design a traffic light controller using FSM and implement using VHDL.

PROGRAM:

library ieee;


use ieee.std_logic_unsigned.all;

entity traffic is

port (clk: in std_logic;

clr: in std_logic;

q: out std_logic_vector(5 downto 0));

end traffic;

architecture traffic of traffic is

type state_type is (s0, s1, s2, s3, s4, s5);

signal state: state_type;

signal count: std_logic_vector(3 downto 0);

constant SEC5: std_logic_vector(3 downto 0) := "1111";

constant SEC1: std_logic_vector(3 downto 0) := "0011";

begin

process(clk, clr)

begin

if clr = '1' then

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Fig:Six colored LEDs can represent a set of traffic lights

State North-South East-West Delay(Sec.)

0 Green Red 5

1 Yellow Red 1

2 Red Red 1

3 Red Green 5

4 Red Yellow 1

5 Red Red 1

Table 1 Traffic Light States

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state

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SIMULATION RESULT

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end if;

when s3 =>

if count < SEC5 then

state

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CLK PATTERNDETECTOR

Q S

STATE DIAGRAM

Fig: output waveform of pattern recognizer

MEALY

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17 PATTERN RECOGNIZER

Aim:To design a pattern recognizer using FSM and implement using VHDL.

PROGRAM:

library ieee;


entity patterndetector is

port (clk,q:in bit;

s:out bit);

end patterndetector; -- detect a 0110 sequence

architecture mealy of patterndetector is

type states is (t1,t2,t3,t4,t5);

signal state: states := t1; -- initial value is a

signal next_state: states := t1; -- initial value

begin

clock: process(clk)

begin

if clk'event and clk = '1' then

state

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s

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MINI

PROJECTS

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Fig1:Serial data transmission using UART

Fig2:Timing diagram of UART message

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Fig3:Block diagram of UART transmitter

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ones during a reset cycle.A state machine is used to control the data paths ,and to identify the

state of the transmit register ,empty or in use.

PROGRAM

libraryieee;

useieee.std_logic_1164.all;

entity uart is

port(shift_ldf:in bit; clkenbt:in bit; clk: in bit; datat : in bit_vector(7 downto 0); resetf:in bit;

Serial_out:out bit; xmitmt:out boolean);

end uart;

architecture uart of uart is

subtypeInt0to9_typ is integer range 0 to 9;

signalxmit_r:bit_vector(9 downto 0); --transmit register

signalcount_r:Int0to9_typ; -- # of serial bits sent

begin

-----------------------------------------------------------------------------------------------------

--Purpose: Models the transmit register of a UART

-- Operation is as follows

--All operations occur on rising edge of clk

--If reset =0 then xmit_r is reset to 1111111111, count_r is reset to 0

--If clkenbt=1 and shift_ldf=0 and resetf=1 then 1 & datat & 0 get loaded in

-- to xmit_r

--If clkenbt=1 and shift_ldf=1 and resetf=1 then 1 & xmit_r(9 downto 0) getloaded --

into xmit_r

--(shift right with a 1 shifted in)

--count_r is incremented to no more than 10

--(i.e. if it is 9 ,then it stays at 9)

----------------------------------------------------------------------------------------------------------

Process

begin

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SIMULATION RESULT

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wait untilclk'event and clk='1'; --rising edge of clock

ifresetf='0' then

xmit_r

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BLOCK DIAGRAM

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TRUTHTABLE SHOWING OPERATION OF ALU

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SIMULATION RESULTS

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CONCLUSION

Here an 8 bit ALU is implemented and the output is verified. It can perform eight

arithmetic operations and eight logical operations.

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20.STATIC RAM

ABSTRACT

Memory can be of two types: ROM and RAM.ROM stands for READ ONLY

MEMORY. We can perform only write operation in ROM RAM stands for RANDOM ACESS

MEMORY.We can perform both write operation and raed operation in RAM.RAM can be of

many types.SRAM is one method of realizing RAM.SRAM stands for static RAM.It consists of

two cross coupled inverters with output of first inverter being connected to input of next.

This project propose a way to realize SRAM using VHDL.The design incorporates two

inputs and one output.One input is used to give inputs and other one is used to select whether

read or write has to done.

OPERATION

A simple memory cell has being designed using an SR latch,but we could have used any

other latches,such as a D-latch.The cell has tri-state output.If select line(sel) is low,the output of

cell is in high impedence.A Read/Write(R/w) input signal controls the cells cycle mode.If R/W

is high ,the cell is in write cycle.Table1 shows the excitation table of the cell,with

inputs(select,r/w,Data-in,current state ) and the corresponding outputs (next-state,output).From

the current state and next state we determine S and R of the latch. For example,if the current state

is 0 and next state 0,then two combinations of SR latch can generate this transition:s=0,R=0 and

s=0,R=1;so SR=OX ,where x is dont care.

STEPS IN IMPLEMENTING SRAM

1. Develop excitatation table for circuit based on required function.2. Obtain reduced Boolean expressions based on k-map reduction.3. Implement the function using basic gates and sr flip flop.4. Writethe VHDL code for SRAM

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CIRCUIT DIAGRAM

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K-MAP SIMPLIFICATION

DIN/Q

SEL/RW00 01 11 10

00 Z Z Z Z

01 Z Z Z Z

11 0 1 1 0

10 0 0 1 1

S = Sel RW Din

DIN/Q

SEL/R

W

0

0

0

1

1

1

1

0

00 0 0 0 0

01 0 0 0 0

11 X 0 0 X

10 X 1 0 0

R = Sel RW Din

DIN/Q

SEL/RW00 01 11 10

00 0 0 0 0

01 0 0 0 0

11 0 X X 0

10 0 0 X 1

OUTPUT = Sel RW Din + Sel RW = R + Sel RW0 ( for sel = 1)

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SIMULATION RESULT

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CONCLUSION

An SRAM module was developed using VHDL.It can perform read and wrire

operations.A single signal R/W is used to select between read and write operations.

vhdl rec (4)

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