vhdl projects 2011
TRANSCRIPT
)1( Generic Multiplexer :
. Generic Multiplexer Circuit n sel m . 2**n ) n . ( m GENERIC n 3 = m VHDL Quartus II FPGA 2. DE
: n 2 . On/Off X . sel . y Pin Assignment !!! - - - -
1
)2( Priority Encoder :
. 7-Levels Priority Encoder Circuit 0 000 . VHDL Quartus II FPGA 2. DE
:- On/Off . - . - Pin Assignment !!!
2
)3( : Barrel Shifter
) . ( Barrel Shifter inp shift 1 outp shift 0 . VHDL Quartus II FPGA 2. DE
:- On/Off inp . shift - . outp - Pin Assignment !!!
3
)4( :
. clk count 8 . clk . VHDL Quartus II FPGA 2. DE
:- Push-Button ) !!! ( . - . count - Pin Assignment !!!
4
)5( Generic Decoder :
. Generic Decoder Circuit ) sel m ( ) ena ( ) x n ( . n 2 ) . m = log2(n 0 = ena x 1 ) ( sel 0 1 :
VHDL Quartus II FPGA 2. DE
:- 2 = m 4 = . n - On/Off sel . ena - . x - Pin Assignment !!!
5
)6( Generic Parity Detctor :
. Generic Parity Detector Circuit
input ) 1+ ( n ) n ( GENERIC . output output 0 input output 1 input . VHDL Quartus II FPGA 2. DE
:- 7 = . n - On/Off . input - . output - Pin Assignment !!!
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)7( Generic Parity Generator :
. Generic Parity Generator Circuit input n ) n ( GENERIC ) 1+ ( n . output n ) output ( input MSB output 0 input 1 input . ) ( . VHDL Quartus II FPGA 2. DE
:- 7 = . n - On/Off . input - . output - Pin Assignment !!!
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)8( n-by-m Encoder :
. n-by-m 8 x 3 ) y )8(2 . ( 3 = log x 1 0 ) ( 1 x . y y ) ZZZ y . ( High Impedance VHDL Quartus II FPGA 2. DE
:- On/Off . x - . y - Pin Assignment !!!
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)9( ALU :
8 . : ) a 4 8 ( ) b 4 8 ( cin sel 4 ) ( . Arithmetic Unit sel Logic Unit sel . ) y 4 8 ( MSB ) sel 0 = )3( sel 1 = )3( . ( sel VHDL Quartus II FPGA 2. DE
:- a b y 4 !!! - On/Off a b cin sel - . y - Pin Assignment !!!9
)01( :
0 9 . ) clk ( 0 9 . digit 4 . VHDL Quartus II FPGA 2. DE
:- Push-Button ) !!! ( . - . digit - Pin Assignment !!!
01
)11( Shift Register :
4 . ) d ( ) clk ( ) rst ( . q d 4 . rst ) . ( clk VHDL Quartus II FPGA 2. DE
:- On/Off . d - 2 Push-Buttons clk . rst - 2 DE . q - Pin Assignment !!!
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)21( 00 99 :
00 99 . ) clk ( ) rst rst 00 ( . 2 7-Segment Displays BCD . ( Seven Segments Display Code ) SSD VHDL Quartus II FPGA 2. DE
:- 2 Push-Buttons clk . rst - 7-Segments 2 DE 1 ) digit ( 2 ) digit ( . - Pin Assignment !!!
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)31( ) ( :
) ( . d q 4 . clk ) sel ( q d ) 2 = sel q 3 d 3 . ( q = q VHDL Quartus II FPGA 2. DE
:- sel 3 . INTEGER RANGE 0 TO - On/Off . d - Push-Button ) !!! ( . - On/Off . sel - . q - Pin Assignment !!!
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)41(
data 7 zeros 3 data ) zeros MSB '1' . : "0101000" 3 ( . VHDL Quartus II FPGA 2. DE
:
- zeros 7 . INTEGER RANGE 0 To - On/Off . data - . zeros - Pin Assignment !!!
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)51( Timer 0 min : 00 sec . 9 min : 59 sec
Timer 0 min : 00 sec . 9 min : 59 sec clk ) ( reset / . start / stop start / stop '1' 0 min : 00 sec . 9 min : 59 sec . 50 MHz 3 . 7-Segments VHDL Quartus II FPGA 2. DE
:- 2 Push-Buttons start / stop . reset - 2 DE 50 MHz . clk 50 MHz !!! 1 Hz - 3 7-Segments 2 DE ) ( . 7-Segments !!! 7-Segments - Pin Assignment !!!
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)61(
data 7 ones zeros 3 data ones data . zeros VHDL Quartus II FPGA 2. DE
:
- ones zeros 0 INTEGER RANGE 7 . TO - On/Off . data - 2 DE ones . zeros - Pin Assignment !!!
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)71( Sequence Detctor d clk . rst . q "111" d :
"111" . q '1' '1' d '1' q '0' '0' . d VHDL Quartus II FPGA 2. DE
:- On/Off 2 DE . d - 2 Push-Buttons clk . rst - 2 DE . q - Pin Assignment !!!
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)81( ( FSM ) Finite States Machine :
. inp clk rst outp . VHDL Quartus II FPGA 2. DE
:- On/Off 2 DE . inp - 2 Push-Buttons clk . rst - 2 DE . outp - Pin Assignment !!!
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)91( : Barrel Shifter
. inp 8 shift 3 inp outp 8 . inp "00001111" shift "010" ) 2 ( outp "00000011" ) ( . VHDL Quartus II FPGA 2. DE
:- 8 On/Off 2 DE . inp - 3 On/Off . shift - 8 ) ( 8 LEDs 2 DE . outp - Pin Assignment !!!
91
)02( 4 :
/ 4 . : clk rst ena ) u_d '0' = u_d '1' = . ( u_d count 4 . VHDL Quartus II FPGA 2. DE
:- 2 Push-Buttons clk . rst - On/Off ena . u_d - 4 2 DE count . - Pin Assignment !!!
02
)12( 4 :
/ 4 . : clk rst ena ) u_d '0' = u_d '1' = ( u_d load ) value 4 ( . count 4 . VHDL Quartus II FPGA 2. DE
:- 2 Push-Buttons clk . rst - On/Off 2 DE ena u_d load . value - 4 2 DE count . - Pin Assignment !!!
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)22( ( Binary-Coded Decimal ) BCD ) 4 ( :
BCD . x ) ( BCD y ) ( BCD cin . s 4 cout '1' 9 . VHDL Quartus II FPGA 2. DE
:- On/Off 2 DE x y . cin - 7-Segments 2DE . s - 2 DE . cout - Pin Assignment !!!
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)32( 4 :
4 . A 4 B 4 . A B : ) AeqB ( A = B AltB ) ( A < B ) AgtB . ( A > B VHDL Quartus II FPGA 2. DE
:- On/Off 2 DE A.B - 2 DE AeqB AltB . AgtB - Pin Assignment !!!32
)42( Shift Register 4 4 : shift_load
4 . clock ) reset ( shift_load ) ( s_input ) 4 ( . p_input shift_load '0' s_input shift_load '1' ) 4 ( p_input ) Q 4 ( . VHDL Quartus II FPGA 2. DE
:- On/Off 2 DE shift_load s_input . p_input - 2 Push-Buttons reset . clock - 4 2 DE . Q - Pin Assignment !!!
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)52( BCD 0 BCD 1 BCD 4 clear : enable
BCD . ) clock ( clear enable '1' '0' . 0 BCD 1 BCD 00 99 . VHDL Quartus II FPGA 2. DE
:- Push-Button . clock - On/Off clear . enable - 8 2 DE 0 BCD 1. BCD - Pin Assignment !!!
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)62( 4 :
.
4 . 0 S 1 S . "00" = 0 S1S ) A 4 ( "10" = 0 S1S s_input ) 0 ( D A0 = s_input . clock "01" = 0 S1S s_input ) 3( D A3 = s_input . clock = 0S1S "11" ) I 4 ( A = I . clock ) reset ( '0' A ) ( . VHDL Quartus II FPGA 2. DE
:- 2 Push-Buttons clock . reset - On/Off 2 DE 0 S 1 S s_input . I - 4 2 DE . A - Pin Assignment !!!62
)72( 4
.
4 . '1' = clear ) ( load . increment '0' = clear '1' = load ) I 4 ( ) A 4 ( I . increment '0' = clear = load '0' '1' = increment . clear load increment '0' . VHDL Quartus II FPGA 2. DE
:- Push-Button clock . - On/Off 2 DE clear load increment . I - 4 2 DE . A - Pin Assignment !!!72