vhdl implementation of insertion sort - ntnudam/fag/78076/dokumenter/vhdl_sort/prosjekt.pdf ·...

COURSE 78076 COMPUTERS PROJECT

SPRING 1999

COPYRIGHT 1999 RUNE NAKIM

VHDL IMPLEMENTATION OFINSERTION SORT

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Rune B. Nakim 1999 Page i

AbstractThe market of internet search engines is growing fast, and the technology behind these are get-ting faster and faster. The bottleneck in these systems today are the sorting of hits to be able to present the best hits first.

To make the sorting more efficient, it could be implemented in hardware. In this project an al-gorithm based on insertion sort is described in VHDL.

The design has been verified and has been found to be working correctly.

The design has been synthesized and the area and timing of the sorter has been discussed.

Page ii Rune B. Nakim 1999

PrefaceThis is a project carried out at the Department of Computer and Information Science at the Nor-wegian University of Science and Technology (NTNU) in the spring of 1999.

In addition to my supervisor, Lasse Natvig, I wish to thank Gunnar Tufte and Knut Førland for their time when I needed to discuss one or two things.

Trondheim, April 27. 1999

Rune B. Nakim

Rune B. Nakim 1999 Page iii

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List of appendixes

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Page vi Rune B. Nakim 1999

Chapter 1 • Introduction

Rune B. Nakim 1999 Page 1

CHAPTER 1 •

INTRODUCTIONThe competition in the field of World Wide Web search engines has increased much recently and the users now have many different offers to choose from. This means that all search engines have to strive to be faster and more user-friendly than the others.

Being fast means that the user does not have to wait more than a few seconds for a search through “the whole web” and being user friendly means that the user finds what he or she was looking for. FAST ASA, a Trondheim based firm, has created search hardware which enables a search engine to search through virtually “the whole web” with response times of about 0.6 seconds (Ryvarden, 1998).

One of the challenges in the field of user-friendliness is to present the most relevant documents first to the user. This means that the hits have to be sorted according to a value set on each. Ac-cording to Halaas (1999) this is the most severe bottleneck in modern search engine systems be-cause the sorting is done in software.

The motivation for this project is to come up with a system which can sort search hits in hard-ware and thus providing faster response times for the whole search engine system.

This report consists of three main chapters:• Background, which describes some of the theory and methodology used in the project,

and other relevant background information. Many of the subjects studied have been pre-sented.

• The design, which describes the specification, the design and how this was developed from the specification, the verification of the design and the result of the synthesis and discussion of these results.

• Final notes, which summarizes what the project work has resulted in.

Chapter 1 • Introduction

Page 2 Rune B. Nakim 1999

1.1 THE ASSIGNMENT

1.1.1 The text of the assignment

“The task is to implement the sorter described by Arisland et al. (1984) using VHDL. The sorter shall be verified using a test bench and synthesized. The project starts with a study of VHDL, with focus on VHDL for synthesis and the process from design to synthesis. The results should be a VHDL description of a working, well structured sorter, and num-bers on the size of the synthesized circuit. Bus and register widths and sorter size should be parameters.”

1.1.2 DecisionsDuring the development of a formulation of the assignment, the following was decided:

• Concentration should be on the sorter, not on the surroundings. The model to be used was that data is read from RAM and written to RAM. The control for this communica-tion is part of the surroundings.

• Design for testability is an important issue in design of ASICs. Despite of this, this issue has not been treated in this project.

1.1.3 GoalsFrom the assignment text and the decisions made, these goals were set for this project:

1. Learn VHDL and specifically syntesizable VHDL. Learn about the design structure and methodology when designing with VHDL and the processes of verification and synthesis.

2. Construct a sorter based on the algorithm described by Arisland et al. (1984) using VHDL.

3. Synthesize the SORTER and discuss the results.4. Learn to use the tools needed for VHDL simulation and synthesis.

Chapter 2 • Background


CHAPTER 2 •

BACKGROUND



2.1 THE PARALLEL SHIFT SORT ALGO-RITHMThis section is based entirely on the article “VLSI parallel shift sort algorithm and design” by Arisland, Aasbø and Nundal (1984).

2.1.1 AlgorithmArisland et al. (1984) presented a parallel shift sort algorithm based on sorting by insertion. The algorithm, which uses the sorting of playing cards as its setting, is shown in Figure 1 on page 4. This is an example of sorting by insertion. For the first element, no decision on where to place it is needed. For each subsequent element, all elements already sorted must be scanned to decide where to place the new element. Finally the element is inserted at the correct place. This way the list of elements is always kept in sorted order.

Steps 2 and 3 are both of order O(N). Including the surrounding while loop, the algorithm is of order O(N2) when run on a sequential computer. Turning to the hardware implementation steps 2 and 3 can be done in parallel, so the algorithm becomes of order O(N). This is optimal for se-quential input/sequential output sorters.

2.1.2 Logic descriptionThe parallel shift sort algorithm is implemented with a cellular array with shared input bus ar-chitecture. This bus is driven only from a single point and the silicon area overhead of having a

fan_size := 0;while more_cards do

1. /* Take next card. */fan_size := fan_size + 1;new_card := input;

2. /* Find position to insert new card. */new_pos := 0;found_pos := false;while not found_pos do

new_pos := new_pos + 1;if new_pos = fan_size thenfound_pos := true

elseif fan[new_pos] >= new_card then

found_pos := true;end_while;

3. /* Shift all cards from insert position to end. */for index := fan_size to new_pos + 1 step - 1 do

fan[index] := fan[index-1]end_for;

4. /* Insert new cars(sic.). */fan[new_pos] := new_card;

end_while;

Figure 1: Insertion sort (Arisland et al., 1984)



shared bus is smaller than if the bus should be driven from each cell. An illustration of the ar-chitecture is shown in Figure 2 on page 5.

Each cell contains a register for storing a key and a disable bit and has the following input and output signals:

• Global data signals for input keys.• Global control signals.• Local data input from preceding cell.• Local control signals from preceding cell.• Local data output.• Local control output.

Each cell is capable of determining whether the data on the global input bus is greater than or equal to the cell’s own register data. The disable bit is shifted one cell position to the right each time a key is entered. The disable bit input to cell #0 is always 0. This way the cells which is part of an active sorting sequence, has a disable bit of 0.

2.1.3 The operationThe first step is to put a key on the global data bus. Then each cell is capable of latching data either from the preceding cell or the input bus, or do nothing.

For each cell to be able to decide what to do, it needs the following information:

• BUS_GE_THIS: True if data on input bus is greater than or equal to data in cell register #i.

• BUS_GE_PREC: True if data on input bus is greater than or equal to data in cell register #i-1.

• DIS_THIS: Content of disable bit for cell #i.• DIS_PREC: Content of disable bit for cell #i-1.

The operation is like this: All cells to the left of the cell supposed to be latching in the new data, will find BUS_GE_THIS to be true and these cells will do nothing. The cell which finds BUS_GE_THIS to be false and BUS_GE_PREC to be true will latch in the input data. All cells to the right of this cell will find BUS_GE_THIS and BUS_GE_PREC to be false and will latch

Figure 2: The datapaths of the architecture used to implement the parallel shift sort (Arisland et al., 1984)

CELL#1

CELL#n-1

CELL#0

Local dataLocal control

Data input bus

Global control signals



inn the data from the output of the cell to the left. The operation is illustrated in Figure 3 on page 6.

2.1.4 Physical implementationThe sorter was implemented in a 4 µm NMOS process. The resulting chip contains 16 sorting cells and is approximately 5.4 x 5.4 mm. Each sorting cell contains a 16-bit sorting key register, 12-bit sequencing register, a 16-bit comparator, a control bit and some control logic. The chip has been customized to minimize routing requirements, by placing the identical sorter cells end to end with no intervening signal routing.

Figure 3: Operation of the parallel shift sort algorithm

3 5 9 X X

X

4

CELL #j j+1 j+2 j+3 j+4

CELL #j j+1 j+2 j+3 j+4

Clockcycle (i):

Clockcycle (i+1):

3 4 5 9 X



2.2 VHDL2.2.1 What is an HDL?Smith (1997, p. 8) defines a HDL this way: A Hardware Description Language (HDL) is a soft-ware programming language used to model the intended operation of a piece of hardware.

A HDL can be used to model hardware at many different levels of abstraction. Several different ways of classifying these levels of abstraction can be found in the literature. The classification adopted here is described by Navabi (1998, p. 18-19). The most abstract is the behavioral level. Then there are the dataflow and the structural levels.

Behavioral level: At this level of abstraction the function of the design is described, including no implementation details. This is appropriate for fast simulation of complex hardware units, verification and functional simulation of design ideas, modeling standard components, and doc-umentation. (Navabi, 1998, p. 19) Figure 4 on page 7 shows an example of this use, where very little information of the structure of the resulting hardware is given.

Dataflow or register transfer level (RTL): A description of this level of abstraction is a con-current representation of the flow of control and movement of data. Concurrent data compo-nents and carriers communicate through busses and interconnections, and a control hardware issues signals for the control of this communication. Dataflow descriptions imply an architec-ture and a unique hardware. Because of the added detail, simulation is slower, and it cannot be used as nontechnical documentation. However, it can be used to by a technically oriented de-signer to describe the components to be synthesized. (Navabi, 1998, p. 19)

Structural level: This is the lowest and most detailed level of description considered. Structur-al descriptions include a list of concurrently active components and their interconnections.The corresponding function of the hardware is not evident form such descriptions unless the com-ponets used are known. A structural description that described wiring of logic gates is said to be a hardware description at gate level. (Navabi, 1998, p. 19)

These levels of abstraction can, and should be mixed in the same project, as described in the section “Top-Down Design Methodology” on page 16.

...

Instruction <= mem(PC);PC <= PC+1;case Instruction of jmp => PC <= mem(PC);

add => ACC <= ACC + mem(PC); PC <= PC+1;

...

end case;

...

Figure 4: Example of abstract behavior modeling



According to Navabi (1998, p. 5), HDLs are used to describe hardware for the purpose of sim-ulation, modeling, testing, design, and documentation.

There are two industry standard HDLs: VHDL and Verilog. Thanks to the effort of VHDL In-ternational (VI) and open Verilog International (OVI), these are established as IEEE standards. Table 1 on page 8 shows these. (Smith, 1997, p. vi)

2.2.2 Why HDL?Improved technology has made it possible to manufacture transistors with submicron channel widths. Because of this, silicon chips containing a million transistors have become common. To cope with such design sizes, new design automation tools have been developed, with automatic synthesis tools being the major advancement. (Smith, 1997, p. vi)

Automatic synthesis is the process of automatically transforming a design description from one form to another. (Navabi, 1998, p. 15) It is preferable that this can be done from as high an ab-straction level as possible, to the implementable gate level.

According to Navabi (1998, p. 15) HDLs are useful media for input and output of hardware syn-thesizers. Therefore HDLs are useful to hardware designers, and it allows them to take full ad-vantage of the top-down design methodology described in “Top-Down Design Methodology” on page 16.

2.2.3 Why VHDL in this project? Why not Verilog?According to Smith (1997, p. 10), hardware structure can be modeled equally effectively in both VHDL and Verilog.

Because such modeling was the objective of this project, both languages could be used. The rea-sons that VHDL was chosen, was that VHDL is the language used by most people at IDI, NTNU and this author had a little experience in using VHDL for very trivial problems, but none what-soever in using Verilog and that the needed software tools was known to handle VHDL.

Further information on the advantages and disadvantages of the two languages, see “VHDL/Verilog compared & contrasted” on page 10 in Smith (1997).

In this project VHDL ‘87 has been chosen, instead of the newer VHDL ‘93. The reason for this was to avoid compatibility problems in case any software tools which had to be used did not support VHDL ‘93.

Table 1: HDL standards

HDL StandardYear of

standardization.

VHDL ‘87 IEEE 1076 1987

VHDL ‘93 IEEE 1076-1993 1993

Verilog IEEE 1364-1995 1995



2.2.4 VHDL packages and data typesChang (1997, p. 11) defines a package as a VHDL unit that can include a number of types, sub-types, constants, procedures and function declarations.

The IEEE 1164 standard, the VHDL logic package called STD_LOGIC_1164, declares (amongst others) the type std_logic. This type is used for bit size signals, instead of the native VHDL type, bit. The bit data type only has two possible values, ‘0’ and ‘1’, while the std_logic type defines nine different values, including Uninitialized and Unknown. These extra values are useful in simulation, e.g. because an uninitialized value is specified as being uninitialized, and not just ‘0’ or ‘1’.

The IEEE 1076.3 VHDL synthesis package NUMERIC_STD, declares the types signed and unsigned. These are array types of the std_logic type declared in STD_LOGIC_1164.This package contains overloaded operators and some type conversion functions on the signed and unsigned types. The reason for using these types is that they make writing syntesizable code more straightforward. This is because they are closer to the resulting hardware implementation than the alternative, the integer type. Type conversions to and from integer is avoided, which makes the code easier to read.

Synopsys has defined their own package STD_LOGIC_ARITH, which includes the same types and the same functions as the NUMERIC_STD package. The Synopsys tools does not provide the NUMERIC_STD package.

2.2.5 VHDL interfaces, implementations and componentsThe interface part of a VHDL model is called the entity. The entity consists of two main parts: generic and port. The generic part is a list of the model parameters, such as bus widths. The port part is a list of input and output signal to and from the model.

The implementation part of a VHDL model is called the architecture. An entity can have several architectures, e.g. on different levels of abstraction. This assists in using the top-down design methodology.

When a model is used as part of another model, it is imported as a component. In the compo-nent declaration in the new model, most of the entity declaration is repeated to provide the new model with the interface information of the component used.

2.2.6 Some VHDL constructsThis section describes how some VHDL constructs have been used in this project. It is not a general description of the possibilities of the contructs.

Generating a variable number componentsTo generate a variable number of components, based on a parameter (generic), the VHDL for/if ... generate construct is used. These constructs is similar to the for ... loop and the if ... then constructs.



Usually the components to be generated are connected, like a n-bit adder generated from 1-bit full adders. To do this, signals are declared signals between the components. The carry signal in an adder should be connected from carry out of full adder n to carry in of full adder n+1. This is done by declaring an array of carry signal. If n is the count variable in the for ... gener-ate loop, then the port map of the full adder would be something like this: port map (..., CarryIn => Carry(n-1), ..., CarryOut => Carry(n), ...). This way Carry(n) connects carry out from com-ponent n to the carry in of component n+1.

Usually the first input and the last output in such a loop is used elsewhere in the design. The cleanest way of writing the for ... generate loop is by treating the first and last case sep-arately, using the if ... generate statement. An example if shown in fig.

entity ADD isgeneric (AdderSize : integer);port(

A, B : in bit_array(AdderSize-1 downto 0);Cin : in bit;S : out bit_array(AdderSize-1 downto 0);Cout : out bit);

end ADD;

architecture RTL of ADD iscomponent FULL_ADDERport (

A, B, Cin : in bit;S, Cout : out bit);

end component;signal Carry : bit_vector(AdderSize-1 downto 0);

beginG1: for n in AdderSize-1 downto 0 generate

G1first: if (n = 0) generatebitFirst: FULL_ADDER port map(A(n), B(n),

Cin,S(n), Carry(n));

end generate;

G1N: if (n > 0) and (n < AdderSize-1) generatebitN: FULL_ADDER port map(A(n), B(n),

Carry(n-1),S(n), Carry(n));

end generate;

G1last: if (n = AdderSize-1) generatebitLast: FULL_ADDER port map(A(n), B(n),

Carry(n-1),S(n), Cout);

end generate;end RTL;

Figure 5: Example of using for/if ... generate - adder



2.2.7 Design/Modeling Recommendations, Issues and TechniquesIn this section, issues of VHDL modeling which is relevant to this project is listed. If nothing is specified, all material is taken from Smith (1997, p. 75-111). These recommendations have been followed throughout the project.

Design and process recommendations1. Adopt a top-down design and modeling methodology and bottom-up optimization

strategy by hierarchical block.2. Define a design’s requirement specification as thightly as practically possible in terms

of input, output, associated timing and functionality before writing HDL models. It is very easy to design the “wrong thing right”.

3. It is good design practise to use global clock and reset signals where possible.4. Consider testability issues early in the total system design process, otherwise synthe-

sis can be a fast and efficient means of producing large amounts of untestable logic.

General HDL recommendations5. Before attempting to code a model at the register transfer level, determine a sound

architecture and partition accordingly.6. Use subprograms wherever possible to help structure a design making the code

shorter and easier to read. A primary advantage of using subprograms is code reuse.7. Make models generic as far as possible for model reuse. This means having parame-

terizable bit widths.8. Make use of abstract data types to make models easier to read and maintain.9. Use meaningful signal names. For active low control signals use <signal_name>_n.

Ensuring simulation accuracy10. Ensure the sensitivity list of process statements are complete.

Synthesis modeling recommendations11. Do not use unbounded integer data types. They default to the maximum range defined

by the language which, for III 1076 ‘93, is 32-bit. This gives the synthesizer more work to do in optimizing away the extra and redundant logic.

12. Standardize on using the IEEE packages STD_Logic_1164 and Numeric_STD as the basic minimum. Use types std_logic for single bit values, and either signed or unsigned for vector array types.

13. Use parentheses in expressions to provide a finer grain of structural control.

Simulation Compilation Issues14. The functions rising_edge or falling_edge should be used from the IEEE 1076.3 syn-

thesis package Numeric_STD, to avoid the following problem: In simulation the value of a signal of type std_logic, could have values other than ‘0’ or ‘1’. When checking for a clock edge, the attribute last_value should be used to ensure that transi-tions such as ‘X’ to ‘1’ is not detected as a clock edge. The problem is that this attribute is not supported for synthesis.



2.2.8 Writing VHDL for synthesisNot all VHDL constructs can be synthesized. Examples of these are timing using the after statement, floating-point calculations and file i/o.

The part of VHDL which can be synthesized, can be used in a way which is synthesized into compact and efficient hardware, or it can be used in such a way that the synthesis tools will ac-tually make the wrong thing.

What is described here is why the models made in this project has been made this way. These descriptions has been taken from (Smith, 1997). The goal of Smith (1997) is to provide tool in-dependent guidelines, and it is the goal in this project to learn these rather than guidelines of a specific synthesis tool. Anyway it is important to notice that tool independent code is not nec-essarily possible to write, and one should always check with the documentation of the synthesis tool used for modeling guidelines.

Where there are different ways of implementing a certain construct with the same hardware re-sult, the one described here is the one used in this project. The reason this one has been chosen, is usually this author’s subjective choice of what gives the most readable code. Anyway, most of the descriptions give general hints of good and bad ways of implementing the construct, and why they are good and bad.

The general advice given in the literature is to be aware of the hardware to be made when writing RTL HDL code, so that the correct operation is synthesized correctly and with minimal com-plexity.

if versus wait in clock edge detectionFigure 6 on page 12 shows two different ways to wait for a rising edge of the signal CLOCK. Both examples assigns the value of A to the signal Y on each rising CLOCK edge. In addition T is assigned the result of A and B, combinatorically. In the example on the left in this figure,

execution is delayed for the whole process until the rising edge of CLOCK, and all signal as-signments in the process will infer flip-flop(s). Therefore the combinatorial part has to be mod-eled in a process of its own (or like here, outside out a process.) In the example on the right, an if statement is used instead of the wait statement. This way, synchronous and combinatorial code can be modeled in the same process.

processbegin

wait until rising_edge(CLOCK);

Y <= A;end process;

T <= A and B;

process (CLOCK, A, B)begin

if (rising_edge(CLOCK) thenY <= A;

elseT <= A and B;

end if;end process;

Figure 6: VHDL code to wait for a rising CLOCK edge.



The other properties are the same. Often the if solution is the only solution, because assign-ments to the same signal must be in the same process. Figure 7 on page 13 shows a model of a flip-flop with asynchronous reset, which would not be possible using the wait solution.

Unwanted latchesOften latches are not wanted and often latches could be inferred when flip-flops was what the designer wanted. The main disadvantage of using latches, instead of flip-flops, is that timing analysis of synthesized circuits can be very complex making it difficult to verify correct opera-tion under all conditions; temperature, voltage and chip manufacturing process variations. In ad-dition some FPGA libraries does not contain latches, and the inferred logic could lead to problems in the design.

To avoid unwanted latches, signals set in one branch of a case or if statement must be set in all branches. For case statement it is also possible to set default values just above the case state-ment. To cover every case choice value, a others clause should be used.

ComparatorsComparators compare two or more inputs and produces an output (logic 0 or logic 1) according to the result.

Comparators are modeled using the if statement with an else clause and no else-if clauses. More than two inputs can not be compared (e.g. if (A = B = C)), but logic operators could be used to achieve the same: e.g. if ((A = B) and (A = C)).

The most common method and the one that it easiest to read is shown in Table 8, “Comparator,” on page 13.

Finite state machinesA state machine consists of three parts: The next state logic which is combinational, the current state register which is sequential, and the output logic, which is combinational. These three parts can be implemented in one, two or three processes. In this project the two combinational parts has been combined into one, so that output signals are set in the same process where the next state is selected.

process (CLOCK, AsynchReset_n)if (AsynchReset_n = ‘0’) then

Q <= ‘0’;elsif (rising_edge(CLOCK) then

Q <= D;end if;

end process;

Figure 7: Flip-flop with asynchronous reset

if (A = B) thenY <= ‘1’;

elseY <= ‘0’;

end if;

Figure 8: Comparator



It is important to include reset functionality into the model, so that the initial state can be known. This reset could be synchronous or asynchronous. One way to model the asynchronous reset used in this project is to use an if statement in the current state register part of the state machine to check for reset before checking for a clock edge, providing the register with an asynchronous reset.

The others clause of the case statement could be used to cover all unused states, and force them to the first (or some other) state.

Other pitfalls:• Do not use a variable to hold the state, because a variable does not hold its value over

simulation time units and should only be used to store temporary values inside a process.• Output signals set in a sequential process infer flip-flops. This is avoided by setting them

combinationally based on the current state.



2.3 DESIGN PARTS AND METHODS

2.3.1 Test benchA test bench can be thought of just as the name states: A bench to put the design in, to test it. More specifically, a test bench is a VHDL design which consists of an entity without any input/output signals, and an architecture. This architecture connects the input and output signals of the design under test (a component) to signals in the test bench. Then the test bench is responsible for producing the input signals for the design under test, following the specified protocol (that is why the interface (entity) is empty. The input data, is usually supplied either from a VHDL process or from a file. The input state of all signals for one clock cycle is called a test vector.

In its simplest form, a test bench does just this. Follow the protocol and input some data. Then the user has to study the output (either the pulse diagram or a file/screen dump) to decide wheth-er the test was successful.

In its more advanced form, a test bench decides for itself whether the test was successful. This is usually done in one of two ways: Both the input data and the expected output is provided by a file (Figure 9 on page 15 shows this), or just the input data is supplied by the file and the test bench compares the result of the design under test with the result of a reference design which is assumed to be correct (Figure 10 on page 16 shows this).

Figure 9: A test bench organization (Chang, 1997, p. 217)

Designundertest

Compare

Testvector

file

Read textfile anddo type

convertion

Input signals convertedfrom the test vector file

Expectedoutputresults

Output signalsfrom Designunder test



2.3.2 Top-Down Design MethodologyAccording to Smith (1997, p. vi) the benefits of adopting a top-down design methodology, using a industry standard HDL, is:

1. design source files are transportable between different EDA tools and,2. the design is independent of any particular silicon vendor’s manufacturing process

technology.

The following description of Top-Down Design, is from Navabi (1998, pp. 36).

Instead of trying to implement the design of a large system all at once, a divide-and conquer strategy is taken in a top-down design process. Top-down design is referred to as recursive par-titioning of a system into its subcomponents until all subcomponents become manageable de-sign parts. Design of a component is manageable if the component is available as part of a library, it can be implemented by modifying an already available part, or it can be described for a synthesis program or an automatic hardware generator.

Figure 11 on page 17 shows that the system under design is initially described at the behavioral level. Then it is partitioned into subcomponents with a behavioral description. These are then

Figure 10: A test bench organization with a reference know GOOD design (Chang, 1997, p. 217)

ReferenceGOODdesign

Designundertest

Pass or fail

Generate inputtest vectors orread from file

Compareoutputs



partitioned, and so on. When the partitioning is done, the subcomponents are mapped into hard-ware in a bottom-up manner.

At every step of a top-down design process a multilevel simulation tool plays an important role in the correct implementation of the design. The simulation tool is used to verify the designers understanding of the problem, by simulating the behavioral model of the system under design. After each level of partitioning, the interconnection of the new behavioral models is simulated to verify that they have the same behavior as the model on the above level. This is also done during the bottom-up implementation stage. Finally, the hardware level model of the system can be compared with the behavioral model.

2.3.3 SimulationFrom Smith (1997, pp. 14):

Simulation is the process of verifying the functional characteristics of models at any level of ab-straction. A simulator simulates the behavior of a hardware model, using the timing defined in an HDL model before synthesis, or the timing from the cells of the target technology, after syn-thesis.

2.3.4 Register transfer level (RTL) synthesisFrom Smith (1997, pp. 14):

Register transfer level synthesis is the process of translating a register transfer level model of hardware, written in a hardware description language at the register transfer level, into an opti-mized technology specific gate level implementation.

Synthesis = Translation + Optimization. The initial translation to a netlist without optimization provides the starting point on the area-time curve for optimization. Then the design is optimized

Figure 11: Top-down design and bottom-up implementation (partly from Navabi, 1998, p. 37)

Des

ign

Impl

emen

tati

on

System under design

Shaded areas designate sub-componentswith hardware implementation.



according to different constraints, e.g. on the area and timing. Figure 12 on page 18 and Figure 13 on page 18 illustrate this process.

Figure 12: Synthesis equals translation and optimization (Smith, 1997, p. 18)

Figure 13: Translation and optimization process flow using RTL level synthesis (Smith, 1997, p. 18)



Chang (1997, pp. 149) presents another view of the synthesis process (Figure 14 on page 19.)

The VHDL synthesis tool reads in VHDL source code. The operating conditions set up the tem-perature and manufacturing process conditions, which affect the timing delay of the circuits. The wire load model describes the statistics of the interconnect wire length based on the tech-nology and the size of the circuits for the synthesis tool to estimate the timing delay due to the interconnects among components. The component library consists of the function of each com-ponent (NAND, NOR, ...), gate timing delay, each output pin drive capability, and the loading of each input pin. The component library may also have large macro cells such as ROM and RAM. The component library is usually provided by the manufacturing vendor. The design con-straints usually specify the clock frequency and input output timing requirements. The synthesis tool usually generates schematics, netlists (VHDL, EDIIF, or other netlist format), timing files (such as Standard Delay Format, SDF), and results (area, number of gates, timing violations, and so on.)

Figure 14: Synthesis framework (Chang, 1997, p. 149)

Synthesiscomponent library

VHDL simulation componentlibrary (may be VITAL)

Synthesiscomponent library

VHDL sourcecode text files

VHDL synthesis tool

Design constraints,operating condition,wire load model Physical layout tool

SDF

Schematic, netlisttiming file (SDF),results

VHDL simulation



2.4 THE SOFTWARE TOOLS USEDAnalysis/compilation and simulation: VeriBest VHDL (SysSim) simulatorPlatform: Windows NTVersion 15.00.00.45VeriBest, Inc.

Aid in simulation: PerlPlatform: UNIX sun4-solarisVersion: 5.004_04Copyright 1987-1997, Larry Wall

VHDL synthesis: Synposys Design AnalyzerPlatform: HP/UXVersion 1998.02-2 -- May 11, 1998Synopsys, Inc.

Word processing: FrameMakerVersion 5.5.6p145Adobe Systems Incorporated

Chapter 3 • The design


CHAPTER 3 •

THE DESIGN



3.1 SPECIFICATIONThis specification gives much of the necessary information about the interface and operation of the sorter, so that it can be used as a black box in the surrounding system, and is the basis for the implementation of the sorter. Two things are not specified as they are part of the project or future projects to determine:

• The clock frequency/-ies.• The number of elements which can be sorted, and the widths of the data inputs.

3.1.1 Assumptions and requirements• Zero number of elements shall never be attempted to be sorted. => The sorter will not

support this.• Elements should be sorted in descending order.• By making some internal signals external, it should be possible to chain several sorters

together.• It should be possible to pause the input/output operation. This is because it could be nec-

essary to wait for input from/output to slow memory, or it should be possible to sort ele-ments as they become available without waiting for all elements before sorting them.

• The circuit which wait for output data from the sorter, should be able to do other work while waiting. After valid data is available at the output of the sorter, an enable from this circuit has to be acquired before writing data.

3.1.2 Interface

Input signals• CLK, 1 bit. Clock signal. Clock rate and other information about the clock signal is not

specified.• Reset_n, 1 bit. Resets the operation of the sorter. Starts input operation. (Active low.)• EnableIn, 1 bit. Data is read only when this input is high.

Figure 15: The Sorter Interface

CLK

Reset_n

EnableIn

LastIn

PointerIn

KeyIn

EnableOutLastOut

KeyOut

PointerOut

Outputting

n

m

n

m

ReadyOut



• KeyIn, n bits. This is the value to be used as the sort key.• PointerIn, m bits. This is a value ‘attached’ to the key, usually a pointer to some data.• LastIn, 1 bit. This signal should be set high during the clock cycle when the last ele-

ment in a sequence is input.• EnableOut, 1 bit. Data is written when this signal is high.

Output signals• ReadyOut, 1 bit. This signal is set high when sorted data is ready to be output.• Outputting, 1 bit. Is high while valid data is at the output.• LastOut, 1 bit. This signal is set high during the clock cycle when the last element in a

sequence is output.• KeyOut, n bits. This is the value to be used as the sort key.• PointerOut, m bits. This is the value ‘attached’ to the key.

3.1.3 OperationThe input is sequential, and the sorting of each element is parallel. Each element is the output sequentially, the element with the smallest key first.

One element should be read and inserted in a sorted list during one clock cycle. When data is written out, one element is written in each clock cycle.

The operation of the sorter has two parts/modes:• input• output

The operation of the sorter is shown in pseudocode in Figure 16 on page 23, and described be-low.

after Reset then

loop indefinatelyReadyIn <= highrepeat

Read operation: Data will be read eachclock cycle where EnableIn is high

until LastIn has been high for one clock cycle

wait until data is ready to be sent outReadyOut <= high, to indicate this

write data every clock cycle where EnableOut is highOutputting is set high when data is written

LastOut <= high together with the last dataelement written

end loop

Figure 16: Pseudocode of sorter operation



After reset the sorter starts input operation. In this mode one element will be read and sorted each clock cycle if EnableIn is high. This will continue until LastIn has been high for one clock cycle. When all elements has been read and sorted, read operation is done. When the sorter is ready to write data out, ReadyOut will be set high. Then the sorter will wait for EnableOut to go high. It is not necessary to wait for ReadyOut before setting EnableOut high.

In output operation one element is written each clock cycle where EnableOut is high, until all elements are written. Outputting will be set together with each element written. LastOut is set high together with the last element written.

After that, input operation is again started.

Figure 17: Input mode of operation

Input operation

Õ CLK

Õ Reset

Ô ReadyIn

Õ EnableIn

Õ LastIn cont’d

Õ KeyIn

Õ PointerIn

Õ EnableOut

Ô ReadyOut

STATE

Notes Legend

Assuming ListLength of 3. Õ = Inngang = 0

The number of data elements written are 5. Ô = Utgang = 1

The first 3 of these are then read out. = n full clock cycles = X = don’t care

= 1 or 0 but not floating

The signals not present in the diagram

are considered don’t care.

Key3

Pointer1

Key5

Pointer5Pointer4

Key4

Pointer2 Pointer3

Key1 Key2

INIT FORWARD/READY_OUT/WRITINGREADREADY_IN



Figure 18: Output mode of operation

Output operation

Õ CLK

Õ Reset

Ô ReadyOut

Õ EnableOut continues

Ô Outputting

Ô DoneOut

Ô KeyOut

Ô PointerOut

Ô ReadyIn

STATE

Notes Legend

Assuming ListLength of 3. Õ = Inngang = 0

The number of data elements written are 5. Ô = Utgang = 1

The first 3 of these are then read out. = n full clock cycles = X = don’t care

The signals not present in the diagramare considered don’t care.

The READY_OUT state may be skipped by settingEnableOut high in the FORWARD or READ state.The FORWARD state is for shifting the elementsforward in the sorter if it is not full.Therefore it isnot always present.

WRITE READY_IN READFORWARD READY_OUT

Key3

Pointer3Pointer2

Key2

Pointer1

Key1



3.2 DESIGN DESCRIPTION

3.2.1 Design evolutionFrom the start it was decided that the sorter was to be implemented using the architecture de-scribed by in “The parallel shift sort algorithm” on page 4 which is taken from Arisland et al. (1984). How this was implemented is explained in the sections below. Therefore there was no need for a higher level behavioral description of the system to assist in the partitioning of the design. The partitioning was done by Arisland et al. Anyway there was a need for a behavioral model of the complete sorter, to verify that the specification had been understood, before com-pleting the design at the register transfer level (RTL). Therefore the first model developed was a high level behavioral model of the parallel shift sort algorithm extended to implement the in-put/output protocol of the specification.

The the RTL model was made. At first the models were written as one intuitively would write such code, using Chang (1997) and some places Navabi (1998) as the main sources of VHDL references, adding the authors software programming background. Later in the project, a very useful book on synthesizable HDL, Smith (1997) became available. With the help of this book, sections of the code was changed so that the synthesis tool could produce better logic from it.

Early in the project work a simple test bench was made which give some simple stimuli to assist in debugging the code during development. This test bench has not been described in this report. Later the test bench was extended to do the thorough verification of the sorter. This test bench read stimuli from a file. The result can be studied as pulse diagrams, or by looking at the file produced which also gives an “Yes” or “No” answer to the question “Does the sorter work?”.

3.2.2 Coding styleThe VHDL descriptions should be as parameterized as possible so that it would be easy to change parameters later in the project. This facilitates re-use of the models, and future simula-tion of the system under different conditions to determine ideal parameters for a specific appli-cation.

Output signals cannot be read from inside an entity, because they are output-only signals, and an internal signal has to be used. The output signal is set to equal the internal one, and the inter-nal signal is used in the code. The internal signal gets the same name as the output signal with the postfix ‘Internal’.

The std_logic and unsigned data types, defined in the STD_LOGIC_1164 and NUMERIC_STD/STD_LOGIC_ARITH packages are used. The reasons for this is convenient simulation, simpler code and more efficient synthesis. More on this in “VHDL packages and data types” on page 9. When simulating in VeriBest, the NUMERIC_STD package has been used, and when synthesizing in Synopsys, the STD_LOGIC_ARITH package as been used. They are functionally equivalent.

3.2.3 ArchitectureFigure 19 on page 27 shows the VHDL entities involved in the project. This figure also illus-trates that the SORTER entity is implemented consisting of one or more SORTER_BOX com-ponents. This means that the SORTER entity has not been completely partitioned into new



entities, but the SORTER_BOX entity is used as stand-alone components in addition to the con-trol logic needed.

The SORTER_BOX components are connected as proposed by Arisland et al. (1984) and de-scribed in “The parallel shift sort algorithm” on page 4. This means that a chain of SORTER_BOX components, each capable of holding one element and determining whether a new element should be clocked in. This chain is illustrated in Figure 20 on page 27, where the line in the middle illustrates that the chain can consist of more than these two components.

3.2.4 Test benchesTwo test benches was made. The first to simulate SORTER_BOX and the second to simulate SORTER.

For SORTER_BOX. This test bench simulates SORTER_BOX with some predefined input data. More on this in “Stage one” on page 39. The input data is shown in Appendix B-1. The code is shown in Appendix A-3.

For SORTER. In addition to showing the pulse diagrams, this test bench compares the result of the sort with the result of the behavioral model of the sorter, but does not test the input/output protocol. The result of the sort is written to a file, together with a message indicating if the sort passed or failed.

Figure 19: The sorter project VHDL entities

Figure 20: The chain of SORTER_BOX components

SORTER

SORTER_BOX

TEST_BENCH TEST_BENCHfor for

SORTERSORTER_BOX

ShiftIn

KeyInPointerIn

CLK and Reset_n is not shown.

ShiftOut

Shif

tIn

Key

InPo

inte

rIn

KeyPrevPointerPrevLEprevDisabledPrev

Shif

tOut

KeyOut

PointerOutLEout

DisabledOut

Shif

tIn

Key

InPo

inte

rIn

KeyPrevPointerPrevLEprevDisabledPrev

Shif

tOut

KeyOut

PointerOutLEout

DisabledOut

KeyInPointerIn

LEfirstDisabledFirst

KeyOut

PointerOutLEoutDisabledOut



This test bench reads input from a file. The input data file consists of lines with three integers separated by tabulators (ASCII value 9 decimal). The first number is the key value, the second number is the pointer value and the third is used to indicate if the line is the last in an input se-quence (1=last, 0=not last). One file can contain several input sequences, and they should be in the file in a continuous manner, not separated by empty lines. An example is shown in Figure 21 on page 28. Here the two sequences 1 (2), 3 (5), 2 (8) and 67 (55), 876 (4453), 432 (66854), 123 (43) are to be sorted (pointer values shown in parentheses).

PERL script. Even though random number generators can be programmed in VHDL, a PERL program was used for generating stimuli files for the test bench. The reasons for this solution was the following:

1. No new test bench had to be made.2. The PERL program for generating the stimuli file is very simple and easy to under-

stand. A random number generator is build into the language.3. It is convenient to use files as stimuli for the simulation because it gives full control

over input and output.

The maximum number of elements in a generated sequence and the maximum value of key and pointer, has to be changed in the top of the source code of the script.

To generate a sequence and write it to a file, use the UNIX command:rand_seq.pl > filename.datTo write more sequences to the same file, write:rand_seq.pl >> filename.datseveral times.

3.2.5 Interfaces (VHDL entities)

SORTERThe parameters are described in Table 2 on page 28. The input and output signals are described in Table 3 on page 29.

1 2 03 5 02 8 167 55 0876 4453 0432 66854 0123 43 1

Figure 21: Syntax of input data file for use with test bench

Table 2: SORTER parameters

Parameter Description

KeySize The size in bits of the Key.

PointerSize The size in bits of the Pointer.



SORTER_BOXThe parameters are described in Table 4 on page 29. The input and output signals are described in Table 5 on page 29.

ListSize The number of elements that the sorter should be able to sort.

Table 3: SORTER inputs and outputs

SignalActive state

In/Out Description

CLK N/A In

See “Interface” on page 22.

Reset_n Low In

EnableIn High In

LastIn High In

KeyIn N/A In

PointerIn N/A In

ReadyIn High Out

EnableOut High Out

KeyOut N/A Out

PointerOut N/A Out

ReadyOut High Out

Outputting High Out

Table 4: SORTER_BOX parameters


KeySize The size in bits of the Key.

PointerSize The size in bits of the Pointer.

Table 5: SORTER_BOX inputs and outputs

SignalActive state

In/Out Description

CLK N/A In Clock signal.

Reset_n Low In Reset signal.

Table 2: SORTER parameters




Test benchesThe interface part of a test bench is empty, because a test bench does not communicate with any-thing. Yes, a test bench can read from and write to files, but there are no signals going in to or coming out from a typical test bench.

3.2.6 Implementations (VHDL architectures)The descriptions given here explain the overall structure of the implementations. For more de-tail, study the VHDL source code.

BEHAVIORAL architecture of SORTERThe behavioral architecture of the sorter is basically an VHDL implementation of the parallel shift sort (PSS) algorithm from Arisland et al. (1984), with the addition of code to control the input/output protocol.

In Figure 22 on page 31 below is shown the BEHAVIORAL architecture of SORTER and the PSS algorithm side by side. The corresponding lines in the two are shown on the same lines. This is to convince that the behavioral implementation will sort correctly. The main differences

ShiftIn High In Set when data to be sorted is at KeyIn/PointerIn.

KeyIn N/A InInput data.

PointerIn N/A In

KeyPrev N/A In Data from the previous SORTER_BOX compo-nent.PointerPrev N/A In

LEprev High In Less-Than-Or-Equal signal from the previous SORTER_BOX component.

DisabledPrev High In Set if the previous SORTER_BOX component is disabled.

ShiftOut High In Set when data is to be shifted out. KeyIn/Point-erIn is ignored, and data is shifted in from KeyPrev/PointerPrev.

KeyOut N/A OutOutput data.

PointerOut N/A Out

LEout High Out Output Less-Than-Or-Equal signal. Set when KeyIn is less than or equal (<=) to the Key stored in this SORTER_BOX component. This signal is independent on whether this compo-nent is disabled.

DisabledOut High Out Set when this component is disabled.

Table 5: SORTER_BOX inputs and outputs

SignalActive state

In/Out Description



between the two, is that the behavioral VHDL description sorts the elements in descending order and that the PSS algorithm sorts them in ascending order. In addition to this, the VHDL descrip-tion has code to control the input/output protocol, but that is not an issue here.

ReadyIn <= ’0’;ReadyOut <= ’0’;Outputting <= ’0’;DoneOut <= ’0’;

if Reset_n/=’1’ thenwait until Reset_n=’1’;

end if;

ReadyIn <= ’1’;

NumberOfElements := 0;more_cards := true;

while more_cards loopwait until CLK’event and CLK=’1’

and EnableIn=’1’;

if NumberOfElements < ListSize thenNumberOfElements :=NumberOfElements + 1;

end if;

-- Take next card.new_key := KeyIn;new_pointer := PointerIn;

if LastIn = ’1’ thenmore_cards := false;

end if;

-- Find position to insert new card.

new_pos := 0;found_pos := false;while not found_pos loop

new_pos := new_pos + 1;

if new_pos = NumberOfElements thenfound_pos := true;

elsif new_pos >= ListSize thenfound_pos := true;

elsiffan(new_pos).Key < new_key then

found_pos := true;end if;

end loop;

fan_size := 0;

while more_cards do/* Take next card. */

fan_size := fan_size + 1;

new_card := input;

/* Find position to insertnew card. */

new_pos := 0;found_pos := false;while not found_pos donew_pos := new_pos + 1;

if new_pos = fan_size thenfound_pos := true

elseif fan[new_pos] >= new_card thenfound_pos := true;

end_while;

Figure 22: Behavioral VHDL description of the the parallel shift sort algorithm to the left, and the parallel shift sort algorithm from Arisland et al. (1984) to the right.



In Figure 23 on page 33 the behavioral VHDL description is shown side by side with the pseudocode of the input/output protocol from “Operation” on page 23, to convince that the be-

-- Shift all cards from insert positionto end.

for idx in NumberOfElementsdownto new_pos + 1 loop

fan(idx) := fan(idx - 1);end loop;

-- Insert new card.if (new_pos < ListSize) then

fan(new_pos) :=(new_key,new_pointer);

end if;

end loop;

/* Shift all cards from insertposition to end. */

for index := fan_size to new_pos + 1 step - 1 do

fan[index] := fan[index-1]end_for;

/* Insert new cars(sic.). */

fan[new_pos] := new_card;

end_while;

ReadyIn <= ’0’;

if (NumberOfElements < ListSize) thenfor idax in 1 to

(ListSize-NumberOfElements) loopwait until CLK’event and CLK=’1’;

end loop;end if;

ReadyOut <= ’1’;

if (EnableOut=’0’) thenwait until EnableOut=’1’;

end if;

Outputting <= ’1’;

for index in NumberOfElementsdownto 1 loop

if (index = 0) thenDoneOut <= ’1’;

end if;

KeyOut <= fan(index).Key;PointerOut <= fan(index).Pointer;

wait until CLK = ’1’ and CLK’event;end loop;

Figure 22: Behavioral VHDL description of the the parallel shift sort algorithm to the left, and the parallel shift sort algorithm from Arisland et al. (1984) to the right.



havioral model implements the protocol correctly. Much of the other code of the behavioral model has been reduced to comments in this figure.

ReadyIn <= ’0’;ReadyOut <= ’0’;Outputting <= ’0’;DoneOut <= ’0’;NumberOfElements := 0;more_cards := true;

if Reset_n/=’1’ thenwait until Reset_n=’1’;

end if;

ReadyIn <= ’1’;

while more_cards loopwait until CLK’event and CLK=’1’

and EnableIn=’1’;

--! Read input data

if LastIn = ’1’ thenmore_cards := false;

end if;

--! Insert new data into the--! sorted sequence

end while;

ReadyIn <= ’0’;

--! Forward data


for index in NumberOfElementsdownto 1 loop

Outputting <= ’0’;if (EnableOut=’0’) then

wait until EnableOut=’1’;end if;


if (index = 1) thenDoneOut <= ’1’;

end if;

--! Write data

wait until CLK = ’1’ and CLK’event;end loop;

after Reset then

loop indefinatelyReadyIn <= high

repeatRead operation: Data willbe read each clock cyclewhere EnableIn is high

until LastIn has been high forone clock cycle

wait until data is ready to besent out

ReadyOut <= high, to indicatethis

write data every clock cyclewhere EnableOut is high

Outputting is set high whendata is written

LastOut <= high together withthe last dataelement written

end loop

Figure 23: Behavioral VHDL description of the the parallel shift sort algorithm to the left, and the pseudocode of the input/output protocol to the right.



RTL architecture of SORTERAs described in “Architecture” on page 26, with some background information in “The parallel shift sort algorithm” on page 4, the SORTER is implemented using a chain of SORTER_BOX components. The parameter ListSize determines the number of instances of the SORTER_BOX component to be generated. A description of how this is achieved in VHDL is described in “Generating a variable number components” on page 9.

A finite state machine (FSM) is used for controlling the operation of the SORTER by providing control signals to the SORTER_BOX components, and for setting the output signals from the SORTER.

The state diagram of the FSM is shown in Table 24 on page 34, and the states are described in Table 6 on page 34.

Figure 24: SORTER FSM state diagram

Table 6: SORTER FSM states

INIT Initialization (does nothing useful)

READY_IN Indicates that the sorter is ready to receive, by setting ReadyIn=’1’.

READ Keeps on indicating that the sorter is ready to receive, by holding ReadyIn at ‘1’.When EnableIn is high, shift data into the sorter, placing the new element in sorted order.

FORWARD If the number of elements in the sorter is less than the maximum number of elements possible (ListSize), the elements have to be for-warded so that the first element to be written out, is at the rightmost block. This is done in this state.

INIT

READREADY_IN

FORWARD

READY_OUT

WRITE

LastIn=’1’ andDisabledOut=’1’

LastIn=’1’ and EnableOut=’1’and DisabledOut=’0’

LastIn=’1’ and EnableOut=’0’and DisabledOut=’0’

EnableOut=’0’and

Disabled(ListSize-2)=’0’

EnableOut=’1’ andDisabled(ListSize-2)=’0’

Disabled(ListSize-2)=’1’

ReadyIn

Signals are indicatedwhen they are ’1’,else they are ’0’

ReadyInShiftIn

ShiftOut

ShiftOutReadyOutOutputting

ReadyOut



RTL architecture of SORTER_BOXThe SORTER_BOX will consist of a data register, a multiplexer, a comparator and some logic de-ciding when data should be loaded into the register and from which input (see Figure 25 on page 35.)

The SORTER_BOX implementation consists of a number of processes. Each one is described briefly below.

Compare: Compares the input key KeyIn with the key stored in the SORTER_BOX Key reg-ister. LE (Less-than-or-equal) is set according to the result of the comparison: ‘1’ if KeyIn <= Key and ‘0’ otherwise. The SORTER_BOX LEout output signal is equal to LE.

SetFromIn/SetFromPrev: The SORTER_BOX has to determine if new data should be clocked into the Key and Pointer registers from the input or from the previous SORTER_BOX, or if no new data should be clocked in. Two comparators are used for this purpose. The first determine if data should be clocked in from the input and the other if data should be clocked in from the previous SORTER_BOX. If none of these are set, new data will not be clocked into the regis-ters. The conditions are described below.

SetFromIn: Data is taken from the input if data is being shifted in for sorting, and one of two conditions are true. The first is that if this SORTER_BOX does contain a sorted element, new input is clocked in if its key is less than or equal to all previous elements’ keys and greater than this element’s key. The second is that if this SORTER_BOX does not contain a sorted element, new input is clocked in if its key is less than or equal to all previous elements’ keys, and if the

READY_OUT Indicates that data is ready to be written, by setting ReadyOut=’1’.

WRITE Keeps on indicating that the sorter is ready to receive, by holding ReadyOut at ‘1’. Data is written out each clock cycle EnableOut is high. Outputting is high whenever valid data is at the output.

Figure 25: SORTER_BOX

Table 6: SORTER FSM states

Dataregister

Logic

From input

From previousSORTER_BOX

<=

Key frominputKey frompreviousSORTER_BOX

LE LEout

CLK



previous SORTER_BOX does contain an element, then this one is the first free SORTER_BOX. The code elements are described in Table 7 on page 36.

SetFromPrev: Data is taken from the previous SORTER_BOX, if the mode of operation is to shift elements out of the SORTER, or if the mode of operation is to shift data in, sorting them, and the new element has been inserted in one of the previous SORTER_BOXes, meaning that elements must be shifted right to give room for the new element. If the last is the case and this SORTER_BOX does not contain an element, it should be used if the previous does contain an element, so that this one is the first free one. The code elements are described in Table 8 on page 36.

Table 7: Conditions for clocking data in from input

Conditions (or’ed) Description

ShiftIn=’1’ Mode of operation is shifting (sorting) from input

and

Element.Disabled=’0’ This SORTER_BOX is currently not empty

and

LE=’0’ Input key > this key, which means that the new ele-ment will not be stored in any of the next SORTER_BOXes.

and

LEprev=’1’ Input key <= key of previous SORTER_BOX, which means that the new element was not stored in the previous SORTER_BOX.

or

Element.Disabled=’1’ This SORTER_BOX is currently empty

and

DisabledPrev=’0’ The previous SORTER_BOX is currently not empty

and

LEprev=’1’ Input key <= key of previous SORTER_BOX, which means that the new element was not stored in the previous SORTER_BOX.

Table 8: Conditions for clocking data in from previous SORTER_BOX


ShiftOut=’1’ Mode of operation is shifting out the data

or



Selection of next element, is done using a concurrent selection statement.

Synchronous: This process meddles the register holding the data element. It has an asynchro-nous reset.

Test bench for SORTER_BOX

Test bench for SORTERThe test bench consists of these five processes; clock, rst, feed, eat and compare. These are described below.

clock: Produces th clock signal with a 50/50 duty cycle and period of 20 ns, beginning at logic 1.

ShiftIn=’1’ Mode of operation is shifting (sorting) from input

and

Element.Disabled=’0’ This SORTER_BOX is currently not empty

and

LE=’0’ Input key > this key, which means that the new ele-ment will not be stored in any of the next SORTER_BOXes.

and

LEprev=’0’ Input key > key of previous SORTER_BOX, which means that the new element was stored in one of the previous SORTER_BOXes.

or

Element.Disabled=’1’ This SORTER_BOX is currently empty

and

DisabledPrev=’0’ The previous SORTER_BOX is currently not empty

and

LEprev=’0’ Input key > key of previous SORTER_BOX, which means that the new element was stored in one of the previous SORTER_BOXes.

Table 8: Conditions for clocking data in from previous SORTER_BOX




rst: Produces the reset signal, which is active low and resets the design by setting this signal to logic 0 for the first 20 ns (one clock cycle) of the simulation.

feed: This process is responsible for producing the input signals to the design. To do this it has to set the correct signals according to the output control signals from the design and according to the clock signal. In essence, follow the protocol of the specification in “Specification” on page 22. A loop has been written to read input data from a file.

eat: This process has been made to record the result of the test. It writes the output sequence to a file, together with an indication of whether the test was successful or not.

compare: To determine if the test was successful or not, the output of the design is compared with the output of the behavioral model of the sorter.

Input is read from a file called ‘tb_1.txt’, and output is written to a file called ‘res_1.txt’.

PERL program: The PERL program initiates the seed for the random number generator to the current time, which is fine for this application. Then a loop generates the numbers, and another loop writes the numbers to standard output, which easily can be redirected to a file by using > or >> in UNIX, as described in “Test benches” on page 27.



3.3 VERIFYING THE DESIGN

3.3.1 Stage oneVerify the SORTER_BOX. The parameters used are: KeySize=16 and PointerSize=32.

The main tool for verifying the SORTER_BOX has been code examination. Because of the sim-plicity of the code, it is though that this should give a good verification. “RTL architecture of SORTER_BOX” on page 35 gives an indication of the thourougness of this examination.

In addition most of the input data cases have been simulated:

Because of the simplicity of the comparator code, this is supposed to be verified when three dif-ferent cases has been tested: Input key < SORTER_BOX’s key, Input key = SORTER_BOX’s key and Input key > SORTER_BOX’s key. For these cases LE=LEout (Less-than-or-Equal) should be 1, 1 and 0 respectively.

From Table 7 on page 36 and Table 7 on page 36 in “SORTER_BOX” on page 29, it is clear that there are five cases where data should be read into the SORTER_BOX. In addition, there are the case where no data should be read in. These six cases are verified during stage one.

The test procedure and the result of the simulation is shown in Appendix B-1.The test bench used is shown in Appendix A-3 and described in “Test benches” on page 27 and “Test bench for SORTER_BOX” on page 37.

An exhaustive test of the case when no data should be written in, have not been performed.

3.3.2 Stage twoWhen, SORTER_BOX had been verified, the input elements is known to be compared correctly to each other. What was left, was to verify that the SORTER_BOXes was connected to each other correctly, and that the protocol for input and output had been implemented correctly.

The parameters used are, ListSize=10, KeySize=16 and PointerSize=32.

The verification of the connection of the SORTER_BOXes to each other, are done by code exam-ination. In addition to this, this is considered correct when the rest of the simulations shows that the SORTER is functioning correctly.

Then there was the verification of the implementation of the protocol. The protocol is controlled by a state machine. Because stage one was successful, we can test this independent of actual data values. To verify this operation, the SORTER is simulated with three different input se-quences, one that is shorter than the number of SORTER_BOXes, one that is equal to this number and one that is longer. The result of these simulations are shown in Appendix B-2. These sim-ulations show the output of both the RTL and the behavioral architectures of SORTER. These pulse diagrams are compared with each other and with the pulse diagrams of the specification shown in Figure 17 on page 24 and Figure 18 on page 25, and they are qualitatively equal. This means that the RTL description successfully implements the protocol of the specification.



The test was successful.

The test bench used is shown in Appendix A-4 and described in “Test benches” on page 27 and “Test bench for SORTER” on page 37.

3.3.3 Stage threeWhen stage one and two was finished, the SORTER should be verified, but to be sure three more simulations was run. In these simulations the sorter output is compared with the output of the behavioral model created early in the project.

First two simulations using randomly generated inputs was run. The input was generated using a the PERL script described in. The maximum number of elements in each sequence and the maximum value of the key and pointer is set in the top of the PERL source code. The number of sequences generated is determined by the number of times the script is run with the same file as source of output.

Then one simulation was run, testing some extreme values.

The test bench used is shown in Appendix A-4 and described in “Test benches” on page 27 and “Test bench for SORTER” on page 37.The PERL script is shown in Appendix A-5 and described in “Test benches” on page 27 and “Test bench for SORTER” on page 37.

Test 1Sorter parameters: ListSize=10, KeySize=16 and PointerSize=16.25 random input sequences.PERL script parameters: Max. number of elements=50 and max. key/pointer value=50.

Input data and results of the simulation are shown in Appendix B-3.


Test 2Sorter parameters: ListSize=101, KeySize=16 and PointerSize=16.10 random input sequences.PERL script parameters: Max. number of elements=150 and max. key/pointer value=65535.



Test 3Sorter parameters: ListSize=10, KeySize=16 and PointerSize=16.

Some extreme values was tested, such as key values of 0 and 65535 (smallest and largest key), and pointer values of 0 and 65535 (smallest and largest pointer).




3.4 SYNTHESIZING AND CHARACTERIZ-ING THE SORTERDuring the development of the VHDL code, it has been a goal to make it synthesizable. By fol-lowing the guidelines of “Design/Modeling Recommendations, Issues and Techniques” on page 11 and “Writing VHDL for synthesis” on page 12, the VHDL code should be synthesiz-able.

Using the Design Analyzer tool from Synopsys, the SORTER_BOX and SORTER, was synthe-sized for different key widths, pointer widths and list lengths, and different optimization con-straints, using the CYB library from Austria Mikro Systeme (AMS). CYB is a 0.8 µm CMOS standard cell process library. There is no particular reason why this technology has been used, other than that it was the one installed on the computer used.

The sythesis has been done as simple as possible, and the only optimization constraints/param-eters set, are constraints on delay and area. Many other parameters could be specified, but that is beyond the scope of this project.

The constraints commands used in the Synopsys Design Analyzer are:• Determining the fastest design: set_max_delay 0 -to all_outputs() +

all_registers(-data_pins) ¨ group_path -critical_range 10000 -default

• Determining the smallest design: set_max_area 0

The results of the synthesis experiments will be analyzed and discussed. Then formulas for coarse approximations to the area at different parameter sizes will be developed. These formulas will be used to find approximated values for the area of a large sorter. The accuracy of this area is not important because it is to be used only to see if the order of the area makes it possible to make such a sorter as an ASIC. Because the technology used in a future implementation is not known, the only important thing here is to see if the area is far to big or if this is something worth more work.

First SORTER_BOX and SORTER was synthesized for different key widths, pointer widths and list lengths. The results of this is shown in Table 9 on page 42 and Table 10 on page 43. This first experiment was done to see if the synthesized circuits was as expected from the VHDL source and that the amount of logic generated did not grow exponentially for increasing param-eter sizes. To examine this, the synthesis could be optimized for either minimal area or minimal data arrival time, with equal efficiency. The latter was chosen.

Table 9: Result of synthesis of SORTER_BOX, optimized for fast design

KeySizePointer-

SizeFlip-flops

Combinational area [sq mm]

Total area [sq mm]

Data arrival time [ns]

1 1 3 0.0261 0.0853 4.97

2 2 5 0.0344 0.1256 5.87

8 8 17 0.1137 0.4013 7.25

16 16 33 0.2553 0.8652 8.17



The first thing worth noticing, was that only flip-flops was inferred (no latches), which is good (see “Unwanted latches” on page 13), and only the number of flip-flops that should be needed to hold data. For SORTER_BOX this is one flip-flop for each bit in the key and the pointer, plus one for holding the disabled bit. For SORTER it is three for holding the current state (seven states, means 3 bits state register), plus the flip-flops of all SORTER components.

The second thing to notice was that both the SORTER_BOX and the SORTER should scale well with different parameter values. Both the area and timing should increase with increasing pa-rameters, but not exponentially. For SORTER the logic needed should be approximately the same, regardless of the number of SORTER_BOX components generated and the widths of the key and pointer. For SORTER_BOX the logic needed should increase some with increasing point-er widths because of the multiplexors needed, and some more with increasing. Table 9 on page 42 and Table 10 on page 43 shows that this is as expected. From Figure 26 on page 44 and Figure 28 on page 45 below it is also clear that the area increases almost linearly, and from

32 32 65 0.4967 1.6968 9.78

8 16 25 0.1504 0.5365 7.28

16 8 25 0.2199 0.7429 7.96

Table 10: Result of synthesis of SORTER, optimized for fast design

KeySizePointer-

SizeListSize

Flip-flops


Total area [sq mm]


8 8 10 3 1.2067 4.4299 7.6

8 8 3 3 0.3782 1.4074 7.3

16 16 3 3 0.7512 2.7338 8.55

8 16 3 3 0.4801 1.8195 7.41

16 8 3 3 0.6548 2.3455 8.27

8 8 32 3 3.8798 14.2240 7.69

Table 9: Result of synthesis of SORTER_BOX, optimized for fast design

KeySizePointer-

SizeFlip-flops


Total area [sq mm]




Figure 27 on page 44 and Figure 29 on page 45 it looks as though the data arrival time increases approximately linearly only for the larger parameters.

Figure 26: Result of synthesis of SORTER_BOX, optimized for fast design. Area at increasing KeySize/PointerSize

Figure 27: Result of synthesis of SORTER_BOX, optimized for fast design. Data arrival time at increasing KeySize/PointerSize

Area

0.0000

0.5000

1.0000

1.5000

2.0000

0 10 20 30 40

KeySize=PointerSize

sq m

m Combination area

Total area

Data arrival time

02468

1012

0 10 20 30 40

KeySize=PointerSize



Figure 28: Result of synthesis of SORTER, optimized for fast design. Area at increasing sizes.

Figure 29: Result of synthesis of SORTER, optimized for fast design. Data arrival time at increasing sizes.

Area

0.00002.00004.00006.00008.0000

10.000012.000014.000016.0000

0 5 10 15 20 25 30 35

Size

sq m

m

Combination area with increasing ListSize

Total area with increasing ListSize

Combinational area with increasing KeySize=PointerSize

Total area with increasing KeySize=PointerSize

Data arrival time

7.27.47.67.8

88.28.48.68.8

0 5 10 15 20 25 30 35

Size

Data arrival time w ith increasing ListSize

Data arrival time w ith increasing KeySize=PointerSize



Formulas making coarse approximations to the total area for different parameter sizes can be found. In these formulas parameters are shown in parenthesis: (KeySize, PointerSize, ListSize)

Then the SORTER was synthesized both for minimal area and minimal data arrival time. The re-sult when using KeySize=8, PointerSize=8 and ListSize=32 is shown in Table 11 on page 46 and Figure 30 on page 47.

Formula 1: Formula for total area, without correction and without ListSize, optimized for minimal area

Formula 2: Formula for total area, with correction and without ListSize, optimized for minimal area

Formula 3: Formula for total area, with correction and with ListSize, optimized for minimal area

Table 11: Timing and area of SORTER (parameters: 8, 8, 32)

OptimizationCombinatorial area [sq mm]

Total area[sq mm]


Minimal data arrival time 3.8798 14.2240 7.69

Minimal area 1.6276 9.2035 5.64

TotalAreaWOcorrWOlistsizeTimingOpt KeySize PointerSize ListSize, ,( )

TotalArea 8 8 3, ,( )

TotalArea 16 8 3, ,( ) TotalArea 8 8 3, ,( )–( )8

------------------------------------------------------------------------------------------------------------ KeySize 8–( )⋅

TotalArea 8 16 3, ,( ) TotalArea 8 8 3, ,( )–( )8

------------------------------------------------------------------------------------------------------------ PointerSize 8–( )⋅

+

+

=

TotalAreaWOlistsizeTimingOpt KeySize PointerSize ListSize, ,( )

TotalAreaWOcorrWOlistsize KeySize PointerSize ListSize, ,( )

TotalArea 16 16 3, ,( )TotalAreaWOcorrWOlistsize 16 16 3, ,( )--------------------------------------------------------------------------------------------------------

⋅

=

TotalAreaTimingOpt KeySize PointerSize ListSize, ,( )

TotalArea 8 8 3, ,( )

TotalAreaWOlistsize KeySize PointerSize ListSize, ,( )3

--------------------------------------------------------------------------------------------------------------------------------------- ListSize 3–( )⋅

+

=



The first thing observed from this experiment is that the data arrival time actually was reduced together with the total area, when the synthesis was optimized for minimal area. This is not re-markable because smaller area means shorter signal paths. What is a little strange is that this solution was not found when optimizing for shortest data arrival time. This is probably because the methods the synthesis tool uses, which is heuristic and therefore not guaranteed to find the optimal solution.

A coarse approximation to the difference between the two areas seen from this experiment is 9.20/14.22=65%. The very coarse approximation to total area when optimizing for minimal area is shown in Formula 4 on page 47.

The numbers for total area can be compared with the area of the chip Arisland et al. made in 1984. This chip contains (see “Physical implementation” on page 6) what could be compared with 16-bit keys, 12-bit pointers and a ListSize of 16. In an 4µm NMOS process of the year 1984, this chip was implemented on approximately 5.4 x 5.4mm = 29.16mm2.

Using Formula 4 on page 47, the area when optimizing for minimal data arrival time was found to be approximately 8.0mm2. This is 27.4% of what Arisland et al. achived. This is not impres-sive. The reason why the improvement is not bigger, is probably because Arisland et al. made the layout of the chip manually, while in this project the area has been calculated from an auto-matic mapping to a standard cell ASIC. Arisland et al. also laid out the cells in such a way that no routing would be needed between the cells. This is probably not possible in an automatically generated mapping to a standard cell ASIC.

To improve the area of the design, at least three possiblilties exist:1. Fine tuning the optimization process by specifying more constraints.2. Manual mapping to the standard cell ASIC.3. Automatic or manual mapping to full custom ASIC.

Figure 30: Timing vs. area of SORTER (parameters: 8, 8, 32)

Formula 4: Formula for total area, optimized for minimal data arrival time

Timing vs. Area

0.0000

2.0000

4.0000

6.00008.0000

10.0000

12.0000

14.0000

16.0000

0 5 10


To

tal a

rea

[sq

mm

]

Optimization on min dataarrival time

Optimization on min.area

TotalAreaAreaOpt KeySize PointerSize ListSize, ,( )TotalAreaTimingOpt KeySize PointerSize ListSize, ,( ) 65 %⋅( )=



Using Formula 4 on page 47 once more, a very coarse approximation to the area of a sorter able to sort 1000 elements, with 16-bit keys and 12-bit pointers. The area of such a sorter chop would be approximately 550mm2. This is large, but by using the improvement options mentioned above it should be possible to make such a chip.

Chapter 4 • Final notes


CHAPTER 4 •

FINAL NOTES



4.1 CONCLUSIONThese are the goals of the project presented in the “Introduction” on page 1:

1. Learn VHDL and specifically syntesizable VHDL. Learn about the design structure and methodology when designing with VHDL and the processes of verification and synthesis.

2. Construct a sorter based on the algorithm described by Arisland et al. (1984) using VHDL.

3. Synthesize the SORTER and discuss the results.4. Learn to use the tools needed for VHDL simulation and synthesis.

Learn VHDL: This author is confident that he is now capable of writing VHDL models using much less intuition and more established methodology than before. He has made it from the point where one try and fail based on previous C++/Pascal experience, to the point where one knows the VHDL language. This is important because of the many differences between software programming languages and hardware description languages.

Construct the sorter: The sorter has been constructed according to the work of Arisland et. al (1984) and the specification set forth in this project. It has been verified and synthesized, and seems to be working according to the expectations.

Synthesize: By synthesizing the design, some characteristics on area and timing has been found. These increase near linearly with increasing input parameters, and that is taken as a proof that the VHDL model could be synthesized well. The size of the synthesized circuit is such that with some streamlining a sorter which can sort 1000 elements should be possible to make.

Learn tools: Although not an expert user, this author has learnt to use VeriBest VHDL Simu-lator and Synopsys Design Analyzer, for VHDL simulation and synthesis, respectively. The steepest part of the learning curve is probably passed, and further use of these tools should be easier.

The final conclusion is that it should be possible to implement a sorter with 1000 elements, so further work on this project is worthwhile.

An original search system may write results to a RAM, and read results from the same RAM before presentation to the user. If the RAM is exchanged for one or more sorters, then the search system could write results to the sorter in addition to RAM, and read results from the sorter in-stead of from RAM before using the pointer to find the original document. This could result in a system where the time to sort the results become negligible compared to the input/output time, thus resulting in a system which can sort in time O(1).



4.2 FUTURE WORKAlthough the sorter has been constructed in a VHDL model, there are much work to be done.

4.2.1 Layout optimizationBefore production of this or a future synthesized VHDL description of the sorter, the layout should be optimized using for example one of these methods:

1. Fine tuning of the optimization process by specifying more constraints.2. Manual mapping to the standard cell ASIC.3. Automatic or manual mapping to full custom ASIC.

4.2.2 Order of output sequencesIf more elements are to be sorted than the sorter are able to sort, the elements with the smallest keys are shifted out of the sorter. To achive this, the largest element has to be in the leftmost cell, so that the smallest element always is in the rightmost cell. This means that the sorted se-quences will be written out in reverse order, with the smallest element first.

If the output from the sorter will be used directly it would be an advantage to have the largest element written first. This could be achived by allowing the sorter to shift data both ways, at the cost of a number of multiplexers in each cell and some tri-state logic to manage the input and output busses to and from the sorter.

4.2.3 Pipelining (overlapping input/output operation)The sorter has been designed to allow future implementation of pipelining. This means that while a sorted sequence is written out, a new sequence can be entered into the sorter.

For this to work, the ability to pause output operation must be abandoned. This is because of the fact that if new elements are entered into the sorter faster than the completed sequence is written out, the latter will be destroyed by the new sequence.

The pipelining can be achieved by setting the disable-bit on all sorted elements before starting the output operation, and then shifting all disabled elements one cell to the right each clock cy-cle.

To get the sorted elements out of the sorter in the correct order as discussed in the last section, give rise to difficulties when implementing pipelining, because the output direction cannot un-conditionally be opposite of the input direction. One solution could be to exchange the input and output direction each time a sequence is sorted. This means, sequence 1 is entered from the left and written out on the left, while sequence 2 is entered on the right and written out on the right.

4.2.4 An idea for faster operationAn idea for faster operation is to control the broadcast hierarchy to reduce the critical path (the longest signal path) in the design. A tree structure provides a shorter longest path than a linear structure. In this design input data, control, reset and clock signals are broadcasted to all sorter cells, so there should be room for improvement on this. The technology used to produce the chip does not nescessary give room for such optimization, but the possibility should be examined.



4.2.5 Chaining of several sorter chipsIt is possible to chain several sorter chips to be able to sort longer sequences. The only addition to the VHDL code to achieve this is to make ports in the SORTER entity for the remaining signals in to and out the sorter cell chain.

Because the signal paths from one chip to the next will be much longer than between two cells inside one chip, such a configuration will have to operate on a lower clock frequency than what one chip could do.

4.2.6 The surroundingsThe sorter needs additional logic to control the input and output of data. This could include a Direct Memory Access (DMA) controller and an interface to this.

Work could also be done on how to best interface the sorter with the FAST ASA search system to achieve the best performance.



4.3 PROBLEMS

4.3.1 Too ambitious At first two conditions was thought necessary:

1. The interface should facilitate future implementation of overlapping input/output operation.

2. It should be possible to connect several sorters in a chain to be able to sort larger num-bers of elements.

It was thought useful to make a behavioural description of the sorter to verify that the operation was according to the specification. When making this description, a list was used to hold the elements. This way the algorithm to sort the elements could be described on a high level which was easy to read.

In addition to this a pipelined implementation was attempted, which could start sorting a second list of elements while the first is written out. The pipelined implementation is obviously more efficient, but the behavioural description of it turned out to be difficult, and this implementation was not completed. To be able to read/sort and write data at the same time, two finite state ma-chines was implemented. This solution was then attempted used also after the pipelining was abandoned, something which complicated the design.

All of this complicated the design, and after many hours of trying to find smart ways of making an understandable design, the implementation of these abitiously advanced designes was not de-veloped further.

The conclusion, after what seemed like many wasted hours of work, was to implement a more simple design, but designing for the possibility of future expansion.

Chapter 5 • References


CHAPTER 5 •

REFERENCES



5.1 REFERENCESArisland, K. Ø., Aasbø, A. C., Nundal, A. VLSI parallel shift sort algorithm and design. INTE-GRATION, the VLSI journal 2 (1984) 331-347

Smith, Douglas J., HDL Chip Design, Second Printing. Madison: Doone Publications, 1997 (IS-BN 0-9651934-3-8)

Navabi, Zainalabedin, VHDL : analysis and modeling of digital systems, 2nd ed. New York: McGraw-Hill, 1998 (ISBN 0-07-046479-0)

Ryvarden, Einar. Internett rundt på 0,6 sekunder. digi.no (16. nov 1998) [http://w3.digi.no/digi98.nsf/web/dd59150520ery7139238575, printed 26. jan 1999]

Halaas, Arne. Personal communication (january 1999)



5.2 BIBLIOGRAPHYChang, K.C., Digital design and modeling with CHDL and synthesis. Los Alamitos: IEEE Com-puter Society Press, 1997 (ISBN 0-8186-7716-3)

All books, and in particular Chang (1997) has been studied to learn VHDL.

APPENDIX A •

CODE LISTINGS

Appendix A-1: SORTER_BOX VHDL code

Page App-2 Rune B. Nakim 1999

APPENDIX A-1: SORTER_BOX VHDL CODE--============================================================================-- File: box.vhd-- Author: Rune B. Nakim---- Contents:-- SORTER_BOX entity-- RTL architecture---- Copyright 1999 Rune B. Nakim--============================================================================

library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all; -- Standard IEEE, use for VeriBest--use ieee.std_logic_arith.all; -- Synopsys, corresponds to numeric_std

-------------------------------------------------------------------------------- SORTER_BOX entity...---- An implementation of the cell of the Arisland et al. (1984) algorithm.---- Parameters:-- KeySize, integer. The size in bits of the Key.-- PointerSize, integer. The size in bits of the Pointer.------ Input signals:-- CLK, 1 bit. Clock signal.-- Reset_n, 1 bit. Reset signal. (Active low.)-- ShiftIn, 1 bit. Set when data to be sorted is at KeyIn/PointerIn.-- KeyIn, n bits. Input data.-- PointerIn, m bits. Input data.-- KeyPrev, n bits. Data from the previous SORTER_BOX component.-- PointerPrev, m bits. Data from the previous SORTER_BOX component.-- LEprev, 1 bit. Less-Than-Or-Equal signal from the previous-- SORTER_BOX component.-- DisabledPrev, 1 bit. Set if the previous SORTER_BOX component is-- disabled.-- ShiftOut, 1 bit. Set when data is to be shifted out. KeyIn/PointerIn-- is ignored, and data is shifted in from-- KeyPrev/PointerPrev.---- Output signals:-- KeyOut, n bits. Output data.-- PointerOut, m bits. Output data.-- LEout, 1 bit. Output Less-Than-Or-Equal signal. Set when KeyIn is-- less than or equal (<=) to the Key stored in this-- SORTER_BOX component. This signal is independent on-- whether this component is disabled.-- DisabledOut, 1 bit. Set when this component is disabled.--entity SORTER_BOX is generic (KeySize : integer;


Rune B. Nakim 1999 Page App-3

PointerSize : integer); port ( CLK: in STD_LOGIC; Reset_n: in STD_LOGIC;

-- Input ShiftIn: in STD_LOGIC; KeyIn: in unsigned (KeySize-1 downto 0); PointerIn: in unsigned (PointerSize-1 downto 0);

-- Input from previous KeyPrev: in unsigned (KeySize-1 downto 0); PointerPrev: in unsigned (PointerSize-1 downto 0); LEprev: in STD_LOGIC; DisabledPrev: in STD_LOGIC;

-- Output ShiftOut: in STD_LOGIC; KeyOut: out unsigned (KeySize-1 downto 0); PointerOut: out unsigned (PointerSize-1 downto 0);

-- Output to next LEout: out STD_LOGIC; DisabledOut: out STD_LOGIC );end SORTER_BOX;

architecture RTL of SORTER_BOX is type SorterElement is record Key : unsigned (KeySize-1 downto 0); Pointer: unsigned (PointerSize-1 downto 0); Disabled : STD_LOGIC; end record; signal Element, nextElement : SorterElement; signal FromIn, FromPrev : STD_LOGIC; signal Sel : unsigned (1 downto 0); signal LE : STD_LOGIC;

begin

Compare: process (KeyIn, Element) begin if KeyIn <= Element.Key then LE <= ’1’; else LE <= ’0’; end if; end process;

LEout <= LE;

process (ShiftIn, LE, LEprev, Element, DisabledPrev) begin if ShiftIn=’1’ and ((LE=’0’ and LEprev=’1’ and Element.Disabled=’0’) or (LEprev=’1’ and Element.Disabled=’1’ and DisabledPrev=’0’)) then FromIn <= ’1’;



else FromIn <= ’0’; end if; end process; process (ShiftOut, ShiftIn, LE, LEprev, Element, DisabledPrev) begin if ShiftOut=’1’ or (ShiftIn=’1’ and ((LE=’0’ and LEprev=’0’ and Element.Disa-bled=’0’) or (LEprev=’0’ and Element.Disabled=’1’ and DisabledPrev=’0’))) then FromPrev <= ’1’; else FromPrev <= ’0’; end if; end process;

Sel <= FromIn & FromPrev; with Sel select nextElement <= (KeyIn, PointerIn, ’0’) when "10", (KeyPrev, PointerPrev, DisabledPrev ) when "01", Element when others;

Synchronuous: process (CLK, Reset_n) begin if Reset_n=’0’ then Element.Disabled <= ’1’; elsif CLK’event and CLK=’1’ then Element <= nextElement; end if; end process;

KeyOut <= Element.Key; PointerOut <= Element.Pointer; DisabledOut <= Element.Disabled;

end RTL;

Appendix A-2: SORTER VHDL code


APPENDIX A-2: SORTER VHDL CODE--============================================================================-- File: sorter.vhd-- Author: Rune B. Nakim---- Contents:-- SORTER entity-- BEHAVIORAL architecture-- RTL architecture---- Copyright 1999 Rune B. Nakim--============================================================================

library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all; -- Standard IEEE, use for VeriBest--use ieee.std_logic_arith.all; -- Synopsys, corresponds to numeric_std

-------------------------------------------------------------------------------- SORTER entity...---- Sorts data to descending keys. Output data in reverse order.---- Parameters:-- KeySize, integer. The size in bits of the Key.-- PointerSize, integer. The size in bits of the Pointer.-- ListSize, integer. The number of elements that the sorter should be-- able to sort.------ Input signals:-- CLK, 1 bit. Clock signal. Clock rate and other information-- about the clock signal is not specified.-- Reset_n, 1 bit. Resets the operation of the sorter.-- Starts input operation. (Active low.)-- EnableIn, 1 bit. Data is read only when this input is high.-- KeyIn, n bits. This is the value to be used as the sort key.-- PointerIn, m bits. This is a value ‘attached’ to the key,-- usually a pointer to some data.-- LastIn, 1 bit. This signal should be set high during the clock-- cyle when the last element in a sequence is input.-- EnableOut, 1 bit. This signal is set high when sorted data is-- ready to be output.-- EnableOut, 1 bit. Output operation is started on the first clock-- cycle signal is high, after data is ready to be-- output.---- Output signals:-- Outputting, 1 bit. Is high while valid data is at the output.-- LastOut, 1 bit. This signal is set high during the clock cyle-- when the last element in a sequence is output.-- KeyOut, n bits. This is the value to be used as the sort key.-- PointerOut, m bits. This is the value ‘attached’ to the key.--



--entity SORTER is generic (KeySize : integer; PointerSize : integer; ListSize : integer); port ( CLK: in STD_LOGIC; Reset_n: in STD_LOGIC;

-- Input mode of operation EnableIn: in STD_LOGIC; LastIn: in STD_LOGIC; KeyIn: in UNSIGNED (KeySize-1 downto 0); PointerIn: in UNSIGNED (PointerSize-1 downto 0); ReadyIn: out STD_LOGIC;

-- Output mode of operation EnableOut: in STD_LOGIC; DoneOut: out STD_LOGIC; KeyOut: out UNSIGNED (KeySize-1 downto 0); PointerOut: out UNSIGNED (PointerSize-1 downto 0);ReadyOut: out STD_LOGIC; Outputting: out STD_LOGIC );end SORTER;---- ...end of SORTER entity------------------------------------------------------------------------------

-------------------------------------------------------------------------------- RTL architecture of SORTER...---- Register Transfer Level (RTL) description of the sorter.--architecture RTL of SORTER is

-- Inludes the SORTER_BOX entity as a component component SORTER_BOX generic (KeySize : integer; PointerSize : integer); port ( CLK: in STD_LOGIC; Reset_n: in STD_LOGIC; ShiftIn: in STD_LOGIC; KeyIn: in UNSIGNED (KeySize-1 downto 0); PointerIn: in UNSIGNED (PointerSize-1 downto 0); KeyPrev: in UNSIGNED (KeySize-1 downto 0); PointerPrev: in UNSIGNED (PointerSize-1 downto 0); LEprev: in STD_LOGIC; DisabledPrev: in STD_LOGIC; ShiftOut: in STD_LOGIC; KeyOut: out UNSIGNED (KeySize-1 downto 0); PointerOut: out UNSIGNED (PointerSize-1 downto 0); LEout: out STD_LOGIC; DisabledOut: out STD_LOGIC );



end component;

-- Type definitions subtype KeyType is UNSIGNED (0 to KeySize-1); subtype PointerType is UNSIGNED (0 to PointerSize-1);

-- Internal signal (copy of out-port) signal DoneOutInternal : STD_LOGIC;

-- STATE MACHINE type StateType is (INIT, READY_IN, READ, FORWARD, READY_OUT, WRITE); signal CurrentState, NextState : StateType;

-- STRUCTURAL DESCRIPTION OF THE SORTER_BOX COMPONENTS -- Global control signals signal ShiftIn: STD_LOGIC; signal ShiftOut: STD_LOGIC; -- Type definitions for the structural description type KeyArray is array (integer range <>) of UNSIGNED (KeySize-1 downto 0); type PointerArray is array (integer range <>) of UNSIGNED (PointerSize-1 downto 0); type LEArray is array (integer range <>) of STD_LOGIC; type DisabledArray is array (integer range <>) of STD_LOGIC;

-- Interconnection signals for the structural description signal Key: KeyArray(ListSize-2 downto 0); signal Pointer: PointerArray(ListSize-2 downto 0); signal LE: LEArray(ListSize-2 downto 0); signal LEout: STD_LOGIC; signal LEfirst: STD_LOGIC;

signal Disabled: DisabledArray(ListSize-2 downto 0); signal DisabledOut: STD_LOGIC; signal DisabledFirst: STD_LOGIC;

begin

---------------------------------------------------------------------------- -- STRUCTURAL DESCRIPTION OF THE SORTER BLOCKS --

LEfirst <= ’0’; DisabledFirst <= ’0’ when (ShiftIn=’1’) else ’1’;

-- Generate the ListSize # of SORTER_BOX components cells : for i in 0 to ListSize-1 generate -- Three cases are handled: The first, the last, and the rest -- The first leftmost : if i = 0 generate



leftmost_cell : SORTER_BOX generic map (KeySize, PointerSize) port map (CLK, Reset_n, ShiftIn, KeyIn, PointerIn, KeyIn, PointerIn, LEfirst, DisabledFirst, ShiftOut, Key(i), Pointer(i), LE(i), Disabled(i)); end generate leftmost;

-- All but the first and the last middle : if i > 0 and i < ListSize-1 generate middle_cell : SORTER_BOX generic map (KeySize, PointerSize) port map (CLK, Reset_n, ShiftIn, KeyIn, PointerIn, Key(i-1), Pointer(i-1), LE(i-1), Disabled(i-1), ShiftOut, Key(i), Pointer(i), LE(i), Disabled(i)); end generate middle;

-- The last rightmost : if i = ListSize-1 generate rightmost_cell : SORTER_BOX generic map (KeySize, PointerSize) port map (CLK, Reset_n, ShiftIn, KeyIn, PointerIn, Key(i-1), Pointer(i-1), LE(i-1), Disabled(i-1), ShiftOut, KeyOut, PointerOut, LEout, DisabledOut); end generate rightmost; end generate cells;

-- End of STRUCTURAL DESCRIPTION OF THE SORTER BLOCKS -- ----------------------------------------------------------------------------

-- DoneOut -- Because out-ports cannot be read, the signal DoneOutInternal is used -- internally in this code, and DoneOut is set to equal DoneOutInternal. -- DoneOut <= DoneOutInternal;

---------------------------------------------------------------------------- -- STATE MACHINE (combinatorial) -- SMcomb: process (CurrentState, EnableOut, LastIn, DisabledOut, Disabled) begin



-- Set the default values of all signals written by this SM ReadyIn <= ’0’;ReadyOut <= ’0’; Outputting <= ’0’; ShiftIn <= ’0’; ShiftOut <= ’0’; DoneOutInternal <= ’0’;

-- The state machine case CurrentState is

when INIT => NextState <= READY_IN; ----------------------------------------

when READY_IN => ReadyIn <= ’1’;

NextState <= READ; ----------------------------------------

when READ => ReadyIn <= ’1’; ShiftIn <= ’1’;

-- Kanskje DisabledOut istedenfor Disabled(ListSize-2) if LastIn=’1’ and Disabled(ListSize-2)=’1’ then NextState <= FORWARD; elsif LastIn=’1’ and EnableOut=’1’ and Disabled(ListSize-2)=’0’ then NextState <= WRITE; elsif LastIn=’1’ and EnableOut=’0’ and Disabled(ListSize-2)=’0’ then NextState <= READY_OUT; else NextState <= CurrentState; end if; ----------------------------------------

when FORWARD => if (DisabledOut=’1’) then ShiftOut <= ’1’; end if;

if EnableOut=’1’ and Disabled(ListSize-2)=’0’ then NextState <= WRITE; elsif EnableOut=’0’ and Disabled(ListSize-2)=’0’ then NextState <= READY_OUT; else NextState <= CurrentState; end if;

when READY_OUT => ReadyOut <= ’1’;



NextState <= WRITE; ----------------------------------------

when WRITE => ReadyOut <= ’1’;if EnableOut=’1’ then ShiftOut <= ’1’; Outputting <= ’1’;end if;

if (Disabled(ListSize-2)=’1’) then DoneOutInternal <= ’1’; end if;

if Disabled(ListSize-2)=’1’ then NextState <= READY_IN; else NextState <= CurrentState; end if; ----------------------------------------

end case;

end process; -- End of STATE MACHINE Output (combinatorial) -- ----------------------------------------------------------------------------

---------------------------------------------------------------------------- -- STATE MACHINE (sequential) -- SMseq: process (CLK, Reset_n) begin if (Reset_n = ’0’) then -- Asynch. Reset_n which sends the FSM CurrentState <= INIT; -- to the INIT state. elsif (CLK’event and CLK=’1’) then -- On rising clock edges, go to CurrentState <= NextState; -- the next state chosen by end if; -- the SMcomb process. end process; ----------------------------------------------------------------------------

end RTL;---- ...end of RTL architecture of SORTER------------------------------------------------------------------------------

-------------------------------------------------------------------------------- BEHAVIORAL architecture of SORTER---- Behavioral description of the sorter.-- Insertion sort implemented using loops and multiple wait statements.--architecture BEHAVIORAL of SORTER is type SorterElement is record



Key : unsigned (0 to KeySize-1); Pointer: unsigned (0 to PointerSize-1); end record;

type SorterList is array (ListSize downto 1) of SorterElement;

begin

Sort: process variable fan : SorterList; variable NumberOfElements : integer; variable new_pos : integer; variable more_cards : boolean; variable found_pos : boolean; variable new_key : unsigned (0 to KeySize-1); variable new_pointer : unsigned (0 to PointerSize-1);

beginReadyIn <= ’0’;ReadyOut <= ’0’;Outputting <= ’0’;DoneOut <= ’0’; NumberOfElements := 0; more_cards := true;

if Reset_n/=’1’ then wait until Reset_n=’1’;end if;

-- wait until CLK’event and CLK=’1’;ReadyIn <= ’1’;

while more_cards loop

wait until CLK’event and CLK=’1’ and EnableIn=’1’;

if NumberOfElements < ListSize then NumberOfElements := NumberOfElements + 1;end if;

-- Take next card. new_key := KeyIn; new_pointer := PointerIn;

if LastIn = ’1’ then more_cards := false; end if;

-- Find position to insert new card. new_pos := 0; found_pos := false; while not found_pos loop new_pos := new_pos + 1;

if new_pos = NumberOfElements then found_pos := true;



elsif new_pos >= ListSize then found_pos := true; elsif fan(new_pos).Key < new_key then found_pos := true; end if; end loop;

-- Shift all cards from insert position to end. for idx in ListSize-1 downto new_pos + 1 loop fan(idx) := fan(idx - 1); end loop;

-- Insert new card. if (new_pos < ListSize) then fan(new_pos) := (new_key,new_pointer); end if;

end loop;

ReadyIn <= ’0’;

if (NumberOfElements < ListSize) then for idax in 1 to (ListSize-NumberOfElements) loop wait until CLK’event and CLK=’1’; end loop;end if;


for index in NumberOfElements downto 1 loop Outputting <= ’0’; if (EnableOut=’0’) then wait until EnableOut=’1’; end if;


if (index = 1) then DoneOut <= ’1’; end if;

KeyOut <= fan(index).Key; PointerOut <= fan(index).Pointer;

wait until CLK = ’1’ and CLK’event; end loop;

end process;

end BEHAVIORAL;---- ...end of BEHAVIORAL architecture of SORTER------------------------------------------------------------------------------

Appendix A-3: SORTER_BOX Test Bench code


APPENDIX A-3: SORTER_BOX TEST BENCH CODElibrary ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;--use ieee.std_logic_arith.all;

use std.textio.all;

use WORK.NakimUtilities.To_StdLogicVector;

entity TESTBENCH isend TESTBENCH;

architecture STIMULUS of TESTBENCH is

component SORTER_BOX generic (KeySize : integer; PointerSize : integer); port ( CLK: in STD_LOGIC; Reset_n: in STD_LOGIC;

-- Input ShiftIn: in STD_LOGIC; KeyIn: in unsigned (KeySize-1 downto 0); PointerIn: in unsigned (PointerSize-1 downto 0);

-- Input from previous KeyPrev: in unsigned (KeySize-1 downto 0); PointerPrev: in unsigned (PointerSize-1 downto 0); LEprev: in STD_LOGIC; DisabledPrev: in STD_LOGIC;

-- Output ShiftOut: in STD_LOGIC; KeyOut: out unsigned (KeySize-1 downto 0); PointerOut: out unsigned (PointerSize-1 downto 0);

-- Output to next LEout: out STD_LOGIC; DisabledOut: out STD_LOGIC ); end component;

constant KeySize : integer := 16; constant PointerSize : integer := 32;

signal CLK: STD_LOGIC; signal Reset_n: STD_LOGIC; signal ShiftIn: STD_LOGIC; signal KeyIn: unsigned (KeySize-1 downto 0); signal PointerIn: unsigned (PointerSize-1 downto 0);



signal KeyPrev: unsigned (KeySize-1 downto 0); signal PointerPrev: unsigned (PointerSize-1 downto 0); signal LEprev: STD_LOGIC; signal DisabledPrev: STD_LOGIC; signal ShiftOut: STD_LOGIC; signal KeyOut: unsigned (KeySize-1 downto 0); signal PointerOut: unsigned (PointerSize-1 downto 0); signal LEout: STD_LOGIC; signal DisabledOut: STD_LOGIC;

begin

U1: SORTER_BOX generic map(KeySize, PointerSize) port map (CLK, Reset_n, ShiftIn, KeyIn, PointerIn, KeyPrev,

PointerPrev, LEprev, DisabledPrev, ShiftOut, KeyOut, PointerOut, LEout, DisabledOut);

clock: process variable clktmp: std_logic := ’0’; begin clktmp := not clktmp; CLK <= clktmp; wait for 10 ns; end process;

rst: processbegin

Reset_n<= ’0’; wait for 20 ns; Reset_n<= ’1’;

wait;end process;

PointerIn <= (others => ’X’);PointerPrev <= (others => ’X’);

feed: process begin

wait for 20 ns;

KeyIn <= TO_UNSIGNED(100, KeySize); KeyPrev <= (others => ’X’); ShiftIn <= ’1’; ShiftOut <= ’0’; LEprev <= ’1’; DisabledPrev <= ’0’; wait for 20 ns;

KeyIn <= TO_UNSIGNED(50, KeySize); KeyPrev <= (others => ’X’); ShiftIn <= ’0’; ShiftOut <= ’0’; LEprev <= ’X’; DisabledPrev <= ’X’; wait for 20 ns;

KeyIn <= TO_UNSIGNED(10, KeySize);



KeyPrev <= (others => ’X’); ShiftIn <= ’0’; ShiftOut <= ’0’; LEprev <= ’X’; DisabledPrev <= ’X’; wait for 20 ns;

KeyIn <= TO_UNSIGNED(200, KeySize); KeyPrev <= (others => ’X’); ShiftIn <= ’0’; ShiftOut <= ’0’; LEprev <= ’X’; DisabledPrev <= ’X’; wait for 20 ns;

KeyIn <= TO_UNSIGNED(200, KeySize); KeyPrev <= TO_UNSIGNED(100, KeySize); ShiftIn <= ’1’; ShiftOut <= ’0’; LEprev <= ’1’; DisabledPrev <= ’0’; wait for 20 ns;


KeyIn <= (others => ’X’); KeyPrev <= TO_UNSIGNED(100, KeySize); ShiftIn <= ’0’; ShiftOut <= ’1’; LEprev <= ’X’; DisabledPrev <= ’1’; wait for 20 ns;


KeyIn <= TO_UNSIGNED(300, KeySize); KeyPrev <= TO_UNSIGNED(100, KeySize); ShiftIn <= ’1’; ShiftOut <= ’0’; LEprev <= ’0’; DisabledPrev <= ’0’;

wait;

end process;



end STIMULUS;

configuration test_behavioural of TESTBENCH is

for STIMULUS -- of TESTBENCH for U1 : SORTER_BOX

use entity WORK.SORTER_BOX(RTL);end for;

end for;

end test_behavioural;

Appendix A-4: Test Bench code


APPENDIX A-4: TEST BENCH CODElibrary ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;--use ieee.std_logic_arith.all;

use std.textio.all;

use WORK.NakimUtilities.To_StdLogicVector;

entity TESTBENCH isend TESTBENCH;

architecture STIMULUS of TESTBENCH is

component SORTER generic (KeySize : integer; PointerSize : integer; ListSize : integer); port ( CLK: in STD_LOGIC; Reset_n: in STD_LOGIC;

-- Input mode of operation EnableIn: in STD_LOGIC; LastIn: in STD_LOGIC; KeyIn: in UNSIGNED (KeySize-1 downto 0); PointerIn: in UNSIGNED (PointerSize-1 downto 0); ReadyIn: out STD_LOGIC;

-- Output mode of operation EnableOut: in STD_LOGIC; DoneOut: out STD_LOGIC; KeyOut: out UNSIGNED (KeySize-1 downto 0); PointerOut: out UNSIGNED (PointerSize-1 downto 0);ReadyOut: out STD_LOGIC; Outputting: out STD_LOGIC ); end component;

constant KeySize : integer := 16; constant PointerSize : integer := 16; constant ListSize : integer := 10;

signal CLK: STD_LOGIC; signal Reset_n: STD_LOGIC; signal EnableIn: STD_LOGIC; signal LastIn: STD_LOGIC; signal KeyIn: UNSIGNED (KeySize-1 downto 0); signal PointerIn: UNSIGNED (PointerSize-1 downto 0); signal ReadyIn: STD_LOGIC; signal EnableOut: STD_LOGIC; signal DoneOut: STD_LOGIC; signal KeyOut: UNSIGNED (KeySize-1 downto 0);



signal PointerOut: UNSIGNED (PointerSize-1 downto 0);signal ReadyOut: STD_LOGIC; signal Outputting: STD_LOGIC; signal ReadyIn_REF: STD_LOGIC; signal DoneOut_REF: STD_LOGIC; signal KeyOut_REF: UNSIGNED (KeySize-1 downto 0); signal PointerOut_REF: UNSIGNED (PointerSize-1 downto 0);signal ReadyOut_REF: STD_LOGIC; signal Outputting_REF: STD_LOGIC;

signal ok_all, ok, ok2 : boolean; signal WritingGoingOnSignal: boolean;

begin

U1: SORTER generic map(KeySize, PointerSize, ListSize) port map (CLK, Reset_n, EnableIn, LastIn, KeyIn, PointerIn, ReadyIn, EnableOut, DoneOut, KeyOut, PointerOut, ReadyOut, Outputting);

U2: SORTER generic map(KeySize, PointerSize, ListSize) port map (CLK, Reset_n, EnableIn, LastIn, KeyIn, PointerIn, ReadyIn_REF, EnableOut, DoneOut_REF, KeyOut_REF, PointerOut_REF, ReadyOut_REF, Outputting_REF);

clock: process variable clktmp: std_logic := ’0’; begin clktmp := not clktmp; CLK <= clktmp; wait for 10 ns; end process;

rst: processbegin Reset_n<= ’0’; wait for 20 ns; Reset_n<= ’1’; wait;end process;

feed: process -- FILE I/O file input_file: text is in "tb_1.txt"; variable read_buf : line; variable data_key: integer; variable data_pointer: integer; variable data_last: integer;

begin wait until CLK’event and CLK=’1’; if Reset_n=’0’ then EnableIn <= ’0’; -- after 1 ns; LastIn <= ’0’; -- after 1 ns; elsif ReadyIn=’1’ then



while not endfile(input_file) loop if ReadyIn=’1’ then readline(input_file, read_buf); read(read_buf, data_key); read(read_buf, data_pointer); read(read_buf, data_last);

EnableIn <= ’1’; KeyIn<= To_StdLogicVector(data_key, KeySize); -- after 1 ns; PointerIn<= To_StdLogicVector(data_pointer, PointerSize); -- after 1 ns;

if data_last = 1 then LastIn <= ’1’; -- after 1 ns;

wait until CLK’event and CLK=’1’; LastIn <= ’0’; -- after 1 ns; EnableIn <= ’0’; -- after 1 ns; else LastIn <= ’0’; -- after 1 ns; end if; end if;

wait until CLK’event and CLK=’1’;end loop; end if;end process;

eat: process -- FILE I/O file output_file: text is out "res_1.txt"; variable write_buf : line;

variable WritingGoingOn : boolean; variable space1: string(1 to 2) := " ("; variable space2: string(1 to 3) := "), "; variable pass_1: string(1 to 5) := "PASS!"; variable fail_1: string(1 to 5) := "FAIL!"; variable pass_all: string(1 to 21) := "All PASSed until now!"; variable fail_all: string(1 to 22) := "Some FAILed until now!";

variable eat_data : boolean;

begin EnableOut <= ’0’;

wait until ReadyOut=’1’;-- wait until rising_edge(CLK) and ReadyOut=’1’;

eat_data := true; while (eat_data) loop

wait until CLK’event and CLK=’1’;

EnableOut <= ’1’;

if Outputting=’1’ then if DoneOut=’1’ then



WritingGoingOn := false; else WritingGoingOn := true; end if; else WritingGoingOn := false; end if;

if WritingGoingOn or WritingGoingOnSignal then write(write_buf, To_Integer(KeyOut)); write(write_buf, space1); write(write_buf, To_Integer(PointerOut)); write(write_buf, space2); if DoneOut=’1’ then writeline(output_file, write_buf);

if (ok) then write(write_buf, pass_1); else write(write_buf, fail_1); end if; writeline(output_file, write_buf);

if (ok_all) then write(write_buf, pass_all); else write(write_buf, fail_all); end if; writeline(output_file, write_buf); end if; end if;

WritingGoingOnSignal <= WritingGoingOn; end loop;end process;

Compare: process (CLK, ReadyIn, Reset_n)begin if (Reset_n=’0’) then ok <= true;ok_all <= true; elsif falling_edge(ReadyIn) then ok <= true; elsif falling_edge(CLK) then if (Outputting=’1’) then ok2 <= ((KeyOut = KeyOut_REF) and (PointerOut = PointerOut_REF)); if not ((KeyOut = KeyOut_REF) and (PointerOut = PointerOut_REF)) then ok <= false; ok_all <= false; end if; end if; end if;end process;

end STIMULUS;



configuration test_behavioural of TESTBENCH is

for STIMULUS -- of TESTBENCH for U1 : SORTER use entity WORK.SORTER(RTL);end for;

for U2 : SORTER use entity WORK.SORTER(BEHAVIORAL);end for; end for;

end test_behavioural;

Appendix A-5: Test bench aid PERL code


APPENDIX A-5: TEST BENCH AID PERL CODE#!/store/bin/perl#$max_number_of_elements = 150; # min = 1$max_element_value = 65535; # min = 0

srand; # defaults to srand(time);

$ElementCount = int(rand $max_number_of_elements-1)+1;

for ($n=0; $n<$ElementCount; $n++){ $Elements[$n] = int(rand $max_element_value);}

for ($n=0; $n<$ElementCount; $n++){ if ($n < $ElementCount-1) { print "$Elements[$n]\t$Elements[$n]\t0\n"; } else { print "$Elements[$n]\t$Elements[$n]\t1\n"; }}

APPENDIX B •

VERIFICATION

Appendix B-1: Stage 1


APPENDIX B-1: STAGE 1Input dataVerification procedure, SORTER_BOX, one row per clock cycle, signals are set on the positive clock edge, clocked outputs not visible until next clock cycle

InputStarting register

valueExpected ouput

Expected ending register

valueDescription

Reset Disabled=1Key=?

Reset Disabled to 1

KeyIn=100KeyPrev=xShiftIn=1ShiftOut=0LEprev=1DisabledPrev=0

Disabled=1Key=Undef.

LEout=1DisabledOut=0

Disabled=1Key=100

Force Key=100 into the register

KeyIn=50KeyPrev=xShiftIn=0ShiftOut=0LEprev=xDisabledPrev=x

Disabled=1Key=100


Disabled=1Key=100

Verify “<” gives LEout=1

No data written.


Disabled=1Key=100


Disabled=0Key=100

Verify “=” gives LEout=1

No data written.


Disabled=0Key=100

LEout=0 Disabled=0Key=100

Verify “>” gives LEout=0

No data written.

KeyIn=200KeyPrev=100ShiftIn=1ShiftOut=0LEprev=1DisabledPrev=0

Disabled=0Key=100


Case 2Read from input



ResultTime: 0-230ns


Disabled=0Key=200


Case 1Read from input

KeyIn=xKeyPrev=100ShiftIn=0ShiftOut=1LEprev=xDisabledPrev=1

Disabled=0Key=300

LEout=x Disabled=1Key=100

Case 3Read from pre-vious


Disabled=1Key=100




Disabled=0Key=75



InputStarting register

valueExpected ouput

Expected ending register

valueDescription



APPENDIX B-2: STAGE 2Notice that these pulse diagrams are sligthly overlapping.Signals ending with ‘_REF’ is signals from the behavioral reference model of SORTER.

Appendix B-3: Stage 3 - Test 1


APPENDIX B-3: STAGE 3 - TEST 1The data presented in this appendix has not been edited, except for insertion of extra empty lines and changing character attributes.



Input data33 33 017 17 039 39 021 21 030 30 013 13 013 13 017 17 038 38 023 23 04 4 044 44 015 15 016 16 024 24 011 11 00 0 1

36 36 043 43 034 34 045 45 025 25 038 38 05 5 038 38 010 10 041 41 03 3 01 1 045 45 02 2 01 1 025 25 025 25 021 21 04 4 024 24 029 29 026 26 036 36 07 7 022 22 03 3 029 29 014 14 1

17 17 032 32 020 20 018 18 025 25 018 18 027 27 032 32 043 43 07 7 0

37 37 021 21 00 0 047 47 037 37 012 12 038 38 048 48 049 49 041 41 00 0 042 42 01 1 00 0 048 48 040 40 01 1 021 21 042 42 015 15 034 34 021 21 042 42 031 31 019 19 029 29 018 18 010 10 016 16 048 48 027 27 07 7 019 19 038 38 1

47 47 00 0 036 36 015 15 027 27 038 38 014 14 021 21 1

23 23 024 24 028 28 1

18 18 024 24 04 4 016 16 030 30 048 48 00 0 037 37 038 38 015 15 0

47 47 013 13 1

24 24 01 1 042 42 030 30 028 28 019 19 016 16 042 42 029 29 030 30 011 11 019 19 032 32 01 1 038 38 07 7 018 18 047 47 019 19 022 22 032 32 021 21 015 15 049 49 037 37 015 15 021 21 036 36 023 23 1

45 45 042 42 039 39 02 2 025 25 036 36 07 7 036 36 044 44 012 12 017 17 03 3 026 26 045 45 036 36 018 18 039 39 06 6 00 0 044 44 00 0 010 10 03 3 025 25 015 15 0

41 41 014 14 031 31 010 10 049 49 016 16 026 26 038 38 046 46 06 6 041 41 036 36 024 24 026 26 00 0 044 44 025 25 036 36 036 36 021 21 1

5 5 015 15 020 20 039 39 045 45 043 43 022 22 00 0 028 28 09 9 039 39 041 41 022 22 030 30 030 30 04 4 04 4 034 34 018 18 019 19 036 36 017 17 040 40 04 4 042 42 07 7 018 18 027 27 014 14 040 40 049 49 043 43 027 27 014 14 038 38 032 32 017 17 0

10 10 022 22 036 36 022 22 043 43 01 1 1

38 38 032 32 014 14 047 47 046 46 041 41 040 40 037 37 032 32 029 29 01 1 047 47 026 26 047 47 010 10 040 40 011 11 042 42 047 47 033 33 03 3 02 2 042 42 00 0 048 48 016 16 031 31 047 47 04 4 00 0 03 3 07 7 046 46 015 15 09 9 1

28 28 01 1 024 24 024 24 027 27 1

48 48 042 42 026 26 030 30 033 33 05 5 012 12 042 42 034 34 0

34 34 031 31 042 42 024 24 041 41 028 28 029 29 018 18 012 12 04 4 037 37 023 23 01 1 021 21 017 17 014 14 041 41 017 17 028 28 036 36 027 27 014 14 049 49 01 1 027 27 042 42 033 33 042 42 1

10 10 039 39 028 28 037 37 013 13 017 17 010 10 011 11 012 12 037 37 024 24 031 31 017 17 1

32 32 023 23 08 8 026 26 027 27 018 18 016 16 010 10 023 23 028 28 09 9 026 26 028 28 045 45 031 31 0



36 36 021 21 040 40 041 41 019 19 011 11 08 8 048 48 1

35 35 011 11 015 15 034 34 024 24 044 44 04 4 023 23 04 4 040 40 046 46 025 25 04 4 047 47 032 32 03 3 019 19 020 20 011 11 038 38 07 7 08 8 013 13 06 6 06 6 040 40 00 0 07 7 032 32 03 3 041 41 011 11 024 24 020 20 013 13 034 34 019 19 015 15 047 47 049 49 042 42 021 21 05 5 1

0 0 032 32 04 4 043 43 012 12 0

2 2 032 32 034 34 047 47 031 31 024 24 049 49 049 49 019 19 05 5 039 39 049 49 1

3 3 040 40 028 28 021 21 027 27 027 27 028 28 021 21 032 32 01 1 016 16 06 6 02 2 038 38 013 13 023 23 038 38 014 14 015 15 043 43 026 26 036 36 020 20 045 45 1

16 16 040 40 015 15 035 35 010 10 018 18 029 29 033 33 01 1 038 38 010 10 029 29 1

18 18 017 17 022 22 047 47 016 16 034 34 047 47 0

31 31 039 39 034 34 00 0 04 4 03 3 019 19 041 41 07 7 048 48 010 10 045 45 029 29 012 12 024 24 048 48 1

32 32 023 23 03 3 040 40 019 19 029 29 027 27 02 2 018 18 016 16 019 19 041 41 05 5 08 8 025 25 022 22 06 6 019 19 034 34 014 14 033 33 05 5 027 27 039 39 02 2 036 36 07 7 043 43 041 41 024 24 021 21 048 48 019 19 09 9 015 15 042 42 047 47 046 46 04 4 022 22 030 30 0

4 4 025 25 048 48 037 37 08 8 015 15 024 24 1

31 31 040 40 029 29 07 7 025 25 06 6 029 29 029 29 010 10 020 20 010 10 09 9 028 28 041 41 042 42 032 32 023 23 024 24 036 36 03 3 036 36 026 26 039 39 1

48 48 027 27 025 25 043 43 015 15 039 39 08 8 06 6 029 29 029 29 09 9 1

48 48 039 39 028 28 06 6 09 9 03 3 044 44 010 10 044 44 05 5 043 43 05 5 1

48 48 0

40 40 02 2 011 11 030 30 010 10 042 42 015 15 040 40 023 23 038 38 039 39 00 0 1

22 22 02 2 01 1 024 24 010 10 023 23 019 19 05 5 046 46 013 13 032 32 039 39 043 43 021 21 033 33 04 4 048 48 038 38 014 14 06 6 044 44 023 23 015 15 037 37 032 32 07 7 025 25 014 14 032 32 046 46 022 22 048 48 012 12 019 19 019 19 038 38 1



Result17 (17), 17 (17), 21 (21), 23 (23), 24 (24), 30 (30), 33 (33), 38 (38), 39 (39), 44 (44), PASS!All PASSed until now!

29 (29), 34 (34), 36 (36), 36 (36), 38 (38), 38 (38), 41 (41), 43 (43), 45 (45), 45 (45), PASS!All PASSed until now!


0 (0), 14 (14), 15 (15), 21 (21), 27 (27), 36 (36), 38 (38), 47 (47), PASS!All PASSed until now!

23 (23), 24 (24), 28 (28), PASS!All PASSed until now!




39 (39), 40 (40), 40 (40), 41 (41), 42 (42), 43 (43), 43 (43), 43 (43), 45 (45), 49 (49), PASS!

All PASSed until now!


1 (1), 24 (24), 24 (24), 27 (27), 28 (28), PASS!All PASSed until now!







10 (10), 15 (15), 16 (16), 18 (18), 29 (29), 29 (29),

33 (33), 35 (35), 38 (38), 40 (40), PASS!All PASSed until now!










APPENDIX B-4: STAGE 3 - TEST 2



Input data4757 4757 023221 23221 035781 35781 058969 58969 034569 34569 063079 63079 038049 38049 02745 2745 038359 38359 041425 41425 018169 18169 048799 48799 07793 7793 040355 40355 028249 28249 014059 14059 061747 61747 032723 32723 020959 20959 028929 28929 045725 45725 0633 633 038459 38459 063837 63837 047633 47633 059423 59423 018213 18213 033711 33711 09209 9209 052633 52633 083 83 060525 60525 053141 53141 016745 16745 044533 44533 048111 48111 032803 32803 063623 63623 056489 56489 049929 49929 055709 55709 030917 30917 04339 4339 059679 59679 028915 28915 04255 4255 07737 7737 050111 50111 042941 42941 029851 29851 062775 62775 04025 4025 035705 35705 055831 55831 057849 57849 041907 41907 028735 28735 0

59307 59307 045395 45395 062535 62535 032507 32507 021241 21241 046551 46551 049563 49563 061223 61223 033805 33805 09297 9297 01651 1651 09211 9211 05677 5677 049083 49083 049359 49359 025905 25905 036405 36405 019635 19635 044029 44029 027441 27441 07789 7789 050303 50303 033845 33845 030417 30417 053225 53225 049011 49011 060343 60343 011403 11403 059729 59729 03833 3833 035155 35155 060209 60209 060233 60233 065283 65283 030867 30867 054833 54833 064067 64067 014075 14075 041795 41795 019257 19257 03537 3537 045641 45641 07319 7319 064387 64387 048519 48519 051269 51269 05561 5561 024705 24705 0847 847 048045 48045 033763 33763 050201 50201 052029 52029 051611 51611 04091 4091 037981 37981 043245 43245 012291 12291 0

26539 26539 015043 15043 035415 35415 09133 9133 034801 34801 011995 11995 049195 49195 011681 11681 06465 6465 031879 31879 013221 13221 1

63627 63627 028283 28283 032229 32229 055607 55607 01283 1283 040855 40855 024263 24263 021667 21667 040151 40151 024375 24375 010299 10299 016479 16479 040527 40527 062415 62415 038479 38479 039093 39093 013597 13597 052997 52997 042095 42095 028313 28313 065059 65059 054025 54025 058335 58335 018631 18631 044713 44713 038239 38239 049589 49589 032331 32331 063245 63245 063303 63303 013387 13387 041641 41641 055557 55557 060301 60301 051259 51259 039789 39789 010575 10575 049635 49635 034009 34009 030531 30531 029937 29937 053175 53175 040999 40999 040593 40593 0485 485 052877 52877 0

31311 31311 030097 30097 09059 9059 051159 51159 055447 55447 02021 2021 039299 39299 058957 58957 055267 55267 054701 54701 013451 13451 01221 1221 036511 36511 023081 23081 029589 29589 021125 21125 054855 54855 025541 25541 022227 22227 058665 58665 013393 13393 054713 54713 07485 7485 036845 36845 023207 23207 060191 60191 09687 9687 055437 55437 014253 14253 037767 37767 044121 44121 024983 24983 03493 3493 0281 281 039283 39283 041547 41547 035253 35253 031 31 07805 7805 017387 17387 021081 21081 012331 12331 021683 21683 064663 64663 01373 1373 046755 46755 038897 38897 016295 16295 07509 7509 033507 33507 054499 54499 039807 39807 046739 46739 048079 48079 033469 33469 07399 7399 043939 43939 028393 28393 0



32893 32893 036841 36841 0317 317 06387 6387 036251 36251 063005 63005 06595 6595 08187 8187 038463 38463 02703 2703 043065 43065 055035 55035 035581 35581 011021 11021 055987 55987 08943 8943 064531 64531 032519 32519 046171 46171 022891 22891 012307 12307 046045 46045 03809 3809 028853 28853 060965 60965 09919 9919 015219 15219 06493 6493 046013 46013 054273 54273 047929 47929 1

34855 34855 026061 26061 043501 43501 029309 29309 022009 22009 027447 27447 08427 8427 05543 5543 08987 8987 048067 48067 043219 43219 046199 46199 043851 43851 05853 5853 014529 14529 031351 31351 021847 21847 01083 1083 044489 44489 023043 23043 037083 37083 052027 52027 060283 60283 028497 28497 022391 22391 034745 34745 0

35795 35795 032021 32021 035205 35205 046179 46179 038585 38585 039573 39573 024149 24149 0665 665 014577 14577 043835 43835 040927 40927 055229 55229 062103 62103 047031 47031 059905 59905 018447 18447 013589 13589 049299 49299 042293 42293 059145 59145 059555 59555 08775 8775 062659 62659 017707 17707 053553 53553 08921 8921 020615 20615 029535 29535 019179 19179 049389 49389 0539 539 025549 25549 022057 22057 023649 23649 015763 15763 032817 32817 027373 27373 020583 20583 03517 3517 019893 19893 03033 3033 05911 5911 052175 52175 030281 30281 037029 37029 03723 3723 023199 23199 03961 3961 08217 8217 030587 30587 056675 56675 030407 30407 1

61783 61783 059505 59505 028309 28309 01615 1615 018457 18457 0

64851 64851 012881 12881 061601 61601 049575 49575 043209 43209 020903 20903 045291 45291 028299 28299 032951 32951 059893 59893 042535 42535 010981 10981 062333 62333 048317 48317 058213 58213 032871 32871 03739 3739 03677 3677 05171 5171 044997 44997 05821 5821 047171 47171 020071 20071 055737 55737 035165 35165 09901 9901 010623 10623 049009 49009 040913 40913 031191 31191 062327 62327 04745 4745 060395 60395 033471 33471 023325 23325 052361 52361 09747 9747 054097 54097 026609 26609 034259 34259 050389 50389 039463 39463 06005 6005 017447 17447 030205 30205 033217 33217 030729 30729 047245 47245 04409 4409 019251 19251 039239 39239 025821 25821 07199 7199 023661 23661 010703 10703 041127 41127 030675 30675 063973 63973 0

6827 6827 062901 62901 020509 20509 025559 25559 08229 8229 052227 52227 058361 58361 1

48171 48171 060495 60495 05131 5131 054785 54785 064151 64151 050013 50013 038073 38073 019557 19557 09867 9867 013235 13235 029091 29091 013823 13823 042087 42087 057479 57479 013347 13347 015979 15979 019211 19211 01621 1621 03805 3805 010095 10095 052301 52301 034307 34307 059127 59127 050639 50639 011507 11507 035177 35177 047315 47315 062371 62371 050217 50217 055667 55667 036937 36937 020529 20529 047743 47743 032183 32183 052315 52315 09539 9539 032855 32855 048523 48523 058989 58989 018947 18947 013285 13285 06819 6819 029951 29951 023375 23375 028325 28325 023837 23837 041447 41447 08595 8595 029267 29267 018727 18727 0



52227 52227 031775 31775 011617 11617 05647 5647 035959 35959 043525 43525 03823 3823 016089 16089 055139 55139 018535 18535 08777 8777 050269 50269 028695 28695 056919 56919 027095 27095 030943 30943 026835 26835 020013 20013 061849 61849 027937 27937 058871 58871 01117 1117 037153 37153 05887 5887 056511 56511 015315 15315 054531 54531 018823 18823 01405 1405 012227 12227 02009 2009 038545 38545 047435 47435 037647 37647 053937 53937 012759 12759 062279 62279 09489 9489 027911 27911 060811 60811 011601 11601 048119 48119 054337 54337 026737 26737 020529 20529 040095 40095 0679 679 01399 1399 028517 28517 030703 30703 040401 40401 050379 50379 034889 34889 058789 58789 05295 5295 038519 38519 064725 64725 046265 46265 0

42225 42225 015987 15987 0469 469 059695 59695 016397 16397 025157 25157 047267 47267 049007 49007 051115 51115 055311 55311 011351 11351 036129 36129 039335 39335 053043 53043 060043 60043 055169 55169 058241 58241 060001 60001 028549 28549 030521 30521 046427 46427 058159 58159 1

29713 29713 050099 50099 017333 17333 052917 52917 016391 16391 042565 42565 045779 45779 061433 61433 059181 59181 031335 31335 05777 5777 025763 25763 027917 27917 016769 16769 038081 38081 039687 39687 044123 44123 026645 26645 060355 60355 044943 44943 026019 26019 06687 6687 011261 11261 062683 62683 033157 33157 034023 34023 037081 37081 058707 58707 015979 15979 024153 24153 061745 61745 038463 38463 033223 33223 035297 35297 048981 48981 0

17505 17505 01219 1219 012993 12993 04221 4221 04623 4623 038013 38013 013283 13283 041915 41915 036549 36549 07613 7613 09535 9535 024699 24699 08257 8257 048179 48179 059041 59041 017531 17531 058655 58655 034087 34087 017 17 014655 14655 010471 10471 017843 17843 044965 44965 051463 51463 0429 429 060547 60547 064725 64725 011087 11087 012071 12071 055037 55037 043351 43351 041153 41153 054081 54081 047627 47627 022391 22391 038575 38575 07229 7229 024135 24135 048625 48625 035337 35337 030789 30789 059319 59319 016707 16707 08665 8665 027267 27267 057603 57603 1

64729 64729 032815 32815 048755 48755 046167 46167 056663 56663 046119 46119 062053 62053 052547 52547 08493 8493 047883 47883 061293 61293 0

58563 58563 02589 2589 043765 43765 027591 27591 016711 16711 053711 53711 019819 19819 017263 17263 027481 27481 065265 65265 043667 43667 052999 52999 063375 63375 062405 62405 04085 4085 053275 53275 063497 63497 052803 52803 051881 51881 051985 51985 03431 3431 012713 12713 019731 19731 09835 9835 036669 36669 04505 4505 063513 63513 059307 59307 050197 50197 05805 5805 016349 16349 026027 26027 041177 41177 046225 46225 025591 25591 051313 51313 02009 2009 035229 35229 029481 29481 044681 44681 065335 65335 08165 8165 053909 53909 053209 53209 055015 55015 042971 42971 0127 127 062977 62977 046629 46629 050271 50271 051835 51835 08751 8751 034925 34925 097 97 044839 44839 014449 14449 049647 49647 01515 1515 0



41831 41831 02199 2199 062353 62353 011971 11971 062235 62235 03205 3205 042583 42583 034435 34435 030035 30035 046095 46095 030319 30319 054827 54827 052239 52239 038473 38473 058775 58775 053567 53567 059247 59247 024681 24681 056609 56609 064603 64603 033903 33903 055835 55835 022369 22369 025935 25935 057119 57119 055125 55125 010417 10417 050353 50353 020573 20573 028599 28599 024541 24541 08441 8441 03847 3847 021335 21335 013861 13861 035613 35613 052407 52407 038187 38187 01709 1709 03229 3229 026107 26107 049867 49867 017789 17789 024361 24361 024079 24079 041441 41441 060909 60909 034223 34223 024077 24077 027367 27367 024749 24749 057081 57081 028593 28593 055705 55705 010541 10541 051649 51649 011143 11143 060087 60087 0

41635 41635 029257 29257 037539 37539 040811 40811 062583 62583 057719 57719 052195 52195 040479 40479 024131 24131 058731 58731 031903 31903 02251 2251 019275 19275 060305 60305 062685 62685 024795 24795 09583 9583 025671 25671 059159 59159 053375 53375 1

47721 47721 031175 31175 03475 3475 036657 36657 038939 38939 09591 9591 04435 4435 026811 26811 012115 12115 03709 3709 04645 4645 021467 21467 03653 3653 021513 21513 031259 31259 02291 2291 033197 33197 061801 61801 012063 12063 056799 56799 044627 44627 09753 9753 013621 13621 059335 59335 051711 51711 018275 18275 015397 15397 025207 25207 060401 60401 04977 4977 020673 20673 013627 13627 027861 27861 07649 7649 027025 27025 060725 60725 020031 20031 0

28139 28139 01815 1815 01327 1327 041383 41383 058861 58861 040825 40825 054015 54015 026329 26329 035971 35971 03525 3525 062037 62037 055791 55791 020263 20263 048295 48295 034073 34073 043215 43215 022085 22085 050327 50327 08509 8509 02073 2073 033485 33485 046495 46495 050201 50201 08107 8107 011607 11607 017545 17545 041799 41799 050827 50827 048817 48817 037789 37789 013043 13043 01645 1645 014843 14843 1

37165 37165 038243 38243 014207 14207 065507 65507 038901 38901 011549 11549 021717 21717 051277 51277 018303 18303 055049 55049 031825 31825 01825 1825 026139 26139 023417 23417 06677 6677 019919 19919 042705 42705 024409 24409 030225 30225 024901 24901 033521 33521 023003 23003 025435 25435 045675 45675 0

5421 5421 011703 11703 036101 36101 058899 58899 036397 36397 07645 7645 047225 47225 058495 58495 023215 23215 021943 21943 054603 54603 026699 26699 037655 37655 048341 48341 012949 12949 034025 34025 052367 52367 020013 20013 045525 45525 07329 7329 058261 58261 043725 43725 020275 20275 048635 48635 055323 55323 08221 8221 055151 55151 057537 57537 021277 21277 055691 55691 09003 9003 064123 64123 060859 60859 030153 30153 044993 44993 025173 25173 053703 53703 046983 46983 060843 60843 031917 31917 052203 52203 035239 35239 07239 7239 09721 9721 026427 26427 03831 3831 02879 2879 054601 54601 010821 10821 062823 62823 039253 39253 028225 28225 036283 36283 050375 50375 018629 18629 014981 14981 050295 50295 024819 24819 0



49431 49431 0701 701 060707 60707 030617 30617 038521 38521 048903 48903 050503 50503 04457 4457 011923 11923 055025 55025 030181 30181 065229 65229 06889 6889 026865 26865 037267 37267 022561 22561 049317 49317 037211 37211 056333 56333 051569 51569 042495 42495 010461 10461 062291 62291 057771 57771 015619 15619 062067 62067 029245 29245 07509 7509 033787 33787 045279 45279 042133 42133 058573 58573 021305 21305 07077 7077 025775 25775 013819 13819 045175 45175 011135 11135 014977 14977 012681 12681 065451 65451 046679 46679 021559 21559 017311 17311 026977 26977 053949 53949 028757 28757 08213 8213 020117 20117 064229 64229 020801 20801 018997 18997 08709 8709 026389 26389 053863 53863 024547 24547 032527 32527 038823 38823 1

42531 42531 059607 59607 058859 58859 042617 42617 040511 40511 057953 57953 057709 57709 014525 14525 014151 14151 055011 55011 057535 57535 021071 21071 07593 7593 052079 52079 032079 32079 05107 5107 03989 3989 04039 4039 038469 38469 054121 54121 064337 64337 063955 63955 045721 45721 012193 12193 043787 43787 057503 57503 027819 27819 012411 12411 022079 22079 052935 52935 065373 65373 043509 43509 061567 61567 058495 58495 036015 36015 039663 39663 036309 36309 057597 57597 013775 13775 048985 48985 046233 46233 052087 52087 040113 40113 03563 3563 062667 62667 013213 13213 059185 59185 022889 22889 040161 40161 0395 395 056225 56225 052555 52555 058417 58417 019785 19785 012005 12005 032255 32255 025269 25269 0

13755 13755 039947 39947 050337 50337 011889 11889 012061 12061 056673 56673 040493 40493 030279 30279 049401 49401 07953 7953 050747 50747 062029 62029 011175 11175 0819 819 050487 50487 0421 421 060727 60727 053101 53101 043545 43545 052699 52699 040437 40437 056323 56323 042909 42909 019379 19379 07257 7257 056435 56435 019707 19707 029069 29069 032901 32901 06541 6541 037401 37401 031535 31535 053053 53053 013581 13581 028497 28497 037675 37675 058453 58453 036523 36523 014491 14491 047533 47533 036023 36023 058047 58047 029769 29769 016599 16599 018387 18387 014923 14923 025927 25927 046745 46745 043159 43159 050337 50337 0199 199 037897 37897 052713 52713 045683 45683 034689 34689 035387 35387 060065 60065 043625 43625 0

31333 31333 050323 50323 021755 21755 061249 61249 08925 8925 063659 63659 05523 5523 053087 53087 026233 26233 039837 39837 028129 28129 030189 30189 07727 7727 05345 5345 020005 20005 046439 46439 043277 43277 018085 18085 013037 13037 058309 58309 062075 62075 017321 17321 025091 25091 024573 24573 041957 41957 1



Result11995 (11995), 12291 (12291), 13221 (13221), 14059 (14059), 14075 (14075), 15043 (15043), 16745 (16745), 18169 (18169), 18213 (18213), 19257 (19257), 19635 (19635), 20959 (20959), 21241 (21241), 23221 (23221), 24705 (24705), 25905 (25905), 26539 (26539), 27441 (27441), 28249 (28249), 28735 (28735), 28915 (28915), 28929 (28929), 29851 (29851), 30417 (30417), 30867 (30867), 30917 (30917), 31879 (31879), 32507 (32507), 32723 (32723), 32803 (32803), 33711 (33711), 33763 (33763), 33805 (33805), 33845 (33845), 34569 (34569), 34801 (34801), 35155 (35155), 35415 (35415), 35705 (35705), 35781 (35781), 36405 (36405), 37981 (37981), 38049 (38049), 38359 (38359), 38459 (38459), 40355 (40355), 41425 (41425), 41795 (41795), 41907 (41907), 42941 (42941), 43245 (43245), 44029 (44029), 44533 (44533), 45395 (45395), 45641 (45641), 45725 (45725), 46551 (46551), 47633 (47633), 48045 (48045), 48111 (48111), 48519 (48519), 48799 (48799), 49011 (49011), 49083 (49083), 49195 (49195), 49359 (49359), 49563 (49563), 49929 (49929), 50111 (50111), 50201 (50201), 50303 (50303), 51269 (51269), 51611 (51611), 52029 (52029), 52633 (52633), 53141 (53141), 53225 (53225), 54833 (54833), 55709 (55709), 55831 (55831), 56489 (56489), 57849 (57849), 58969 (58969), 59307 (59307), 59423 (59423), 59679

(59679), 59729 (59729), 60209 (60209), 60233 (60233), 60343 (60343), 60525 (60525), 61223 (61223), 61747 (61747), 62535 (62535), 62775 (62775), 63079 (63079), 63623 (63623), 63837 (63837), 64067 (64067), 64387 (64387), 65283 (65283), PASS!All PASSed until now!

16295 (16295), 16479 (16479), 17387 (17387), 18631 (18631), 21081 (21081), 21125 (21125), 21667 (21667), 21683 (21683), 22227 (22227), 22891 (22891), 23081 (23081), 23207 (23207), 24263 (24263), 24375 (24375), 24983 (24983), 25541 (25541), 28283 (28283), 28313 (28313), 28393 (28393), 28853 (28853), 29589 (29589), 29937 (29937), 30097 (30097), 30531 (30531), 31311 (31311), 32229 (32229), 32331 (32331), 32519 (32519), 32893 (32893), 33469 (33469), 33507 (33507), 34009 (34009), 35253 (35253), 35581 (35581), 36251 (36251), 36511 (36511), 36841 (36841), 36845 (36845), 37767 (37767), 38239 (38239), 38463 (38463), 38479 (38479), 38897 (38897), 39093 (39093), 39283 (39283), 39299 (39299), 39789 (39789), 39807 (39807), 40151 (40151), 40527 (40527), 40593 (40593), 40855 (40855), 40999 (40999), 41547 (41547), 41641 (41641), 42095 (42095), 43065 (43065), 43939 (43939), 44121 (44121), 44713 (44713), 46013 (46013), 46045 (46045), 46171 (46171), 46739 (46739), 46755 (46755), 47929 (47929),

48079 (48079), 49589 (49589), 49635 (49635), 51159 (51159), 51259 (51259), 52877 (52877), 52997 (52997), 53175 (53175), 54025 (54025), 54273 (54273), 54499 (54499), 54701 (54701), 54713 (54713), 54855 (54855), 55035 (55035), 55267 (55267), 55437 (55437), 55447 (55447), 55557 (55557), 55607 (55607), 55987 (55987), 58335 (58335), 58665 (58665), 58957 (58957), 60191 (60191), 60301 (60301), 60965 (60965), 62415 (62415), 63005 (63005), 63245 (63245), 63303 (63303), 63627 (63627), 64531 (64531), 64663 (64663), 65059 (65059), PASS!All PASSed until now!

539 (539), 665 (665), 1083 (1083), 3033 (3033), 3517 (3517), 3723 (3723), 3961 (3961), 5543 (5543), 5853 (5853), 5911 (5911), 8217 (8217), 8427 (8427), 8775 (8775), 8921 (8921), 8987 (8987), 13589 (13589), 14529 (14529), 14577 (14577), 15763 (15763), 17707 (17707), 18447 (18447), 19179 (19179), 19893 (19893), 20583 (20583), 20615 (20615), 21847 (21847), 22009 (22009), 22057 (22057), 22391 (22391), 23043 (23043), 23199 (23199), 23649 (23649), 24149 (24149), 25549 (25549), 26061 (26061), 27373 (27373), 27447 (27447), 28497 (28497), 29309 (29309), 29535 (29535), 30281 (30281), 30407 (30407), 30587 (30587), 31351 (31351), 32021 (32021), 32817 (32817), 34745 (34745), 34855 (34855), 35205 (35205), 35795 (35795),



37029 (37029), 37083 (37083), 38585 (38585), 39573 (39573), 40927 (40927), 42293 (42293), 43219 (43219), 43501 (43501), 43835 (43835), 43851 (43851), 44489 (44489), 46179 (46179), 46199 (46199), 47031 (47031), 48067 (48067), 49299 (49299), 49389 (49389), 52027 (52027), 52175 (52175), 53553 (53553), 55229 (55229), 56675 (56675), 59145 (59145), 59555 (59555), 59905 (59905), 60283 (60283), 62103 (62103), 62659 (62659), PASS!All PASSed until now!

1615 (1615), 3677 (3677), 3739 (3739), 4409 (4409), 4745 (4745), 5171 (5171), 5821 (5821), 6005 (6005), 6827 (6827), 7199 (7199), 8229 (8229), 9747 (9747), 9901 (9901), 10623 (10623), 10703 (10703), 10981 (10981), 12881 (12881), 17447 (17447), 18457 (18457), 19251 (19251), 20071 (20071), 20509 (20509), 20903 (20903), 23325 (23325), 23661 (23661), 25559 (25559), 25821 (25821), 26609 (26609), 28299 (28299), 28309 (28309), 30205 (30205), 30675 (30675), 30729 (30729), 31191 (31191), 32871 (32871), 32951 (32951), 33217 (33217), 33471 (33471), 34259 (34259), 35165 (35165), 39239 (39239), 39463 (39463), 40913 (40913), 41127 (41127), 42535 (42535), 43209 (43209), 44997 (44997), 45291 (45291), 47171 (47171), 47245 (47245), 48317 (48317), 49009 (49009), 49575 (49575), 50389 (50389), 52227 (52227), 52361 (52361), 54097 (54097),

55737 (55737), 58213 (58213), 58361 (58361), 59505 (59505), 59893 (59893), 60395 (60395), 61601 (61601), 61783 (61783), 62327 (62327), 62333 (62333), 62901 (62901), 63973 (63973), 64851 (64851), PASS!All PASSed until now!

13823 (13823), 15315 (15315), 15979 (15979), 15987 (15987), 16089 (16089), 16397 (16397), 18535 (18535), 18727 (18727), 18823 (18823), 18947 (18947), 19211 (19211), 19557 (19557), 20013 (20013), 20529 (20529), 20529 (20529), 23375 (23375), 23837 (23837), 25157 (25157), 26737 (26737), 26835 (26835), 27095 (27095), 27911 (27911), 27937 (27937), 28325 (28325), 28517 (28517), 28549 (28549), 28695 (28695), 29091 (29091), 29267 (29267), 29951 (29951), 30521 (30521), 30703 (30703), 30943 (30943), 31775 (31775), 32183 (32183), 32855 (32855), 34307 (34307), 34889 (34889), 35177 (35177), 35959 (35959), 36129 (36129), 36937 (36937), 37153 (37153), 37647 (37647), 38073 (38073), 38519 (38519), 38545 (38545), 39335 (39335), 40095 (40095), 40401 (40401), 41447 (41447), 42087 (42087), 42225 (42225), 43525 (43525), 46265 (46265), 46427 (46427), 47267 (47267), 47315 (47315), 47435 (47435), 47743 (47743), 48119 (48119), 48171 (48171), 48523 (48523), 49007 (49007), 50013 (50013), 50217 (50217), 50269 (50269), 50379 (50379), 50639 (50639),

51115 (51115), 52227 (52227), 52301 (52301), 52315 (52315), 53043 (53043), 53937 (53937), 54337 (54337), 54531 (54531), 54785 (54785), 55139 (55139), 55169 (55169), 55311 (55311), 55667 (55667), 56511 (56511), 56919 (56919), 57479 (57479), 58159 (58159), 58241 (58241), 58789 (58789), 58871 (58871), 58989 (58989), 59127 (59127), 59695 (59695), 60001 (60001), 60043 (60043), 60495 (60495), 60811 (60811), 61849 (61849), 62279 (62279), 62371 (62371), 64151 (64151), 64725 (64725), PASS!All PASSed until now!

17 (17), 429 (429), 1219 (1219), 4221 (4221), 4623 (4623), 5777 (5777), 6687 (6687), 7229 (7229), 7613 (7613), 8257 (8257), 8665 (8665), 9535 (9535), 10471 (10471), 11087 (11087), 11261 (11261), 12071 (12071), 12993 (12993), 13283 (13283), 14655 (14655), 15979 (15979), 16391 (16391), 16707 (16707), 16769 (16769), 17333 (17333), 17505 (17505), 17531 (17531), 17843 (17843), 22391 (22391), 24135 (24135), 24153 (24153), 24699 (24699), 25763 (25763), 26019 (26019), 26645 (26645), 27267 (27267), 27917 (27917), 29713 (29713), 30789 (30789), 31335 (31335), 33157 (33157), 33223 (33223), 34023 (34023), 34087 (34087), 35297 (35297), 35337 (35337), 36549 (36549), 37081 (37081), 38013 (38013), 38081 (38081), 38463 (38463), 38575 (38575), 39687 (39687), 41153



(41153), 41915 (41915), 42565 (42565), 43351 (43351), 44123 (44123), 44943 (44943), 44965 (44965), 45779 (45779), 47627 (47627), 48179 (48179), 48625 (48625), 48981 (48981), 50099 (50099), 51463 (51463), 52917 (52917), 54081 (54081), 55037 (55037), 57603 (57603), 58655 (58655), 58707 (58707), 59041 (59041), 59181 (59181), 59319 (59319), 60355 (60355), 60547 (60547), 61433 (61433), 61745 (61745), 62683 (62683), 64725 (64725), PASS!All PASSed until now!

25591 (25591), 25671 (25671), 25935 (25935), 26027 (26027), 26107 (26107), 27367 (27367), 27481 (27481), 27591 (27591), 28593 (28593), 28599 (28599), 29257 (29257), 29481 (29481), 30035 (30035), 30319 (30319), 31903 (31903), 32815 (32815), 33903 (33903), 34223 (34223), 34435 (34435), 34925 (34925), 35229 (35229), 35613 (35613), 36669 (36669), 37539 (37539), 38187 (38187), 38473 (38473), 40479 (40479), 40811 (40811), 41177 (41177), 41441 (41441), 41635 (41635), 41831 (41831), 42583 (42583), 42971 (42971), 43667 (43667), 43765 (43765), 44681 (44681), 44839 (44839), 46095 (46095), 46119 (46119), 46167 (46167), 46225 (46225), 46629 (46629), 47883 (47883), 48755 (48755), 49647 (49647), 49867 (49867), 50197 (50197), 50271 (50271), 50353 (50353), 51313 (51313), 51649 (51649), 51835 (51835), 51881 (51881),

51985 (51985), 52195 (52195), 52239 (52239), 52407 (52407), 52547 (52547), 52803 (52803), 52999 (52999), 53209 (53209), 53275 (53275), 53375 (53375), 53567 (53567), 53711 (53711), 53909 (53909), 54827 (54827), 55015 (55015), 55125 (55125), 55705 (55705), 55835 (55835), 56609 (56609), 56663 (56663), 57081 (57081), 57119 (57119), 57719 (57719), 58563 (58563), 58731 (58731), 58775 (58775), 59159 (59159), 59247 (59247), 59307 (59307), 60087 (60087), 60305 (60305), 60909 (60909), 61293 (61293), 62053 (62053), 62235 (62235), 62353 (62353), 62405 (62405), 62583 (62583), 62685 (62685), 62977 (62977), 63375 (63375), 63497 (63497), 63513 (63513), 64603 (64603), 64729 (64729), 65265 (65265), 65335 (65335), PASS!All PASSed until now!

1327 (1327), 1645 (1645), 1815 (1815), 2073 (2073), 2291 (2291), 3475 (3475), 3525 (3525), 3653 (3653), 3709 (3709), 4435 (4435), 4645 (4645), 4977 (4977), 7649 (7649), 8107 (8107), 8509 (8509), 9591 (9591), 9753 (9753), 11607 (11607), 12063 (12063), 12115 (12115), 13043 (13043), 13621 (13621), 13627 (13627), 14843 (14843), 15397 (15397), 17545 (17545), 18275 (18275), 20031 (20031), 20263 (20263), 20673 (20673), 21467 (21467), 21513 (21513), 22085 (22085), 25207 (25207), 26329 (26329), 26811 (26811), 27025 (27025), 27861 (27861), 28139

(28139), 31175 (31175), 31259 (31259), 33197 (33197), 33485 (33485), 34073 (34073), 35971 (35971), 36657 (36657), 37789 (37789), 38939 (38939), 40825 (40825), 41383 (41383), 41799 (41799), 43215 (43215), 44627 (44627), 46495 (46495), 47721 (47721), 48295 (48295), 48817 (48817), 50201 (50201), 50327 (50327), 50827 (50827), 51711 (51711), 54015 (54015), 55791 (55791), 56799 (56799), 58861 (58861), 59335 (59335), 60401 (60401), 60725 (60725), 61801 (61801), 62037 (62037), PASS!All PASSed until now!

20801 (20801), 21277 (21277), 21305 (21305), 21559 (21559), 21717 (21717), 21943 (21943), 22561 (22561), 23003 (23003), 23215 (23215), 23417 (23417), 24409 (24409), 24547 (24547), 24819 (24819), 24901 (24901), 25173 (25173), 25435 (25435), 25775 (25775), 26139 (26139), 26389 (26389), 26427 (26427), 26699 (26699), 26865 (26865), 26977 (26977), 28225 (28225), 28757 (28757), 29245 (29245), 30153 (30153), 30181 (30181), 30225 (30225), 30617 (30617), 31825 (31825), 31917 (31917), 32527 (32527), 33521 (33521), 33787 (33787), 34025 (34025), 35239 (35239), 36101 (36101), 36283 (36283), 36397 (36397), 37165 (37165), 37211 (37211), 37267 (37267), 37655 (37655), 38243 (38243), 38521 (38521), 38823 (38823), 38901 (38901), 39253 (39253), 42133 (42133), 42495 (42495),



42705 (42705), 43725 (43725), 44993 (44993), 45175 (45175), 45279 (45279), 45525 (45525), 45675 (45675), 46679 (46679), 46983 (46983), 47225 (47225), 48341 (48341), 48635 (48635), 48903 (48903), 49317 (49317), 49431 (49431), 50295 (50295), 50375 (50375), 50503 (50503), 51277 (51277), 51569 (51569), 52203 (52203), 52367 (52367), 53703 (53703), 53863 (53863), 53949 (53949), 54601 (54601), 54603 (54603), 55025 (55025), 55049 (55049), 55151 (55151), 55323 (55323), 55691 (55691), 56333 (56333), 57537 (57537), 57771 (57771), 58261 (58261), 58495 (58495), 58573 (58573), 58899 (58899), 60707 (60707), 60843 (60843), 60859 (60859), 62067 (62067), 62291 (62291), 62823 (62823), 64123 (64123), 64229 (64229), 65229 (65229), 65451 (65451), 65507 (65507), PASS!All PASSed until now!

21071 (21071), 21755 (21755), 22079 (22079), 22889 (22889), 24573 (24573), 25091 (25091), 25269 (25269), 25927 (25927), 26233 (26233), 27819 (27819), 28129 (28129), 28497 (28497), 29069 (29069), 29769 (29769), 30189 (30189), 30279 (30279), 31333 (31333), 31535 (31535), 32079 (32079), 32255 (32255), 32901 (32901), 34689 (34689), 35387 (35387), 36015 (36015), 36023 (36023), 36309 (36309), 36523 (36523), 37401 (37401), 37675 (37675), 37897 (37897), 38469 (38469), 39663

(39663), 39837 (39837), 39947 (39947), 40113 (40113), 40161 (40161), 40437 (40437), 40493 (40493), 40511 (40511), 41957 (41957), 42531 (42531), 42617 (42617), 42909 (42909), 43159 (43159), 43277 (43277), 43509 (43509), 43545 (43545), 43625 (43625), 43787 (43787), 45683 (45683), 45721 (45721), 46233 (46233), 46439 (46439), 46745 (46745), 47533 (47533), 48985 (48985), 49401 (49401), 50323 (50323), 50337 (50337), 50337 (50337), 50487 (50487), 50747 (50747), 52079 (52079), 52087 (52087), 52555 (52555), 52699 (52699), 52713 (52713), 52935 (52935), 53053 (53053), 53087 (53087), 53101 (53101), 54121 (54121), 55011 (55011), 56225 (56225), 56323 (56323), 56435 (56435), 56673 (56673), 57503 (57503), 57535 (57535), 57597 (57597), 57709 (57709), 57953 (57953), 58047 (58047), 58309 (58309), 58417 (58417), 58453 (58453), 58495 (58495), 58859 (58859), 59185 (59185), 59607 (59607), 60065 (60065), 60727 (60727), 61249 (61249), 61567 (61567), 62029 (62029), 62075 (62075), 62667 (62667), 63659 (63659), 63955 (63955), 64337 (64337), 65373 (65373), PASS!




APPENDIX B-5: STAGE 3 - TEST 3Input Data100 100 00 0 065535 65535 0200 200 1

0 65535 0100 100 065535 0 1

Result0 (0), 100 (100), 200 (200), 65535 (65535), PASS!All PASSed until now!

0 (65535), 100 (100), 65535 (0), PASS!



APPENDIX C •

SCHEMATICS

OPTIMIZED FOR

MINIMAL DATA

ARRIVAL TIME

Appendix C-1: SORTER_BOX (8,8)


APPENDIX C-1: SORTER_BOX (8,8)

Appendix C-2: SORTER (8,8,32)


APPENDIX C-2: SORTER (8,8,32)

Appendix C-2: SORTER (8,8,32)



APPENDIX D •

SCHEMATICS

OPTIMIZED FOR

MINIMAL AREA

Appendix D-1: SORTER_BOX (8,8)


APPENDIX D-1: SORTER_BOX (8,8)

Appendix D-2: SORTER (8,8,32)


APPENDIX D-2: SORTER (8,8,32)

vhdl implementation of insertion sort - ntnudam/fag/78076/dokumenter/vhdl_sort/prosjekt.pdf ·...

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