VHDL FILE

Submitted by:

Nitin Sonkusre(67/EC/08)

1. Introduction

VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language. In the mid-1980’s the U.S. Department of Defense and the IEEE sponsored the development of this hardware description language with the goal to develop very high-speed integrated circuit. It has become now one of industry’s standard languages used to describe digital systems. The other widely used hardware description language is Verilog. Both are powerful languages that allow you to describe and simulate complex digital systems. A third HDL language is ABEL (Advanced Boolean Equation Language) which was specifically designed for Programmable Logic Devices (PLD). ABEL is less powerful than the other two languages and is less popular in industry. This tutorial deals with VHDL, as described by the IEEE standard 1076-1993.

Although these languages look similar as conventional programming languages, there are some important differences. A hardware description language is inherently parallel, i.e. commands, which correspond to logic gates, are executed (computed) in parallel, as soon as a new input arrives. A HDL program mimics the behavior of a physical, usually digital, system. It also allows incorporation of timing specifications (gate delays) as well as to describe a system as an interconnection of different components.

VHDL allows one to describe a digital system at the structural or the behavioral level. The behavioral

level can be further divided into two kinds of styles: Data flow and Algorithmic. The dataflow

representation describes how data moves through the system. This is typically done in terms of data

flow between registers (Register Transfer level). The data flow model makes use of concurrent

statements that are executed in parallel as soon as data arrives at the input. On the other hand,

sequential statements are executed in the sequence that they are specified. VHDL allows both

concurrent and sequential signal assignments that will determine the manner in which they are

executed. Examples of both representations will be given later.

1.Design of six basic gates (And,or nand nor,xor,xnor) for one bit.

Entity declaration:

entity gates is

port(x,y: in bit;

oand,oor,onand,onor,oxor,oxnor:out bit);

end entity;

architecture arch_gates of gates is

begin

oand<=x and y;

oor<=x or y;

onand<=x nand y;

onor<=x nor y;

oxor<=x xor y;

oxnor<=x xnor y;

end arch_gates;

Testbench:

entity gates_tb is

end entity;

architecture arch_gates_tb of gates_tb is

component gates is

port(x,y: in bit;

oand,oor,onand,onor,oxor,oxnor:out bit);

end component;

signal in1,in2,oand,oor,onand,onor,oxor,oxnor:bit;

begin

inst:gates port map(in1,in2,oand,oor,onand,onor,oxor,oxnor);

process

begin

in1 <='0';in2 <='0';

wait for 100 ns;

in1 <='1';in2 <='1';

wait for 100 ns;

in1 <='1';in2 <='0';

wait for 100 ns;

in1 <='0';in2 <='1';

wait for 100 ns;

end process;

end arch_gates_tb;

OUTPUT:

2. Design of six basic gates (And,or nand nor,xor,xnor) for four bits.

Entity declaration:

entity gates4bit is

port(x,y: in bit_vector(3 downto 0);

oand,oor,onand,onor,oxor,oxnor:out bit_vector(3 downto 0));

end entity;

architecture arch_gates4bit of gates4bit is

begin

oand(0)<=x(0) and y(0); oand(1)<=x(1) and y(1);

oand(2)<=x(2) and y(2); oand(3)<=x(3) and y(3);

oor(0)<=x(0) or y(0); oor(1)<=x(1) or y(1);

oor(2)<=x(2) or y(2); oor(3)<=x(3) or y(3);

onand(0)<=x(0) nand y(0); onand(1)<=x(1) nand y(1);

onand(2)<=x(2) nand y(2); onand(3)<=x(3) nand y(3);

onor(0)<=x(0) nor y(0); onor(1)<=x(1) nor y(1);

onor(2)<=x(2) nor y(2); onor(3)<=x(3) nor y(3);

oxor(0)<=x(0) xor y(0); oxor(1)<=x(1) xor y(1);

oxor(2)<=x(2) xor y(2); oxor(3)<=x(3) xor y(3);

oxnor(0)<=x(0) xnor y(0); oxnor(1)<=x(1) xnor y(1);

oxnor(2)<=x(2) xnor y(2); oxnor(3)<=x(3) xnor y(3);

end arch_gates4bit;

Test bench:

entity gates4bit_tb is

end entity;

architecture arch_gates4bit_tb of gates4bit_tb is

component gates4bit is

port(x,y: in bit_vector(3 downto 0);

oand,oor,onand,onor,oxor,oxnor:out bit_vector(3 downto 0));

end component;

signal in1,in2,oand,or,onand,onor,oxor,oxnor:bit_vector(3 downto 0);

begin

inst:gates4bit port map(in1,in2,oand,oor,onand,onor,oxor,oxnor);

process

begin

in1 <="0000";in2 <="0000";

wait for 100 ns;

in1 <="0001";in2 <="0001";

wait for 100 ns;

in1 <="0010";in2 <="0010";

wait for 100 ns;

in1 <="0011";in2 <="0011";

wait for 100 ns;

in1 <="0100";in2 <="0100";

wait for 100 ns;

in1 <="0101";in2 <="0101";

wait for 100 ns;

in1 <="0110";in2 <="0110";

wait for 100 ns;

in1 <="0111";in2 <="0111";

wait for 100 ns;

in1 <="1000";in2 <="1000";

wait for 100 ns;

in1 <="1001";in2 <="1001";

wait for 100 ns;

end process;

end arch_gates4bit_tb;

OUTPUT:

3. Design of a half adder using basic gates for one bit

Entity declaration:

entity halfadder is

port(x,y:in bit;s,c:out bit);

end entity;

architecture arch_halfadder of halfadder is

begin

s<=x xor y;

c<=x and y;

end arch_halfadder;

Test bench:

entity ha_testbench is

end entity;

architecture arch_ha_testbench of ha_testbench is

component halfadder is

port(x,y:in bit;s,c:out bit);

end component;

signal in1,in2,sum,carry:bit;

begin

inst:halfadder port map(in1,in2,sum,carry);

process

begin

in1 <='0';in2 <='0';

wait for 100 ns;

in1 <='0';in2 <='1';

wait for 100 ns;

in1 <='1';I n2 <='0';

wait for 100 ns;

in1 <='1';in2 <='1';

wait for 100 ns;

end process;

end arch_ha_testbench;

OUTPUT:

4. Design of a Full Adder using a half adder for one bit

Entity Declaration :

entity fa is port(x,y,z: in bit; sf,cf: out bit); end entity; entity ta is port(p,q,r: in bit; st,ct: out bit); end entity; entity ha is port(a,b: in bit; sh,ch: out bit); end entity; architecture arch_ha of ha is begin sh<=a xor b; ch<=a and b; end arch_ha; architecture archi_ta of ta is begin st<=p xor r; ct<=(p and r) or q; end archi_ta;

Test bench :

entity fa_tb is end entity; entity ta_tb is end entity; entity ha_tb is end entity; architecture archit_fa_tb of fa_tb is component ha is port( a,b: in bit; sh,ch:out bit); end component; component ta is port(p,q,r: in bit; st,ct: out bit); end component; signal i1,i2,i3,sh,ch,sf,cf: bit; begin inst1: ha port map(i1,i2,sh,ch); inst2: ta port map(sh,ch,i3,sf,cf); process begin

i1<='0';i2<='0';i3<='0'; wait for 150 ns; i1<='0';i2<='0';i3<='1';

wait for 150 ns; i1<='0';i2<='1';i3<='0'; wait for 150 ns; i1<='0';i2<='1';i3<='1'; wait for 150 ns; i1<='1';i2<='0';i3<='0'; wait for 150 ns; i1<='1';i2<='0';i3<='1'; wait for 150 ns; i1<='1';i2<='1';i3<='0'; wait for 150 ns; i1<='1';i2<='1';i3<='1'; wait for 150 ns; i1<='0';i2<='1';i3<='1'; wait for 150 ns; end process; end archit_fa_tb;

OUTPUT:

5. Design of Full Subtractor using a half subtractor

Entity declaration:

entity fsub is port(x,y,z: in bit; df,cf: out bit); end entity; entity tsub is port(p,q,r: in bit; dt,ct: out bit); end entity; entity hsub is port(a,b: in bit; dh,ch: out bit); end entity; architecture arch_hsub of hsub is begin dh<=a xor (not b); ch<=a and (not b); end arch_hsub; architecture archi_tsub of tsub is begin dt<=p xor r; ct<=(p and r) or q; end archi_tsub;

Testbench:

entity fsub_tb is end entity;

entity tsub_tb is end entity;

entity hsub_tb is end entity;

architecture archit_fsub_tb of fsub_tb is component hsub is port( a,b: in bit; dh,ch:out bit); end component; component tsub is port(p,q,r: in bit; dt,ct: out bit);

end component; signal i1,i2,i3,dh,ch,df,cf: bit;

begin inst1:hsub port map(i1,i2,dh,ch); inst2:tsub port map(dh,ch,i3,df,cf);

process begin

i1<='0';i2<='0';i3<='0'; wait for 150 ns; i1<='0';i2<='0';i3<='1'; wait for 150 ns; i1<='0';i2<='1';i3<='0'; wait for 150 ns; i1<='0';i2<='1';i3<='1'; wait for 150 ns; i1<='1';i2<='0';i3<='0'; wait for 150 ns; i1<='1';i2<='0';i3<='1'; wait for 150 ns; i1<='1';i2<='1';i3<='0'; wait for 150 ns; i1<='1';i2<='1';i3<='1'; wait for 150 ns; i1<='0';i2<='1';i3<='1'; wait for 150 ns; end process; end archit_fsub_tb;

OUTPUT:

6. Design a 3x8 decoder.

Entity declaration:

entity decoder is

port (a,b,c:in BIT; o:out BIT_VECTOR(0 to 7)); end entity; architecture decoder_arch of decoder is begin process(a,b,c) variable abar,bbar,cbar:BIT; begin abar:= not a; bbar:= not b; cbar:= not c; o(0)<=abar and bbar and cbar; o(1)<=abar and bbar and c; o(2)<=abar and b and cbar; o(3)<=abar and b and c; o(4)<=a and bbar and cbar; o(5)<=a and bbar and c; o(6)<=a and b and cbar; o(7)<=a and b and c; end process; end decoder_arch;

Testbench: The Test Bench entity decoder_tb is end entity; architecture decoder_tb_arch of decoder_tb is component decoder is port (a,b,c:in BIT; o:out BIT_VECTOR(0 to 7)); end component; signal a,b,c:BIT; signal o: BIT_vector(0 to 7); begin inst:decoder port map(a,b,c,o); process begin a<='0'; b<='0'; c<='0'; wait for 100 ns;

a<='0'; b<='0'; c<='1'; wait for 100 ns; a<='0'; b<='1'; c<='0'; wait for 100 ns; a<='0'; b<='1'; c<='1'; wait for 100 ns; a<='1'; b<='0'; c<='0'; wait for 100 ns; a<='1'; b<='0'; c<='1'; wait for 100 ns; a<='1'; b<='1'; c<='0'; wait for 100 ns; a<='1'; b<='1'; c<='1'; wait for 100 ns; end process; end decoder_tb_arch;

OUTPUT:

7. Design a D flip flop Entity declaration:

entity flipflop1 is port( d,clk:in BIT; q:out BIT); end entity; architecture flipflop_arch of flipflop1 is begin q<=d when clk<='1'; end flipflop_arch;

Testbench: entity flipflop_tb is port (d,clk:in BIT; q:out BIT); end entity; architecture flipflop_tb_arch of flipflop_tb is component flipflop1 is port (d,clk:in BIT; q:out BIT); end component; signal t1,t2,t3:BIT; begin inst1:flipflop1 port map(t1,t2,t3); process begin t1<='1'; t2<='1'; wait for 20 ns; t1<='1'; t2<='0'; wait for 20 ns; t1<='0'; t2<='1'; wait for 20 ns; end process; end flipflop_tb_arch;

OUTPUT:

8. Design a 8x1 multiplexer using two 4x1 multiplexers

Entity declaration:

entity multi8 is port (a:in BIT_vector(0 to 7); sel:in BIT_vector(0 to 2); d:out BIT); end entity; architecture arch_multi8 of multi8 is component multi4 is port (x: in BIT_vector(0 to 3); s:in BIT_vector(0 to 1); dd:out BIT); end component; signal o1,o2:BIT; begin inst1:multi4 port map(a(0 to 3), sel(0 to 1),o1); inst2:multi4 port map(a(4 to 7), sel(0 to 1),o1); d<= o1 when sel(2)='0' else o2 when sel(2)='1'; end arch_multi8;

Test Bench: entity multi8_tb is end entity; architecture arch_multi8_tb of multi8 is component multi8 is port (a:in BIT_vector(0 to 7); sel:in BIT_vector(0 to 1); d:out BIT); end component; signal in1:BIT_vector(0 to 7); signal in2:BIT_vector(0 to 2); signal o1:BIT; begin inst: multi8 port map (in1,in2,o1); process begin in1<="10010101"; in2<="000"; wait for 100 ns; in1<="10010001"; in2<="001"; wait for 100 ns; in1<="10011100"; in2<="010"; wait for 100 ns;

in1<="10010010"; in2<="011"; wait for 100 ns; end process; end arch_multi8_tb;

OUTPUT:

0

1 1 1

1 0 1

0 1 0

0 0 0

1

1 1 1

1 0 0

0 1 1

0 0 0

9. To construct 4 Bit Comparator.

Entity declaration:

entity compare is

port(a,b: in bit_vector(3 downto 0); f1,f2,f3: out bit); end entity; architecture arch_compare of compare is begin

process(a,b) begin if(a>b) then

f1<='0'; f2<='0'; f3<='1';

elsif(a<b) then f1<='1'; f2<='0'; f3<='0';

else f1<='0'; f2<='1'; f3<='0';

end if; end process; end arch_compare;

Test Bench: entity compare_tb is end entity; architecture arch_compare_tb of compare_tb is component compare is port(a,b: in bit_vector(3 downto 0); f1,f2,f3: out bit); end component; signal ina,inb: bit_vector(3 downto 0); signal of1,of2,of3: bit; begin inst: compare port map(ina,inb,of1,of2,of3); process begin ina <="0000"; inb <="0000"; wait for 100 ns; ina<="1111"; inb<="1111"; wait for 100 ns;

ina<="0101"; inb<="1010"; wait for 100 ns; ina<="1010"; inb<="1011"; wait for 100 ns; ina<="1011"; inb<="1010"; wait for 100 ns; ina<="0010"; inb<="0011"; wait for 100 ns; end process; end arch_compare_tb;

OUTPUT:

10. To construct 8-Bit Shift Register Include flipflop1.vhdl in the workspace

Entity declaration:

entity shift8 is port(dd,clka: in bit; oo: out bit); end shift8; architecture arch_shift8 of shift8 is signal output: bit_vector(6 downto 0):="0000000"; component dff is port (d,clk: in bit; q: out bit); end component; begin d0: dff port map(dd,clka,output(0)); d1: dff port map(output(0),clka,output(1)); d2: dff port map(output(1),clka,output(2)); d3: dff port map(output(2),clka,output(3)); d4: dff port map(output(3),clka,output(4)); d5: dff port map(output(4),clka,output(5)); d6: dff port map(output(5),clka,output(6)); d7: dff port map(output(6),clka,oo); end arch_shift8;

TESTBENCH: entity shift8_tb is end entity; architecture arch_shift8_tb of shift8_tb is component shift8 is port(dd,clka: in bit; oo: out bit); end component; signal outp,inp,clk: bit; constant clk_period: time:= 50 ns; begin inst: shift8 port map(inp,clk,outp); clk_process:process begin clk<='0'; wait for clk_period/2; clk<='1'; wait for clk_period/2; end process; stim_process:process begin

inp<='1'; wait for clk_period; inp<='0'; wait for clk_period; inp<='1'; wait for clk_period; inp<='0'; wait for clk_period; inp<='1'; wait for clk_period; inp<='0'; wait for clk_period; inp<='1'; wait for clk_period; end process; end arch_shift8_tb;

OUTPUT:

INDEX

S.No. Experiment Page no. Date Signature

1 Design of six basic gates (And,or nand nor,xor,xnor) for one bit

4-5

2 Design of six basic gates (And,or nand nor,xor,xnor) for four bits

6-7

3 Design of a half adder using basic gates for one bit

8-9

4 Design of a Full Adder using a half adder for one bit

10-11

5 Design of Full Subtractor using a half subtractor

12-13

6 Design a 3x8 decoder 14-15 7 Design a D flip flop 16-17

8 Design a 8x1 multiplexer using two 4x1 multiplexers

18-19

9 To construct 4 Bit Comparator 20-21 10 To construct 8-Bit Shift Register 22-23