very low-power, current feedback operational … = 1.2kΩ, rl = 1kΩ, and g = +2 (see figure 1 for...

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OPA683

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Copyright © 2001-2008, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SBOS221E – NOVEMBER 2001 – REVISED JULY 2008

Very Low-Power, Current FeedbackOPERATIONAL AMPLIFIER With Disable

FEATURES REDUCED BANDWIDTH CHANGE VERSUS GAIN 150MHz BANDWIDTH G = +2 > 90MHz BANDWIDTH TO GAIN > +10 LOW DISTORTION: < –69dBc at 5MHz HIGH OUTPUT CURRENT: 110mA SINGLE +5V TO +12V SUPPLY OPERATION DUAL ±2.5V TO ±6V SUPPLY OPERATION LOW SUPPLY CURRENT: 0.94mA LOW SHUTDOWN CURRENT: 100µA

V+

VO

V–

IERR

RG

RF

U.S. Patent No. 6,724,260

Z(S) IERR

+

Low-Power Amplifier

9

6

3

0

–3

–6

–9

–12

–15

–18

–21

Nor

mal

ized

Gai

n (d

B)

1 10 200100

RF = 1.2kΩ

Frequency (MHz)

OPA683 BANDWIDTH vs GAIN

G = 10

G = 20G = 50

G = 100

G = 2

G = 5

DESCRIPTIONThe OPA683 provides a new level of performance in very low-power, wideband, current feedback amplifiers. This CFBplus ampli-fier is among the first to use an internally closed-loop input bufferstage that enhances performance significantly over earlier low-power CFB amplifiers. While retaining the benefits of very lowpower operation, this new architecture provides many of theadvantages of a more ideal CFB amplifier. The closed-loop inputstage buffer gives a very low and linearized impedance path at theinverting input to sense the feedback error current. This improvedinverting input impedance gives exceptional bandwidth retention tomuch higher gains and improved harmonic distortion over earliersolutions limited by inverting input linearity. Beyond simple highgain applications, the OPA683 CFBplus amplifier can allow the gainsetting element to be set with considerable freedom from amplifierbandwidth interaction. This allows frequency response peakingelements to be added, multiple input inverting summing circuits to

OPA683OPA683

APPLICATIONS LOW POWER BROADCAST VIDEO DRIVERS EQUALIZING FILTERS SAW FILTER HIGH GAIN POST AMPLIFIERS SHORT LOOP ADSL CO DRIVERS MULTICHANNEL SUMMING AMPLIFIERS PROFESSIONAL CAMERAS ADC INPUT DRIVERS

have greater bandwidth, and low-power line drivers to meet thedemanding requirements of studio cameras and broadcast video.The output capability for the OPA683 also sets a new mark inperformance for very low-power current feedback amplifiers. De-livering a full ±4VPP swing on ±5V supplies, the OPA683 also hasthe output current to support this swing into a 100Ω load. Thisminimal output headroom requirement is complemented by asimilar 1.2V input stage headroom giving exceptional capability forsingle +5V operation.The OPA683’s low 0.94mA supply current is precisely trimmed at25°C. This trim, along with low shift over temperature and supplyvoltage, gives a very robust design over a wide range of operatingconditions. System power may be further reduced by using theoptional disable control pin. Leaving this disable pin open, or holdingit HIGH, gives normal operation. If pulled LOW, the OPA683 supplycurrent drops to less than 100µA while the I/O pins go to a highimpedance state.

PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.

All trademarks are the property of their respective owners.

OPA6832SBOS221Ewww.ti.com

ABSOLUTE MAXIMUM RATINGS(1)

Power Supply ............................................................................... ±6.5VDC

Internal Power Dissipation ................................. See Thermal InformationDifferential Input Voltage .................................................................. ±1.2VInput Voltage Range ............................................................................ ±VS

Storage Temperature Range: ID, IDBV ......................... –65°C to +125°CLead Temperature (soldering, 10s) .............................................. +300°CJunction Temperature (TJ ) ........................................................... +175°C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”may cause permanent damage to the device. Exposure to absolute maximumconditions for extended periods may affect device reliability.

SPECIFIEDPACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY

OPA683 SO-8 D –40°C to +85°C OPA683D OPA683ID Rails,100

" " " " " OPA683IDR Tape and Reel, 2500

OPA683 SOT23-6 DBV –40°C to +85°C A83 OPA683IDBVT Tape and Reel, 250

" " " " " OPA683IDBVR Tape and Reel, 3000

PACKAGE/ORDERING INFORMATION(1)

ELECTROSTATICDISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-ments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handlingand installation procedures can cause damage.

ESD damage can range from subtle performance degradation tocomplete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changescould cause the device not to meet its published specifications.

1

2

3

6

5

4

Output

–VS

Noninverting Input

+VS

DIS

Inverting Input

1 2 3

6 5 4

A83Pin Orientation/Package Marking

1

2

3

4

8

7

6

5

NC

Inverting Input

Noninverting Input

–VS

DIS

+VS

Output

NC

NC = No Connection

PIN CONFIGURATION

OPA683 RELATED PRODUCTS

SINGLES DUALS TRIPLES QUADS FEATURES

OPA684 OPA2683 OPA3684 OPA4684 Low-Power CFBplus

OPA691 OPA2691 OPA3691 — High Slew Rate CFBOPA685 — — — > 500MHz CFB

Top View SO-8 Top View SOT23-6

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this document, or see the TI websiteat www.ti.com.

OPA683 3SBOS221E www.ti.com

ELECTRICAL CHARACTERISTICS: VS = ±5VBoldface limits are tested at +25°C.RF = 1.2kΩ, RL = 1kΩ, and G = +2 (see Figure 1 for AC performance only), unless otherwise noted.

OPA683ID, IDBV

TYP MIN/MAX OVER TEMPERATURE

0°C to –40°C to MIN/ TESTPARAMETER CONDITIONS +25°C +25°C(1) 70°C(2) +85°C(2) UNITS MAX LEVEL(3)

AC PERFORMANCE (See Figure 1)Small-Signal Bandwidth (VO = 0.5VPP) G = +1, RF = 1.2kΩ 200 MHz typ C

G = +2, RF = 1.2kΩ 150 124 121 117 MHz min BG = +5, RF = 1.2kΩ 121 MHz typ C

G = +10, RF = 1.2kΩ 94 MHz typ BG = +20, RF = 1.2kΩ 72 MHz typ C

Bandwidth for 0.1dB Gain Flatness G = +2, VO = 0.5VPP, RF = 1.2kΩ 37 15 14 14 MHz min BPeaking at a Gain of +1 RF = 1.2kΩ, VO = 0.5VPP 1.8 6.5 7.7 8.0 dB max BLarge-Signal Bandwidth G = +2, VO = 4VPP 63 MHz typ CSlew Rate G = –1, VO = 4V Step (see Figure 2) 540 450 450 430 V/µs min B

G = +2,VO = 4V Step 400 345 338 336 V/µs min BRise-and-Fall Time G = +2, VO = 0.5V Step 4.6 ns typ C

G = +2, VO = 4VStep 7.8 ns typ CHarmonic Distortion G = +2, f = 5MHz, VO = 2VPP

2nd-Harmonic RL = 100Ω –63 –54 –54 –54 dBc max BRL ≥ 1kΩ –65 –55 –55 –55 dBc max B

3rd-Harmonic RL = 100Ω –67 –62 –62 –62 dBc max BRL ≥ 1kΩ –74 –67 –66 –66 dBc max B

Input Voltage Noise f > 1MHz 4.4 5.0 5.5 5.8 nV/√Hz max BNoninverting Input Current Noise f > 1MHz 5.1 5.8 6.4 6.7 pA/√Hz max BInverting Input Current Noise f > 1MHz 11.6 11.9 12.3 12.4 pA/√Hz max BDifferential Gain G = +2, NTSC, VO = 1.4VP, RL = 150Ω 0.06 % typ CDifferential Phase G = +2, NTSC, VO = 1.4VP, RL = 150Ω 0.03 deg typ C

DC PERFORMANCE(4)

Open-Loop Transimpedance Gain (ZOL) VO = 0V, RL = 1kΩ 700 300 270 250 kΩ min AInput Offset Voltage VCM = 0V ±1.5 ±3.5 ±4.1 ±4.3 mV max AAverage Offset Voltage Drift VCM = 0V ±12 ±12 µV/°C max BNoninverting Input Bias Current VCM = 0V ±2.0 ±4.0 ±4.6 ±4.8 µA max AAverage Noninverting Input Bias Current Drift VCM = 0V ±15 ±15 nA/°C max BInverting Input Bias Current VCM = 0V ±3.0 ±10 ±11 ±11.5 µA max AAverage Inverting Input Bias Current Drift VCM = 0V ±20 ±20 nA°/C max B

INPUTCommon-Mode Input Range(5) (CMIR) ±3.75 ±3.65 ±3.65 ±3.60 V min ACommon-Mode Rejection Ratio (CMRR) VCM = 0V 60 53 52 52 dB min ANoninverting Input Impedance 50 2 kΩ || pF typ CInverting Input Resistance (RI) Open-Loop, DC 4.5 Ω typ C

OUTPUTVoltage Output Swing 1kΩ Load ±4.1 ±4.0 ±4.0 ±3.9 V min ACurrent Output, Sourcing VO = 0 150 130 125 120 mA min ACurrent Output, Sinking VO = 0 –110 –100 –95 –90 mA min AClosed-Loop Output Impedance G = +2, f = 100kHz 0.007 Ω typ C

DISABLE (Disabled LOW)Power-Down Supply Current (+VS) VDIS = 0 –100 –150 –170 –180 µA typ CDisable Time VIN = +1, See Figure 1 60 ms typ CEnable Time VIN = +1, See Figure 1 40 ns typ COff Isolation G = +2, 5MHz 70 dB typ COutput Capacitance in Disable 1.7 pF typ CTurn On Glitch G = +2, RL = 150Ω, VIN = 0 ±70 mV typ CTurn Off Glitch G = +2, RL = 150Ω, VIN = 0 ±20 mV typ CEnable Voltage 3.4 3.5 3.6 3.7 V min ADisable Voltage 1.8 1.7 1.6 1.5 V max AControl Pin Input Bias Current (DIS) VDIS = 0V 80 120 130 135 µA max A

POWER SUPPLYSpecified Operating Voltage ±5 V typ CMaximum Operating Voltage Range ±6 ±6 ±6 V max AMinimum Operating Voltage Range ±1.4 V min CMax Quiescent Current VS = ±5V 0.94 1.03 1.04 1.05 mA max AMin Quiescent Current VS = ±5V 0.94 0.85 0.80 0.77 mA min APower-Supply Rejection Ratio (–PSRR) Input Referred 62 55 54 54 dB typ A

TEMPERATURE RANGESpecification: D, DBV –40 to +85 °C typ CThermal Resistance, θJA Junction-to-Ambient

D SO-8 125 °C/W typ CDBV SOT-23-6 150 °C/W typ C

NOTES: (1) Junction temperature = ambient for 25°C tested specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient+2°C at high temperature limit for over temperature tested specifications. (3) Test levels: (A) 100% tested at 25°C. Over temperature limits by characterization andsimulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. VCM is the inputcommon-mode voltage. (5) Tested < 3dB below minimum specified CMR at ± CMIR limits.


OPA683ID, IDBV

TYP MIN/MAX OVER TEMPERATURE

0°C to –40°C to MIN/ TESTPARAMETER CONDITIONS +25°C +25°C(1) 70°C(2) +85°C(2) UNITS MAX LEVEL(3)

ELECTRICAL CHARACTERISTICS: VS = +5VBoldface limits are tested at +25°C.RF = 1.4kΩ, RL = 1kΩ, and G = +2 (see Figure 3 for AC performance only), unless otherwise noted.

AC PERFORMANCE (See Figure 3)Small-Signal Bandwidth (VO = 0.2VPP) G = +1, RF = 1.4kΩ 145 MHz typ

G = +2, RF = 1.4kΩ 119 96 92 90 MHz min BG = +5, RF = 1.4kΩ 95 MHz typ C

G = +10, RF = 1.4kΩ 87 MHz typ CG = +20, RF = 1.4kΩ 60 MHz typ C

Bandwidth for 0.1dB Gain Flatness G = +2, VO < 0.5VPP, RF = 1.2kΩ 14 9 8 8 MHz min BPeaking at a Gain of +1 RF = 1.4kΩ, VO < 0.5VPP 1 6 8 8 dB max BLarge-Signal Bandwidth G = +2, VO = 2VPP 70 MHz typ CSlew Rate G = +2, VO = 2V Step 210 180 175 170 V/µs min BRise-and-Fall Time G = +2, VO = 0.5V Step 5.9 ns typ C

G = +2, VO = 2VStep 7.8 ns typ CHarmonic Distortion G = 2, f = 5MHz, VO = 2VPP

2nd-Harmonic RL = 100Ω to VS/2 –60 –54 –53 –53 dBc max BRL ≥ 1kΩ to VS/2 –66 –55 –55 –55 dBc max B

3rd-Harmonic RL = 100Ω to VS/2 –59 –58 –58 –58 dBc max BRL ≥ 1kΩ to VS/2 –63 –57 –56 –56 dBc max B

Input Voltage Noise f > 1MHz 4.4 5.0 5.5 5.8 nV/√Hz max BNoninverting Input Current Noise f > 1MHz 5.1 5.8 6.4 6.7 pA/√Hz max BInverting Input Current Noise f > 1MHz 11.6 11.9 12.3 12.4 pA/√Hz max BDifferential Gain G = +2, NTSC, VO = 1.4VP, RL = 150Ω 0.24 % typ CDifferential Phase G = +2, NTSC, VO = 1.4VP, RL = 150Ω 0.19 deg typ C

DC PERFORMANCE(4)

Open-Loop Transimpedance Gain (ZOL) VO = VS/2, RL = 1kΩ to VS/2 700 300 270 250 kΩ min AInput Offset Voltage VCM = VS/2 ±1.0 ±3.0 ±3.6 ±3.8 mV max AAverage Offset Voltage Drift VCM = VS/2 ±12 ±12 µV/°C max BNoninverting Input Bias Current VCM = VS/2 ±2 ±4 ±4.6 ±4.8 µA max AAverage Noninverting Input Bias Current Drift VCM = VS/2 ±12 ±12 nA/°C max BInverting Input Bias Current VCM = VS/2 ±3 ±8 ±8.7 ±8.9 µA max AAverage Inverting Input Bias Current Drift VCM = VS/2 ±15 ±15 nA°/C max B

INPUTLeast Positive Input Voltage(5) 1.1 1.25 1.29 1.34 V max AMost Positive Input Voltage(5) 3.9 3.75 3.73 3.67 V min ACommon-Mode Rejection Ratio (CMRR) VCM = VS/2 58 51 50 50 dB min ANoninverting Input Impedance 50 2 kΩ || pF typ CInverting Input Resistance (RI) Open-Loop 4.8 Ω typ C

OUTPUTMost Positive Output Voltage RL = 1kΩ to VS/2 4.2 4.1 4.1 4.0 V min ALeast Positive Output Voltage RL = 1kΩ to VS/2 0.8 0.9 0.9 1.00 min ACurrent Output, Sourcing VO = VS/2 80 65 63 58 mA min ACurrent Output, Sinking VO = VS/2 70 52 50 45 mA min AClosed-Loop Output Impedance G = +2, f = 100kHz 0.009 Ω typ C

DISABLE (Disabled LOW)Power-Down Supply Current (+VS) VDIS = 0 100 µA typ COff Isolation G = +2, 5MHz 70 dB typ COutput Capacitance in Disable 1.7 pF typ CTurn On Glitch G = +2, RL = 150Ω, VIN = VS/2 ±70 mV typ CTurn Off Glitch G = +2, RL = 150Ω, VIN = VS/2 ±20 mV typ CEnable Voltage 3.4 3.5 3.6 3.7 V min ADisable Voltage 1.8 1.7 1.6 1.5 V max AControl Pin Input Bias Current (DIS) VDIS = 0V 80 120 130 135 µA max A

POWER SUPPLYSpecified Single-Supply Operating Voltage 5 V typ CMax Single-Supply Operating Voltage 12 12 12 V max AMin Single-Supply Operating Voltage 2.8 V min CMax Quiescent Current VS = +5V 0.82 0.91 0.91 0.91 mA max AMin Quiescent Current VS = +5V 0.82 0.71 0.69 0.67 mA min APower-Supply Rejection Ratio (+PSRR) Input Referred 65 dB typ C

TEMPERATURE RANGESpecification: D, DBV –40 to +85 °C typ CThermal Resistance, θJA Junction-to-Ambient

D SO-8 125 °C/W typ CDBV SOT-23-6 150 °C/W typ C

NOTES: (1) Junction temperature = ambient for 25°C tested specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient+2°C at high temperature limit for over temperature tested specifications. (3) Test levels: (A) 100% tested at 25°C. Over temperature limits by characterization andsimulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. VCM is the inputcommon-mode voltage. (5) Tested < 3dB below minimum specified CMR at ± CMIR limits.


TYPICAL CHARACTERISTICS: VS = ±5VTA = 25°C, RF = 1.2kΩ, RL = 1kΩ, and G = +2 (see Figure 1 for AC performance only), unless otherwise noted.

INVERTING PULSE RESPONSE

Time (10ns/div)

Out

put V

olta

ge (

200m

V/d

iv)

Out

put V

olta

ge (

800m

V/d

iv)

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

3.2

2.4

1.6

0.8

0

–0.8

–1.6

–2.4

–3.2

Large-Signal Right Scale

Small-Signal Left Scale

See Figure 2

G = –1

9

6

3

0

–3

Frequency (MHz)

1 20010 100

NONINVERTING LARGE-SIGNALFREQUENCY RESPONSE

Gai

n (d

B)

G = +2RL = 1kΩ

See Figure 1

VO = 0.5VPP

VO = 1VPP

VO = 5VPP

VO = 2VPP

3

0

–3

–6

–9

–12

Frequency (MHz)

1 20010 100

INVERTING LARGE-SIGNAL FREQUENCY RESPONSE

Gai

n (d

B)

G = –1RL = 1kΩ VO = 0.5VPP

See Figure 2

VO = 2VPP

VO = 1VPP

VO = 5VPP

NONINVERTING PULSE RESPONSE

Time (10ns/div)

Out

put V

olta

ge (

200m

V/d

iv)

Out

put V

olta

ge (

800m

V/d

iv)

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

3.2

2.4

1.6

0.8

0

–0.8

–1.6

–2.4

–3.2



See Figure 1

G = +2

6

3

0

–3

–6

–9

–12

Frequency (MHz)

1 20010 100

NONINVERTING SMALL-SIGNALFREQUENCY RESPONSE

Nor

mal

ized

Gai

n (3

dB/d

iv)

VO = 0.5VPPRF = 1.2kΩ

G = 100

See Figure 1

G = 50

G = 10

G = 1

G = 2

G = 5

3

0

–3

–6

–9

–12

Frequency (MHz)

1 20010 100

INVERTING SMALL-SIGNAL FREQUENCY RESPONSE

Nor

mal

ized

Gai

n (3

dB/d

iv)

VO = 0.5VPPRF = 1.2kΩ

See Figure 2

G = –10G = –24

G = –5 G = –1

G = –2


TYPICAL CHARACTERISTICS: VS = ±5V (Cont.)TA = 25°C, RF = 1.2kΩ, RL = 1kΩ, and G = +2 (see Figure 1 for AC performance only), unless otherwise noted.

HARMONIC DISTORTION vs LOAD RESISTANCE

100 1kLoad Resistance (Ω)

Har

mon

ic D

isto

rtio

n (d

Bc)

–50

–55

–60

–65

–70

–75

–80

–85

–90

VO = 2VPPf = 5MHzG = +2

See Figure 1

2nd-Harmonic

3rd-Harmonic

–50

–60

–70

–80

–90

Frequency (MHz)

0.1 201 10

HARMONIC DISTORTION vs FREQUENCY

Har

mon

ic D

isto

rtio

n (d

Bc)

VO = 2VPPRL = 1kΩ

See Figure 1

2nd-Harmonic

3rd-Harmonic

HARMONIC DISTORTION vs OUTPUT VOLTAGE

0.5 1 5Output Voltage (VPP)

Har

mon

ic D

isto

rtio

n (d

Bc)

–50

–60

–70

–80

–90

f = 5MHzRL = 1kΩ

2nd-Harmonic

3rd-Harmonic See Figure 1

HARMONIC DISTORTION vs NONINVERTING GAIN

Gain (V/V)

Har

mon

ic D

isto

rtio

n (d

Bc)

See Figure 1

1 10 20

–50

–55

–60

–65

–70

–75

–80

–85

–90

VO = 2VPPf = 5MHzRL = 1kΩ 2nd-Harmonic

3rd-Harmonic

HARMONIC DISTORTION vs INVERTING GAIN

1 10 20Inverting Gain (–V/V)

Har

mon

ic D

isto

rtio

n (d

Bc)

–50

–55

–60

–65

–70

–75

–80

–85

–90

3rd-Harmonic

2nd-Harmonic

VO = 2VPPf = 5MHzRL = 1kΩ

See Figure 2

5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE

±2.5 ±3 ±3.5 ±4 ±4.5 ±5 ±5.5 ±6Supply Voltage (±V)

Har

mon

ic D

isto

rtio

n (d

Bc)

–50

–60

–70

–80

–90

VO = 2VPPRL = 1kΩ 2nd-Harmonic

3rd-Harmonic

See Figure 1



100

10

1

Frequency (Hz)

102 107103 104 105 106

INPUT VOLTAGE AND CURRENT NOISE DENSITY

Vol

tage

Noi

se (

nV/√

Hz)

Cur

rent

Noi

se (

pA/√

Hz)

Noninverting Current Noise5.2pA/√Hz

Voltage Noise4.4nV/√Hz

Inverting Current Noise11.6pA/√Hz

160

140

120

100

80

60

40

20

0

CLOAD (pF)

1 10010

RS vs CLOAD

RS (

Ω)

0.5dB Peaking

2-TONE, 3RD-ORDER INTERMODULATION DISTORTION

VPP at 1kΩ Load (each tone)

3rd-

Ord

er S

purio

us L

evel

(dB

c)

–45

–55

–65

–75

–851MHz

20MHz

0.1 0.4 1 2

5MHz

10MHz

+5V

–5V

50Ω

1kΩ

PI

PO

1.2kΩ

1.2kΩ

OPA683

6

5

4

3

2

1

0

Time (ms)

0 10010 20 4030 8070 906050

DISABLE TIME

VDIS

VOUT

VO

UT a

nd V

DIS

(V

)

VIN = 1VDCSee Figure 1

–40

–50

–60

–70

–80

–90

–100

Frequency (MHz)

0.1 1001 10

DISABLED FEEDTHRU

Fee

dthr

u (d

B)

G = +2VDIS = 0V

See Figure 1

9

6

3

0

–3

–6

Frequency (MHz)

1 20010 100

SMALL-SIGNAL BANDWIDTH vs CLOAD

Nor

mal

ized

Gai

n (d

B)

10pF

100pF

47pF

22pF

RS VO

+5V

–5V

50Ω

CL

VI

1.2kΩ

1.2kΩ

1kΩ

OPA683



CMRR and PSRR vs FREQUENCY

102 103 104 105 106 107 108

Frequency (Hz)

Com

mon

-Mod

e R

ejec

tion

Rat

io (

dB)

Pow

er-S

uppl

y R

ejec

tion

Rat

io (

dB)

70

60

50

40

30

20

10

0

CMRR

+PSRR

–PSRR

OPEN-LOOP TRANSIMPEDANCE GAIN AND PHASE

104 105 106 107 108 109

Frequency (Hz)

Ope

n-Lo

op T

rans

impe

danc

e G

ain

(dB

Ω) 120

100

80

60

40

20

0

Ope

n-Lo

op P

hase

(°)

0

–30

–60

–90

–120

–150

–180

20log (ZOL)

∠ ZOL

0.2

0.15

0.1

0.05

0

Number of 150Ω Video Loads

1 42 3

COMPOSITE VIDEO DIFFERENTIAL GAIN/PHASE

Diff

eren

tial G

ain

(%)

Diff

eren

tial P

hase

(°)

Gain = +2NTSC, Positive Video

dG

dP

TYPICAL DC DRIFT OVER TEMPERATURE

–50 –25 0 25 50 75 100 125

Ambient Temperature (°C)

Inpu

t Bia

s C

urre

nts

(µA

)an

d O

ffset

Vol

tage

(m

V)

4

3

2

1

0

–1

–2

–3

–4

Input Offset Voltage

Noninverting Input Bias Current

Inverting Input Bias Current

OUTPUT CURRENT AND VOLTAGE LIMITATIONS

–150 –100 –50 0 50 100 150IO (mA)

VO (

V)

5

4

3

2

1

0

–1

–2

–3

–4

–5

1W PowerLimit

R L =

100

Ω

R L = 50

Ω

R L =

500Ω

1W PowerLimit

SUPPLY AND OUTPUT CURRENTvs TEMPERATURE

–25 0 25 50 75 100 125Ambient Temperature (°C)

Out

put C

urre

nt (

mA

)

200

175

150

125

100

1

0.95

0.9

0.85

0.8

Sup

ply

Cur

rent

(m

A)

Sourcing Output Current

Sinking Output Current

Supply CurrentRight Scale



SETTLING TIME

0 10 20 30 40 50 60Time (ns)

% E

rror

to F

inal

Val

ue

0.05

0.04

0.03

0.02

0.01

0

–0.01

–0.02

–0.03

–0.04

–0.05

2V StepSee Figure 1

DISABLED SUPPLY CURRENT vs TEMPERATURE

–50 –25 250 50 75 100 125Ambient Temperature (°C)

Dis

able

d S

uppl

y C

urre

nt (

µA)

110

100

90

80

70

60

+VS Current

NONINVERTING OVERDRIVE RECOVERY

Time (100ns/div)

Inpu

t Vol

tage

(0.

8V/d

iv)

Out

put V

olta

ge (

1.6V

/div

)4.0

3.2

2.4

1.6

0.8

0

–0.8

–1.6

–2.4

–3.2

–4.0

8.0

6.4

4.8

3.2

1.6

0

–1.6

–3.2

–4.8

–6.4

–8.0

See Figure 1

Input VoltageLeft Scale

Output VoltageRight Scale

INPUT AND OUTPUT RANGE vs SUPPLY VOLTAGE

± Supply Voltage

± 4± 3± 2 ± 5 ± 6

Inpu

t and

Out

put V

olta

ge R

ange

6

5

4

3

2

1

0

–1

–2

–3

–4

–5

–6

InputVoltageRange

OutputVoltageRange

CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY

Frequency (Hz)

100k 1M1k 10k100 10M 100M

Out

put I

mpe

danc

e (Ω

)

100

10

1

0.01

0.001

1.2kΩ ZO

1.2kΩ

OPA683

INVERTING OVERDRIVE RECOVERY

Time (100ns/div)

Inpu

t Vol

tage

(1.

6V/d

iv)

Inpu

t Vol

tage

(1.

6V/d

iv)

8.0

6.4

4.8

3.2

1.6

0

–1.6

–3.2

–4.8

–6.4

–8.0

8.0

6.4

4.8

3.2

1.6

0

–1.6

–3.2

–4.8

–6.4

–8.0

Input VoltageLeft Scale See Figure 2

Output VoltageRight Scale


TYPICAL CHARACTERISTICS: VS = +5VTA = 25°C, RF = 1.4kΩ, RL = 1kΩ, and G = +2 (see Figure 3 for AC performance only), unless otherwise noted.

6

3

0

–3

–6

–9

–12

–15

–18

Frequency (MHz)

1 20010 100

NONINVERTING SMALL-SIGNALFREQUENCY RESPONSE

Nor

mal

ized

Gai

n (d

B)

See Figure 3

G = 50RF = 1.4kΩVO = 0.2VPP

RL = 1kΩG = 1

G = 2

G = 20

G = 10

G = 5

3

0

–3

–6

–9

–12

Frequency (MHz)

1 20010 100

INVERTING LARGE-SIGNAL FREQUENCY RESPONSEG

ain

(dB

)

VO = 0.2VPP

See Figure 4

VO = 1VPP

VO = 0.5VPP

VO = 2VPP

G = –1RL = 1kΩ

9

6

3

0

–3

Frequency (MHz)

1 20010 100

NONINVERTING LARGE-SIGNALFREQUENCY RESPONSE

Gai

n (d

B)

0.5VPP

1VPP

0.2VPP

2VPPSee Figure 3

G = +2RL = 1kΩ

3

0

–3

–6

–9

–12

Frequency (MHz)

1 20010 100

INVERTING SMALL-SIGNAL FREQUENCY RESPONSE

Nor

mal

ized

Gai

n (3

dB/d

iv)

See Figure 4

RF = 1.4kΩVO = 0.2VPP

RL = 1kΩ

G = –1

G = –10G = –28

G = –5G = –2

NONINVERTING PULSE RESPONSE

Time (10ns/div)

Out

put V

olta

ge (

100m

V/d

iv)

Out

put V

olta

ge (

400m

V/d

iv)

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

1.6

1.2

0.8

0.4

0

–0.4

–0.8

–1.2

–1.6



See Figure 3

INVERTING PULSE RESPONSE

Time (10ns/div)

Out

put V

olta

ge (

100m

V/d

iv)

Out

put V

olta

ge (

400m

V/d

iv)

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

1.6

1.2

0.8

0.4

0

–0.4

–0.8

–1.2

–1.6



See Figure 4


TYPICAL CHARACTERISTICS: VS = +5V (Cont.)TA = 25°C, RF = 1.4kΩ, RL = 1kΩ, and G = +2 (see Figure 3 for AC performance only), unless otherwise noted.

HARMONIC DISTORTION vs LOAD RESISTANCE

100 1kLoad Resistance (Ω)

Har

mon

ic D

isto

rtio

n (d

Bc)

–50

–55

–60

–65

–70

–75

–80

–85

–90

VO = 2VPPf = 5MHz

See Figure 3

3rd-Harmonic

2nd-Harmonic

–50

–60

–70

–80

–90

Frequency (MHz)

0.1 201 10

HARMONIC DISTORTION vs FREQUENCY

Har

mon

ic D

isto

rtio

n (d

Bc)

VO = 2VPPRL = 1kΩ

See Figure 3

2nd-Harmonic

3rd-Harmonic

–50

–60

–70

–80

–90

Output Voltage (VPP)

0.5 31 2

HARMONIC DISTORTION vs OUTPUT VOLTAGE

Har

mon

ic D

isto

rtio

n (d

Bc)

3rd-Harmonic

2nd-Harmonic

See Figure 3

G = +2RL = 1kΩf = 5MHz

0.3

0.25

0.2

0.15

0.1

0.05

0

Number of 150Ω Video Loads

1 42 3

COMPOSITE VIDEO DIFFERENTIAL GAIN/PHASE

Diff

eren

tial G

ain

(%)

Diff

eren

tial P

hase

(°)

dP

dG

G = +2NTSC, Positive Video

2-TONE, 3RD-ORDER INTERMODULATION DISTORTION

0.1 1

VPP at 1Ω Load (each tone)

3rd-

Ord

er S

purio

us L

evel

(dB

c)

–45

–55

–65

–75

–85

See Figure 3

10MHz

20MHz

5MHz

SUPPLY AND OUTPUT CURRENTvs TEMPERATURE

–50 –25 0 25 50 10075 125Ambient Temperature (°C)

Out

put C

urre

nt (

mA

)

100

90

80

70

60

50

0.95

0.9

0.85

0.8

0.75

0.7

Sup

ply

Cur

rent

(m

A)

Left ScaleSinking Output Current

Right ScaleSupply Current

Sourcing Output CurrentLeft Scale


APPLICATIONS INFORMATIONVERY LOW POWER CURRENT-FEEDBACKOPERATION

The OPA683 gives a new level of performance in very lowpower current-feedback op amps. Using a new input stagebuffer architecture, the OPA683 CFBplus amplifier gives im-proved bandwidth to higher gains than previous < 1mAsupply current amplifiers. This closed-loop internal buffergives a very low and linearized impedance at the invertingnode—isolating the amplifier’s AC performance from gainelement variations. This allows both the bandwidth anddistortion to remain nearly constant over gain—moving closerto the ideal current-feedback performance of Gain Bandwidthindependence. This low power amplifier also delivers excep-tional output power—its ±4V swing on ±5V supplies with> 100mA output drive gives excellent performance intostandard video loads or doubly-terminated 50Ω cables. Single+5V supply operation is also supported with similar band-widths, but reduced output power capability. For improvedharmonic distortion driving heavier loads, in a low powerCFBplus amplifier, consider the OPA684, while for evenhigher output power, consider the OPA691.

Figure 1 shows the DC-coupled, gain of +2, dual power-supply circuit used as the basis of the ±5V Electrical Charac-teristics and Typical Characteristics. For test purposes, theinput impedance is set to 50Ω with a resistor to ground whilethe output load is a 1kΩ resistor. Voltage swings reported inthe specifications are taken directly at the input and outputpins while load powers (dBm) are interpreted as the voltageswing at the output converted to dBm as if the load were50Ω. For the circuit of Figure 1, the total effective load will be1kΩ || 2.4kΩ = 706Ω. Gain changes are most easily accom-plished by simply resetting the RG value—holding RF con-stant at its recommended value of 1.2kΩ. The disable controlline (DIS) is typically left open to ensure normal amplifieroperation. It may, however, be asserted LOW to reduce theamplifier quiescent to 100µA typically.

Figure 2 shows the DC-coupled, gain of –1V/V, dual power-supply circuit used as the basis of the Inverting TypicalCharacteristics. Inverting operation offers several perfor-mance benefits. Since there is no common-mode signalacross the input stage, the slew rate for inverting operationis higher and the distortion performance is slightly improved.An additional input resistor, RM, is included in Figure 2 to setthe input impedance equal to the 50Ω. The parallel combina-tion of RM and RG set the input impedance. As the desiredgain increases for the inverting configuration, RG is adjustedto achieved the desired gain and RM is also adjusted to holda 50Ω input match. A point will be reached where RG willequal 50Ω, RM is then removed and the input match is set byRG only. With RG fixed to achieve an input match to 50Ω, toincrease gain, RF is simply increased. This will, however,quickly reduce the achievable bandwidth as the feedbackresistor increases from its recommended value of 1.2kΩ. Ifthe source does not require an input match to 50Ω, eitheradjust RM to the get the desired load or remove it and let theRG resistor alone provide the input load.

RF1.2kΩ

VOOPA683

+5V

–5V

DIS 1kΩ

50Ω

RG1.2kΩ

RG = 50Ω

VI

0.1µF 6.8µF

0.1µF 6.8µF

+

+

FIGURE 1. DC-Coupled, G = +2V/V, Bipolar Supply, Speci-fication and Test Circuit.

FIGURE 2. DC-Coupled, G = –1V/V, Bipolar Supply, Speci-fication and Test Circuit.

RF1.2kΩ

OPA683

+5V

–5V

DIS

RT52.3Ω

RG1.2kΩ

RS = 50Ω

0.1µF 6.8µF

0.1µF 6.8µF

+

+

VI

VO

1kΩ

These circuits are showing ±5V operation. The same circuitcan be applied with bipolar supplies ranging from ±2.5V to±6V. Internal supply independent biasing gives nearly thesame performance for the OPA683 over this wide range ofsupplies. Generally, the optimum feedback resistor value (fornominally flat frequency response at G = +2) will increase invalue as the total supply voltage across the OPA683 isreduced.

See Figure 3 for the AC-coupled, single +5V supply, gain of+2V/V circuit configuration used as a basis for the +5V onlyElectrical Characteristics and Typical Characteristics. Thekey requirement of broadband single-supply operation is tomaintain input and output signal swings within the usablevoltage ranges at both the input and the output. The circuitof Figure 3 establishes an input midpoint bias using a simpleresistive divider from the +5V supply (two 12.5kΩ resistors)to the noninverting input. The input signal is then AC-coupled


into this midpoint voltage bias. The input voltage can swingto within 1.25V of either supply pin, giving a 2.5VPP inputsignal range centered between the supply pins. The inputimpedance of Figure 3 is set to give a 50Ω input match. If thesource does not require a 50Ω match, remove this and drivedirectly into the blocking capacitor. The source will then seethe 6.25kΩ load of the biasing network. The gain resistor(RG) is AC-coupled, giving the circuit a DC gain of +1—whichputs the noninverting input DC bias voltage (2.5V) on theoutput as well. The feedback resistor value has been ad-justed from the bipolar supply condition to re-optimize for aflat frequency response in +5V only, gain of +2 operation. Ona single +5V supply, the output voltage can swing to within1.0V of either supply pin while delivering more than 50mAoutput current giving 3VPP output swing into an AC-coupled100Ω load if required (8dBm maximum at the matched load).The circuit of Figure 3 shows a blocking capacitor driving intoa 1kΩ load resistor. Alternatively, the blocking capacitorcould be removed if the load is tied to a supply midpoint orto ground if the DC current required by the load is accept-able.

Figure 4 shows the AC-coupled, single +5V supply, gain of–1V/V circuit configuration used as a basis for the +5V onlyTypical Characteristics. In this case, the midpoint DC bias onthe noninverting input is also decoupled with an additional0.1µF decoupling capacitor. This reduces the source imped-ance at higher frequencies for the noninverting input biascurrent noise. This 2.5V bias on the noninverting input pinappears on the inverting input pin and, since RG is DCblocked by the input capacitor, will also appear at the outputpin. One advantage to inverting operation is that since thereis no signal swing across the input stage, higher slew ratesand operation to even lower supply voltages is possible. Toretain a 1VPP output capability, operation down to a 3Vsupply is allowed. At a +3V supply, the input stage issaturated, but for the inverting configuration of a current-feedback amplifier, wideband operation is retained evenunder this condition.

The circuits of Figure 3 and 4 show single-supply operationat +5V. These same circuits may be used up to singlesupplies of +12V with minimal changes in the performance ofthe OPA683.

LOW POWER, VIDEO LINE DRIVERAPPLICATIONS

For low power, video line driving, the OPA683 provides theoutput current and linearity to support multiple load compos-ite video signals. Figure 5 shows a typical ±5V supply videoline driver application. The improved 2nd-harmonic distortionof the CFBplus architecture, along with the OPA683’s highoutput current and voltage, gives exceptional differential gainand phase performance in a very low power solution. As theTypical Characteristics show, a single video load shows adG/dP of 0.06%/0.03°. Multiple loads may also be driven with< 0.15%/0.1° dG/dP for up to 4 parallel video loads where theamplifier is driving an equivalent load of 37.5Ω.

RF1.4kΩ

OPA683

+5V

DIS

50Ω Source

0.1µF 6.8µF+

12.5kΩ

2.5V

12.5kΩ50Ω

RG1.4kΩ

0.1µF

0.1µF

0.1µF

VI

VO

1kΩ

FIGURE 3. AC-Coupled, G = +2V/V, Single-Supply, Specifi-cation and Test Circuit.

RF1.4kΩ

OPA683

+5V

DIS

50Ω Source

0.1µF

0.1µF

2.5V

6.8µF+

RG1.4kΩ

12.5kΩ

12.5kΩ

VI

0.1µF

52.3Ω

0.1µF

VO

1kΩ

FIGURE 4. AC-Coupled, G = –1V/V, Single-Supply, Specifi-cation and Test Circuit.

1.2kΩ

OPA683

+5V

DIS

–5V

75Ω75Ω

1.2kΩ

75Ω Load

Supply Decoupling not shown.

Coax

VIDEOIN

FIGURE 5. Gain of +2 Video Cable Driver.


VERY LOW POWER ACTIVE FILTER

The OPA683 provides an exceptionally capable gain blockfor implementing Sallen-Key type filters. Typically, the band-width interaction with gain setting for low power amplifiers,constrain these filters to using unity-gain amplifiers. Sincethe OPA683 CFBplus design holds very high bandwidth tohigh gains, implementations that provide signal gain, as wellas the desired filter shape, are easily implemented. Figure 6shows an example of a 5MHz 2nd-order low-pass filter wherethe amplifier is providing a voltage gain of 4. This single-supply implementation (applicable to single +12V operationas well) consumes only 5.1mW quiescent power. The two12.5kΩ resistors bias the input and output at the supplymidpoint while the three 0.1µF capacitors block off the DCcurrent paths to ground for this mid-scale operating point.The filter resistors and capacitors have been adjustedto provide a Butterworth (Q = 0.707) response with aωO = 2π • 5MHz. This gives a flat passband response with a–3dB cutoff at 5MHz. Figure 7 shows the small-signal fre-quency response for the circuit of Figure 6.

HIGH GAIN HF AMPLIFIER

Where high gains at moderate frequencies are required in anHF receiver channel, the OPA683 can provide a very lowpower solution with moderate input noise figure. Figure 8shows a technique that can improve the noise figure with noadded power. An input transformer provides a noiselessvoltage gain at the cost of higher source impedance for theamplifier’s noninverting input current noise. The circuit ofFigure 8, using a 1:4 turns ratio (1:16 impedance ratio)transformer, reduces the input noise figure from about 20dBfor just the amplifier to 10.6dB in combination. The bandwidthfor this circuit will be principally set by the transformer sincethe OPA683 will give > 80MHz for the gain of 20V/V shownin Figure 8. The overall circuit gives a gain to a matched 50Ωload of 32dB (40V/V) from the transformer input. This ex-ample circuit provides this gain using only 10mW of quies-cent power with application from 500kHz to 30MHz.

1.4kΩ

OPA683

+5V

12.5kΩ

12.5kΩ

467Ω

0.1µF

VI0.1µF

446Ω157Ω

100pF

SupplyDe-couplingNot Shown

VO

1kΩ

150pF

0.1µF

15

12

9

6

3

0

–3

–6

–9

Frequency (Hz)

1k 20M100k10k 1M 10M

LOW POWER 5MHz LP ACTIVE FILTER

Gai

n (d

B)

FIGURE 6. 5MHz, 2nd-Order Low Pass Filter.

FIGURE 7. Low Power Active Filter Frequency Response.

OPA683

+5V

–5V

50Ω

50Ω

63Ω

0.01µF

800Ω

PI

PO

PO = 32dBPI

1.2kΩ

50Ω

10.6dBNoise Figure

1:4

FIGURE 8. Low Power, High Gain HF Amplifier.

LOW POWER, ADC DRIVER

Where a low power, single-supply interface to a single-endedinput +5V ADC is required, the circuit of Figure 9 can providea very flexible, high performance solution. Running in an AC-coupled inverting mode allows the noninverting input to beused for the common-mode voltage from the ADS820 con-verter. This midpoint reference biases both the noninvertingconverter input and the amplifier noninverting input. With anAC-coupled gain path, this +2.5V DC bias has a gain of +1to the output putting the output at the DC midpoint for theconverter. The output then drives through an isolating resis-tor (60Ω) to the inverting input of the converter which isfurther decoupled by a 22pF external capacitance to add toits 5pF input capacitance. This coupling network provides ahigh cutoff low-pass while also giving a low source imped-ance at high frequencies for the converter. The gain for thiscircuit is set by adjusting RG to the desired value. For a 2VPP

maximum output driving the light load of Figure 9, theOPA683 will provide < –80dBc THD through 1MHz as shownin the Typical Characteristics. One of the important advan-tages for this CFBplus amplifier is that this distortion does notdegrade significantly at higher gains.


DESIGN-IN TOOLSDEMONSTRATION FIXTURES

Two printed circuit boards (PCBs) are available to assist inthe initial evaluation of circuit performance using the OPA683in its two package options. Both of these are offered free ofcharge as unpopulated PCBs, delivered with a user's guide.The summary information for these fixtures is shown inTable I.

The buffer gain is typically very close to 1.00 and is normallyneglected from signal gain considerations. It will, howeverset the CMRR for a single op amp differential amplifierconfiguration. For the buffer gain α < 1.0, the CMRR =–20 • log(1 – α). The closed loop input stage buffer used inthe OPA683 gives a buffer gain more closely approaching1.00 and this shows up in a slightly higher CMRR than anyprevious current feedback op amp. The 60dB typical CMRRshown in the Electrical Characteristics implies a buffer gainof 0.9990.

RI, the buffer output impedance, is a critical portion of thebandwidth control equation. The OPA683 reduces this ele-ment to approximately 4.5Ω using the loop-gain of the inputbuffer stage. This significant reduction in buffer output im-pedance, on very low power, contributes significantly toextending the bandwidth at higher gains.

ORDERING LITERATUREPRODUCT PACKAGE NUMBER NUMBER

OPA683ID SO-8 DEM-OPA-SO-1A SBOU009OPA683IDBQ SOT23-6 DEM-OPA-SOT-1A SBOU010

TABLE I. Demonstration Fixtures by Package.

The demonstration fixtures can be requested at the TexasInstruments web site (www.ti.com) through the OPA683product folder.

OPERATING SUGGESTIONSSETTING RESISTOR VALUES TO OPTIMIZEBANDWIDTH

Any current-feedback op amp like the OPA683 can hold highbandwidth over signal gain settings with the proper adjust-ment of the external resistor values. A low-power part like theOPA683 typically shows a larger change in bandwidth due tothe significant contribution of the inverting input impedanceto loop-gain changes as the signal gain is changed. Figure10 shows a simplified analysis circuit for any current feed-back amplifier.

The key elements of this current feedback op amp model are:

α ⇒ Buffer gain from the noninverting input to the inverting input

RI ⇒ Buffer output impedance

iERR ⇒ Feedback error current signal

Z(s) ⇒ Frequency dependent open loop transimpedance gainfrom iERR to VO

OPA683

+5V

DIS

60Ω

RG

RG

RI1.4kΩ

50Ω

22pF

VI

VO

1.4kΩ

0.1µF

VO = – VI

IN

IN

CM

ADS82010-Bit

20MSPS

2.5VDC

+2.5V

2VPPMax

FIGURE 9. Low Power, Single-Supply, ADC Driver.

RF

VO

RG

RIZ(S) iERR

iERR

α

VI

FIGURE 10. Current Feedback Transfer Function AnalysisCircuit.


A current-feedback op amp senses an error current in theinverting node (as opposed to a differential input error volt-age for a voltage feedback op amp) and passes this on to theoutput through an internal frequency dependent transimped-ance gain. The Typical Characteristics show this open-looptransimpedance response. This is analogous to the open-loop voltage gain curve for a voltage feedback op amp.Developing the transfer function for the circuit of Figure 10gives Equation 1:

(1)

VV

RR

R RRR

Z

NGR R NG

Z

NGRR

O

I

F

G

F IF

G

S

F I

S

F

G

=+

++ +

=+ +

= +

αα

1

1

1 1

1

( )

( )

This is written in a loop-gain analysis format where the errorsarising from a non-infinite open-loop gain are shown in thedenominator. If Z(s) was infinite over all frequencies, thedenominator of Equation 1 would reduce to 1 and the idealdesired signal gain shown in the numerator would be achieved.The fraction in the denominator of Equation 1 determines thefrequency response. Equation 2 shows this as the loop-gainequation.

(2)

Z

R R NGLoop GainS

F I

( )

+=

If 20 • log(RF + NG • RI) were drawn on top of the open-looptransimpedance plot, the difference between the two wouldbe the loop gain at a given frequency. Eventually, Z(s) rollsoff to equal the denominator of Equation 2 at which point theloop gain has reduced to 1 (and the curves have intersected).This point of equality is where the amplifier’s closed-loopfrequency response given by Equation 1 will start to roll off,and is exactly analogous to the frequency at which the noisegain equals the open-loop voltage gain for a voltage feed-back op amp. The difference here is that the total impedancein the denominator of Equation 2 may be controlled some-what separately from the desired signal gain (or NG).

The OPA683 is internally compensated to give a maximallyflat frequency response for RF = 1.2kΩ at NG = 2 on ±5Vsupplies. That optimum value goes to 1.4kΩ on a single +5Vsupply. Normally, with a current feedback amplifier, it ispossible to adjust the feedback resistor to hold this band-width up as the gain is increased. The CFBplus architecturehas reduced the contribution of the inverting input impedanceto provide exceptional bandwidth to higher gains withoutadjusting the feedback resistor value. The Typical Character-istics show the small-signal bandwidth over gain with a fixedfeedback resistor.

At very high gains, 2nd-order effects in the buffer outputimpedance cause the overall response to peak up. If desired,it is possible to retain a flatter frequency response at highergains by adjusting the feedback resistor to higher values asthe gain is increased. Figure 11 shows the empirically deter-mined feedback resistor and resulting –3dB bandwidth fromgains of +2 to +100 to hold a < 0.5dB peaked response.Here, since a slight peaking was allowed, a lower nominal RF

is suggested at a gain of +2 giving > 250MHz bandwidth.This exceeds that shown in the Electrical Characteristics dueto the slightly lower feedback resistor allowing a modestpeaking in the response. Figure 12 shows the measuredfrequency response curves with the adjusted feedback resis-tor value. While the bandwidth for this low-power part doesreduce at higher gains, going over a 50:1 gain range givesonly a factor of 10 bandwidth reduction. The 25MHz band-width at a gain of 100V/V is equivalent to a 2.5GHz gainbandwidth product voltage feedback amplifier capability. Evenbetter bandwidth retention to higher gains can be deliveredby the slightly higher quiescent power OPA684.

3900

3400

2900

2400

1900

1400

900

Voltage Gain (V/V)

2 2010

RF

5 50 100

Fee

dbac

k R

esis

tor

(Ω)

325

275

225

175

125

75

25

Ban

dwid

th (

MH

z)

–3dB Bandwidth

VO = 0.5VPP

3

0

–3

–6

–9

–12

Frequency (MHz)

1 20010 100

No

rma

lize

d G

ain

(d

B)

G = 5

G = 100

G = 2

G = 10

G = 50

G = 20

FIGURE 11. Bandwidth and RF Optimized vs Gain.

FIGURE 12. Small-Signal Frequency Response with Opti-mized RF.


OUTPUT CURRENT AND VOLTAGE

The OPA683 provides output voltage and current capabilitiesthat can support the needs of driving doubly-terminated 50Ωlines. Changing the 1kΩ load in Figure 1 to a 100Ω will givea total load that is the parallel combination of the 100Ω loadand the 2.4kΩ total feedback network impedance. This 96Ωload will require no more than 36mA output current to supporta ±3.5V output voltage swing. This is within the specifiedminimum output current of +58mA/–45mA over the full tem-perature range.

The specifications described above, though familiar in theindustry, consider voltage and current limits separately. Inmany applications, it is the voltage • current, or V-I product,which is more relevant to circuit operation. Refer to the“Output Voltage and Current Limitations” plot in the TypicalCharacteristics. The X and Y axes of this graph show thezero-voltage output current limit and the zero-current outputvoltage limit, respectively. The four quadrants give a moredetailed view of the OPA683’s output drive capabilities.Superimposing resistor load lines onto the plot shows theavailable output voltage and current for specific loads.

The minimum specified output voltage and current overtemperature are set by worst-case simulations at the coldtemperature extreme. Only at cold startup will the outputcurrent and voltage decrease to the numbers shown in theElectrical Specifications. As the output transistors deliverpower, their junction temperatures will increase, decreasingtheir VBE’s (increasing the available output voltage swing)and increasing their current gains (increasing the availableoutput current). In steady state operation, the availableoutput voltage and current will always be greater than thatshown in the over-temperature specifications since the out-put stage junction temperatures will be higher than theminimum specified operating ambient.

To maintain maximum output stage linearity, no output shortcircuit protection is provided. This will not normally be aproblem since most applications include a series matchingresistor at the output that will limit the internal power dissipa-tion if the output side of this resistor is shorted to ground.However, shorting the output pin directly to the adjacentpositive power-supply pin (8-pin packages) will, in mostcases, destroy the amplifier. If additional short-circuit protec-tion is required, consider a small series resistor in the power-supply leads. This will, under heavy output loads, reduce theavailable output voltage swing. A 5Ω series resistor in eachpower-supply lead will limit the internal power dissipation toless than 1W for an output short circuit while decreasing theavailable output voltage swing only 0.25V for up to 50mAdesired load currents. Always place the 0.1µF power-supplydecoupling capacitors after these supply current limitingresistors directly on the supply pins.

DRIVING CAPACITIVE LOADS

One of the most demanding and yet very common loadconditions for an op amp is capacitive loading. Often, thecapacitive load is the input of an ADC—including additionalexternal capacitance which may be recommended to im-

prove ADC linearity. A high-speed, high open-loop gainamplifier like the OPA683 can be very susceptible to de-creased stability and closed-loop response peaking when acapacitive load is placed directly on the output pin. When theamplifier’s open-loop output resistance is considered, thiscapacitive load introduces an additional pole in the signalpath that can decrease the phase margin. Several externalsolutions to this problem have been suggested. When theprimary considerations are frequency response flatness, pulseresponse fidelity and/or distortion, the simplest and mosteffective solution is to isolate the capacitive load from thefeedback loop by inserting a series isolation resistor betweenthe amplifier output and the capacitive load. This does noteliminate the pole from the loop response, but rather shifts itand adds a zero at a higher frequency. The additional zeroacts to cancel the phase lag from the capacitive load pole,thus increasing the phase margin and improving stability.

The Typical Characteristics show the recommended “RS vsCapacitive Load” and the resulting frequency response at theload. The 1kΩ resistor shown in parallel with the loadcapacitor is a measurement path and may be omitted.Parasitic capacitive loads greater than 3pF can begin todegrade the performance of the OPA683. Long PC boardtraces, unmatched cables, and connections to multiple de-vices can easily cause this value to be exceeded. Alwaysconsider this effect carefully, and add the recommendedseries resistor as close as possible to the OPA683 output pin(see Board Layout Guidelines).

DISTORTION PERFORMANCE

The OPA683 provides low distortion in a very low poweramplifier. The CFBplus architecture also gives two significantareas of distortion improvement. First, in operating regionswhere the 2nd-harmonic distortion due to output stagenonlinearities is very low (frequencies < 1MHz, low outputswings into light loads) the linearization at the inverting nodeprovided by the CFBplus design gives 2nd-harmonic distor-tions that extend into the –90dBc region. Previous currentfeedback amplifiers have been limited to approximately–85dBc due to the nonlinearities at the inverting input. Thesecond area of distortion improvement comes in a distortionperformance that is more gain independent than prior solu-tions. To the extent that the distortion at a particular outputpower is output stage dependent, 2nd-harmonic particularly,and to a lesser extend 3rd-harmonic distortion, is constant asthe gain is increased. This is due to the constant loop gainversus signal gain provided by the CFBplus design. As shownin the Typical Characteristics, while the 2nd-harmonic isconstant with gain, the 3rd-harmonic degrades at highergains.

Relative to alternative amplifiers with < 1mA supply current,the OPA683 holds much lower distortion at higher frequen-cies (> 5MHz) and to higher gains. Generally, until thefundamental signal reaches very high frequency or powerlevels, the 2nd-harmonic will dominate the distortion with alower 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortionslightly for the OPA683. Remember that the total load in-


cludes the feedback network—in the noninverting configura-tion (see Figure 1) this is the sum of RF + RG, while in theinverting configuration it is just RF. Also, providing an addi-tional supply decoupling capacitor (0.1µF) between the sup-ply pins (for bipolar operation) improves the 2nd-order distor-tion slightly (3dB to 6dB).

In most op amps, increasing the output voltage swing in-creases harmonic distortion directly. A low-power part like theOPA683 includes quiescent boost circuits to provide the full-power bandwidth shown. These act to increase the bias in avery linear fashion only when high slew rate or output powerare required. The Typical Characteristics show the 2nd-har-monic increasing slightly from 500mVPP to 5VPP outputs whilethe 3rd-harmonics also increase with output power.

The OPA683 has an extremely low 3rd-order harmonic distor-tion—particularly for light loads and at lower frequencies. Thisalso gives low 2-tone, 3rd-order intermodulation distortion asshown in the Typical Characteristics. Since the OPA683includes internal power boost circuits to retain good full-powerperformance at high frequencies and outputs, it does not showa classical 2-tone, 3rd-order intermodulation intercept charac-teristic. Instead, it holds relatively low and constant 3rd-orderintermodulation spurious levels over power. The Typical Char-acteristics show this spurious level as a dBc below the carrierat fixed center frequencies swept over single-tone voltageswing at a 1kΩ load. Very light loads such as ADC inputs forwill see < –85dBc 3rd-order spurious to 1MHz for full-scaleinputs. For much lower 3rd-order intermodulation distortionthrough 200MHz, consider the OPA685.

NOISE PERFORMANCE

Wideband current-feedback op amps generally have a higheroutput noise than comparable voltage feedback op amps. TheOPA683 offers an excellent balance between voltage andcurrent noise terms to achieve low output noise in a low- poweramplifier. The inverting current noise (11.6pA/√Hz) is lowerthan most other current feedback op amps while the inputvoltage noise (4.4nV/√Hz) is lower than any unity-gain stable,comparable slew rate, voltage feedback op amp. This low inputvoltage noise was achieved at the price of higher noninvertinginput current noise (5.1pA/√Hz). As long as the AC sourceimpedance looking out of the noninverting node is less than300Ω, this current noise will not contribute significantly to thetotal output noise. The op amp input voltage noise and the twoinput current noise terms combine to give low output noiseunder a wide variety of operating conditions. Figure 13 showsthe op amp noise analysis model with all the noise termsincluded. In this model, all noise terms are taken to be noisevoltage or current density terms in either nV/√Hz or pA/√Hz.

The total output spot noise voltage can be computed as thesquare root of the sum of all squared output noise voltagecontributors. Equation 3 shows the general form for theoutput noise voltage using the terms shown in Figure 13.

(3)

E E I R kTR G I R kTR GO NI BN S S N BI F F N= + ( ) +

+ ( ) +2 2 2 2

4 4

4kTRG

RG

RF

RS

OPA683

IBI

EO

IBN

4kT = 1.6E –20Jat 290°K

ERS

ENI

4kTRS√

4kTRF√

Dividing this expression by the noise gain (NG = (1 + RF/RG))will give the equivalent input referred spot noise voltage at thenoninverting input, as shown in Equation 4.

(4)

E E I R kTRI RG

kTRGN NI BN S S

BI F

N

F

N= + ( ) + +

+2 22

44

Evaluating these two equations for the OPA683 circuit andcomponent values (see Figure 1) will give a total output spotnoise voltage of 17.6nV/√Hz and a total equivalent input spotnoise voltage of 8.8nV/√Hz. This total input referred spotnoise voltage is higher than the 4.4nV/√Hz specification forthe op amp voltage noise alone. This reflects the noiseadded to the output by the inverting current noise times thefeedback resistor. As the gain is increased, this fixed outputnoise power term contributes less to the total output noiseand the total input referred voltage noise given by Equation3 will approach just the 4.4nV/√Hz of the op amp itself. Forexample, going to a gain of +20 in the circuit of Figure 1,adjusting only the gain resistor to 63.2Ω, will give a total inputreferred noise of 4.6nV/√Hz. A more complete description ofop amp noise analysis can be found in the TI application noteAB-103 (SBOA066). Refer to Texas Instruments’ web site atwww.ti.com.

DC ACCURACY AND OFFSET CONTROL

A current-feedback op amp like the OPA683 provides excep-tional bandwidth in high gains, giving fast pulse settling butonly moderate DC accuracy. The Electrical Characteristicsshow an input offset voltage comparable to high slew ratevoltage-feedback amplifiers. However, the two input biascurrents are somewhat higher and are unmatched. Whereasbias current cancellation techniques are very effective withmost voltage feedback op amps, they do not generallyreduce the output DC offset for wideband current-feedbackop amps. Since the two input bias currents are unrelated inboth magnitude and polarity, matching the source imped-ance looking out of each input to reduce their error contribu-tion to the output is ineffective. Evaluating the configurationof Figure 1, using worst case +25°C input offset voltage and

FIGURE 13. Op Amp Noise Analysis Model.


the two input bias currents, gives a worst case output offsetrange equal to:

±(NG • VOS(MAX)) ± (IBN • RS/2 • NG) ± (IBI • RF)

where

NG = noninverting signal gain

= ±(2 • 3.5mV) ± (4µA • 25Ω • 2) ± (1.2kΩ • 10µA)

= ±7mV ± 0.1mV ± 12mV

= ±19.1mV

While the last term, the inverting bias current error, is dominantin this low-gain circuit, the input offset voltage will become thedominant DC error term as the gain exceeds 4V/V. Whereimproved DC precision is required in a high-speed amplifier,consider the OPA642 single and OPA2822 dual voltage-feedback amplifiers.

DISABLE OPERATION

The OPA683 provides an optional disable feature that maybe used to reduce system power when channel operation isnot required. If the VDIS control pin is left unconnected, theOPA683 will operate normally. To disable, the control pinmust be asserted LOW. Figure 14 shows a simplified internalcircuit for the disable control feature.

In normal operation, base current to Q1 is provided throughthe 250kΩ resistor while the emitter current through the 40kΩresistor sets up a voltage drop that is inadequate to turn onthe two diodes in Q1’s emitter. As VDIS is pulled LOW,additional current is pulled through the 40kΩ resistor eventu-ally turning on these two diodes (≈ 33µA). At this point, anyfurther current pulled out of VDIS goes through those diodesholding the emitter-base voltage of Q1 at approximately 0V.

25kΩ 250kΩ

40kΩ

ISControl –VS

+VS

VDIS

Q1

FIGURE 14. Simplified Disable Control Circuit.

This shuts off the collector current out of Q1, turning theamplifier off. The supply current in the disable mode are onlythose required to operate the circuit of Figure 14.

When disabled, the output and input nodes go to a highimpedance state. If the OPA683 is operating in a gain of +1(with a 1.2kΩ feedback resistor still required for stability), thiswill show a very high impedance (1.7pF || 1MΩ) at the outputand exceptional signal isolation. If operating at a gain greaterthan +1, the total feedback network resistance (RF + RG) willappear as the impedance looking back into the output, butthe circuit will still show very high forward and reverseisolation. If configured as an inverting amplifier, the input andoutput will be connected through the feedback networkresistance (RF + RG) giving relatively poor input to outputisolation.

The OPA683 provides very high power gain on low quiescentcurrent levels. When disabled, internal high impedance nodesdischarge slowly which, with the exceptional power gainprovided, give a self powering characteristic that leads to aslow turn off characteristic. Typical full turn off times to rated100µA disabled supply current are 60ms. Turn on times arevery fast—less than 40ns.

THERMAL ANALYSIS

The OPA683 will not require external heat-sinking for mostapplications. Maximum desired junction temperature will setthe maximum allowed internal power dissipation as de-scribed below. In no case should the maximum junctiontemperature be allowed to exceed 175°C.

Operating junction temperature (TJ) is given by TA + PD • θJA.The total internal power dissipation (PD) is the sum ofquiescent power (PDQ) and additional power dissipated in theoutput stage (PDL) to deliver load power. Quiescent power issimply the specified no-load supply current times the totalsupply voltage across the part. PDL will depend on therequired output signal and load but would, for a groundedresistive load, be at a maximum when the output is fixed ata voltage equal to 1/2 either supply voltage (for equal bipolarsupplies). Under this condition PDL = VS

2/(4 • RL) where RL

includes feedback network loading.

Note that it is the power in the output stage and not into theload that determines internal power dissipation.

As an absolute worst case example, compute the maximumTJ using an OPA683IDBV (SOT23-6 package) in the circuitof Figure 1 operating at the maximum specified ambienttemperature of +85°C and driving a grounded 100Ω load.

PD = 10V • 1.05mA + 52 /(4 • (100Ω || 2.4kΩ)) = 76mW

Maximum TJ = +85°C + (0.076W • 150°C/W) = 96°C.

This maximum operating junction temperature is well belowmost system level targets. Most applications will be lowerthan this since an absolute worst case output stage powerwas assumed in this calculation.


BOARD LAYOUT GUIDELINES

Achieving optimum performance with a high frequency am-plifier like the OPA683 requires careful attention to boardlayout parasitics and external component types. Recommen-dations that will optimize performance include:

a) Minimize parasitic capacitance to any AC ground forall of the signal I/O pins. Parasitic capacitance on theoutput and inverting input pins can cause instability: onthe noninverting input, it can react with the source imped-ance to cause unintentional band-limiting.. To reduceunwanted capacitance, a window around the signal I/Opins should be opened in all of the ground and powerplanes around those pins. Otherwise, ground and powerplanes should be unbroken elsewhere on the board.

b) Minimize the distance (< 0.25") from the power-supplypins to high frequency 0.1µF decoupling capacitors.At the device pins, the ground and power-plane layoutshould not be in close proximity to the signal I/O pins.Avoid narrow power and ground traces to minimize induc-tance between the pins and the decoupling capacitors.The power-supply connections should always be decoupledwith these capacitors. An optional supply decouplingcapacitor across the two power supplies (for bipolar op-eration) will improve 2nd-harmonic distortion performance.Larger (2.2µF to 6.8µF) decoupling capacitors, effective atlower frequency, should also be used on the main supplypins. These may be placed somewhat farther from thedevice and may be shared among several devices in thesame area of the PC board.

c) Careful selection and placement of external compo-nents will preserve the high frequency performanceof the OPA683. Resistors should be a very low reactancetype. Surface-mount resistors work best and allow atighter overall layout. Metal film and carbon compositionaxially-leaded resistors can also provide good high fre-quency performance. Again, keep their leads and PCboard trace length as short as possible. Never use wire-wound type resistors in a high-frequency application.Since the output pin and inverting input pin are the mostsensitive to parasitic capacitance, always position thefeedback and series output resistor, if any, as close aspossible to the output pin. Other network components,such as noninverting input termination resistors, shouldalso be placed close to the package. Where double sidecomponent mounting is allowed, place the feedback resis-tor directly under the package on the other side of theboard between the output and inverting input pins. Thefrequency response is primarily determined by the feed-back resistor value as described previously. Increasing itsvalue will reduce the peaking at higher gains, whiledecreasing it will give a more peaked frequency responseat lower gains. The 1.2kΩ feedback resistor used in theElectrical Characteristics at a gain of +2 on ±5V supplies

is a good starting point for design. Note that a 1.2kΩfeedback resistor, rather than a direct short, is required forthe unity-gain follower application. A current-feedback opamp requires a feedback resistor even in the unity-gainfollower configuration to control stability.

d) Connections to other wideband devices on the boardmay be made with short direct traces or throughonboard transmission lines. For short connections, con-sider the trace and the input to the next device as alumped capacitive load. Relatively wide traces (50mils to100mils) should be used, preferably with ground andpower planes opened up around them. Estimate the totalcapacitive load and set RS from the plot of recommendedRS versus capacitive load. Low parasitic capacitive loads(< 5pF) may not need an RS since the OPA683 isnominally compensated to operate with a 2pF parasiticload. If a long trace is required, and the 6dB signal lossintrinsic to a doubly-terminated transmission line is ac-ceptable, implement a matched impedance transmissionline using microstrip or stripline techniques (consult anECL design handbook for microstrip and stripline layouttechniques). A 50Ω environment is normally not neces-sary on board, and in fact a higher impedance environ-ment will improve distortion as shown in the distortionversus load plots. With a characteristic board trace imped-ance defined based on board material and trace dimen-sions, a matching series resistor into the trace from theoutput of the OPA683 is used as well as a terminatingshunt resistor at the input of the destination device.Remember also that the terminating impedance will bethe parallel combination of the shunt resistor and the inputimpedance of the destination device: this total effectiveimpedance should be set to match the trace impedance.The high output voltage and current capability of theOPA683 allows multiple destination devices to be handledas separate transmission lines, each with their own seriesand shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long tracecan be series-terminated at the source end only. Treat thetrace as a capacitive load in this case and set the seriesresistor value as shown in the plot of “RS vs CapacitiveLoad”. This will not preserve signal integrity as well as adoubly-terminated line. If the input impedance of thedestination device is LOW, there will be some signalattenuation due to the voltage divider formed by the seriesoutput into the terminating impedance.

e) Socketing a high-speed part like the OPA683 is notrecommended. The additional lead length and pin-to-pincapacitance introduced by the socket can create an ex-tremely troublesome parasitic network which can make italmost impossible to achieve a smooth, stable frequencyresponse. Best results are obtained by soldering theOPA683 onto the board.


INPUT AND ESD PROTECTIONThe OPA683 is built using a very high speed complementarybipolar process. The internal junction breakdown voltagesare relatively low for these very small geometry devices.These breakdowns are reflected in the Absolute MaximumRatings table where an absolute maximum 13V across thesupply pins is reported. All device pins have limited ESDprotection using internal diodes to the power supplies asshown in Figure 15.

These diodes provide moderate protection to input overdrivevoltages above the supplies as well. The protection diodescan typically support 30mA continuous current. Where highercurrents are possible (e.g. in systems with ±15V supply partsdriving into the OPA683), current limiting series resistorsshould be added into the two inputs. Keep these resistorvalues as low as possible since high values degrade bothnoise performance and frequency response.

ExternalPin

+VCC

–VCC

InternalCircuitry

FIGURE 15. Internal ESD Protection.


Revision History

DATE REVISION PAGE SECTION DESCRIPTION

Changed Storage Temperature Range from −40°C to +125C to−65°C to +125C.

3, 4 Electrical Characteristics, Added minimum supply voltage.Power Supply

15 Design-In Tools Board part number changed.

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

3/06 D

7/08 E2 Abs Max Ratings

PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2014

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

OPA683ID ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA683

OPA683IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 A83

OPA683IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS& no Sb/Br)


OPA683IDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS& no Sb/Br)


OPA683IDG4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)


OPA683IDR ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)


(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

http://www.ti.com/product/OPA683?CMP=conv-poasamples#samplebuy






http://www.ti.com/productcontent

PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2014

Addendum-Page 2

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

OPA683IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 13-Jan-2018

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

OPA683IDR SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 13-Jan-2018

Pack Materials-Page 2

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very low-power, current feedback operational … = 1.2kΩ, rl = 1kΩ, and g = +2 (see figure 1 for...

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