verilog basics 4 blocks condstatement loops

7/31/2019 Verilog Basics 4 Blocks CondStatement Loops

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Digital System Design

Verilog:

Blocks, Conditional Statement, Loops

Dr. Bassam Jamil


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33

Block Types


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always and initial block syntax

Initial block syntax:Initial beginstatement1;statement2;.

End

OR Initial statement;

always block syntaxalways @ ( sensitivity list) begin

.

end

ORalways @ ( * )

begin . end


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Initial Block


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Initial Block Example


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always Block

module clock_gen

reg_clk;

initialclk = 1b0;

always @ (clk)

#10 clk = ~ clk ;

initial begin#1000 $finish;

end

endmodule


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always Block

module clock_gen

reg_clk;

initialclk = 1b0;

always @ (clk)#10 clk = ~ clk ;

initial begin#1000 $finish;

end

endmodule


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More always Block Examples

Always Block Examples Notes

always @(a or b or ci)

begin

sum = a + b + ci;end

always block executes

statements repeatedly.

always @(posedge clk)q


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Mux4 Example

Implement Mux4 using Structural

Behavioral data flow)

Behavioral procedural using if statement

Behavioral procedural using case statement

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Conditional Statements

If statement syntax: if(expression) statement or statement_group

if(expression) statement or statement_group

else statement or statement_group


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Conditional Statements: Nested If


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Conditional Statements: Multi-way If


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Conditional Statements: case statement

Case syntaxcase (net_or_register_or_literal)

case_match1: statement or statement_group

case_match2,

case_match3: statement or statement_group

default: statement or statement_group

endcase


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Conditional Statements: casex/casez

casez (net_or_register_or_literal)

Special version of the case statement which uses a Zlogic value to represent don't-care bits.

casex (net_or_register_or_literal)

Special version of the case statement which uses Z or

X logic values to represent don't-care bits.


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Conditional Statements: case statement


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Loop Statements


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Forever

reg clk;Initial begin

clk = 0;

forever #10 clk = ~ clk;

end

Syntax:foreverstatement or statement_group


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Repeat

Wait for

5 clocks

Syntax:

repeat (number)

statement orstatement_group


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While Statement

Syntax:while (expression)

statement orstatement_group

Count number of 1s inregisterin


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For Statement

Sntax:

for(initial_assignment;

expression;

step_assignment)

statement or statement_group


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Parallel Statements

Syntax:fork

statement1;

statement2;

statementN;

join

All statements

start at the

same time.


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Parallel Statements

begin/end and fork/join blocks

have same effect


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Named Block and disable statement

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Mux4 Modeling

Will model the mux4 in various modeling styles: Structural

Behavioral Continuous Assignment

Behavioral Procedural using if statement

Behavioral Procedural using case statement

S


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Structural to Behavioral

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M B h i l (C i )


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Mux 4 Behavioral (Cont. assign)

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M 4 E l


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Mux4 Example

verilog basics 4 blocks condstatement loops

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