verilog a users

Verilog-AUser’s Manual Draft

SILVACO International January 20044701 Patrick Henry Drive, Bldg. #2Santa Clara, CA 95054 Telephone: (408) 567-1000FAX: (408) 496-6080

Verilog-AUser’s ManualCopyright 2004

SILVACO International4701 Patrick Henry Drive, Building #2

Santa Clara, CA 95054

Phone: (408) 567-1000FAX: (408) 496-6080E-Mail: [email protected]: www.silvaco.com

ii SILVACO International

Notice

The information contained in this document is subject to change without notice.

SILVACO International MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE.

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This document contains proprietary information, which is protected by copyright. All rights are reserved. No part of this document may be photocopied, reproduced, or translated into another language without the prior written consent of SILVACO International.

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SILVACO International iii

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iv SILVACO International

Preface

This manual describes SILVACO VERILOG®-A language, the analog subset of the Verilog-AMS version 2.0 language (IEEE 1364). VERILOG-A belongs to the "Analog Hardware Description Language" (AHDL) class of computer languages. AHDLs are intended to help design analog systems in high level behavioral forms for continuous systems.

The SMARTSPICE VERILOG-A INTERFACE provides the capability to include in a netlist one or several modules described in VERILOG-A.

Requirements

The VERILOG-A INTERFACE is supported on the following UNIX platforms: Sun Solaris 2.7 and 2.8, Red Hat linux 7.3 and HP 11.0. VERILOG-A is also supported on Windows NT 4.0, Windows 2000 or XP. On the UNIX platforms, a C compiler (the gcc compiler, 2.8.1 or 2.95.3, or the SUN C compiler, SC4 or SC6) could be be used in the VERILOG-A simulation flow for a speedup purpose. The intention of this manual is not to explain in detail all the features of the VERILOG-A language. For further information, the reader should consult the LANGUAGE REFERENCE MANUAL OF VERILOG-A, version 2.0 provided by Accellera (formerly OVI).

Typographic and Syntax Conventions

Typographical conventions are used to emphasize or distinguish certain kinds of text in this manual. The formal syntax used in this document uses the definition operator, := , to define and describe the elements of the VERILOG-A language.

• Lowercase words represent syntactic categories. For example:module_declaration

• Some names begin with a part that indicates how the name is used. For example:node_identifier

represents an identifier that is used to declare or reference a node.

• Boldface words represent elements of the syntax that must be used exactly as presented. Such items include keywords, operators, and punctuation marks. For example:endmodule

• Vertical bars indicate alternatives. One can choose to use any one of the items separated by the bars. For example:attribute ::=abstol| access| ddt_nature| idt_nature| units| huge //Vendor compactibility specific| blowup //Vendor compactibility specific| identifier

• Square brackets enclose optional items. For example,input declaration ::=input [ range ] list_of_port_identifiers ;

• Braces enclose an item that can be repeated zero or more times. For example,list_of_ports ::=( port , port )

• Code examples are displayed in Courier font./* This is an example of Courier font.*/

SILVACO International v

• Within the text, the variables are in Courier italic. This is Courier italic font.

• Within the text, the keywords, filenames, names of natures, and names of disciplines are set in Courier font, like this: keyword, file_name, name_of_nature, name_of_discipline.

• If a statement is too long to fit on one line, the remainder of the statement is indented on the next line, like this:egfet = 1.16-(7.02e-4*$temperature*$temperature)

/($temperature+1108);

vi SILVACO International

Table of Contents

Chapter 1:Modeling Analog System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1: Modeling with the Verilog-A Language Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11.2: Representing a System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.2.1: Nets and nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11.3: Verilog-A Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21.4: Conservative Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.4.1: Kirchhoff’s Laws . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31.4.2: Reference Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41.4.3: Reference Directions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.5: Signal-Flow Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41.6: Mixed Conservative and Signal-Flow Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Chapter 2:Makeup of Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1: Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12.2: Declaring Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22.3: Declaring the Module Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.3.1: Module Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32.3.2: Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32.3.3: Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.4: Structural Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-72.4.1: Module Instantiations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.5: Behavioral Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-102.5.1: Defining Analog Behavior with Control Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-112.5.2: Using Integration and Differentiation with Analog Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.6: Using Internal Nodes in Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-142.6.1: Using Internal Nodes in Behavioral Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-142.6.2: Using Internal Nodes in Higher Order Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

Chapter 3:Lexical Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1: Lexical Tokens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13.2: White Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13.3: Comments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23.4: Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23.5: Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.5.1: Integer Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23.5.2: Real Constants. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.6: Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53.6.1: Special Characters in Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.7: Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63.7.1: Ordinary Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63.7.2: Escaped Identifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

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Verilog-A User’s Manual

3.8: Keywords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73.9: System Tasks and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-93.10: Compiler Directives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Chapter 4:Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1: Integer Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14.2: Real Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.2.1: Converting Real Numbers to Integer Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24.3: Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.3.1: A Parameter Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34.3.2: Permissible Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44.3.3: Parameter Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54.3.4: Genvars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.4: Natures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-64.4.1: Base Nature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-74.4.2: Derived Nature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

4.5: Disciplines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-104.5.1: Binding Natures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-104.5.2: Compatibility of Disciplines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-114.5.3: Multi-Disciplinary Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-134.5.4: Empty Disciplines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-144.5.5: Discipline of Wires and Undeclared Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-144.5.6: Overriding Nature Attributes From Discipline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-144.5.7: Deriving Natures From Disciplines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-154.5.8: Ground Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15

4.6: Net Disciplines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-164.7: Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-164.8: Implicit Branches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17

Chapter 5:Statements for the Analog Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1: Analog Procedural Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15.1.1: Block Statements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15.1.2: Procedural Assignment Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.2: Sequential Block Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35.3: Conditional Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.3.1: Analog Conditional Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55.4: Case Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

5.4.1: Analog Case Statements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55.4.2: Constant Expression in Case Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5.5: Looping Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65.5.1: Repeat and While Statements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65.5.2: For Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5.6: Analog Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-75.7: Signal Access Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-75.8: Probes and Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

5.8.1: Probes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-95.8.2: Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-95.8.3: The four controlled sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

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5.8.4: Behavioral Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-105.8.5: Resistor and Conductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-115.8.6: RLC Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-115.8.7: Simple Implicit Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-125.8.8: Port Branches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

5.9: Switch Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-135.9.1: Unassigned Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14

5.10: Signal Access for Vector Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-145.10.1: Accessing Net and Branch Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-165.10.2: Accessing Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16

5.11: Contribution Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-175.11.1: Branch Contribution Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-175.11.2: Relations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-185.11.3: Evaluation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-185.11.4: Value Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-195.11.5: Indirect Branch Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-195.11.6: Multiple Indirect Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-215.11.7: Indirect Assignments and Contributions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21

Chapter6:Expressions and Operators for Analog Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.1: Overview of Expressions and Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16.2: Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.2.1: Operators With Real Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26.2.2: Real to Integer Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26.2.3: Arithmetic Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36.2.4: Binary Operator Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36.2.5: Expression Evaluation Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46.2.6: Arithmetic Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46.2.7: Relation Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66.2.8: Case Equality Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66.2.9: Logical Quality Operators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66.2.10: Logical Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-76.2.11: Bit-Wise Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-76.2.12: Shift Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-96.2.13: Ternary Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-96.2.14: Event OR Operator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-96.2.15: Concatenations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10

6.3: Analog Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-116.3.1: Restrictions To Analog Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-116.3.2: Vector or Array Arguments To Analog Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-116.3.3: Analog Operators and Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-126.3.4: Time Derivative Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-126.3.5: Time Integral Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-126.3.6: Circular Integrator Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-136.3.7: Absolute Delay Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-146.3.8: Transition Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-156.3.9: Slew Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-206.3.10: last_crossing function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-226.3.11: Laplace Transform Filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-226.3.12: Z-Transform Filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-256.3.13: Limited Exponential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27

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Chapter7:Built-In Mathematical Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.1: Standard Mathematical Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17.2: Trigonometric and Hyperbolic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

Chapter 8:Analog Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.1: Detecting and Using Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18.1.1: Event Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18.1.2: Event OR Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28.1.3: Event Triggered Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28.1.4: Global Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28.1.5: Monitored Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

Chapter 9:Simulator Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.1: Analysis Dependent Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19.1.1: Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19.1.2: AC stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29.1.3: Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.2: Discontinuity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-59.3: Bounding the Time Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-79.4: Querying the Simulation Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

9.4.1: Obtaining Current Simulation Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-89.4.2: Obtaining the Current Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-89.4.3: Obtaining the Thermal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9

9.5: Generating Random Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-99.6: Generating Random Numbers in Specified Distributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11

9.6.1: Uniform Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-119.6.2: Normal (Gaussian) Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-129.6.3: Exponential Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-129.6.4: Poisson Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-139.6.5: Chi-Square Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-149.6.6: Student’s T Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-149.6.7: Erlang Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15

9.7: Silvaco System Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-169.7.1: $sit_get_prev . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-169.7.2: $sit_get_ddv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16

9.8: Displaying Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-179.9: Specifying Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-209.10: Working with Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20

9.10.1: Opening a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-209.10.2: Special $fopen Formatting Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-219.10.3: Writing to a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-229.10.4: Closing a File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24

9.11: User-Defined Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-249.11.1: Declaring an Analog User-Defined Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-249.11.2: Returning a Value from a User-Defined Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-259.11.3: Calling a User-Defined Analog Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26

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Chapter 10:Instantiating Modules and Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1

10.1: Instantiating Verilog-A Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-110.1.1: Creating and Naming Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-110.1.2: Mapping Instance Ports to Module Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10.2: Connecting the Ports of Module Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-310.2.1: Port Connection Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-410.2.2: Multilevel Hierarchal Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

10.3: Overriding Parameter Values in Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-710.3.1: Overriding Parameter Values from the Instantiation Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7

10.4: Instantiating Analog Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-910.4.1: B device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-910.4.2: C device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-910.4.3: D device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1010.4.4: E,F,G,H devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1010.4.5: I, V devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1310.4.6: J device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1510.4.7: K, L devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1510.4.8: M device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1610.4.9: O device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1610.4.10: Q device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1610.4.11: R device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1710.4.12: S device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1710.4.13: T device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1710.4.14: U device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1710.4.15: W device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1810.4.16: SPICE Model Card Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1810.4.17: SPICE Subcircuit Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1810.4.18: Instantiating Analog Primitives that Use Array Valued Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 10-1910.4.19: Instantiating Modules that Use Unsupported Parameter Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19

Chapter 11:Grammer Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

Chapter 12:Standard Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

12.1: “discipline.h” content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-112.1.1: "Constants.h" file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7

Chapter 13:The SmartSpice Verilog-A Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1

13.1: Choosing the SILVACO C-INTERPRETER or a third-party C compiler . . . . . . . . . . . . . . . . . . . . . . . . . . 13-213.2: The SmartSpice Verilog-A interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2

13.2.1: New Verilog-A Language Features Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-213.2.2: Attributes HUGE, BLOWUP, MAXDELTA (Cadence Compatibility) . . . . . . . . . . . . . . . . . . . . . . . . . . 13-313.2.3: The power function: $pwr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-313.2.4: The mathematical functions: hypot(x,y) and atan2(x,y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-413.2.5: Analysis Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-413.2.6: Usage of the .PRINT and .PLOT Smartspice commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-413.2.7: Usage of the command .MODIF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5

SILVACO International TOC-xi


13.2.8: Usage of the command .ST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-513.3: The Verilog-A compiler configuration file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-513.4: The .verilog card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-613.5: Module instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-613.6: Model Card with Verilog-A module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-713.7: The Smartspice Verilog-A interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8

13.7.1: DLL support for Windows platforms with the compiler VC++ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-813.8: Verilog-A error and warning messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10

13.8.1: Parsing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1013.8.2: Parsing warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1413.8.3: Simulation errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1513.8.4: Simulation Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16

Chapter 14:Device Modeling in Verilog-A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1

14.1: Device Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-114.2: MOSFET Model Tutorial for Verilog-A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

14.2.1: MOSFET Model Parameter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-214.3: Temperature Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7

14.3.1: Temperature Model Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-714.3.2: DC Current Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1114.3.3: Capacitance Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14

14.4: MOSFET Model LEVEL=3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1514.4.1: Model Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1514.4.2: MOS_LEVEL 3 Verilog-A Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1614.4.3: EKV MOSFET Model - using Silvaco Verilog-A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16

14.5: EKV MOSFET Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1714.5.1: Geometry Device Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1714.5.2: Effective Channel Length and Width Calculations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1714.5.3: Model Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1714.5.4: Handling of LEVEL 2/3 Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2114.5.5: Temperature Compensation Equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2114.5.6: DC Current Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2214.5.7: Charge Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2614.5.8: Noise Model Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28

14.6: Berkeley BSIM3v3 MOSFET Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2914.6.1: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2914.6.2: Model Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2914.6.3: Effective Channel Length and Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3914.6.4: Temperature Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3914.6.5: I-V Model Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4014.6.6: Capacitance Model Equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4414.6.7: NQS Model Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-54

14.7: Berkeley MOSFET Model BSIM4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5514.7.1: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5514.7.2: Instance Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5514.7.3: Effective Channel Length and Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6614.7.4: Gate Dielectric Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6714.7.5: Temperature Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6714.7.6: I-V Model Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6914.7.7: Capacitance Model Equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7714.7.8: Asymmetric MOS Junction Diode Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-79

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Table of Contents

14.7.9: Source/Drain Diffusion Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8114.8: BJT Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-82

14.8.1: Gummel-Poon BJT Model Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8214.9: Mextram Transistor Model (LEVEL=504) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-90

14.9.1: Model Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9114.9.2: Model constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9314.9.3: Temperature scaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9414.9.4: Geometry scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9614.9.5: DC current Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9714.9.6: Description of charges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10314.9.7: Extended Modeling of the Reverse Current Gain EXMOD = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10614.9.8: Distributed High Frequency Effects In the Intrinsic Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10814.9.9: Heterojunction features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10914.9.10: Noise Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10914.9.11: Self-heating feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-110

14.10: The HICUM Bipolar Transistor Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11114.10.1: Model Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11214.10.2: Temperature Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11914.10.3: DC Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12214.10.4: Description of Charges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-126

14.11: The VBIC Bipolar Transistor Model (LEVEL=5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ) 14-13014.11.1: VBIC Model Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13014.11.2: DC Current Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13614.11.3: Charge and Capacitance Equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14114.11.4: Excess Phase Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14414.11.5: Temperature Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-144

14.12: Interfacing Verilog-A Compact Model Code to the Input Deck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14814.13: .MODEL Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14814.14: Compiling Verilog-A Compact Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14914.15: Interfacing Verilog-A Compact Model Code to a Schematic Symbol . . . . . . . . . . . . . . . . . . . . . . . . 14-14914.16: Declaring Verilog-A Modules Within a SmartSpice Input Deck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-150

Chapter 15:Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1

15.1: Digital circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-115.1.1: Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-115.1.2: Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-315.1.3: Nand. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-415.1.4: NOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-715.1.5: EXOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1015.1.6: DFF (D-type Flip Flop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1215.1.7: 4bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1515.1.8: 4bit Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16

15.2: Analog Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1715.2.1: LPF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1715.2.2: HPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2015.2.3: BPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21

15.3: Analog Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2315.3.1: OPAMP (Operational Amplifier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2315.3.2: Sample hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2615.3.3: ADC (Pipelined ADC and user defined resolution). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2815.3.4: ADC to DAC Example: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-33

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15.3.5: Delta-Sigma Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3415.4: Example 1: DFF with Spice Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3615.5: Simulation with SmartSpice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3915.6: Example 2: PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-41

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Chapter 1:Modeling Analog System

1.1: Modeling with the Verilog-A Language OverviewThe VERILOG-A language is a high-level Analog Hardware Description Language (AHDL) that uses modules as the basic component to describe the structure and behavior of analog systems and their components. With the analog statements of VERILOG-A, one can describe a wide range of conservative systems and signal-flow systems; such as electrical, mechanical, fluid dynamic, and thermodynamic systems. To simulate systems that contain VERILOG-A components, the user must have a VERILOG-Alicense and the SMARTSPICE SIMULATOR installed on their system.

To describe a system, the user must specify both the structure of the system, and the behavior of its components. In VERILOG-A with the SMARTSPICE CIRCUIT SIMULATOR, the user defines structures at different levels. At the highest level, the user can define the overall system structure in a netlist. At lower, more specific levels, the user can define the internal structure of modules by defining the interconnections among submodules.

1.2: Representing a SystemA system is a collection of interconnected components that when acted upon by a stimulus produce a response. A hierarchical system is a system in which the components are also systems. A primitive component (leaf component) is a component that has no subcomponents. Each primitive component connects to zero or more nets. Each net connects to a signal which can traverse multiple levels of the hierarchy. The behavior of each component is defined in terms of the values of the nets to which it connects. The VERILOG-A language allows analog and mixed-signal systems to be described by a set of components or modules.

A signal is a hierarchical collection of nets which, because port connections, are contiguous. The nets for a signal are in the discrete domain called a digital signal. The nets that make up a signal are in the continuous domain; the signal is an analog signal. The net that consists of signals from the continuous and discrete domains is called a mixed signal.

The components interconnect through ports and nets to build a hierarchy, as illustrated in Figure 1-1.

1.2.1: Nets and nodesNets in VERILOG-A connect analog signals that are assigned values from a continuous domain. A node is a point of physical connection between nets of continuous-time descriptions. Analog signals are also referred to as nodes.

Nodes obey conservation-law semantics.

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Verilog-A User’s Manual Draft

Figure 1-1: Nets and Nodes

1.3: Verilog-A SystemsTwo types of analog systems can be described with VERILOG-A: conservative and signal-flow systems. A conservative type of system, which includes those described by conventional spice, incorporates a set of constraints within the system that insures conservation of changes, fluxes, etc. within the system. Signal flow systems employ a different level of formulations, which focuses only on the propagation of signals throughout the system.

1-2 SILVACO International

Modeling Analog System

1.4: Conservative SystemsA conservative system is a system where two values are assigned to every node: a potential value and a flow value. The potential of a node is shared by all ports and nets connected to it. The flow of a node is such that the sum of all continuous nodes are equal to zero. For this reason, the conservation laws, such as Kirchoff ’s Potential Law (KPL) and Kirchoff’s Flow Law (KFL), can be applied to every node. KPL and KFL are generalizations of KVL and KCL for electrical systems which allow the conservation laws to be applied to any conservative system.

1.4.1: Kirchhoff’s LawsIn formulating continuous system equations, VERILOG-A uses two sets of relationships. The first are the constitutive relationships which describe the behavior of each component. Constitutive relationships can be kept inside the simulator as built-in primitives, or they can be provided by VERILOG-A’s module definitions.

The second set of relationships, interconnected relationships, describe the structure of the network. Interconnected relationships, which contain information on how the components are connected to each other, are only a function of the system topology. They are independent of the nature of the components.

SMARTSPICE VERILOG-A simulator uses Kirchhoff ’s Laws to define the relationships between the nodes and the branches. Kirchhoff ’s Laws are typically associated with electrical circuits that relate voltages and currents. However, by generalizing the concepts of voltages and currents to potentials and flows, Kirchhoff ’s Laws can be used to formulate interconnection relationships for any type of system.

Kirchhoff ’s Laws provide the following properties relating the quantities present on nodes and branches, as shown in Figure 1-2.

• Kirchhoff ’s Flow Law (KFL): The algebraic sum of all flows out of a node at any instant is zero (0).• Kirchhoff ’s Potential Law (KPL): The algebraic sum of all the branch potentials around a loop at

any instant is zero (0).

These laws imply a node is infinitely small; so there is negligible difference in potential between any two points on the node and a negligible accumulation of flow.

Conservative Systems Electrical Systems

KPL KVL

KFL KCL



Figure 1-2: Kirchhoff’s Flow Law (KFL) and Potential Law (KPL)

1.4.2: Reference NodesThe potential of a single node is defined with respect to a reference node. The reference node, called ground in electrical systems, has a potential of zero.

1.4.3: Reference DirectionsEach branch has a reference direction for the potential and flow. For example, consider the following schematic. With the reference direction shown, the potential in this schematic is positive whenever the potential of the terminal marked with a plus sign is larger than the potential of the terminal marked with a minus sign. VERILOG-A uses associated reference directions. Consequently, a positive flow is defined as one that enters the branch through the terminal marked with the plus sign, and exits through the terminal marked with the minus sign.

1.5: Signal-Flow SystemsSignal-flow systems associate only a single value with each node. As a result, a signal-flow port must be unidirectional. If the component has two ports, one port is the input and the other one must be the output.

1.6: Mixed Conservative and Signal-Flow SystemsOne can model systems that contain a mixture of conservative nodes and signal-flow nodes, when practicing the top-down design cycle. It allows the flexibility for the designers to initially use signal-flow models easily in the design cycle, and gradually convert component models to conservative forms as the design progresses.


Chapter 2:Makeup of Modules

2.1: OverviewThis chapter introduces the concept of modules. A VERILOG-A module can be divided into 3 parts:

• The first part is an interface declaration that includes port signal declarations (the connection points of the module) and parameter declarations (characterization of the behavior of the component).

• The second part is the structural description that defines the connection with sub-components. Every module can instantiate other modules, referred to as child modules. This instantiation mechanism allows an hierarchical organization of a system through its parametric specifications and connections.

• The third part is a behavioral description that defines relations or equations between the input signals of the module and the output signals.

Verilog-A Module

The following example defines a temperature compensated resistor to illustrate the form of a module.

The entire module is enclosed between the keywords module and endmodule.

Interface declarations:

module resistor(p, n);

inout p, n; | port signal declarationselectrical p, n; |

parameter real r=100 from (0:inf); | parameter declarationsparameter real tc=1.8 from [0:3); |

module res(in, out);

// port declarationsinout in,out;electrical in, out;

// parameter declarationsparameter real R = 1;

interface declaration

// structural description<module instantiation statements>

structural description

// behavioral descriptionanalog begin<analog behavioral statements>end

endmodule // end module res

behavioral description



Behavioral description:

real rtc;analog begin @(initial_step) begin rtc = r*(1+tc*$temperature); end I(p, n) <+ V(p, n)/rtc;endendmodule

2.2: Declaring ModulesThe following syntax is used to declare a module:

module_declaration ::=module_keyword module_identifier [ ( list_of_ports ) ] ;[ module_items ]endmodule

module_keyword ::= module| macromodule

module_items ::= module_item | analog_block

module_item ::= module_item_declaration | module_instantiation

module_item_declaration ::= parameter_declaration| input_declaration| output_declaration| inout_declaration| ground_declaration| integer_declaration| net_discipline_declaration| real_declaration

module_identifier: The name of the module being declared.list_of_ports: An ordered list of the module’s ports.module_items: The different types of declarations and definitions.


Makeup of Modules

2.3: Declaring the Module InterfaceUse the module interface declarations to define:

• Name of the module• Ports of the module• Parameters of the module

For example, the module interface declaration declares a module named resistor, ports named p and n, and a parameter of type real named r.

module resistor(p, n);inout p, n;electrical p, n;parameter real r = 50;

2.3.1: Module NameTo define the name for a module, put an identifier after the keyword module. Input and output ports are listed in parentheses following the identifier. Multiple parts are separated by commas.

module capacitor(.., ..);

2.3.2: PortsTo declare the ports used in a module, use port declarations. To specify the type and direction of a port, use the related declarations described in this section.

list_of_ports ::=port , port

port ::=port_expression

port_expression ::= port_identifier| port_identifier [ constant_expression ]| port_identifier [ constant_range ]

constant_range ::=msb_constant_expression : lsb_constant_expression

Example

module and(in1, in2, out); // define three ports



Port Type

To declare the type of a port, use a net discipline declaration in the body of the module. If the user does not declare the type of a port, they can only use the port in a structural description. In other words, a user can pass the port to module instances, but cannot access the port in a behavioral description.

Ports declared as vectors must use identical ranges for the port type and port direction declarations.

Examples

electrical out, in1, in2; // types of ports

voltage P, N; // types of ports

m1 and1(out1, ina, inb); // module instantiation (section 2.4.1)

capacitor #(1u) C1(out, ref); // module instantiation (section 2.4.1)

Port Direction

The user must declare the port direction for every port in the list of port sections of the module declaration. To declare the direction of a port, use one of the following three syntaxes.

input_declaration ::= input [ range ] list_of_port_identifiers ;

output_declaration ::= output [ range ] list_of_port_identifiers ;

inout_declaration ::= inout [ range ] list_of_port_identifiers ;

range ::=[ constant_expression : constant_expression ]

Port Declaration Example

Conservative signals:

module conservative(a, b);inout a, b; Ports a, b used on both sides (bidirectional)electrical a, b;

analog V(a, b) <+ I(a, b)*R;

endmodule

input: Declares that the signals on the port cannot be set. Input signals can be used in expressions.

output: Declares that the signals on the port can be set. Output signals cannot be used in expressions.

inout: Declares that the port is bidirectional. The signals on the port can be both set and used in expressions. inout is the default port direction.


Makeup of Modules

Signal-flow signals:

module signal_flow(out, in);voltage out, in;output out; out port used for sourceinput in; in port used for probe

parameter real gain = 8.0;

analog V(out) <+ gain*V(in);

endmodule

2.3.3: ParametersWith parameter declarations, the user specifies parameters that can be changed when a module is used as an instance in a design. Using parameters allows each instance to be customized.

For each parameter the user must specify a default value, and can also specify an optional type and an optional valid range.

Syntax

Examples

parameter real R0 = 1.0;parameter real P0 = 1.0 from (0:inf);parameter integer ip0 = 2 exclude 0;parameter real t0 = 1.0 from (0:10];parameter t2 = 5.0;parameter real t3 = 4;

In all cases, the lower bound range must be numerically smaller than the upper bound range. For more information of the parameter declarations, please see "Chapter 4:" "Data Types".

ParameterOptional type specifier

Parameter name = default value expression

Optional range specification

realor

integer

from or exclude(or[ lower bound : upper bound ]or)



The following example illustrates how to declare parameters and variables in a module.

Module diode has a parameter area that defaults to 4. If area is not specified for an instance, it receives a value of 4. Similarly, the other parameters: is, n, cjo, m, phi, and t_t, have specified default values too.

Module diode also defines three local variables: vd, id, and qd.

Module interface declarations

module diode(p, n);inout p, n;electrical p, n;

Parameter declarations

parameter real area=4;parameter real is=1e-14;parameter real z=2 from (0:10);parameter real cjo=0;parameter real m=0.5;parameter real phi=0.7;parameter real t_t=1p;

real vd, id, qd; //Internal variables (local variables)

Behavioral description

analog begin vd = V(p, n); id = area*is*(exp(vd/(z*$vt)) - 1); qd = t_t*id + area*vd *cjo/pow((1 - vd/phi), m); I(p, n) <+ id + ddt(qd);end

endmodule


Makeup of Modules

2.4: Structural DescriptionsA structural description in VERILOG-A is any description in which a module instantiates another module within its definition. A structural description of the system will connect to one or more signals of each module through the module’s ports or connection points.

2.4.1: Module InstantiationsInstantiation allows one module to duplicate another module into itself by instantiating it. When one module instantiates another, it can modify the values of any parameters declared within the instantiated module, as following:

• Module instance parameter value assignment by port order, called positional association of module parameter. Positional and order are used interchangeably in this manual.

• Module instance parameter by port name, called named association of module parameters.

The general format of module instantiation:

mod_name <#(param_assigns)> inst_name(port_assigns)

where param_assigns (or parameter name in child module) and port_assigns can be either by positional(ordered) or name associated, and they cannot be mixed within a module instantiation.

Positional (Ordered) Association and Assignment of Parameters

The following example will illustrate the positional (ordered) connections of module instantiation.

Example

//module interface declarations for 4 bit A/D

module a2d(d0, d1, d2, d3, in, clk);input in, clk; //direction of portsoutput d0, d1, d2, d3;electrical in, clk; //type of portselectrical d0, d1, d2, d3;

parameter real vrange = 1.0; //default parameter #1parameter real tdel = 10n; //default parameter #2parameter real trise = 10n; //default parameter #3parameter real tfall = 10n; //default parameter #4

...

endmodule

//module interface declarations for 4 bit D/A

module d2a(d0, d1, d2, d3, in, clk);



output out; //direction of portsinput d0, d1, d2, d3, clk;electrical out; //type of portselectrical d0, d1, d2, d3, clk;

parameter real vthresh = 0.7; //default parameter #1parameter real tdel = 10n; //default parameter #2parameter real trise = 10n; //default parameter #3parameter real tfall = 10n; //default parameter #4

...

endmodule

module sum(out, posin, negin);inout out, posin, negin;electrical out, posin, negin;

...

endmodule

module gain(out, in);inout out, in;

...

endmodule

//structural instantiations of all child modules

module sub_a2d(bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7, in, clock);output bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7;input in, clock;electrical bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7;electrical in, clock;

//internal signalselectrical a_out, rem_out, gain_out;

//structure instantiation for new parameter and port ordersa2d #(.vrange(5.0)) //assigned of new parameter vrange = 5.0 lsb_a2d(bit0, bit1, bit2, bit3, gain_out, clock), msb_a2d(bit4, bit5, bit6, bit7, in, clock);

//structure instantiation for new parameter and port ordersd2a #(.vthresh (2.5)) //assigned of new parameter vrange = 2.5 convtr(aout, bit4, bit5, bit6, bit7, clock);


Makeup of Modules

//structure instantiation for port orders onlysum sum1(rem_out, aout);gain gain1(gain_out, rem_out);

endmodule

Since vrange = 1.0 is parameter #1 and tdel = 10ns is parameter #2, respectively, one can rewrite structure instantiation with the new assigned parameter as:

a2d #(5.0) lsb_a2d(bit0, bit1, bit2, bit3, gain_out, clock), msb_a2d(bit4, bit5, bit6, bit7, in, clock);

or can rewrite if all four parameters need to be assigned by their positional orders:

a2d #(5.0, 10n, 15n, 15n) lsb_a2d(bit0, bit1, bit2, bit3, gain_out, clock), msb_a2d(bit4, bit5, bit6, bit7, in, clock);

where port orders of child modules lsb_a2d and msb_a2d are corresponding to ports in the parent module a2d:

Name Association

In addition to ordered or positional association, name association can also be applied.

Example

a2d #(5.0, 10n) lsb_a2d(bit0, bit1, bit2, bit3, gain_out, clock), msb_a2d(bit4, bit5, bit6, bit7, in, clock);

can be written as:

a2d #(.vrange(5.0), .tdel(10n)) lsb_a2d(.d0(bit0), .d1(bit1), .d2(bit2), .d3(bit3), .in(gain_out),

.clk(clock)), msb_a2d(.d0(bit4), .d1(bit5), .d2(bit6), .d3(bit7), .in(in),

.clk(clock));

For more examples of module instantiation, see "Chapter 10:" "Instantiating Modules and Primitives".

a2d (d0, d1, d2, d3, in, clk);

lsb_a2d (bit0, bit1, bit2, bit3, gain_out, clock),

msb_a2d (bit4, bit5, bit6, bit7, in, clock);



2.5: Behavioral DescriptionsThe behavioral characteristics of a module are defined within an analog block.

analog_block ::= analog statement

statement ::= null_statement | block statement | branch_contribution | Indirect_branch_assignment | procedural_assignment | conditional_statement | loop_statement | case_statement | generate_statement | event_controlled_statement | discontinuity_function | bound_step_function | last_crossing_function | system_task_enable

analog statement can only appear within the analog block. The syntax for a block is the following:

block_statement ::= begin [ : block_identifier block_item_declaration ] statement end

In the analog block, it is possible code contribution statements with the contribution operator (<+) that define relationships among analog signals in the module.

Example

output_signal <+ f(input_signal);

V(n1, n2) <+ expression;I(n1, n2) <+ expression;

where output_signal is a branch of potential and flow sources of V(n1,n2) and I(n1,n2), respectively. It is possible to define f(input_signal) expression to be any combination of linear, nonlinear, algebraic, or differential expressions involving module signals, constants, and parameters.

The modules that are written can contain at most a single analog block. When an analog block is used, the user must place it after the interface declarations and local declarations.

The following module, which produces the sum and product of its inputs, illustrates the form of the analog block. Here the block contains two contribution statements.


Makeup of Modules

Example

module summult(in1, in2, outsum, outmult);input in1, in2;output outsum, outmult;voltage in1, in2, outsum, outmult;analog begin V(outsum) <+ V(in1) + V(in2); V(outmult) <+ V(in1) * V(in2);end

endmodule

Module dcvolts illustrates an analog block containing a single statement:

module dcvolts (outvolt);output outvolt;voltage outvolt;analog V(outvolt) <+ 5.0;

endmodule

2.5.1: Defining Analog Behavior with Control FlowThe user can also incorporate conditional control flow into a module. With control flow, it is possible to define the behavior of a module in regions.

The following module, for example, describes a voltage deadband amplifier vdba. If the input voltage is greater than vin_high or less than vin_low, the amplifier is active. When the amplifier is active, the output is gain times the differential voltage between the input voltage and the edge of the deadband. When the input is in the deadband between vin_low and vin_high, the amplifier is quiescent and the output voltage is zero.

module vdba(in, out);input in;output out;electrical in, out;parameter real vin_low = -1.0;parameter real vin_high = 1.0;parameter real gain = 1 from (0:inf);analog begin if (V(in) >= vin_high) V(out) <+ gain*(V(in) - vin_high); else if (V(in) <= vin_low) V(out) <+ gain*(V(in) - vin_low); else V(out) <+ 0;end

endmodule



2.5.2: Using Integration and Differentiation with Analog SignalsThe relationships defined among analog signals can include time domain differentiation and integration. VERILOG-A provides a time derivative function, ddt, and two time integral functions, idtand idtmod, that can be used to define such relationships. For example, a user might write a behavioral description for an inductor as follows:

Figure 2-1: Inductor model and reference direction

module inductor(p, n);inout p, n;electrical p, n;parameter real L = 0.1u from [0:inf];analog begin V(p, n) <+ L * ddt(I(p, n)); I(p, n) <+ idt(V(p, n))/L;end

endmodule

In module inductor, the voltage across the external ports of the component is defined as equal to the L times the derivative of the current flowing between the ports, and its current is equal to the integral of voltage divided by L.

To define a higher order derivative, the user must use an internal node or signal. For example, module deriv_2 defines internal node n1, and sets V(n1) equal to the derivative of V(in). Then the module sets V(out) equal to the derivative of V(n1), in effect taking the second order derivative of V(in).

module deriv_2(in, out);input in;output out;electrical in, out;electrical n1; // Defines an internal node with electrical properties.parameter real scale = 1e-6;analog begin V(n1) <+ scale*ddt(V(in)); V(out) <+ scale*ddt(V(n1));end

endmodule

VL Ldi dt⁄=

iL1L---- V p n,( ) td

0

t

∫=


Makeup of Modules

Note: If scale is not specified, the output of the module would be in magnitude of 1e6 due to a fast varying “noise” component of differentiating an unknown input signal.

For time domain integration, use the idt or idtmod functions, as illustrated in module integrator.

module integrator(in, out);input in;output out;electrical in, out;parameter real scale = 1e-6;analog begin V(out) <+ idt(scale*V(in), 0);end

endmodule

Module integrator sets the output voltage to the integral of the input voltage. The second term in the idt function is the initial condition. Without initial condition, idt must be used in a system description with feedback that forces its argument to zero; it is possible that convergence will not likely be achieved.



2.6: Using Internal Nodes in ModulesUsing VERILOG-A, the user can implement complex designs in a variety of different ways. For example, it is possible to define behavior in modules at the leaf level, and use the netlist to define the structure of the system. The user can also define structure within modules by defining internal nodes. With internal nodes, you can directly define behavior in the module, or introduce internal nodes as a means of solving higher order differential equations that define the network.

2.6.1: Using Internal Nodes in Behavioral DefinitionsConsider the following RLC circuit.

Figure 2-2: RLC circuit

Module rlc uses an internal node Tmp and the ports in, ref, and out, to directly define the behavioral characteristics of the RLC circuit. Notice how Tmp does not appear in the list of ports for the module.

module rlc(in, out, ref);inout in, out, ref;electrical in, out, ref;parameter real R=1, L=1, C=1;

electrical Tmp;analog begin V(in, Tmp) <+ R*I(in, Tmp); V(Tmp, out) <+ L*ddt(I(Tmp, out)); I(out, ref) <+ C*ddt(V(out, ref));end

endmodule

The following code shows a structural description of an RLC circuit with the new parameter assignments. There are three module instantiations inside the module rlc. The module resistor is instantiated with an instance named R1, the module inductor with an instance name L1, and the module capacitor with an instance name C1.

// Verilog-A module:‘include “discipline.h”

module rlc(in, out, ref);input in, ref;output out;


Makeup of Modules

electrical in, out, ref;electrical Tmp;

resistor #(200) R1(in, Tmp);inductor #(125m) L1(Tmp, out);capacitor #(1u) C1(out, ref);

endmodule // rlc

Figure 2-3: RLC module hierarchy

Where the resistor, inductor and capacitor modules are:

res.va:

‘include “discipline.h”

//Resistor

module resistor(p, n);input p, n;electrical p, n;

parameter real R=1.0 from (0:inf];

analog begin V(p, n) <+ R*I(p, n);end

endmodule

in out in out in out

capacitorinductorresistor

instance R1 instance L1 instance C1

Tmp

out refinmodule rlc



ind.va:


//Inductor

module inductor(p, n);input p, n;electrical p, n;

parameter real L=0 from (0:inf];

analog begin V(p, n) <+ L*ddt(I(p, n));end

endmodule

cap.va:


//Capacitor

module capacitor(p, n);input p, n;electrical p, n;

parameter real C=0 from (0:inf];

analog begin I(p, n) <+ C*ddt(V(p, n);end

endmodule

and the SMARTSPICE Netlist is:

*****VERILOG-A/AMS RLC CIRCUIT

.verilog “ind.va”

.verilog “cap.va”

.verilog “res.va”

*voltage sourcesvin in 0 sin (0 5 10e06 0 0)

* Verilog-A rlc module instantiation for model cardYVLGresistor in Tmp paramsR YVLGinductor Tmp out paramsLYVLGcapacitor out 0 paramsC


Makeup of Modules

*Analysis.tran 1n 800n

.options POST opts nomod probe

*output data.print V(in) V(out)

*create a VLG model card.model paramsR VLG MODULE = resistor+ R=100.model paramsC VLG MODULE = capacitor+ C=10p.model paramsL VLG MODULE = inductor+ L=10uh

.end

Note: The parameter values in the model card will override the previous parameters.

Figure 2-4: RLC Waveforms



2.6.2: Using Internal Nodes in Higher Order SystemsThe user can also represent the RLC circuit by its governing differential equations. The transfer function is given by:

In the time domain, this becomes:

If one set:

one can write:

Module rlc then becomes:

module rlc(in, out, ref);inout in, out, ref;electrical in, out, ref;parameter real R=1, L=1, C=1;electrical Tmp;analog begin V(Tmp, ref) <+ ddt(V(out, ref)); V(out, ref) <+ V(in) - (R*C*V(Tmp) - L*C*ddt(V(Tmp));end

endmodule

H s( ) 1

LCs2 RCs 1+ +------------------------------------------

VoutVin

--------------= =

Vout Vin R C dVoutdt

------------------ L Cd2Vout

dt2--------------------⋅–⋅ ⋅–=

V TMP( ) dVoutdt

------------------=

Vout Vin RC V TMP( )⋅– L CdV TMP( )dt

---------------------------⋅–=


Chapter 3:Lexical Conventions

3.1: Lexical TokensA SMARTSPICE VERILOG-A source file (module_name.va) is a stream of lexical tokens. Lexical tokens consist of one or more characters. The source file is a free format where spaces and newlines are not syntactically significant, other than being token separators.

Lexical tokens for VERILOG-A are:

• White Space• Comments• Operators• Numbers• Strings• Identifiers• Keywords• System Tasks and Functions• Compiler Directories

3.2: White SpaceWhite space consists of blanks, tabs, new-line characters, and form feeds. VERILOG-A ignores these characters except in strings or when they separate other lexical tokens. For example, this code fragment:

@(cross(V(Vctr 1p, Vctr 1n) - Vth, 0.0, 1.0u));

is syntactically identical to:

@(cross(V(Vctr 1p, Vctr 1n) - Vth, 0.0, 1.0u));



3.3: CommentsVerilog-A has two forms to introduce comments. A one_line comment starts with the two characters // and end with a new line. Block comments start with /* and end with */. Block comments cannot be nested. The one_line comment token // does not have any special meaning in a block comment.

short_comment ::= // any_ASCII_characters_except_end_of_line \n // This is a one_line comment

long_comment ::= /* any_ASCII_character */

/* This is a block comment or multiple line comment */

/* This is /* an illegal */ comment */

3.4: OperatorsOperators are single, double, or triple character sequences used in expressions. Unary operators are to the left of an operand, while Binary operators are between the operands. A conditionaloperator has two operator characters which separate the operands.

x = ~ y; // ~ is unary operator. y is operand.

z = x + y; // + is a binary operator. x and y are operands.

y = a ? b : c; // ?: is a ternary operator. a, b, and c are operands.

3.5: NumbersVERILOG-A supports two basic literal data types for arithmetic operations: integer constants and real constants. The syntax for constants is:

3.5.1: Integer ConstantsThe syntax for an integer constant is:

integer_constant ::= [ sign ] unsign_num

sign ::= + | -

unsign_num ::= decimal_digit _ | decimal_digit

decimal_digit ::=


Lexical Conventions

0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9

The simulator ignores the underscore character (_), so one can use it anywhere in a decimal number, except as the first character. Using the underscore character can make long numbers more legible.

Examples of integer constants include:

277195000277_195_000 //Same as the previous number-634 //A negative number0005

3.5.2: Real ConstantsThe syntax for a real constant is:

real_constant ::= [ sign ] unsign_num .unsign_num | [ sign ] unsign_num [.unsign_num] e [ sign ] unsign_num | [ sign ] unsign_num [.unsign_num] E [ sign ] unsign_num | [ sign ] unsign_num [.unsign_num ] scale_factor

sign ::= + | -

unsign_num ::= decimal_digit _ | decimal_digit

decimal_digit ::= 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9

scale_factor ::=T | G | M | K | k | m | u | n | p | f | a

scale_factor represents one of the scale factors listed below. If you use scale_factor, you must not have any white space between the number and the letter. Be certain to use the correct case for the scale_factor:

T (tera) = 1012

G (giga) = 109

M (mega) = 106

K,k (kilo) = 103

m (milli) = 10-3

u (micro) = 10-6

n (nano) = 10-9

p (pico) = 10-12

f (femto) = 10-15

a (atto) = 10-18



Examples of real constants include:

3.5K // 35001e-6 // 0.000001-8.6e9-5e-40.7u50p // 50*10e-121.5G // 1.5*10e9413_556.523_642


Lexical Conventions

3.6: StringsA string is a sequence of characters enclosed by double quotes (“ ”) and contained on a single line. Strings are treated as a sequence of one_byte ASCII value.

3.6.1: Special Characters in StringsCertain characters can only be used in strings when preceded by an introductory character called an escape character. Table 3-1 lists these characters in the right-hand column, with the escape sequence that represents the character in the left-hand column.

“a / b” // is a string.

“Welcome to Verilog-A” // is a string.

Table 3-1:

Escape String Character produced by escape string

\n New line character.

\t Tab character.

\\ \ character.

\” character

\ooo A character specified in 1-3 octal digits (0 < o < 7).

″



3.7: IdentifiersAn identifier is used to give an object a unique name so it can be referenced. An identifier can be any sequence of letters, digits, dollar signs ($), and the underscore character (_). The first character of an identifier cannot be a digit or a $; it can be a letter or an underscore. Identifiers are case sensitive, and associated with a data type (see "Chapter 4:" "Data Types"). There are two types of identifiers: ordinary identifiers, and escaped identifiers.

3.7.1: Ordinary IdentifiersThe first character of an ordinary identifier must be a letter or an underscore character (_), but the remaining characters can be any sequence of letters, digits, dollar signs ($), and the underscore. Examples include:

power_gain_bandwidthMyValueMyTime_my$value2

3.7.2: Escaped IdentifiersEscaped identifiers start with the backslash character (\) and end with white space (space, tab, newline, or formfeed). They provide a means of including any of the printable ASCII characters in an identifier (the decimal values 33 through 126, or 21 through 7E in hexadecimal).

Neither the leading backslash character nor the terminating white space is considered to be part of the identifier. Therefore, an escaped identifier \cpu3 is treated the same as a non-escaped identifier cpu3.

\base+index\+clock\***error-condition***\(a, b)\a*(b+c)+d


Lexical Conventions

3.8: KeywordsKeywords are predefined non-escape identifiers which are used to define the language constructs. Preceding a keyword with an escape character (\) causes it to be interrupted as an escaped identifier.

All keywords are defined in lowercase only. Keywords are reserved identifiers used to delimit the language constructs.

VERILOG HDL (IEEE 1364) Keywords supported:

VERILOG-A (2.0 OVI) Keywords that are supported:

begin case default else

end endease endfunction endmodule

for forever function if

initial inout input module

output repeat

abs absdelay abstol access

acos acosh ac_stim analog

analysis asin asinh atan

atan2 atanh bound_step branch

ceil continuous connectrules cos

cosh cross ddt ddt_nature

delay discrete discipline discontinuity

domain driver_update endconnectrules enddiscipline

endnature exclude exp final_step

flicker_noise floor flow from

generate genvar ground hypot

idt idtmod idt_nature inf

initial_step integer laplace_nd laplace_np

laplace_zd laplace_zp last_crossing limexp

ln log max min

nature noise_table parameter potential

pow real sin sinh

slew sqrt strobe tan

tanh timer transition units

white_noise zi_nd zi_np zi_zd

zi_zp



VERILOG HDL (IEEE 1364) Keywords that are not supported (but are still reserved identifiers):

always and assign buf

bufif0 bufif1 casex casez

cmos deassign defparam disable

edge endprimitive endspecify endtable

endtask event force fork

highz0 highz1 ifnone join

large macromodule medium nand

negedge nmos nor not

notif0 notif1 or pmos

posedge primitive pull0 pull1

pulldown pullup rcmos reg

release realtime rnmos rpmos

rtran rtranif0 rtranif1 scalared

small specify specparam strong0

strong1 supply0 supply1 table

task time tran tranif0

tranif1 tri tri0 tri1

triand trior trireg vectored

wait wand weak0 weak1

while wire wor xnor

xor


Lexical Conventions

3.9: System Tasks and FunctionsThe VERILOG-A language supports a variety of system tasks and functions, which are useful to control the current simulator to display the results of the simulation. The $ character introduces a language construct which enables development of user-defined tasks and functions. A name following the $ is interpreted as a system task or a system function.

Syntax:

system_task_function ::= $system_task_identifier | (list_of_arguments)|; |$system_function_identifier | (list_of_arguments)|;

list_of_arguments ::= argument , |argument |

argument ::= expression

Any valid identifier, including keywords already in use in contexts other than this construct can be used as a system task or function name.

Examples:

$display(“display a message”);$realtime();

3.10: Compiler DirectivesThe character (the ASCII value 60, called open quote or accent grave) introduces a language construct used to implement compiler directives. The compiler behavior dictated by a compiler directive takes effect as soon as the compiler reads the directive. The directive remains in effect for the rest of the compilation unless a different compiler directive specifies otherwise. A compiler directive in one description file can therefore control compilation behavior in multiple description files. Any valid identifier, including keywords already in use in contexts other than this construct can be used as a directive name.

The following compiler directives are:

‘define‘default_discipline‘endif‘ifdef‘include‘resetall‘undef

Examples

‘define threshold 1.0‘include “constant.h”‘include “discipline.h”



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Chapter 4:Data Types

4.1: Integer NumbersUse the integer declaration to declare variables of type integer.

integer_declaration ::= integer list_of_identifiers ;

list_of_identifiers ::= var_name , var_name

var_name ::= variable_identifier | array_identifier [ range ]

range ::= upper_limit_const_exp : lower_limit_const_exp

In VERILOG-A, the user can declare an integer number in a range at least as great as: -231

to 231 - 1.

To declare an array, specify the upper and lower indexes of the range. Be sure that each index is a constant expression that evaluates to an integer value.

integer A[1:128]; // Declares an array A of 128 integersinteger x, y, z[0:20]; // Declares 2 integers x, y, and an array z of 21

integers

parameter integer max_size = 20 from [1:50];integer cur_vector[1:max_size];

/* If the max_size parameter is not overridden, theprevious two statements declare an array of 20 integers. */

4.2: Real NumbersUse the real declaration to declare variables of type real.

real_declaration ::= real list_of_identifiers ;

list_of_identifiers ::= var_name , var_name

var_name ::= variable_identifier | array_identifier [ range ]

range ::= upper_limit_const_exp : lower_limit_const_exp



In VERILOG-A, the user can declare real numbers in a range at least as great as 10-37 to 10+37. To declare an array of real numbers, specify the upper and lower indexes of the range. Be sure that each index is a constant expression that evaluates to an integer value.

Note: Real and integer variables have default initial values of zero.

4.2.1: Converting Real Numbers to Integer NumbersVERILOG-A converts a real number to an integer number by rounding the real number to the nearest integer. If the real number is equally distant from the two nearest integers, VERILOG-A converts the real number to the integer farthest from zero. The following example illustrates what happens when real numbers are assigned to integer numbers.

integer int_valA, int_valB, int_valC;real real_valA, real_valB, real_valC;

real_valA = -1.8;int_valA = real_valA; // int_valA is -2

realvalB = 1.6 ;int_valB = real_valB; // int_valB is 2

real_valC = -1.6;int_valC = real_valC; // int_valC is -2

If either operand in an expression is real, VERILOG-A converts the other operand to real before applying the operator. This conversion process can result in a loss of information.

real real_var;real_var = 9.0;real_var = 5/8 * real_var; // real_var is 9.0, not 5.625

In this example, both 5 and 8 are integers, so 1 is the result of the division. VERILOG-A converts 1 to 1.0 before multiplying the converted number by 9.0.


Data Types

4.3: ParametersUse the parameter declaration to specify a module’s parameters.

parameter_declaration ::= parameter [opt_type] list_of_param_assignments ;

opt_type ::= real | integer

list_of_param_assignments ::= declarator_init , declarator_init

declarator_init ::= parameter_identifier = constant_exp opt_range

• opt_type is described in Section 4.3.1:“A Parameter Type”.

• opt_range is described in Section 4.3.2:“Permissible Values”.

• parameter_identifier is the name of a parameter being declared.

As specified in the syntax, the right-hand side of each declarator_init assignment is required to be a constant expression. It is possible to include in the constant expression only constant numbers and previously defined parameters.

Parameters are constants, so the value of a parameter at runtime cannot be changed. However, the user can customize module instances by changing parameter values during compilation. See Chapter 10, “Instantiating Modules and Primitives,” for more information.

Consider the following code fragment. The parameter superior is defined by a constant expression that includes the parameter subord.

parameter integer hold = 15;parameter integer superior = 5*hold;

In this example, changing the value of subord also changes the value of superior because the value of superior depends on the value of subord.

4.3.1: A Parameter TypeThe user must specify a default for each parameter that is defined, but the parameter type specifier is optional. If the parameter type specifier is omitted, VERILOG-A determines the parameter type from the constant expression. If a type is specified, and it conflicts with the type of the constant expression, one specified type takes precedence.

The three parameter declarations in the following examples all have the same effect. The first example illustrates a case where the type of the expression agrees with the type specified for the parameter.

parameter integer rate = 13;



The second example omits the parameter type, so VERILOG-A derives it from the integer type of the expression.

parameter rate = 15;

In the third example, the expression type is real, which conflicts with the specified parameter type. The specified type, integer, takes precedence.

parameter integer rate = 15.0;

In all three cases, rate is declared as an integer parameter with the value 15.

4.3.2: Permissible ValuesUse the optional range specification to designate permissible values for a parameter. If needed, the user can specify more than one range.

opt_range ::= from value_range_specifier | exclude value_range_specifier | exclude value_constant_expression

value_range_specifier ::= start_paren expression1 : expression2 end_paren

start_paren ::= [ | (

end_paren ::= ] | )

expression1 ::= constant_expression | -inf

expression2 ::= constant_expression | inf

Ensure that the first expression in each range specifier is smaller than the second expression. Use a bracket, either "[" for the lower bound or "]" for the upper, to include an end point in the range. Use a parenthesis, either "(" for the lower bound or ")" for the upper, to exclude an end point from the range. To indicate the value infinity in a range, use the keyword inf. To indicate negative infinity, use -inf.

For example, the following declaration gives the parameter current_value the default of -20.0. The range specification allows current_value to acquire values in the range - ∞< cur_val < 0.

parameter real maxval = 0.0;parameter real current_value = -20.0 from (-inf:maxval);


Data Types

The following declaration:

parameter integer positive_value = 25 from (0:50];

gives the parameter positive_value the default of 25. The range specification for positive_valueallows it to acquire values in the range 0 < positive_value <= 50. In addition to defining a range of permissible values for a parameter, you can use the keyword exclude to define certain values as illegal.

parameter low = 15;parameter high = 20;parameter integer int_value = 0 from [0:inf) exclude (low:high] exclude 2;

In this example, both a range of values, 15 < int_value <= 20, and the single value 2 are defined as illegal for the parameter.

4.3.3: Parameter ArraysVERILOG-A requires arrays to be initialized in their definitions and allows overriding of their values as with other parameter types.

Parameter types have the following restrictions:

• Type of a parameter array shall be declared.• An array assigned to an instance of a module shall be of the exact size of the array bounds of that

instance.• Changing the array size via a parameter assignment assigns an array of the new size from the

same module as the parameter assignment that changed the parameter array size.

Example

parameter real z_array [0:4] = 1.0, 3.198, 4.56, 2.00, 1.96;

where z_array is a real array with five elements with values 1.0, 3.198, 4.56, 2.00 and 1.96.

4.3.4: GenvarsGenvars are integer valued variables used as loop indexes:

genvar_declaration :: = genvar list_of_genvar_identifiers :list_of_genvar_identifiers :: = genvar_identifier , genvar_identifier ;

Example

genvar i;

analog begin

.....



for (i=0; i < 8; i=i+1) begin V(out[i]) < + transition(value[i], td, tr); end

.....

end

The genvar variable i can only be assigned within the loop control. Assignments to the genvar variable i can consist only of expressions of static values.

4.4: NaturesThe nature declaration is used to specify a collection of attributes. The attributes of a nature characterize the analog quantities that are solved during a simulation. Attributes define the units (such as meter, volts, and newton), access symbols and tolerances associated with an analog quantity, and can define other characteristics as well. After defining a nature, it can be used as part of the definition of disciplines and other natures. Access functions defined in natures are used to access the potential and flow quantities associated to the nodes.

nature_declaration ::= nature nature_name [ nature_descriptions ] endnature

nature_name ::= nature_identifier

nature_descriptions ::= nature_description | nature_description nature_descriptions

nature_description ::= attribute = constant_expression ;

attribute ::= abstol | access | ddt_nature | idt_nature | units | identifier | Silvaco_supported_attribute

Silvaco_supported_attribute ::= huge | blowup For Vendor compatibility | maxdelta

Each nature declaration must:

• Be defined between the keywords nature and endnature.

• Be named with a unique identifier.


Data Types

• Include all the required attributes listed in the Attribute Requirements table (see Table 4-2). • Be declared at the top level.

The user cannot nest nature declarations inside other nature, discipline, or module declarations.

The VERILOG-A language specification allows one to define a nature in two ways. One may define the nature directly by describing its attributes. A nature defined in this way is a base nature. The other way one can define a nature is to derive it from another nature or a discipline. In this case, the new nature is called a derived nature.

4.4.1: Base NatureTo declare a base nature, define the attributes of the nature. The following code declares the nature current and voltage. The expression associated with each attribute must be a constant expression.

nature currentunits = "A";access = I;idt_nature = charge;abstol = 1e-12;huge = 1e6;

endnature

nature voltageunits = "V";access = V;abstol = 1u;

endnature

The following table describes the predefined attributes.

Table 4-1: Predefined Atributes

Attribute Description

abstol The abstol attribute provides a tolerance measure (metric) for convergence of potential or flow calculation. It specifies the maximum negligible for signals associated with the nature. This attribute is required for all base natures. It is legal for a derived nature to change abstol, but if left unspecified it shall inherit the abstol from its parent nature. The constant expression assigned to it shall evaluate to a real value.

access The access attribute identifies the name for the access function. When the nature is used to bind a potential, the name is used as an access function for the potential; when the nature is used to bind the flow, the name is used as an access function for the flow.

This attribute is required for all base natures. It is illegal for a derived nature to change the access attribute; the derived nature always inherits the access attribute of its parent nature. If specified, the constant expression assigned to it shall be an identifier (by name, not as a string).



idt_nature The idt_nature attribute provides a relationship between a nature and the nature representing its time integral.

idt_nature can be used to reduce the need to specified tolerances on the idt() operator. If this operator is applied directly on nets, the tolerance can be taken from the node, which eliminates the need to give a tolerance with the operator.

If specified, the constant expression assigned to idt_nature shall be the name (not a string) of a nature which is defined elsewhere. It is possible for a nature to be self-referencing with respect to its idt_nature attribute. In other words, the value of idt_nature can be the nature that the attribute itself is associated with.

The idt_nature attribute is optional; the default value is the nature itself. While it is possible to override the parent’s value of idt_nature using a derived nature, the nature thus specified shall be related (share the same base nature) to the nature the parent uses for its idt_nature.

ddt_nature The ddt_nature attribute provides a relationship between a nature and the nature representing its time derivative.

ddt_nature can be used to reduce the need to specified tolerances on the ddt() operator. If this operator is applied directly on nets, the tolerance can be taken from the node, which eliminates the need to give a tolerance with the operator.

If specified, the constant expression assigned to ddt_nature shall be the name (not a string) of a nature which is defined elsewhere. It is possible for a nature to be self-referencing with respect to its ddt_nature attribute. In other words, the value of ddt_nature can be the nature that the attribute itself is associated with.

The ddt_nature attribute is optional; the default value is the nature itself. While it is possible to override the parent’s value of ddt_nature using a derived nature, the nature thus specified shall be related (share the same base nature) to the nature the parent uses for its ddt_nature.

units The units attributed provides a binding between the value of the access functions and the units for that value. The units field is provided so simulators can annotate the continuous signals with their units and is also used in the net capability rule check.

This attribute is required for all base natures. It is illegal for a derived nature to define or change the units; the derived nature always inherits its parent nature units. If specified, the constant expression assigned to it shall be a string.

Other Vendor Compatibility Attributes

huge Specifies the maximum change in signal value allowed during a single iteration. The simulator uses huge to facilitate convergence when signal values are very large. Default is 45.036e06




Data Types

Table 4-2: Attribute Requirements

4.4.2: Derived NatureA nature can be derived from an already declared nature. This allows the new nature to have the same attributes as the attributes of the existing nature. This new nature, derived nature, uses an existing parent nature. If a nature is not derived from any other nature, it is called a base nature.

A derived nature can declare additional attributes or override attribute values of the parent nature. The attributes of the derived nature is are accessed in the same manner as accessing attributes of any other nature.

Example

nature Net_current units = “A”; access = I; abstol = 1u; endnature

// An alias nature total_Net_current : Net_current

blowup Specifies the maximum allowed value for signals associated with the nature. If the signal exceeds this value, the simulator reports an error and stops running. Default is 1.0e09

maxdelta Specifies the maximum change allowed on a Newton-Raphson iteration. Default is 0.3

Attribute Required or optional The constant expression must be

abstol Required A real value

access Required for all base natures An identifier

units Required for all base natures A string

blowup Optional A real value

ddt_nature Optional The name of a nature defined elsewhere

huge Optional A real value

idt_nature Optional The name of a nature defined elsewhere

maxdelta Optional A real value





endnature

nature New_current : Net_current // derived abstol = 1m; // modified max = 12.3; // new attribute endnature

4.5: DisciplinesUse the discipline declaration to specify the characteristics of a discipline. You can then use the discipline to declare nets.

discipline_declaration ::= discipline discipline_identifier [ discipline_description discipline_description ] enddiscipline

discipline_description ::= nature_binding | domain_binding

nature_binding ::= potential nature_identifier ; | flow nature_identifier ;

domain_binding ::= domain continuous ; | domain discrete ;

Disciplines are declared at the top level. In other words, one cannot nest a discipline declaration inside other discipline, nature, or module declarations. Discipline identifiers have global scope, so one can use discipline identifiers to associate nets with disciplines (declare nets) inside any module. A discipline shall be defined between the keywords discipline and enddiscipline.

4.5.1: Binding NaturesDisciplines bind a nature to potential and/or a flow. The name of the nature is specified in the discipline. The nature binding for potential is specified using the keyword potential. The nature binding for flow is specified using the keyword flow.

The access function defined in the nature is bound to the potential is used in the model, obeys Kirchhoff ’s Potential Law (KPL), and is referred to as the potential access function. While the access function defined in the nature is bound to the flow, obeys Kirchhhoff ’s Flow Law (KFL), and is referred to as the flow access function.

The first example defines a single binding, one between potential and the nature Voltage. A discipline with a single binding is called a signal-flow discipline.

discipline voltage potential Voltage;//A signal-flow discipline must be bound to potential.enddiscipline


Data Types

The next declaration, for the electrical discipline, defines two bindings. Disciplines with two natures are called a conservative discipline.

discipline electrical potential Voltage; flow Current;enddiscipline

When defining a conservative discipline, the nature bound to potential must be different from the nature bound to flow.

Example

Nature and discipline definitions for electrical systems.

// current in amperes nature current units = “A”; access = I; abstol = 1e-12; endnature

// potential in volts nature voltage units = “V”; access = V; abstol = 1e-6; endnature

discipline electrical potential Voltage; flow Current; enddiscipline

4.5.2: Compatibility of DisciplinesCertain operations in VERILOG-A, such as declaring branches, are allowed only if the disciplines involved are compatible.

• Any discipline is compatible with itself.• Any empty discipline incompatible with all disciplines.

Consider the following declarations.

nature Voltage access = V; units = "V"; abstol = 1u;endnature



nature Current access = I; units = "A"; abstol = 1p;endnature

discipline emptydisenddiscipline

discipline electrical potential Voltage; flow Current;enddiscipline

discipline sig_flow_v potential Voltage;enddiscipline

To determine whether the electrical and sig_flow_v disciplines are compatible:

The electrical and sig_flow_v have defined natures for potential.

In fact, electrical and sig_flow_v have the same nature for potential, but electrical has a defined nature for flow, but sig_flow_v does not. The Disciplines are compatible.

Examine these declarations:

nature Position access = x; units = "m"; abstol = 1u;endnature

nature Force access = F; units = "N"; abstol = 1n;endnature

discipline mechanical potential Position; flow force;enddiscipline

The electrical and mechanical disciplines are not compatible.

Both disciplines have defined natures for potential, but the Position nature is not the same as the Voltage nature. The Disciplines not compatible end point.


Data Types

Table 4-3: Predefined disciplines in the standard definition Verilog-A file

4.5.3: Multi-Disciplinary ExampleDisciplines in VERILOG-A allow designs of multiple disciplines to be easilydefined and simulated. This example shows how an application spanning multiple disciplines can be modeled in Verilog-A. It models a DC-motor driven by a voltage source.

module motor_circuitt;parameter real freq=400;ground gnd;electrical drive;rotational shaft; motor m1(drive, gnd, shaft); vsource #(.freq(freq), .ampl(2.0)) v1(drive, gnd);

endmodule

// vp: positive terminal [V,A] vn:negative terminal [V,A]// shaft:motor shaft [rad,Nm]// INSTANCE parameters// Km = motor constant [Vs/rad]Kf = flux constant [Nm/A]// j = inertia factor [Nms^2/rad] D= drag (friction) [Nms/rad]// Rm = motor resistance [Ohms] Lm = motor inductance [H]// A model of a DC motor driving a shaft

module motor(vp, vn, shaft);inout vp, vn, shaft;electrical vp, vn;rotational shaft;parameter real Km = 4.5, Kf = 6.2;parameter real j = .004, D = 0.1;parameter real Rm = 5.0, Lm = .02;analog begin V(vp, vn) <+ Km*Theta(shaft) + Rm*I(vp, vn) + ddt(Lm*I(vp, vn)); Tau(shaft) <+ Kf*I(vp, vn) - D*Theta(shaft) - ddt(j*Theta(shaft));end

endmodule

discipline potential nature flow nature potential access flow access

electrical Voltage Current V I

magnetic Magneto_Motive_Force

Flux MMF Phi

thermal Temperature Power Temp Pwr

kinematic Position Force Pos F

rotational Angle Angular_Force Theta Tau



4.5.4: Empty DisciplinesIt is possible to define a discipline with no nature bindings. These are known as empty disciplines and they can be used in structural descriptions to let the components connected to a net determine which natures are to be used for the net. Such disciplines may have a domain binding or they may be domain-less, thus allowing the domain to be determined by the connectivity of the net.

Example

discipline neutralenddiscipline

discipline interconnectdomain continuous;enddiscipline

4.5.5: Discipline of Wires and Undeclared NetsIt is possible for a module to have nets where there are no discipline declarations. If such a net appears bound only to ports in module instantiations, it may have no declaration at all or may be declared to have a wire type such as wire. If it is referenced in behavioral code, then it must have a wire type. In these cases, the net shall be treated as having an empty discipline. If the net is referenced in behavioral code or if its net type is other than wire, then it shall be treated as having empty discipline with a domain binding of discrete, otherwise it shall be treated as having empty discipline with no domain binding.

This allows netlists (modules which describe connectivity only, with no behavior) which use wire as an interconnect to be valid.

4.5.6: Overriding Nature Attributes From DisciplineA discipline can override the value of the bound nature for the pre-defined attributes as shown for the flow ttl_curr in the example below.To do so from a discipline declaration, the bound nature and attribute needs to be defined, as shown for the abstol value within the discipline ttl in the example below.

The general form is shown as the attr_override terminal in Syntax 3-5: the keyword flow or potential, then the hierarchical separator . and the attribute name, and, finally, set all of this equal to (=) the new value (e.g., flow.abstol = 10u).

Examples

nature ttl_currunits = "A";access = I;abstol = 1u;endnature

nature ttl_voltunits = "V";access = V;abstol = 100u;endnature


Data Types

discipline ttlpotential ttl_volt;flow ttl_curr;flow.abstol = 10u;enddiscipline

4.5.7: Deriving Natures From DisciplinesA nature can be derived from the nature bound to the potential or flow in a discipline. This allows the new nature to have the same attributes as the attributes for the nature bound to the potentialor the flow of the discipline. If the nature binding to the potential or the flow of a discipline changes, the new nature shall automatically inherit the attributes for the changed nature. In order to derive a new nature from flow or potential of a discipline, the nature declaration shall also include the discipline name followed by the hierarchical separator (.) and the keyword flow or potential, as shown for ttl_net_curr in the example below. A nature derived from the flow or potential of a discipline can declare additional attributes or override values of the attributes already declared.

Examples

nature ttl_net_curr : ttl.flowendnature // abstol = 10u as modified in ttlnature ttl_net_volt : ttl.potentialabstol = 1m; // modified for this naturemax = 12.3; // new attribute for this natureendnature

4.5.8: Ground DeclarationEach ground declaration is associated with an already declared net of continuous discipline. The node associated with the net will be the global reference node in the circuit. If used in behavioral code, the net shall be used in only the differential source and probe forms, e.g., V(gnd) is not allowed. The net must be assigned a continuous discipline to be declared ground.

Syntax

ground_declaration ::=ground [ range ] list_of_nets;

Example

module example_ground(in, out);input in;output out;electrical in, out;electrical gnd;ground gnd;parameter real V_source = 5.0;resistor #(.r(10K)) r1(out,gnd);analog beginV(out) <+ V(in,gnd)*2;endendmodule



4.6: Net DisciplinesNet discipline declaration is used to associate nets with previously defined disciplines.

net_discipline_declaration ::= discipline_idendifier [range] list_of_nets ; wire [range] list_of_nets ;

range ::= [ msb_expression : lsb_expression ]

list_of_nets ::= net_identifier net_identifier , list_of_nets

msb_expression ::= constant_expression

lsb_expression ::= constant_expression

A net declared without a range is called a scalar net. A net declared with a range is called a vector net.

electrical [1:10] nodes; //Declares a vector netwire [3:0] connection_1, connection_2; //Declares two vector nets

Example

module multiple_inputs(multi_ports);input [0:5] multi_ports;electrical [0:5] multi_ports;analog begin generate i (0, 5) v(multi_ports [i]) <+ 0.0; end

endmodule

4.7: BranchesA branch is a path between two nets. If both nets are conservative, then the branch is conservative, and it defines a branch potential and a branch flow. If one net is a signal_flow net, then the branch is a signal_flow branch and defines either a branch potential or a branch flow, but not both.

Each branch declaration is associated with two nets from which it derives a discipline. These nets are referred to as the branch terminals. Only one net needs to be specified, in which case the second net defaults to ground and the discipline for the branch is derived from the specified net. The syntax for declaring branches is shown:

branch_declaration ::= branch list_of_branches ;


Data Types

list_of_branches ::= terminals list_of_branch_identifiers

terminals ::= ( net_identifier ) | ( net_identifier , net_identifier )

list_of_branch_identifiers ::= branch_identifier | branch_identifier , list_of_branch_identifiers

4.8: Implicit BranchesThe user might find it more convenient or clearer to refer to branches by their branch terminals. The following is an example of a named branch.

Example

module diode (p, n);inout p, n;electrical p, n;

parameter real area = 4;parameter real is = ie - 14;parameter real z = 2 from (0:10);parameter real cjo = 0;parameter real m = 0.5;parameter real phi = 0.7;parameter real t_t = ip;

branch (p, n) diode; //Declared branchreal vd, id, qd;

analog begin vd = V (diode); id = area* is *(exp (Vd/(z*$Vt)) -1); qd = t_t * id + area * Vd; I (diode) <+ id + ddt (qd); end

endmodule


Chapter 5:Statements for the Analog Block

5.1: Analog Procedural BlockVERILOG-A behavioral description is encapsulated within the analog procedural block. The analog procedural block defines the behavior as a procedural sequence of statements. The conditional and looping constructs are available for defining behaviors within the analog procedural block. The syntax for an analog block is:

analog_block ::= analog analog_statement ;

analog_statement ::= analog_seq_block |analog_seq_block |analog_branch_contribution |analog_indirect_branch_assignment |analog_procedural_assignment |analog_conditional_statement |analog_for_statement |analog_case_statement |analog_event_controlled statement |system_task_enable |statement

statement ::= |seq_block |procedural_assignment |conditional_statement |loop_statement |case_statement

5.1.1: Block StatementsThe block statements, also referred to as sequential blocks, are a means of grouping two or more statements together so they act syntactically like a single statement. The keywords begin and end delimit the block statements. The procedural statements in a block statement are executed sequentially in the given order.

Sequential Blocks

The syntax for sequential blocks is shown below:

seq_block ::= begin [ : block_identifier block_item_declaration ] statement end

analog_seq_block ::= begin [ : block_identifier block_item_declaration ] analog_statement end



block_item_declaration ::= parameter_declaration | integer_declaration | real_declaration

An analog_seq_block is a seq_block which encapsulates one or more analog_statements.

Block Names

Name a sequential block by adding a :block_identifier after the keyword begin. The naming of a block allows local variables to be declared for that block.

All local variables are static - that is, a unique location exists for all variables, and leaving or entering blocks does not affect the values stored in them.

The block names give a means of uniquely identifying all variables at any simulation time.

5.1.2: Procedural Assignment StatementsUse the procedural assignment statement to modify integer and real variables:

procedural_assignment ::= lexpr = expression ;

analog_procedural_assignments ::=lexpr = analog_expression ;

lexpr ::= integer_identifier | real_identifier | array_element

array_element ::= integer_identifier [ constant_expression ] | real_identifier [ constant_expression ]

The left-hand operand of the procedural assignment must be a modifiable integer or real variable, or an element of an integer or real array. The type of the left-hand operand determines the type of the assignment.

The right-hand operand can be any arbitrary scalar expression constituted from legal operands and operators.

In the following code fragment, the variable phase is assigned a real value. The value must be real because phase is defined as a real variable.

real phase;analog begin phase = idt( gain*V(in));

One can also use procedural assignment statements to modify array values. For example, if z is declared as:


Statements for the Analog Block

real z[0:3], sum;

one can make assignments such as:

z[0] = 15.7;z[1] = 16.1;z[2] = 17.1;z[3] = 13.5;sum = z[0] + z[1] + z[2] + z[3];

5.2: Sequential Block StatementUse a sequential block when you want to group two or more statements together so that they act like a single statement.

analog_seq_block ::= begin [ : block_identifier block_item_declaration ] analog_statement end

block_item_declaration ::= parameter_declaration integer_declaration | real_declaration

The statements included in a sequential block run sequentially.

If adding a block identifier, you can also declare local variables for use within the block. All the local variables declared are static. In other words, a unique location exists for each local variable, and entering or leaving the block does not affect the value of a local variable.

The following example uses two named blocks, declaring a local variable in each of them. Although the variables have the same name, the simulator handles them separately because each variable is local to its own block.

integer i;...for ( i = 0; i < 15; i = i + 1 ) begin if ( i%2 ) begin : odd integer i; // Declares a local variable i = i + 1; $display("Odd numbers counted = %d", i ); end else begin : even integer i; // Declares a local variable i = i + 1; $display("Even numbers counted = %d" , i ); endend



5.3: Conditional StatementUse the conditional statement to run a statement under the control of specified conditions.

conditional_statement ::= if ( expression ) true_statement_or_null [ else false_statement_or_null ]

If expression evaluates to a nonzero number (true), the simulator executes true_statement. If expression evaluates to zero (false), and the else statement is present, the simulator skips true_statement and executes false_statement.

Since the numeric value of the if expression is tested for being zero (0), shortcuts are possible as listed below.

if (expression)if (expression ! = 0)

There can be confusion when an else is omitted from a nested if() sequence because the else part of an if-else is optional. Always associate the else with the closest previous if(), which lacks an else.

In the example below, the else goes with the inner if(), as shown by indentation.

if (index > 0) if (i > j) result = i; else // else applies to preceding if result = j;

If that association is not desired, a begin-end shall be used to force the proper association, as shown below.

if (index > 0) begin if (i > j) result = i;endelse result = j;

The most general way of writing a multi-way decision is through the nesting of if statements (known as an if-else-if construct). The expressions are evaluated in order. Whenever any expression is True, the statement associated with it shall be executed, and this action shall terminate the whole chain. Each statement is either a single statement or a sequential block of statements.



5.3.1: Analog Conditional StatementsAnalog conditional statements are syntactically equivalent to conditional statements, with the exception of the True and/or False statements which are analog_statements. The conditional expression shall be a genvar_expression.

analog_conditional_statement ::=if ( genvar_expression ) true_analog_statement_or_null ;[ else false_analog_statement_or_null ; ]

5.4: Case Statementthe case statement is a multi-way decision statement which tests if an expression matches one of a number of other expressions, and if so, branches the expression accordingly.

Syntax

case_statement ::= case (expression) case_item case_item endcase | casex (expression) case_item case_item endcase | casez (expression) case_item case_item endcase

case_item ::=expression , expression : statement_or_null| default [ : ] statement_or_null

The default statement is optional. Use of multiple default statements in one case statement is illegal.

The case expression and the case_item expression can be computed at runtime, but neither expression is required to be a constant expression.

The case_item expressions are evaluated and compared in the exact order in which they are given. During this linear search, if one of the case_item expressions matches the case expression given in parentheses, then the statement associated with that case_item is executed. If all comparisons fail, and the default item is given, then the default item statement is executed; otherwise none of the case_item statements are executed.

5.4.1: Analog Case StatementsAnalog case statements are syntactically equivalent to case statements, although the case item statements can also be analog_statements, as seen below:

analog_case_statement ::= case (genvar_expression) analog_case_item analog_case_item endcase | casex (genvar_expression) analog_case_item analog_case_item endcase | casez (genvar_expression) analog_case_item analog_case_item endcase

analog_case_item ::=genvar_expression , genvar_expression : analog_statement_or_null| default [ : ] analog_statement_or_null



5.4.2: Constant Expression in Case StatementsA constant expression can be used for a case expression. The value of the constant expression shall be compared against case_item expressions.

Example

The following example demonstrates the usage by modeling a 3-bit priority encoder.

integer [2:0] encode;

case (1) encode[2] : $display(“Select Line 2”); encode[1] : $display(“Select Line 1”); encode[0] : $display(“Select Line 0”); default $strobe(“Error : One of the bits expected ON”);endcase

The case expression here is a constant expression (1). The case_items are expressions (array elements) and are compared against the constant expression for a match.

5.5: Looping StatementThere are several types of looping statements: repeat ( ), while ( ), and for ( ). These statements provide a means of controlling the execution of a statement zero (0), one (1), or more times.

The for ( ) looping statements can be used to describe analog behaviors using analog operators.

Analog operators are not allowed in the repeat ( ), while ( ), and for ( ) looping statements. They are allowed in analog_for and generate statements.

5.5.1: Repeat and While Statementsrepeat( ) executes a statement a fixed number of times. Evaluation of the expression decides how many times a statement is executed.

while( ) executes a statement until an expression becomes False. If the expression starts out False, the statement is not executed at all.

The repeat and while expressions are evaluated once before the execution of any statement in order to determine the number of times, if any, the statements are executed.

Syntax

repeat_statement ::= repeat ( expression ) statement

while_statement ::= while ( expression ) statement

5.5.2: For StatementsThe for ( ) statement is a looping construct which, using an index variable, controls the execution of its associated statement(s). If the associated statement is an analog_statement, then the control



mechanism shall consist of genvar_assignments and genvar_expressions to follow to the restrictions associated with the use of analog operators. If the associated statements are not analog_statements, the for ( ) statement can use procedural assignments and expressions, which also include genvar_expressions.

The for ( ) statement controls execution of its associated statement(s) by a three step process:

1. It executes an assignment normally used to initialize an integer which controls the number of loops executed.

2. It evaluates an expression; if the result is zero (0), the for-loop exits: otherwise the for-loopexecutes its associated statement(s) and then performs Step 3.

3. It executes an assignment normally used to modify the value of the loop control variable and repeats Step 2.

Syntax

for_statement ::= for ( procedural_assignment ; expression ; procedural assignment ) statement

analog_for_statement ::= for ( genvar_assignment ; genvar_expression ; genvar_assignment ) analog_statement

analog_for statements are syntactically equivalent to for ( ) statements, except the associated statement is also an analog statement (which contains analog operations). The analog statement puts the additional restriction upon the procedural assignment and conditional expressions of the for-loop to be statically evaluated.

Example

genvar i

analog begin ..... for (i = 0; i < 8; i = i + 1) begin V(out[i]) <+ transition(value[i], td, tr, tf); end .....end

5.6: Analog SignalsAnalog signals are easily distinguished from digital signals. An analog signal has a discipline with a continuous domain. This section describes analog branch assignments, signal access mechanisms, and operators in VERILOG-A.

5.7: Signal Access FunctionsAccess functions are used to access signals on nets, ports, and branches. There are two types of access functions: branch access functions, and port access functions. The name of the access function for a signal is taken from the discipline of the net, port, or the branch where the signal or port



associated, and uses the ( ) operator. A port access function also takes its name from the discipline of the port to which it is associated, but uses the port access ( <> ) operator.

If the signal or port access function is used in an expression, the access function returns the value of the signal. If the signal access function is being used on the left side of a branch assignment, or contribution statement, a value to the signal is assigned. A port access function cannot be used on the left side of the branch assignment or contribution statement.

Table 5-1 shows how access functions can be applied to branches, nets, and ports. In the table: b1refers to a branch, n1 and n2 refer to nets or ports, and p1 refers to a port. These branches, ports and nets belong to the electrical discipline, where V is the name of the access function for the voltage (potential) and I is the name of the access function for the current (flow).

A branch identifier will be the argument expression list for signal access functions, or a list of one or two nets (or port) expressions. If two net expressions are given as arguments to a flow access function, they will not evaluate the same signal. The net identifiers will be scalar, or resolve to a constant net of a composite net type (array or bus) accessed by a genvar expression.

Example

I(n1, n2) creates an unnamed branch from n1 to n2 (if it does not already exist) and then accesses the branch flow. I(n1) does the same from n1 to the global reference node (ground). Therefore:

• Accessing the flow from a net (or port) to a net (or port) defines an unnamed branch. Accessing the potential on a single net (or port) defines an unnamed branch from that net (or port) to the global reference node (ground).

• It is also possible to access the flow passing through a port into a module. The name of the access function is derived from the flow nature of the discipline of the port. In this case ( <> ) is used to delimit the port name rather than ( ).

Example

I(<p1>) is used to access the current flow into the module through the electrical port p1. (See section 5.8.8:“Port Branches” for details.)

Table 5-1: Access Function Examples

Example Comments

V(b1) Accesses the voltage across branch b1.

V(n1) Accesses the voltage of n1 (a net or a port) relative to ground.

V(n1, n2) Accesses the voltage difference between n1 and n2 (nets or ports).

I(b1) Accesses the current on branch b1.

I(n1) Accesses the current flowing from n1 (a net or port) to ground.

I(n1, n2) Accesses the current flowing between n1 and n2.

I(n1, n1) Error

I(<pl>) Accesses the current flow into the module through port p1.



5.8: Probes and SourcesAn analog component can be represented using a network of probes and controlled sources. VERILOG-Auses the concept of probes and sources as a means of unambiguously representing a network. The mapping between these representations are defined in the following sections.

5.8.1: ProbesIf no value is specified for either the potential or the flow, the branch is a probe. If the flow of the branch is used in an expression anywhere in the module, the branch is a flow probe, otherwise it will be a potential probe. Using both potential and the flow of a probe branch is illegal. The models for probe branches are shown in Figure 5-1.

Figure 5-1: Equivalent Circuit Models for Probe Branches

The branch potential of a flow probe is zero (0). The branch flow of a potential probe is zero (0).

5.8.2: SourcesA branch (named or unnamed) is a source branch if either the potential or the flow of that branch is assigned a value by a contribution statement anywhere in the module. If the branch potential is specified, then it is a potential source, and if the branch flow is specified it is a flow source. A branch cannot simultaneously be a potential and a flow source, although it can switch between them as a switch branch.

Both the potential and the flow of a source branch are accessible in expressions anywhere in the module. The module for potential and flow sources are shown in Figure 5-2.

Lower case f is a mode which measures the flow through the branch, and p is a mode which measures the potential across the branch.



Figure 5-2: Equivalent Circuit Models for Source Branches

The following examples demonstrate how to formulate models, the correspondence between the behavioral description, and the equivalent probe/source model.

5.8.3: The four controlled sourcesThe following example is used with each of the four behavioral statements listed below. When inserted into this example, each statement creates a unique controlled source.

Example

module control_source(p, n, ps, ns);electrical p, n, ps, ns;parameter real A=1.0;branch(ps, ns) in;branch(p, n) out;analog begin

// add behavioral statement here

endendmodule

5.8.4: Behavioral StatementsThe model for a voltage controlled voltage source is:

V(out) <+ A*V(in);

The model for a voltage controlled current source is:

I(out) <+ A*V(in);

The model for a current controlled voltage source is:

V(out) <+ A*I(in);

The model for a current controlled current source is:

I(out) <+ A*I(in);



5.8.5: Resistor and ConductorFigure 5-3 shows the model for a linear conductor

Figure 5-3: Linear Conductor Model

The assignment to I(cond) makes cond a current source branch, and V(cond) accesses the potential probe built into the current source branch.

Figure 5-4 shows the model for a linear resistor.

Figure 5-4: Linear Resistor Model

The assignment to V(res) makes res a potential source branch, and I(res) accesses the optional flow probe built into the potential source branch.

5.8.6: RLC CircuitsA series RLC circuit is formulated by summing the voltage across its three components:

Which can be defined as:

V(p, n) <+ R*I(p, n ) + L*ddt(I(p, n)) + idt(I(p, n))/C;

A parallel RLC circuit is formulated by summing the currents through its three components:

v t( ) Ri t( ) L ddt------i t( ) 1

C---- i τ( ) τd

∞–

t

∫+ +=



Which can be defined as:

I(p, n) <+ V(p, n )/R + C*ddt(V(p, n)) + idt(V(p, n))/L;

5.8.7: Simple Implicit DiodeVERILOG-A allows components to be described with illicit equations.

Example

In the following example is a simple diode with a series resistor, and the module is implicit because the diode current I(a, c) appears on both sides of the contribution operator. The current of the diode branch is specified, making it a flow source branch. In addition, both the voltage and current of diode branch in the behavioral description.

I(a, c) <+ is*(limexp((V(a, c) - rs*I(a, c)) /$vt) - 1);

Figure 5-5: Diode with a series resistor

5.8.8: Port BranchesThe port access function accesses the flow into a port of a module. The name of the access function is derived from the flow nature of the discipline of the port. However, (<>) is used to delimit the port name, e. g. I(<a>) accesses the current through module port a.

Example

Writing the junction diode so that the diode current is monitored, and a message is issued if it exceeds a given value.

module diode(a, c);electrical a, c;branch(a, c) i_diode, junc_cap;parameter real is=1e-14, tf=0, cjo=0, imax=1, phi=0.7;

analog begin I(i_diode) <+ is*(limexp(V(i_diode)/$vt) - 1); I(junc_cap) <+ ddt(tf*I(i_diode) - 2*cjo*sqrt(phi*(phi*V(junc_cap))));

i t( ) v t( )R

---------- C ddt------v t( ) 1

L---- v τ( ) τd

∞–

t

∫+ +=



if (I(<a>) > imax) $strobe(“warning: diode is melting!”);end

endmodule

The expression V(<a>) is invalid for ports and nets where V is the potential access function. The port branch I(<a>) cannot be used on the left side of a contribution operator <+.

5.9: Switch BranchesSource branches are able to switch between being potential and flow sources. To switch a branch to a potential source, assign to its potential. To switch a branch to a flow source, assign to its flow. This type of branch is useful when modeling ideal switches and mechanical stops. The full circuit model for a switched branch is shown in Figure 5-6.

Figure 5-6: Circuit Model for a Switched Source Branch

Example

An ideal relay (a controlled switch) can be implemented as

module relay(p, n, ps, ns);electrical p, n, ps, ns;parameter vth = 0.5;integer closed;analog begin closed = (V(ps, pn) > vth ? 1 : 0); if (closed) V(p, n) <+ 0; else I(p, n) <+ 0;end

endmodule



5.9.1: Unassigned SourcesIf a value is not assigned to a branch, the branch flow is set to zero (0).

Example

if (closed) V(p, n) <+ 0;

is equivalent to

if (closed) V(p, n) <+ 0;else I(p, n) <+ 0;

5.10: Signal Access for Vector BranchesVERILOG-A allows the user to arrange ports, nets, and branches as vectors. However, the access functions can only be applied to scalars, or individual elements of a vector. The scalar element of a vector is selected with an index. For example, V(in[1]) accesses the voltage in[1]. The index must be a genvar expression consisting of literals and/or genvar variables, which can only be assigned to as the iteration index for loops, and allow signal access within looping constructs.

Examples

The following is an application of access functions to elements of an analog signal vector.

// N-bit DAC example.

module dac(out, in, clk);parameter integer width=8 from [2:24];parameter real fullscale=1.0, vth=2.5, td=1n, tt=1n;output out;input [0:width - 1] in;input clk;electrical out;electrical [0:width - 1] in;electrical clk;

real aout;genvar i;

analog begin @(cross(V(clk) - vth, +1)) begin aout = 0; for (i = width - 1; i >= 0; i = i - 1) begin if (V(in(i) > vth) begin aout = aout + fullscale/pow(2, width - i); end end end V(out) <+ transition(aout, td, tt);



end

endmodule

// 8-bit fixed-width DAC example.

module dac8(out, in, clk);parameter real fullscale=1.0, vth=2.5, td=1n, tt=1n;output out;input [0:7] in;input clk;electrical out;electrical [0:7] in;electrical clk;

real aout;

analog begin @(cross(V(clk) - 2.5, +1)) begin aout = 0; aout = aout + ((V(in[7]) > vth) ? fullscale/2.0 : 0.0); aout = aout + ((V(in[6]) > vth) ? fullscale/4.0 : 0.0); aout = aout + ((V(in[5]) > vth) ? fullscale/8.0 : 0.0); aout = aout + ((V(in[4]) > vth) ? fullscale/16.0 : 0.0); aout = aout + ((V(in[3]) > vth) ? fullscale/32.0 : 0.0); aout = aout + ((V(in[2]) > vth) ? fullscale/64.0 : 0.0); aout = aout + ((V(in[1]) > vth) ? fullscale/128.0 : 0.0); aout = aout + ((V(in[0]) > vth) ? fullscale/256.0 : 0.0); end

V(out) <+ transition(aout, td, tt); end

endmodule

Syntax

access_function_reference ::= bvalue | pvalue

bvalue ::= access_identifier (analog_signal_list)

analog_signal_list ::= branch_indefier | array_branch_identifier [ genvar_expression ] | net_or_port_scalar_expression | net_or_port_scalar_expression , net_or_port_scalar_expression

net_or_port_scalar_expression ::=



| net_or_port_identifier | array_net_or_port_identifier [ genvar_expression ] | vector_net_or_port_identifier [ genvar_expression ]

pvalue ::= flow_access_identifier ( < port_scalar_expression > )

port_scalar_expression ::= port_identifier | array_port_identifier [ genvar_expression ] | vector_port_identifier [ genvar_expression ]

5.10.1: Accessing Net and Branch SignalsSignals on nets and branches can be accessed by the access function of the discipline associated with them. The name of the net and branch is specified by the argument to the access function.

Example

electrical out, in;parameter real gm = 1;

analog I(out) <+ gm*V(in);

electrical p, n;branch(p, n) res;parameter real R = 50;

analog V(res) <+ R*I(res);

5.10.2: Accessing AttributesThe attributes of a net or branch are attached to the nature of a potential or a flow, and can be accessed through the hierarchal referencing operator ( . ).

Example

electrical a, b, n1, n2;branch(n1, n2) cap;parameter real c = 1p;

analog begin I(a, b) <+ c*ddt(V(a, b)), a.potential.abstol); I(cap) <+ c*ddt(V(cap)), n1.potential.abstol);end



Syntax

attribute_reference ::= net_identifier.pot_or_flow.attribute_identifier

5.11: Contribution StatementsVERILOG-A describes analog behavior by way of the branch contribution operator <+, which is only valid within an analog block. Branch contribution statements use the branch contribution operator in order to describe behavior by way of a mathematical mapping of input to output signals.

5.11.1: Branch Contribution StatementBranch contribution statements consist of two sides, a left hand and a right hand, which are separated by a branch contribution operator. The right hand side is an expression that either evaluates to, or promotes to a real value. The left hand side specifies the source branch signal where the right hand side shall be assigned, and consists of a signal access function applied to a branch.

Analog behaviors can be described by the following:

V(n1, n2) <+ expression;

or

I(n1, n2) <+ expression;

(n1, n2) is an unnamed source branch, V(n1, n2) is the potential on the branch, and I(n1, n2)is the flow on the branch. The nature of the expression can be linear, non-linear, or dynamic. The left hand side cannot use a port access function. See the following example models a resistor and a capacitor.

Example

module resistor(p, n);electrical p, n;parameter real r = 0;

analog V(p, n) <+ r*I(p, n);

endmodule

module capacitor(p, n);electrical p, n;parameter real c = 0;

analog I(p, n) <+ c*ddt(V(p, n));

endmodule



5.11.2: RelationsSource branch relations are defined by branch contribution statements. The branch is directed from the first net of the access functions to the second net. If the second net is not specified, the global reference node (ground) is used as the reference point.

The path of the flow between the two nets in a module is the branch relation. The potential and the flow out of the net are the two quantities. In electrical circuits, the potential of a net is its voltage, and the flow out is the current. Each branch also has two quantities, the potential and flow across the branch.

Example

module amp(out, in);

input in;output out;voltage out, in;parameter real Gain = 1;

analog V(out) <+ Gain*V(in);

endmodule

5.11.3: EvaluationFor source branch contributions the statement is evaluated as following:

• The simulator evaluates the right hand side.• The value of the right hand side is added to any previously retained value of the branch for any

later assignments to the branch. If there are no previously retained values, the right hand side is retained.

• After the simulation, the retained value is assigned to the source branch.

Adding additional contribution statements to model the input admittance and output impedance adds parasitics to the amplifier.

Example

module amp(out, in);

input in;output out;voltage out, in;parameter real Gain=1, Rin=1, Cin=1, Rout=1, Lout=1;

analog begin // gain of amplifier V(out) <+ Gain*V(in);

// model input admittance I(in) <+ V(in)/Rin; I(in) <+ Cin*ddt(V(in));



// model output impedance V(out) <+ Rout*I(out); V(out) <+ Lout*ddt(I(out));

end

endmodule

5.11.4: Value RetentionIf a flow is added to a branch that already has a value retained for the potential, the potential is discarded and the branch is converted to a flow source. Alternately, if a potential is added to a branch that already has a value retained for the flow, the flow is discarded and the branch is converted to a potential source. This is used to model switches, but it is illegal to add to an external switch from within an analog block.

Example

module switch(p, n, cp, cn);electrical p, n, cp, cn;parameter real thresh = 0.01;

analog begin // resolve threshold crossings @(cross(V(cp, cn) - thresh, 0));

if (V(cp, cn) > thresh) V(p, n) <+ 0; else

I(p, n) <+ 0;end

endmodule

Syntax

analog_branch_contribution ::= bvalue <+ analog_expression;

5.11.5: Indirect Branch AssignmentsVERILOG-A allows descriptions that implicitly specify a branch voltage or current in a fixed point form. Branch voltage or current is assigned a value by the expression that uses it. See section 5.8.7:“Simple Implicit Diode” where I(a,c) appeared on both sides of the contribution operator.

Example

Consider the model for an ideal opamp. The output is driven to the voltage which results in the input voltage being zero (0). The constitutive equation is:

V(in) == 0;



which can be formulated as:

V(out) <+ V(out) + V(in);

This statement defines the output of the opamp to be a controlled voltage source by assigning to V(out) and defines the input to be high impedance by only probing the input voltage. The desired behavior results because the description is formulated in such a way it reduces to V(in) = 0. This approach does not result in the right tolerances being applied to the equation if out and in have different disciplines.

Verilog-A includes a special syntax to use in this situation. The above branch contribution can be rewritten using an indirect branch assignment:

V(out) : V(in) == 0;

which reads “find V(out) so that V(in) == 0”.

This indicates that out is driven with a voltage source, and the source voltage needs to satisfy the given equation. Branches that are referenced in the equation are only probed, not driven. In particular, V(in) acts as a voltage probe.

Example

A complete description of an ideal opamp is:

module opamp(out, pos_in, neg_in);electrical out, pos_in, neg_in;

analog V(out) : V(pos_in, neg_in) == 0;

endmodule

Syntax

analog_indirect_branch_assignments ::= bvalue : nexpr == analog_expression;

nexpr ::= bvalue |pvalue |ddt (bvalue | pvalue) |idt (bvalue | pvalue)



5.11.6: Multiple Indirect AssignmentsFor multiple indirect assignments statements, the targets can be paired with any equation.

Examples

The following differential equation:

can be written as:

V(x) : ddt(V(x)) == f(V(x), V(y), V(z));V(y) : ddt(V(y)) == g(V(x), V(y), V(z));V(z) : ddt(V(z)) == h(V(x), V(y), V(z));

or

V(y) : ddt(V(x)) == f(V(x), V(y), V(z));V(z) : ddt(V(y)) == g(V(x), V(y), V(z));V(x) : ddt(V(z)) == h(V(x), V(y), V(z));

or

V(z) : ddt(V(x)) == f(V(x), V(y), V(z));V(x) : ddt(V(y)) == g(V(x), V(y), V(z));V(y) : ddt(V(z)) == h(V(x), V(y), V(z));

without affecting the results.

5.11.7: Indirect Assignments and ContributionsIndirect assignments and contributions are incompatible. Once a value is indirectly assigned to a branch, it cannot be contributed to using the branch contribution operator <+. It is illegal to indirectly assign or contribute to an external branch which has an indirect branch assignment.

dxdt------- f x y z, ,( )=

dydt------- g x y z, ,( )=

dzdt------ h x y z, ,( )=


Chapter 6:Expressions and Operators for Analog Blocks

6.1: Overview of Expressions and OperatorsAn expression is a construct that combines operands with operators to produce a result that is a function of the values of the operands and the semantic meaning of the operators. Any legal operand is also an expression.

A constant expression is an expression whose operands are constant numbers, and previously defined parameters; and whose operators all come from among the unary, binary, and ternaryoperators described in this chapter.

The operators listed below, with the single exception of the conditional operator, associate from left to right. That means that when operators have the same precedence, the one farthest to the left is evaluated first.

6.2: OperatorsThe symbols for the VERILOG-A operators are similar to those in the C programing language. Table 6-1lists these operators:

Table 6-1: Operators

+ - * / Arithmetic

% Modulus

> >= < <= Relational

!== === Case equality

!= == Logical equality

! Logical negation

&& Logical and

|| Logical or

~ Bit-wise negation

& Bit-wise and

| Bit-wise inclusive or

^ Bit-wise exclusive or

^~ ~^ Bit-wise equivalence

<< Left shift

>> Right shift

?: Conditional

or Event or

Concatenation, replication



6.2.1: Operators With Real OperandsThe operators in Table 6-2 are legal when applied to real operands. All other operators are considered illegal when used with real operands.

The result of using logical or relational operators on real numbers is an integer value 0 (false) or 1 (true).

Table 6-3 lists those operators which shall not be used to operate on real numbers.

6.2.2: Real to Integer ConversionReal numbers are converted to integers by rounding the real number to the nearest integer, rather than by truncating. When a real number is assigned to an integer, the implicit conversion takes place. The ties are rounded away from zero (0).

Examples

// The real numbers 35.6 and 35.5 both become 36 when// converted to an integer and 35.2 becomes 35.

// Converting -1.5 to integer yields -2, converting 1.5 to// integer yields 2.

Table 6-2: Legal Operators for use in Real Expressions

unary+ unary- Unary Operators

+ - * / Arithmetic

% Modulus

> >= < <= Relational

!= == Logical equality

! && || Logical

?: Conditional

or Event or

Table 6-3: Operators not allowed for Real Expressions

!== === Case equality

~ & | ^ ^~ ~^ Bit-wise

<< >> Shift

Concatenation and replication operator.


Expressions and Operators for Analog Blocks

6.2.3: Arithmetic ConversionA common data type for each operand is determined before the operator is applied. If either operand is real, the other is likewise converted to real. Implicit conversion takes place when an integer number is used with a real number in an operand.

Examples

a = 3 + 5.0;// The expression “3 + 5.0” is evaluated by “casting” the // integer 3 to the real 3.0, and the result of the expression is 8.0.

b = 1 / 2;// The above is integer division and the result is 0.

c = 8.0 + (1 / 2);// (1 / 2) is treated as integer division, but the result of the// expression is 8.0

6.2.4: Binary Operator PrecedenceTable 6-4 shows the precedence order of binary operators and the conditional operator (?:).

The operators shown in Table 6-4 have the same precedence. The rows are arranged in order of decreasing precedence for the operators.

All operators associate from left to right, except for the conditional operator which associates from right to left. The association refers to the order in which the operators of the same precedence are evaluated.

Table 6-4: Precedence Rules for Binary Operators

+ - ! ~ (unary) Highest precedence

* / %

+ - (binary)

<< >>

< <= > >=

== != === !==

& ~&

^ ^~ ~^

| ~|

&&

||

?: (conditional operator Lowest precedence



Example

When B is added to A and the C is extracted from the result of A + B:

A + B - C

When operators differ in precedence, the operators with higher precedence associate first.

Examples

B is divided by C (division has higher precedence than addition) and then the result is added to A:

A + B / C

Parentheses can be used to change the operator precedence:

(A + B) / C// not the same as A + B / C

6.2.5: Expression Evaluation OrderThe operators follow the associativity rules while valuating an expression as described in section 6.2.4:“Binary Operator Precedence”. However, if the final result of an expression can be determined early, the entire expression does not need to be evaluated, as long as the remaining expression does not contain analog expressions. This is called short circuiting and expression evaluation.

Example

integer A, B, C, result;result = A & (B | C);

If A is known to be zero (0), the result of the expression can be determined as zero (0) without evaluating the sub-expression B | C.

6.2.6: Arithmetic Operators

Unary Operators

The unary operators each require a single operand. The unary operators have the highest precedence of all the operators discussed in this chapter. The unary arithmetic operators take precedence over the binary operators. Table 6-5 shows the unary operators

Table 6-5: Unary Operators Defined

+m Unary plus m (same as m)

-m Unary minus m

! Logical Negator

~ Bitwise Unary Negator



Binary Operators

Table 6-6 shows the binary arithmetic operators. The binary operators each require two operands.

Integer division truncates any fractional part towards zero (0).

The modulus operator, for example y % z, gives the remainder when the first operand is divided by the second, and zero (0) when z divides y exactly. The result of a modulus operation takes the sign of the first operand.

For the case of the modulus operator where either argument is real, the operation performed is:

a % b = a - floor1(a/b)*b;

Table 6-7 gives examples of modulus operations.

Table 6-6: Arithmetic Operators Defined

a + b a plus b

a - b a minus b

a * b a multiply by b

a / b a divide by b

a % b a modulo b

1. floor(a/b)= largest integer less than or equal to (a/b).

Table 6-7: Examples of Modulus Operations

Modulus expression Result Comments

11 % 3 2 11/3 yields a remainder of 2.

12 % 3 0 12/3 yields no remainder.

-10 % 3 -1 The result takes the sign of the first operand

11 % -3 2 The result takes the sign of the first operand

10 % 3.75 2.5 [10 - floor (10/3.75) * 3.75 ] yields a remainder of 2.5.



6.2.7: Relation OperatorsTable 6-8 lists and defines the relational operators.

An expression using these relational operators yields the value zero (0) if the specified relation is false, or the value one (1) if it is true. All the relational operators have the same precedence. Relational operators have lower precedence than arithmetic operators. The following examples show the implications of this precedence rule.

Examples

a < Fxx - 1 // this expression is the same asa < (Fxx -1) // this expression, but...Fxx - (1 < a) // this one is not the same asFxx - 1 < a // this expression

When Fxx - (1 < a) is evaluated, the relational expression is evaluated first, and then either zero (0) or one (1) is subtracted from Fxx. When Fxx - 1 < a is evaluated, the value of Fxx operand is reduced by one (1) and then compared with a.

6.2.8: Case Equality OperatorsThe case equality operators share the same level of precedence as the logical equality operators.

6.2.9: Logical Quality OperatorsThe logical equality operators rank lower in precedence than the relational operators. Table 6-9 lists and defines the equality operators.

Both equality operators have the same precedence. These operators compare the value of the operands. As with the relational operators, the result shall be zero (0) if comparison fails, or else one (1) if it succeeds.

Table 6-8: Relational Operators Defined

a < b a less than b

a > b a greater than b

a <= b a less than or equal to b

a >= b a greater than or equal to b

Table 6-9: Equality Operators Defined

a == b a equal to b

a != b a not equal to b



6.2.10: Logical OperatorsThe operators logical and (&&), and logical or (| |) are logical connectives. The result of the evaluation of a logical comparison can be one (1, defined as true) or zero (0 defined as false). The precedence of && is greater than that of || and both are lower than relational and equality operators. A third logical operator is the unary logical negation operator (!). The negation operator converts a non-zero or true operand into zero (0), and a zero or false operand into one (1).

Examples

The following expression performs a logical and three sub-expressions without needing any parentheses:

a < param1 && b != c && index != lastone

However, parentheses can be used to clearly show the precedence intended, as in the following rewrite of the above example:

(a < param1) && (b != c) && (index != lastone)

6.2.11: Bit-Wise OperatorsBit-wise operators perform bit-wise manipulations on the operands. The operator combines a bit in one operand with its corresponding bit in the other operand to calculate one bit for the result.

See Table 6-10 through Table 6-14 for details.



Table 6-14: Bit-Wise unary negation operator

~

0 1

1 0

Table 6-13: Bit-Wise binary exclusive nor operator

^~~^

0 1

0 1 0

1 0 1

Table 6-12: Bit-Wise binary or operator

Table 6-12:

| 0 1

0 0 1

1 1 1

Table 6-11: Bit-Wise exclusive or operator

^ 0 1

0 0 1

1 1 0

Table 6-10: Bit-Wise binary and operator

& 0 1

0 0 0

1 0 1



6.2.12: Shift OperatorsThe shift operators (<< >>) perform left and right shifts of their left operand by the number of bit positions given by the right operand. Both fill the vacated bit positions with zeros (0). The right operand is treated as an unsigned number.

Example

integer start, result;analog begin start = 1; result = (start << 2);end

In this example, the register result is assigned the binary value 0100, which 0001 shifted to the left two positions and zero-filled.

6.2.13: Ternary OperatorThere is only one ternary operator, the conditional operator. The conditional operator has the lowest precedence of all the operators listed in this chapter. A complete conditional operator expression looks like this:

conditional_expr ? true_expr : false_expr

If conditional_expr is true, the conditional operator evaluates to true_expr, otherwise to false_expr.

The conditional operator is right associative.

This operator performs the same function as the if-else construct. For example, the contribution statement:

V(out) <+ V(in) > 2.5 ? 0.0 : 5.0;

is equivalent to:

If (V(in) > 2.5) V(out) <+ 0.0;else V(out) <+ 5.0;

6.2.14: Event OR OperatorThe event or operator performs the occurance of any one of the elements that trigger the execution of the procedural statement following the event.

Example

analog begin @(initial_step or cross(V(smpl) -2.5, +1)) begin



Vout = (V(in) > 2.5); endV(out) <+ Vout;

end

The initial step is a global event, and cross() returns a monitered event. The variable Voutis set to zero (0) or one (1) whenever either event occurs.

6.2.15: ConcatenationsA concatenation is used for joining scalar elements into compound elements (buses or arrays) for the built-in types integer or real, or for elements declared type net_discipline. The concatenation is expressed using the brace characters ( ), with commas separating the expressions within.

Examples

module x; parameter real p1[0:2] = 1.0, 2.0, 3.0; ...endmodule

module y; parameter real pole1=0, pole2=0, pole3=0; x #(.p1(pole1, pole2, pole3) x1; ...endmodule

Module x defines a real array parameter p1. Module y instantiates x and overrides the array value of the parameter p1 of module x via the concatenation of the scalar parameters pole1, pole2, and pole3.

Concatenation can be expressed using a replication multiplier.

Example

c, 2a, b // equivalent to : c, a, b, a, b

The replication multiplier is a constant expression.



6.3: Analog OperatorsAnalog operators operate on an expression and return a value. They are functions that operate on more than just the current value of their arguments, they maintain their internal state, and their output is a function of both the input and the internal state.

Analog operators are referred to as filters. They include time derivative, time integral, and delay operators from calculus. They also include the transition and slew filters, which remove discontinuity from piece wise constant and continuous waveforms. They also include more traditional filters, such as those described with laplace and Z-transform descriptions.

One special analog operator is the limexp() function, which is a version of the exp() function with built in limits to improve convergence.

6.3.1: Restrictions To Analog OperatorsAnalog operators are subject to several important restrictions because they maintain their internal state.

• Analog operators shall not be used inside conditional (if and case) or looping (for) statements unless the conditional expression controlling the statement consists of terms which cannot change their value during the course of an analysis, i.e, unless the conditional expression is a genvar expression.

• Analog operators are not allowed in the repeat and while looping statements.

• Analog operators can only be used inside an analog block; they cannot be used inside an initialor always block, or inside a user defined function.

• It is illegal to specify a null argument in the argument list of an analog operator, except as specified elsewhere in this document.

These restrictions help prevent usage which could cause the internal state to be corrupted or become out of date, which results in anomalous behavior.

6.3.2: Vector or Array Arguments To Analog OperatorsSome analog operators require arrays or vectors to be passed as arguments: Laplace filters, Z-transform filters, and noise_table. An array can be passed as:

• array_identifier

• const_array_expression

A const_array_expression allows the arrays to be passed within the argument list without explicit declaration of the array object, as shown:

Syntax

const_array_expression const_arrayinit_element , const_arrayinit_element

const_arrayinit_element ::= constant_expression | integer_constant_expression constant_expression



6.3.3: Analog Operators and EquationsSimulators formulate the mathematical description of the system in terms of first order differential equations and solve them numerically. There is no direct way to solve a set of nonlinear differential equations so iterative approaches are used. When using iterative approaches, some criteria (tolerances) is needed to determine when the algorithm knows when it is close enough to the solution and then stops the iteration. Thus, each equation, at a minimum, shall have a tolerance defined and associated with it.

Occasionally, analog operators require new equations and new unknowns be introduced by the simulator to convert a module description into a set of first order differential equations. In this case, the simulator attempts to determine from context which tolerance to associate with the new equation and new unknown. Alternatively, these operators can be used to specify tolerances.

Specifying natures also directly enforces reusability, and allows other signal attributes to be accessed by the simulator.

6.3.4: Time Derivative OperatorThe ddt operator computes the time derivative of its argument, as shown in Table 6-15.

In DC analysis, ddt() returns zero (0). The optional parameter abstol is used as an absolute tolerance if needed. Whether an absolute tolerance is needed depends on the context where ddt() is used. The absolute tolerance, abstol or derived nature, applies to the output of the ddt operator and is the largest signal level that is considered negligible.

6.3.5: Time Integral OperatorThe idt operator computes the time integral of its argument, as shown in Table 6-16.

Table 6-15: Time Derivative

Operator Comments

ddt(expr)Returns , the time derivative of x, where x is expr.

ddt(expr, abstol) Same as above, except absolute tolerance is specified explicitly.

ddt(expr, nature) Same as above, except nature is specified explicitly.

Table 6-16: Time Integral

Operator Comments

idt(expr)Returns , the time integral of x from 0 to t with the initial

condition being computed in the DC analysis. Where x is expr.

idt(expr, ic)Returns , the time integral of x from 0 to t with the ini-

tial condition ic. In DC analysis, ic is returned. Where x is expr.

ddt------x t( )

x τ( ) τd0

t

∫

x τ( ) τ ic+d0

t

∫



When specified with initial conditions, idt() returns the value of the initial condition in DC and IC analyses whenever assert is given and is non-zero. Without initial conditions, idt() multiplies its arguments by infinity in DC analysis. Hence, without initial conditions, it can only be used in a system with feedback which forces its argument to zero (0).

The optional parameter abstol or nature is used to derive an absolute tolerance if needed. Whether an absolute tolerance is needed depends on the context where idt() is used. The asolute tolerance applies to the input of the idt operator and is the largest signal level that is considered negligible.

6.3.6: Circular Integrator OperatorThe idtmod operator, also called the circular integrator, converts an expression argument into its indefinitely integrated form similar to the idt operator, as shown it Table 6-17.

idt(expr, ic, assert)Returns , the time integral of x from t0 to t with the ini-

tial condition ic. idt returns ic when assert is non-zero. t0 is the time when assert last became 0. Where x is expr.

idt(expr, ic, assert, abstol) Same as above, except absolute tolerance is specified explic-itly.

idt(expr, ic, assert, nature) Same as above, except nature is specified explicitly.

Table 6-17: Circular Integrator

Operator Comments

idtmod(expr)Returns , the time integral of x from 0 to t with the initial

condition being computed in the DC analysis. Where x is expr.

idtmod(expr, ic)Returns , the time integral of x from 0 to t with the ini-

tial condition ic. In DC analysis, ic is returned. Where x is expr.

idtmod(expr, ic, modulus) Returns k, where 0 < k < modulus and k is

. Where x is

expr.

idtmod(expr, ic, modu-lus,offset)

Returns k, where 0 < k < offset + modulus and k is

. Where x is expr.

Table 6-16: Time Integral

Operator Comments

x τ( ) τ ic+dt0

t

∫

x τ( ) τd0

t

∫

x τ( ) τ ic+d0

t

∫

x τ( ) τ ic n mo×=+d ulus k n ...-3, -2, -1, 0, 1, 2, 3...=,+d0

t

∫

x τ( ) τ ic n mo×=+d ulus k+d0

t

∫



The initial condition is optional. If the initial condition is not specified, it defaults to zero (0). Regardless, the initial condition shall force the DC solution to the system.

If idtmod() is used in a system with feedback configuration which forces expr to zero (0), the initial condition can be omitted without any unexpected behavior during simulation. For example, an operational amplifier alone needs an initial condition, but the same amplifier with the right external feedback circuitry does not need a forced DC solution.

The output of the idtmod() function shall remain in the range:

offset <= idtmod < offset + modulus

The modulus shall be an expression which evaluates to a positive value. If the modulus is not specified, then idtmod() will behave like idt() and not limit the output of the integrator..

The default for offset is zero (0).

The following relationships between idtmod() and idt() shall hold at all times.

Examples

if:

y = idt(expr, ic);z = idtmod(expr, ic, modulus, offset);

then:

y = n*modulus + z; // n is an integer

where:

offset < z < modulus + offset

In this example, the circular integrator is useful in cases where the integral can get very large, such as a VCO. In a VCO we are only interested in the output values in the range [0, 2π]:

phase = idtmod(fc + gain*V(in), 0, 1, 0);V(OUT) <+ sin(2*‘M_PI*phase);

Here, the circular integrator returns a value in the range [0,1].

6.3.7: Absolute Delay Operatorabsdelay() implements the absolute transport delay for continuous waveforms (use the transitionoperator to delay discrete value waveforms). The general form is:

absdelay(input, td [, maxdelay])

idtmod(expr, ic, modu-lus,offset, abstol)

Same as above, except absolute tolerance is specified explicitly.

idtmod(expr, ic, modu-lus,offset,nature)

Same as above, except nature is specified explicitly.

Table 6-17: Circular Integrator

Operator Comments



input is delayed by the amount td. In all cases, td will be a positive number. If the optional maxdelay is specified, then td can vary; but it shall be an error if it becomes larger than maxdelay. If maxdelay is not specified, changes to td will be ignored. If maxdelay is specified, changes to tdare ignored and the initial value of maxdelay is used.

In DC and operating point analyses, absdelay() returns the value of its input. In AC and other small signal analyses, the absdelay operator phase-shifts the input expression to the output of the delay operator based on the following formula:

td is evaluated as a constant at a particular time for any small signal analysis. In time domain analyses, absdelay() introduces a transport delay equal to the instantaneous value of td based on the following formula:

The transport delay td can be either constant (typical case) or vary as a function of time (when maxdelay is defined). A time dependent transport delay is shown in Figure 6-1 with a ramp input to the absdelay operator for both positive and negative changes in the transport delay td and a maxdelay of 5.

Figure 6-1: Transport Delay Example

From time 0 to 2s, the output remains at input (0). With a delay of 2s, the output then starts tracking input(t - 2). At 3s, the transport delay changes from 2s to 4s, switching the outputback to input(0), since input(max(t-td, 0)) returns 0. The output remains at this level until 4s when it once again starts tracking the input from t = 0. At 5s the transport delay goes to 1s and the output correspondingly jumps from its current value to the value defined by input(t - 1).

6.3.8: Transition Filtertransition() smooths out piecewise constant waveforms. The transition filter is used to imitate transitions and delays on digital signals (for non-piecewise constant signals, see section 6.3.9). This function provides controlled transitions between discrete signal levels by setting the rise time and fall time of signal transitions, as shown in Figure 6-2.

Output ω( ) Input ω( ) e jωtd–⋅=

Output t( ) Input max t td 0,–( )( )=



Figure 6-2: Transition Filter

transition() stretches instantaneous changes in signals over a finite amount of time and can delay the transitions, as shown in Figure 6-3.

Figure 6-3: Shifting The Transition Filter

Syntax

The general form is:

transition(expr [ , td [ , rise_time [ , fall_time [ , time_tol ]]]])

transition() takes the following arguments (all real-valued expressions):

• the input expression, expr

• the delay time, td (shall be non-negative)

• the rise time (shall be greater than or equal to 0)• the fall time (shall be greater than or equal to 0)• the time_tol (shall be positive)

The input expression is expected to evaluate over time to a piecewise constant waveform. When applied, transition() forces all positive transitions of expr to occur over rise_time and all negative transitions to occur in fall_time (after an initial delay of td). Thus, td models transport delay and rise_time and fall_time model inertial delay.

transition() returns a real number which describes a piecewise linear function over time. The transition function causes the simulator to place time-points at both corners of a transition. If time_tol is not specified, the transition function causes the simulator to assure each transition is adequately resolved.

td, rise_time, fall_time, and time_tol are optional. If td is not specified, it is taken to be zero (0.0). If only a positive rise_time value is specified, the simulator uses it for both rise and fall



times. If neither rise nor fall time is specified or is equal to zero (0.0), the rise and fall time defaults to the value defined by ‘default_transition.

If ‘default_transition is not specified, the default behavior approximates the ideal behavior of a zero-duration transition. Forcing a zero-duration transition is undesirable because it could cause convergence problems. Instead, a negligible, but non-zero, transition time is used. The small non-zero transition time allows the simulator to shrink the timestep small enough so a smooth transition occurs, and convergence problems are avoided. The simulator does not force a time point at the trailing corner of a transition to avoid causing the simulator to take very small time steps, which would result in poor performance.

In DC analysis, transition() passes the value of the expr directly to its output. The transition filter is designed to smooth out piecewise constant waveforms. When applied to waveforms which vary smoothly, the simulation results are generally unsatisfactory. In addition, applying the transition function to a continuously varying waveform can cause the simulator to run slowly. Use transition() for discrete signals and slew() (see section 6.3.9:“Slew Filter”) for continuous signals.

Use short transitions with caution because they can cause the simulator to slow down to meet accuracy constraints.

The next code fragment demonstrates how the transition filter might be used.

// comparator modelanalog begin if ( V(in) > 0 ) begin Vout = 5; end else begin Vout = 0; end V(out) <+ transition(Vout);end

Warning: The transition filter is designed to smooth out piecewise constant waveforms. If one apply the transition filter to smoothly varying waveforms, the simulator might run slowly, and the results questionable. For smoothly varying waveforms, consider using the slew filter instead.

If interrupted on a rising transition, the transition filter adjusts the slope so that at the revised end of the transition the value is that of the new destination.



In the following example, a rising transition is interrupted when it is about three fourths complete, and the value of the new destination is below the value at the point of interruption. The transition filter computes the slope that would complete a transition from the new origin (not the value at the point of interruption) in the specified fall_time. The transition filter then uses the computed slope to transition from the current value to the new destination.

Figure 6-4: Complete Transition

An interruption in a falling transition causes the transition filter to behave in an equivalent manner.

With larger delays, it is possible for a new transition to be specified before a previously specified transition starts. The transition filter handles this by deleting any transitions that would follow a newly scheduled transition. A transition filter can have an arbitrary number of transitions pending. A transition filter is used in this way to implement the transport delay of discretely valued signals.

The following example implements a D-type flip flop. The transition filter smooths the output waveforms.

Example

module d_ff(vin_d, vclk, vout_q, vout_qbar);

If the new destination value is below the value at the point of interruption, the transition filter.

If the new destination value is above the value at the point of interruption, the transition filter.

1. Uses the value of the original destination as the value of the new origin.

1. Retains the original origin.

2. Adjusts the slope of the transition to the rate at which the value would decay from the value of the new origin to the value of the new destination in fall_time seconds.

2. Adjusts the slope of the transition to the rate at which the value would increase from the value of the origin to the value of the new destination in rise_time seconds.

3. Causes the value of the filter output to decay at the new slope, from the value at the point of interruption to the value at the new destination.

3. Causes the value of the filter output to increase at the new slope, from the value at the point of interruption to the at the new destination.



input vclk, vin_d;output vout_q, vout_qbar;electrical vout_q, vout_qbar, vclk, vin_d;parameter real vlogic_high = 5;parameter real vlogic_low = 0;parameter real vtrans_clk = 2.5;parameter real vtrans = 2.5;parameter real tdel = 3u from [0:inf);parameter real trise = 1u from (0:inf);parameter real tfall = 1u from (0:inf);integer x;analog begin @(cross( V(vclk) - vtrans_clk, +1 )) x = (V(vin_d) > vtrans); V(vout_q) <+ transition(vlogic_high*x + vlogic_low*!x,tdel, trise, tfall); V(vout_qbar) <+ transition(vlogic_high*!x + vlogic_low*x, tdel, trise, tfall);end

endmodule

The following example illustrates a use of the transition filter that should be avoided. The expression is dependent on a continuous signal and, as a consequence, the filter runs slowly.

I(p, n) <+ transition(V(p, n)/out1, tdel, trise, tfall); // Do not do this.

However, the following approach can be used to implement the same behavior in a statement that runs much faster.

I(p, n) <+ V(p, n)*transition(1/out1, tdel, trise, tfall); // Do this instead.

Examples

Example 1 - QAM modulator

In this example, the transition function is used to control the rate of change of the modulation signal in a QAM modulator.

module qam16(out, in);parameter freq=1.0, ampl=1.0, dly=0, ttime=1.0/freq;input [0:4] in;output out;electrical [0:4] in;electrical out;real x, y, thresh;integer row, col;

analog beginrow = 2*(V(in[3]) > thresh) + (V(in[2]) > thresh);col = 2*(V(in[1]) > thresh) + (V(in[0]) > thresh);x = transition(row - 1.5, dly, ttime);y = transition(col - 1.5, dly, ttime);V(out) <+ ampl*x*cos(2*‘M_PI*freq*$abstime) + ampl*y*sin(2*‘M_PI*freq*$abstime);

$bound_step(0.1/freq);end



endmodule

Example 2 - A/D converter

In this example, an analog behavioral N-bit analog to digital converter, demonstrates the ability of the transition function to handle vectors.

module adc(in, clk, out);parameter bits = 8, fullscale = 1.0, dly = 0, ttime = 10n;input in, clk;output [0:bits-1] out;electrical in, clk;electrical [0:bits-1] out;real sample, thresh;integer result[0:bits-1];

genvar i;

analog begin @(cross(V(clk)-2.5, +1)) begin

sample = V(in);thresh = fullscale/2.0;for (i = bits - 1; i >= 0; i = i - 1) begin if (sample > thresh) begin

result[i] = 1.0; sample = sample - thresh;end else begin result[i] = 0.0;end sample = 2.0*sample;

end end

for (i = 0; i < bits; i = i + 1) begin V(out[i]) <+ transition(result[i], dly, ttime); endend

endmodule

6.3.9: Slew FilterUse the slew filter to control the rate of change of a waveform. A typical use for slew is generating continuous signals from piecewise continuous signals. For discrete signals, consider using the transition filter instead.

slew(expr [ , max_pos_rate [ , max_neg_rate ] ] )

expr is a dynamic expression with a real value.

max_pos_rate is a dynamic real number greater than zero, which is the maximum positive slew rate.

max_neg_rate is a dynamic real number less than zero, which is the maximum negative slew rate.



If only one rate is specified, its absolute value is used for both rates. If no rates are given, slew passes the signal through unchanged. If the rate of change of expr is less than the specified maximum slew rates, slew returns the value of expr..

When applied, slew forces all transitions of expr faster than max_pos_rate to change at the max_pos_rate rate for positive transitions, and limits negative transitions to the max_neg_raterate.

Figure 6-5: Slew Filter

The slew filter is particularly valuable for controlling the rate of change of sinusoidal waveforms. The transition function distorts such signals, whereas slew preserves the general shape of the waveform.

The following 4-bit digital-to-analog converter uses the slew function to control the rate of change of the analog signal at its output.

Example

module dac4(d, out);input [0:3] d;inout out;electrical [0:3] d;electrical out;parameter real slewrate = 0.1e6 from (0:inf);real Ti;real Vref;real scale_fact;analog begin Ti = 0; Vref = 1.0; scale_fact = 2; generate ii (3,0,-1) begin Ti = Ti + ((V(d[ii]) > 2.5) ? (1.0/scale_fact) : 0); scale_fact = scale_fact/2; end V(out) <+ slew( Ti*Vref, slewrate );end

endmodule



6.3.10: last_crossing functionRelated to the cross() function, the last_crossing() function returns a real value representing the simulation time when a signal expression last crossed zero (0). The general form is:

last_crossing( expr , direction ) ;

The direction flag is interpreted in the same way as in the cross() function. The last_crossing() function is subject to the same usage restrictions as the cross() function. The last_crossing() function does not control the timestep to get accurate results; it uses linear interpolation to estimate the time of the last crossing. However, it can be used with the cross function for improved accuracy.

Example

The following example measures the period of its input signal using the cross() and last_crossing() functions.

module period(in);input in;voltage in;integer crossings;real latest, previous;

analog begin @(initial_step) begin crossings = 0; previous = 0; end

@(cross(V(in), +1)) begin crossings = crossings + 1; previous = latest; end latest = last_crossing(V(in), +1);

@(final_step) begin if (crossings < 2) $strobe("Could not measure period."); else $strobe("period = %g, crossings = %d", latest-previous, crossings); endend endmodule

Before the expression crosses zero (0) for the first time, the last_crossing() function returns a negative value.

6.3.11: Laplace Transform FiltersThe Laplace transform filters implement lumped linear continuous-time filters. Each filter takes an optional parameter ε, which is a real number or a nature used for deriving an absolute tolerance (if



needed). Whether an absolute tolerance is needed depends on the context where the filter is used. The zeros argument may be represented as a null argument. The null argument is characterized by two adjacent commas (,,) in the argument list.

laplace_zp

laplace_zp() implements the zero-pole form of the Laplace transform filter. The general form is:

laplace_zp( expr , ζ , ρ [ , ε ] )

where ζ (zeta) is a vector of M pairs of real numbers. Each pair represents a zero, the first number in the pair is the real part of the zero and the second is the imaginary part. Similarly, ρ (rho) is the vector of N real pairs, one for each pole. The poles are given in the same manner as the zeros. The transfer function is:

where and are the real and imaginary parts of the kth zero (0), while and are the real

and imaginary parts of the kth pole. If a root (a pole or zero) is real, the imaginary part shall be specified as zero (0). If a root is complex, its conjugate shall also be present. If a root is zero, then the term associated with it is implemented as s, rather than (1 - s/r) (where r is the root).

laplace_zd

laplace_zd() implements the zero-denominator form of the Laplace transform filter. The general form is:

laplace_zd( expr , ζ , d [ , ε ] )

where ζ (zeta) is a vector of M pairs of real numbers. Each pair represents a zero, the first number in the pair is the real part of the zero and the second is the imaginary part. Similarly, d is the vector of N real numbers containing the coefficients of the denominator. The transfer function is:

H s( )

1s

ζkr jζk

i+--------------------–

k 0=

M 1–

∏

1s

ρkr jρk

i+---------------------–

k 0=

N 1–

∏----------------------------------------------=

ζrk

ζik

ρrk

ρik

H s( )

1s

ζkr jζk

i+--------------------–

k 0=

M 1–

∏

dksk

k 0=

N 1–

∑----------------------------------------------=



where and are the real and imaginary parts of the kth zero, while dk is the coefficient of the kth

power of s in the denominator. If a zero is real, the imaginary part shall be specified as zero (0). If a zero is complex, its conjugate shall also be present. If a zero is zero (0), then the term associated with it is implemented as s, rather than (1 - s/ζ).

laplace_np

laplace_np() implements the numerator-pole form of the Laplace transform filter. The general form is:

laplace_np( expr , n , ρ [ , ε ] )

where nk is a vector of M real numbers containing the coefficients of the numerator. Similarly, ρ (rho) is a vector of N pairs of real numbers. Each pair represents a pole, the first number in the pair is the real part of the pole and the second is the imaginary part. The transfer function is:

where nk is the coefficient of the kth power of s in the numerator, while and are the real and

imaginary parts of the kth pole. If a pole is real, the imaginary part shall be specified as zero (0). If a pole is complex, its conjugate shall also be present. If a pole is zero (0), then the term associated with it is implemented as s, rather than (1 - s/ρ).

laplace_nd

laplace_nd() implements the numerator-denominator form of the Laplace transform filter.

The general form is:

laplace_nd( expr , n , d [ , ε ] )

where n is an vector of M real numbers containing the coefficients of the numerator, and d is a vector of N real numbers containing the coefficients of the denominator. The transfer function is:

ζrk

ζik

H s( )

nksk

k 0=

M 1–

∑

1s

ρkr jρk

i+---------------------–

k 0=

N 1–

∏----------------------------------------------=

ρrk

ρik

H s( )

nksk

k 0=

M

∑

dksk

k 0=

N

∑----------------------=



where nk is the coefficient of the kth power of s in the numerator and dk is the coefficient of the kth

power of s in the denominator.

Examples

V(out) <+ laplace_zp(V(in), -1,0, -1,-1,-1,1);

implements:

and

V(out) <+ laplace_nd(V(in), 0,1, -1,0,1);

implements:

This example:

V(out) <+ laplace_zp(white_noise(k), , 1,0,1,0,-1,0,-1,0);

implements a band-limited white noise source as:

6.3.12: Z-Transform FiltersThe Z-transform filters implement linear discrete-time filters. Each filter supports a parameter Twhich specifies the sampling period of the filter. A filter with unity transfer function acts like a simple sample-and-hold, which samples every T second and exhibits no delay. The zeros argument may be represented as a null argument. The null argument is characterized by two adjacent commas (,,) in the argument list.

All Z-transform filters share three common arguments: T, τ, and t0. T specifies the period of the filter, is mandatory, and shall be positive. τ specifies the transition time, is optional, and shall be nonnegative.

If the transition time is specified and is non-zero, the timestep is controlled to accurately resolve both the leading and trailing corner of the transition. If it is not specified, the transition time is taken to be one (1) unit of time (as defined by the ‘default_transition compiler directive) and the timestep is not controlled to resolve the trailing corner of the transition. If the transition time is specified as zero (0), then the output is abruptly discontinuous. A Z-filter with zero (0) transition time shall not be directly assigned to a branch.

Finally t0 specifies the time of the first transition, and is also optional. If not given, the first transition occurs at t=0.

H s( ) 1 s+

1s

1 j+-----------+

1s

1 j–----------+

----------------------------------------------------=

H s( ) s

s2 1–--------------=

v2out

k

s2 1–2

-------------------=



zi_zp

zi_zp() implements the zero-pole form of the Z-transform filter. The general form is:

zi_zp( expr , ζ , ρ , T [ , τ [ , t0 ] ] )

where ζ (zeta) is a vector of M pairs of real numbers. Each pair represents a zero, the first number in the pair is the real part of the zero (0) and the second is the imaginary part. Similarly, ρ (rho) is the vector of N real pairs, one for each pole. The poles are given in the same manner as the zeros. The transfer function is:

where and are the real and imaginary parts of the kth zero, while and are the real and

imaginary parts of the kth pole. If a root (a pole or zero) is real, the imaginary part shall be specified as zero. If a root is complex, its conjugate shall also be present. If a root is zero (0), then the term associated with it is implemented as z, rather than (1 - z/r) (where r is the root).

zi_zd

zi_zd() implements the zero-denominator form of the Z-transform filter.

The form is:

zi_zd( expr , ζ , d , T [ , τ [ , t0] ] )

where ζ (zeta) is a vector of M pairs of real numbers. Each pair represents a zero, the first number in the pair is the real part of the zero and the second is the imaginary part. Similarly, d is the vector of N real numbers containing the coefficients of the denominator. The transfer function is:

where and are the real and imaginary parts of the kth zero, while dk is the coefficient of the

kth power of s in the denominator. If a zero is real, the imaginary part shall be specified as zero (0). If a zero is complex, its conjugate shall also be present. If a zero is zero (0), then the term associated with it is implemented as z, rather than (1 - z/ζ).

H z( )

1 z 1– ζ( kr jζk

i )+–

k 0=

M 1–

∏

1 z 1– ρ( kr jρk

i )+–

k 0=

N 1–

∏------------------------------------------------------=

ζrk

ζik

ρrk

ρik

H z( )

1 z 1– ζ( kr jζk

i )+–

k 0=

M 1–

∏

dkz 1–

k 0=

N 1–

∑-----------------------------------------------------=

ζrk

ζik



zi_np

zi_np() implements the numerator-pole form of the Z-transform filter. The general form is:

zi_np( expr , n , ρ , T [ , τ [ , t0] ] )

where n is a vector of M real numbers containing the coefficients of the numerator. Similarly, ρ (rho) is a vector of N pairs of real numbers. Each pair represents a pole, the first number in the pair is the real part of the pole and the second is the imaginary part. The transfer function is:

where nk is the coefficient of the kth power of s in the numerator, while and are the real and

imaginary parts of the kth pole. If a pole is real, the imaginary part shall be specified as zero (0). If a pole is complex, its conjugate shall also be present. If a pole is zero (0), then the term associated with it is implemented as z, rather than (1 - z/ρ).

zi_nd

zi_nd() implements the numerator-denominator form of the Z-transform filter. The

general form is:

zi_nd( expr , n , d , T [ , τ [ , t0] ] )

where n is an vector of M real numbers containing the coefficients of the numerator and d is a vector of N real numbers containing the coefficients of the denominator. The transfer function is:

where nk is the coefficient of the kth power of s in the numerator and dk is the coefficient of the kth

power of s in the denominator.

6.3.13: Limited ExponentialThe limexp() function is an operator whose internal state contains information about the argument on previous iterations. It returns a real value which is the exponential of its single real argument, however, it internally limits the change of its output from iteration to iteration in order to improve

H z( )

nkz k–

k 0=

M 1–

∑

1 z 1– ρ( kr jρk

i )+–

k 0=

N 1–

∏------------------------------------------------------=

ρrk

ρik

H z( )

nkz k–

k 0=

M 1–

∑

dkz k–

k 0=

N 1–

∑-------------------------=



convergence. On any iteration where the change in the output of the limexp() function is bound, the simulator is prevented from terminating the iteration. Thus, the simulator can only converge when the output of limexp() equals the exponential of the input. The general form is:

limexp ( expr )

The apparent behavior of limexp() is not distinguishable from exp(), except using limexp() to model semiconductor junctions generally results in dramatically improved convergence. There are different ways of implementing limiting algorithms for the exponential.

Table 6-18 summarizes the arguments of the analog operators defined in this section.

If a dynamic expression is passed as an argument which expects a constant expression, the value of the dynamic expression at the start of the analysis defaults to the constant value of the argument. Any further change in value of that expression is ignored during the iterative analysis.

Table 6-18: Analog Operator Arguments

Operator Constant Expression Arguments Dynamic Expression Arguments

ddt abstol expr

idt abstol expr, ic, assert

idtmod abstol expr, ic, modulus, offset

cross expr_tol, time_tol expr, dir

last_crossing expr, dir

delay maxdelay expr, td

transition expr, td, rise_time, fall_time

slew expr, max_pos_slew_rate, max_neg_slew_rate

zi_zpzi_zdzi_npzi_nd

zeros, poles, T, t0 expr, τ

laplace_zplaplace_zdlaplace_nplaplace_nd

poles, abstol, zero expr

timer Time_tol start_time, period

limexp expr


Chapter 7:Built-In Mathematical Functions

7.1: Standard Mathematical FunctionsThese are the standard mathematical functions supported by VERILOG-A. The operands must be integers or real numbers.

Table 7-1: Mathematical Functions

Function Description Domain Returned Value

ln(x) Natural logarithm x > 0 Real

log(x) Decimal logarithm x > 0 Real

exp(x) Exponential x < 80 Real

limexp (expr) expr is a dynamic expression of type Real. The limexp function limits the iteration step size to improve conver-gence. limexp behaves like the exp function.

Real

sqrt(x) Square root x > 0 Real

min(x,y) Minimum All x, all y Integer, if x and y are integers; otherwise, real

max(x,y) Maximum All x, all y Integer, if x and y are integers; otherwise, real

abs(x) Absolute All x Integer, if x is integer; otherwise, real

pow(x,y) Power of (xy) All y, if x > 0 y >= 0, if x = 0 y inte-ger, if x < 0

Real

floor(x) Largest integer less than or equal to x

All x Integer

ceil(x) Smallest integer larger than or equal to x

All x Integer



7.2: Trigonometric and Hyperbolic FunctionsThese are the trigonometric and hyperbolic functions supported by VERILOG-A. The operands must be integers or real numbers. The simulator converts operands to real numbers if necessary.

The trigonometric and hyperbolic functions require operands specified in radians.

Table 7-2: Trigonometric and Hyperbolic Functions

Function Description Domain

sin(x) Sine All x

cos(x) Cosine All x

tan(x) Tangent x≠ n(π/2), n is odd

asin(x) Arc-sine -1 <= x <= 1

acos(x) Arc-cosine -1 <= x <= 1

atan(x) Arc-tangent All x

atan2(x,y) Arc-tangent of x/y All x, all y

hypot(x,y) Sqrt(x2 + y2) All x, all y

sinh(x) Hyperbolic sine All x

cosh(x) Hyperbolic cosine All x

tanh(x) Hyperbolic tangent All x

asinh(x) Arc-Hyperbolic sine All x

acosh(x) Arc-Hyperbolic cosine x >= 1

atanh(x) Arc-Hyperbolic tangent -1 <= x <= 1


Chapter 8:Analog Events

8.1: Detecting and Using EventsUse the @ operator to run a statement under the control of particular events.

The analog behavior of a component can be controlled using events. Events have the following characteristics:

• events have no time duration• events can be triggered and detected in different parts of the behavioral model• events do not block the execution of an analog block• events can be detected using the @ operator• events do not hold any data• there can be both digital and analog events

There are two types of analog events, global events (see Section 8.1.4:“Global Events”) and monitored events (see Section 8.1.5:“Monitored Events”). Null arguments are not allowed in analog events.

8.1.1: Event DetectionAnalog event detection consist of an event expression followed by a procedural statement, as shown below:

Syntax

event_control_statement ::= event_control statement_or_null

event_control ::= @ event_identifier | @ ( event_expression )

analog_event_expression ::= global_event | event_function | digital_expression | event_identifier | posedge digital_expression | negedge digital_expression | event_expression or event_expression

The procedural statement following the event expression is executed whenever the event described by the expression changes. The analog event detection is non-blocking, meaning the execution of the procedural statement is skipped unless the analog event has occurred. The event expression consists of one or more signal names, global events, or monitored events separated by the or operator.

The parenthesis around the event expression are required.



8.1.2: Event OR OperatorThe “OR-ing” of events indicates the occurrence of any one of the events specified shall trigger the execution of the procedural statement following the event. The keyword or is used as an event OR operator.

Example

analog begin @(initial_step or cross(V(smpl)-2.5,+1)) begin vout = (V(in) > 2.5); end V(out) <+ vout;end

Here, initial_step is a global event and cross() returns a monitored event. The variable vout is set to zero (0) or one (1) whenever either event occurs.

8.1.3: Event Triggered StatementsThe following two restrictions apply to statements which are evaluated as a result of an event being triggered.

• The statement can not have expressions which use analog operators. This statement can not maintain its internal state since it is only executed intermittently when the corresponding event is triggered.

• The statement can not be a contribution statement because it can generate discontinuity in analog signals.

8.1.4: Global EventsGlobal events are generated by a simulator at various stages of simulation. The user model can not generate these events. These events are detected by using the name of the global event in an event expression with the @ operator.

Global events are pre-defined in VERILOG-A. These events can not be redefined in a model.

The pre-defined global events are shown below:

Syntax

global_event ::= initial_step [ ( analysis_list ) ] | final_step [ ( analysis_list ) ]

analysis_list ::= analysis_name , analysis_name

analysis_name ::= " analysis_identifier "


Analog Events

initial_step and final_step generate global events on the first and the last point in an analysis respectively. They are useful when performing actions which should only occur at the beginning or the end of an analysis. Both global events can take an optional argument, consisting of an analysis list for the active global event.

Example

@(initial_step(“ac”, “dc”)) // active for dc and ac only@(initial_step(“tran”)) // active for transient only

Table 8-1 describes the return value of initial_step and final_step for standard analysis types. Each column shows the return-on-event status. One (1) represents Yes and zero (0) represents No. A VERILOG-A simulator can use any or all of these typical analysis types.

OP = Operating Point. pX = analysis point X where X = 1 to N.

Example

The following example measures the bit-error rate of a signal and prints the result at the end of the simulation.

module bitErrorRate(in, ref);input in, ref;electrical in, ref;parameter real period=1, thresh=0.5;integer bits, errors;

analog begin

Table 8-1: Reaturn Values for initial_step and final_step

AnalysisDCOP

TRANOP p1 pN

ACOP p1 pN

NOISEOP p1 pN

initial_step() 1 1 0 0 1 0 0 1 0 0

initial_step(“ac”) 0 0 0 0 1 0 0 0 0 0

initial_step(“noise”) 0 0 0 0 0 0 0 1 0 0

initial_step(“tran”) 0 1 0 0 0 0 0 0 0 0

initial_step(“dc”) 1 0 0 0 0 0 0 0 0 0

initial_step(unkown) 0 0 0 0 0 0 0 0 0 0

final_step() 0 0 0 1 0 0 1 0 0 1

final_step(“ac”) 0 0 0 0 0 0 1 0 0 0

final_step(“noise”) 0 0 0 0 0 0 0 0 0 1

final_step(“tran”) 0 0 0 1 0 0 0 0 0 0

final_step(“dc”) 1 0 0 0 0 0 0 0 0 0

final_step(unkown) 1 0 0 0 0 0 0 0 0 0



@(initial_step) begin bits = 0; errors = 0; end

@(timer(0, period)) begin if ((V(in) > thresh) != (V(ref) > thresh)) errors = errors + 1; bits = bits + 1; end

@(final_step) $strobe("bit error rate = %f%%", 100.0 * errors / bits ); end

endmodule

initial_step and final_step take a list of quoted strings as optional arguments. The strings are compared to the name of the analysis being run. If any string matches the name of the current analysis name, the simulator generates an event on the first point and the last point of that particular analysis, respectively.

If no analysis list is specified, the initial_step global event is active during the solution of the first point (or initial DC analysis) of every analysis. The final_step global event, without an analysis list, is only active during the solution of the last point of every analyses.

8.1.5: Monitored EventsMonitored events are detected using event functions with the @ operator. The triggering of a monitored event is implicit due to change in signals, simulation time, or other runtime conditions.

Syntax

event_function ::= cross_function | timer_function

cross function

The cross() function is used for generating a monitored analog event to detect threshold crossings in analog signals when the expression crosses zero (0) in the specified direction. In addition, cross() controls the timestep to accurately resolve the crossing. The general form is:

cross ( expr [ , dir [ , time_tol [ , expr_tol ] ] ] ) ;

where expr is required, and dir, time_tol, and expr_tol are optional. All arguments are real expressions, except dir (which is an integer expression). If the tolerances are not defined, then the tool (e.g., the simulator) sets them. If either or both tolerances are defined, then the direction shall also be defined.

The direction indicator can only evaluate to +1, -1, or 0. If it is set to 0 or is not specified, the event and timestep control occur on both positive and negative crossings of the signal. If dir is +1 (or -1), the


Analog Events

event and timestep control only occur on rising edge (falling edge) transitions of the signal. For any other transitions of the signal, the cross() function does not generate an event.

expr_tol and time_tol are defined as shown in Figure 8-1. They represent the maximum allowable error between the estimated crossing point and the true crossing point.

Figure 8-1: Relationship between time tolerance in expression tolerance

If expr_tol is defined, time_tol shall also be defined and both tolerances shall be satisfied at the crossing.

Example

The following description of a sample-and-hold illustrates how the cross() function can be used.

module sh(in, out, smpl);output out;input in, smpl;electrical in, out, smpl;real state;

analog begin @(cross(V(smpl) - 2.5, +1)) state = V(in); V(out) <+ transition(state, 0, 10n);end

endmodule

The cross() function maintains its internal state and has the same restrictions as analog operators. In particular, it shall not be used inside an if(), case(), casex(), or casez() statement unless the conditional expression is a genvar expression. In addition, cross() is not allowed in the repeat() and while() iteration statements. It is allowed in the analog_for statements.

timer function

The timer() function is used to generate analog events to detect specific points in time. The general form is:

timer ( start_time [ , period [ , time_tol ] ] ) ;



where start_time is required; period and time_tol are optional arguments. All arguments are real expressions.

The timer() function schedules an event which occurs at an absolute time (start_time). The analog simulator places a time point within timetol of an event. At that time point, the event evaluates to True.

If time_tol is not specified, the default time point is at, or just beyond, the time of the event. If the period is specified as greater than zero (0), the timer function schedules subsequent events at multiples of period.

Example

A pseudo-random bit stream generator is an example how the timer function can be used.

module bitStream (out);output out;electrical out;parameter period = 1.0;integer x;

analog begin @(timer(0, period)) x = $random + 0.5; V(out) <+ transition( x, 0.0, period/100.0 );end

endmodule


Chapter 9:Simulator Functions

9.1: Analysis Dependent FunctionThis section describes the analysis() function, which is used to determine what type of analysis is being performed, and the small-signal source functions. The small-signal source functions only affect the behavior of a module during small-signal analyses. The small-signal analyses provided by SMARTSPICE include the AC and noise analyses, but others are possible. When not active, the small-signal source functions return zero (0).

9.1.1: AnalysisThe analysis() function takes one or more string arguments and returns one (1) if any argument matches the current analysis type. Otherwise it returns zero (0). The general form is:

analysis( analysis_list )

There is no fixed set of analysis types. Each simulator can support its own set. However, simulators shall use the types listed in Table 9-1 to represent analyses which are similar to those provided by SMARTSPICE.

Any unsupported type names are assumed to not be a match.

Table 9-2 describes the implementation of the analysis function. Each column shows the return value of the function. A status of one (1) represents True and zero (0) represents False.

Table 9-1: Analysis Types

Name Analysis Description

“ac” .AC analysis

“dc” .OP or .DC analysis

“noise” .NOISE analysis

“tran” .TRAN analysis

“ic” The inital condition analysis which precedes a transient analysis.

“static” Any equilibrium point calculation, including a DC analysis as well as those that precede another analysis, such as the DC analysis which precedes an AC or noise analysis, or the IC analysis which precedes a transient analysis.

“nodeset” The phase during an equilibrium point calculation where nodesets are forced.



Using the analysis() function, it is possible to have a module behave differently depending on which analysis is being run.

Example

To implement nodesets or initial conditions using the analysis function and switch branches, use the following:

if (analysis("ic")) V(cap) <+ initial_value;else I(cap) <+ ddt(C*V(cap));

9.1.2: AC stimulusA small-signal analysis computes the steady-state response of a system which has been linearized about its operating point and is driven by a small sinusoid. The sinusoidal stimulus is provided using the ac_stim() function. The general form is:

ac_stim( [analysis_name [ , mag [ , phase ] ] ] )

The AC stimulus function returns zero (0) during large-signal analyses (such as DC and transient) as well as on all small-signal analyses using names which do not match analysis_name. The name of a small-signal analysis is implementation dependent, although the expected name (of the equivalent of a SPICE AC analysis) is “ac”, which is the default value of analysis_name. When the name of the small-signal analysis matches analysis_name, the source becomes active and models a source with magnitude mag and phase phase. The default magnitude is one (1) and the default phase is zero (0). phase is given in radians.

Table 9-2: Return Values for analysis functions

Analysis Arguments Simulator Analysis DC TRAN AC NOISE OP TRAN OP AC OP AC

First part of “static”

“nodeset 1 1 0 1 0 1 0

Initial DC state “static” 1 1 0 1 0 1 0

Initial condition “ic” 0 1 0 0 0 0 0

DC “dc” 1 0 0 0 0 0 0

Transient “tran” 0 1 1 0 0 0 0

Small-signal “ac” 0 0 0 1 1 0 0

Noise “noise” 0 0 0 0 0 1 1


Simulator Functions

9.1.3: NoiseSeveral functions are provided to support noise modeling during small-signal analyses. To model large-signal noise during transient analyses, use the $random() system task. The noise functions are often referred to as noise sources. There are three noise functions, one models white noise processes, another models 1/f or flicker noise processes, and the last interpolates a vector to model a process where the spectral density of the noise varies as a piecewise linear function of frequency. The noise functions are only active in smallsignal noise analyses and return zero (0) otherwise.

white_noise

White noise processes are those whose current value is completely uncorrelated with any previous or future values. This implies their spectral density does not depend on frequency. They are modeled using:

white_noise( pwr [ , name ] )

which generates white noise with a power of pwr.

Example

The thermal noise of a resistor could be modelled using:

I(a,b) <+ V(a,b)/R + white_noise(4*‘P_K*$temperature/R, "thermal");

The optional name argument acts as a label for the noise source used when the simulator outputs the individual contribution of each noise source to the total output noise. The contributions of noise sources with the same name from the same instance of a module are combined in the noise contribution summary.

flicker_noise

The flicker_noise() function models flicker noise. The general form is:

flicker_noise( pwr , exp [ , name ] )

which generates pink noise with a power of pwr at 1Hz which varies in proportion to 1/f exp.


noise_table

The noise_table() function interpolates a vector to model a process where the spectraldensity of the noise varies as a piecewise linear function of frequency. The general form is:



noise_table( vector [ , name ] )

where vector contains pairs of real numbers: the first number in each pair is the frequency in Hertz and the second is the power. Noise pairs are specified in the order of ascending frequencies. noise_table() performs piecewise linear interpolation to compute the power spectral density generated by the function at each frequency.


Noise model for diode

The noise of a junction diode could be modelled as shown in the following example.

I(a,c) <+ is*(exp(V(a,c) / (n * $vt)) - 1) + white_noise(2*‘P_Q*I(<a>)) + flicker_noise(kf*pow(abs(I(<a>)), af), ef);

Correlated noise

Each noise function generates noise which is uncorrelated with the noise generated by other functions. Perfectly correlated noise is generated by using the output of one noise function for more than one noise source. Partially correlated noise is generated by combining the output of shared and unshared noise functions.

Examples

Example 1 - Two noise voltages are perfectly correlated.

n = white_noise(pwr);V(a,b) <+ c1*n;V(c,d) <+ c2*n;

Example 2 - Partially correlated noise sources can also be modelled.

n1 = white_noise(1-corr);n2 = white_noise(1-corr);n12 = white_noise(corr);V(a,b) <+ Kv*(n1 + n12);I(b,c) <+ Ki*(n2 + n12);


Simulator Functions

9.2: DiscontinuityThe $discontinuity function informs the simulator about a discontinuity in signal behavior.

discontinuity_function ::= $discontinuity[ (constant_expression) ]

constant_expression, which must be zero or a positive integer, is the degree of the discontinuity. For example, $discontinuity, which is equivalent to $discontinuity(0), indicates a discontinuity in the equation, and $discontinuity(1) indicates a discontinuity in the slope of the equation.

Discontinuities created by switch branches or built-in functions, such as transition and slew, do not need to be announced.

Using the $discontinuity function does not guarantee that the simulator will be able to handle a discontinuity successfully.

The following example shows the $discontinuity function while describing the behavior of a source that generates a triangular wave. As the TriangularWave (see Figure 9-1) shows, the triangular wave is continuous, but as the Triangular Wave First Derivative (see Figure 9-2) shows, the first derivative of the wave is discontinuous.

Figure 9-1: Triangular Wave

Figure 9-2: Triangular Wave First Derivative

Example

The module triangular_source describes this triangular wave source.

module triangular_source(vout);output vout;voltage vout;parameter real wavelength=10.0, amplitude=1.0;integer slope;real i_start;

analog begin



@(timer(0, wavelength)) begin slope = +1; i_start = $abstime; $discontinuity(1); // Change from neg to pos slope end @(timer(wavelength/2, wavelength)) begin slope = -1; i_start = $abstime; $discontinuity(1); // Change from pos to neg slope end V(vout) <+ amplitude * slope * (4*($abstime - i_start) / wavelength-1);end

endmodule

The two $discontinuity functions in trisource tell the simulator about the discontinuities in the derivative. In response, the simulator uses analysis techniques that take the discontinuities into account.

Example

The module relay, as another example, uses the $discontinuity function while modeling a relay.

module relay(p1, p2, pos, neg);inout p1, p2;input pos, neg;electrical p1, p2, pos, neg;parameter real r = 1;analog begin @(cross(V(pos, neg)-1, 0, 0.01n, pos.potential.abstol)) $discontinuity(0); if (V(pos, neg) >= 1) I(p1, p2) <+ V(p1, p2) / r; else I(p1, p2) <+ 0;end

endmodule

The $discontinuity function in relay tells the simulator that there is a discontinuity in the current when the voltage crosses the value 1. For example, passing a triangular wave like that shown in the Relay Voltage (see Figure 9-3) through module relay produces the discontinuous current shown in the Relay Current (see Figure 9-4).


Simulator Functions

Figure 9-3: Relay Voltage

Figure 9-4: Relay Current

9.3: Bounding the Time StepUse the $bound_step function to specify the maximum time allowed between adjacent time points during simulation.

bound_step_function ::= $bound_step( max_step )

max_step ::= constant_expression

By specifying appropriate time steps, the simulator is forced to track signals as closely as one model requires. For example, module sinwave forces the simulator to simulate at least 50 time points during each cycle.

Example

module sinwave(out_signal);output out_signal;voltage out_signal;parameter real freq=2.0, ampl=2.0;analog begin V(out_signal) <+ ampl * sin(2.0*’M_PI*freq*$abstime); $bound_step(0.02 / freq); // Max time step = 1/50 periodend

endmodule



9.4: Querying the Simulation EnvironmentUse the simulation environment functions described in the following sections to obtain information about the current simulation environment.

9.4.1: Obtaining Current Simulation TimeVERILOG-A provide two environment parameter functions that one can use to obtain the current simulation time: $abstime and $realtime.

$abstime Function

Use the $abstime function to obtain the current simulation time in seconds.

abstime_function ::= $abstime

$realtime Function

Use the $realtime function to obtain the current simulation time in seconds.

realtime_function ::= $realtime[(time_scale)]

time_scale is a value used to scale the returned simulation time. The valid values are the integers 1, 10, and 100, followed by one of the scale factors in the following table.

If time_scale is not specified, the return value is scaled to the ’time_unit of the module that invokes the function.

For example, to print out the current simulation time in seconds, code:

$strobe("Simulation time = %e", $realtime(1s));

9.4.2: Obtaining the Current Ambient TemperatureUse the $temperature function to obtain the ambient temperature of a circuit in degrees Kelvin.

temperature_function ::= $temperature

Scale Factor Meaning

s Seconds

ms Milliseconds

us Microseconds

ns Nanoseconds

ps Picoseconds

fs Femtoseconds


Simulator Functions

9.4.3: Obtaining the Thermal VoltageUse the $vt function to obtain the thermal voltage, (kT/q), of a circuit.

vt_function ::= $vt[(temp)]

temp is the temperature, in degrees Kelvin, at which the thermal voltage is to be calculated. If temp is not specified, the thermal voltage is calculated at the temperature returned by the $temperaturefunction.

9.5: Generating Random NumbersUse the $random function to generate a signed integer, 32-bit, pseudorandom number.

$random [ ( seed ) ] ;

seed is a reg, integer, or time variable used to initialize the function. The seed provides a starting point for the number sequence, and allows one to restart at the same point. If, as SILVACO recommends, seed is used, you must assign a value to the variable before calling the $random function.

The $random function generates a new number every time step.

Individual $random statements with different seeds generate different sequences, and individual $random statements with the same seed generate identical sequences.

The following code fragment uses the absolute value function and the modulus operator to generate integers between 0 and 99.

Example

module rand_gen(outpin);electrical outpin;integer rand_seed, rand_num;analog begin @(initial_step) begin rand_seed = 124; // Initialize the seed end rand_num = abs($random(rand_seed) % 100); if (rand_num < 5) V(outpin) <+ 0.0; else V(outpin) <+ 3.0;end

endmodule

or

module DataStream (out);output out;electrical out;

parameter PERIOD = 1.0u;parameter TR = 1p;



parameter TF = 1p;parameter seed = 5;

real y;integer rand_seed, x;

analog

begin@(initial_step) rand_seed = seed @(timer(0, period)) x = abs($random(rand_seed) %100); if (x >= 49) y = 1.8; else y = 0.0; V(out) <+ transition(y, 0.0, TR, TF); end

endmodule


Simulator Functions

9.6: Generating Random Numbers in Specified DistributionsVERILOG-A provides functions that generate random numbers in the following distribution patterns:

• Uniform• Normal (Gaussian)• Exponential• Poisson• Chi-square• Student's T• Erlang

9.6.1: Uniform DistributionUse the $rdist_uniform function to generate random real numbers (or the $dist_uniformfunction to generate integer numbers) that are evenly distributed throughout a specified range.

$rdist_uniform ( seed , start , end ) ;$dist_uniform ( seed , start , end ) ;

seed is a scalar integer variable used to initialize the sequence of generated numbers. seed must be a variable because the function updates the value of seed at each iteration. To ensure generation of a uniformdistribution, change the value of seed only when one initialize the sequence.

start is an integer expression that specifies the smallest number that the $dist_uniformfunction is allowed to return. start must be smaller than end.

end is an integer expression that specifies the largest number that the $dist_uniform function is allowed to return. end must be larger than start.

The following module returns a series of real numbers, each of which is between 20 and 80 inclusively.

Example

module uniform_check(outpin);electrical outpin;parameter integer start_range = 20; integer seed, end_range;real rand_num;analog begin @(initial_step) begin seed = 25; // Initialize the seed end_range = 80; end rand_num = $rdist_uniform(seed, start_range, end_range); $display("Random number is %g", rand_num ); $display("Current seed is %d", seed); V(outpin) <+ rand_num;end

endmodule



9.6.2: Normal (Gaussian) DistributionUse the $rdist_normal function to generate random real numbers (or the $dist_normalfunction to generate integer numbers) that are normally distributed.

$rdist_normal ( seed , mean , standard_deviation ) ;$dist_normal ( seed , mean , standard_deviation ) ;

seed is a scalar integer variable used to initialize the sequence of generated numbers. seed must be a variable because the function updates the value of seed at each iteration. To ensure generation of a normal distribution, change the value of seed only when one initialize the sequence.

mean is an integer expression that specifies the value to be approached by the mean value of the generated numbers.

standard_deviation is an integer expression that determines the width of spread of the generated values around mean. Using a larger standard_deviation spreads the generated values over a wider range.

To generate a gaussian distribution, use a mean of 0 and a standard_deviation of 1. For example, the following module returns a series of real numbers that together form a gaussian distribution.

Example

module normal_check(outpin);electrical outpin;integer seed;real rand_num;analog begin @(initial_step) begin seed = 25; end rand_num = $rdist_normal( seed, 0, 1 ); $display("Random number is %g", rand_num); V(outpin) <+ rand_num;end

endmodule

9.6.3: Exponential DistributionUse the $rdist_exponential function to generate random real numbers (or the $dist_exponential function to generate integer numbers) that are exponentially distributed.

$rdist_exponential ( seed , mean ) ;$dist_exponential ( seed , mean ) ;

seed is a scalar integer variable used to initialize the sequence of generated numbers. seed must be a variable because the function updates the value of seed at each iteration. To ensure generation of an exponential distribution, change the value of seed only when one initialize the sequence.

mean is an integer value greater than zero. mean specifies the value to be approached by the mean value of the generated numbers. For example, the following module returns a series of real numbers that together form an exponential distribution.


Simulator Functions

Example

module expo_check(outpin);electrical outpin;integer seed, mean;real rand_num;analog begin @(initial_step) begin seed = 25; mean = 6; end rand_num = $rdist_exponential(seed, mean); $display("Random number is %g", rand_num ); V(outpin) <+ rand_num;end

endmodule

9.6.4: Poisson DistributionUse the $rdist_poisson function to generate random real numbers (or the $dist_poissonfunction to generate integer numbers) that form a Poisson distribution.

$rdist_poisson ( seed , mean ) ;$dist_poisson ( seed , mean ) ;

seed is a scalar integer variable used to initialize the sequence of generated numbers. seed must be a variable because the function updates the value of seed at each iteration. To ensure generation of a Poisson distribution, change the value of seed only when one initialize the sequence.

mean is an integer value greater than zero. mean specifies the value to be approached by the meanvalue of the generated numbers. For example, the following module returns a series of real numbers that together form a Poisson distribution.

Example

module pois_check(outpin);electrical outpin;integer seed, mean;real rand_num;analog begin @(initial_step) begin seed = 25; mean = 6; end rand_num = $rdist_poisson(seed, mean); $display("Random number is %g", rand_num ); V(outpin) <+ rand_num;end

endmodule



9.6.5: Chi-Square DistributionUse the $rdist_chi_square function to generate random real numbers (or the $dist_chi_square function to generate integer numbers) that form a chi-square distribution.

$rdist_chi_square ( seed , degree_of_freedom ) ;$dist_chi_square ( seed , degree_of_freedom ) ;

seed is a scalar integer variable used to initialize the sequence of generated numbers. seed must be a variable because the function updates the value of seed at each iteration. To ensure generation of a chi-square distribution, change the value of seed only when one initialize the sequence.

degree_of_freedom is an integer value greater than zero. degree_of_freedom determines the width of spread of the generated values. Using a larger degree_of_freedom spreads the generated values over a wider range. For example, the following module returns a series of real numbers that together form a chi-square distribution.

Example

module chi_check(outpin);electrical outpin;integer seed, dof;real rand_num;analog begin @(initial_step) begin seed = 25; dof = 6; end rand_num = $rdist_chi_square(seed, dof); $display("Random number is %g", rand_num ); V(outpin) <+ rand_num;end

endmodule

9.6.6: Student’s T DistributionUse the $rdist_t function to generate random real numbers (or the $dist_t function to generate integer numbers) that form a Student’s T distribution.

$rdist_t ( seed , degree_of_freedom ) ;$dist_t ( seed , degree_of_freedom ) ;

seed is a scalar integer variable used to initialize the sequence of generated numbers. seed must be a variable because the function updates the value of seed at each iteration. To ensure generation of a Student’s T distribution, change the value of seed only when one initialize the sequence.

degree_of_freedom is an integer value greater than zero. degree_of_freedom determines the width of spread of the generated values. Using a larger degree_of_freedom spreads the generated values over a wider range. For example, the following module returns a series of real numbers that together form a Student’s T distribution.

Example

module student_T_check(outpin);electrical outpin;integer seed, dof;


Simulator Functions

real rand_num;analog begin @(initial_step) begin seed = 25; dof = 12; end rand_num = $rdist_t(seed, dof); $display("Random number is %g", rand_num ); V(outpin) <+ rand_num;end

endmodule

9.6.7: Erlang DistributionUse the $rdist_erlang function to generate random real numbers (or the $dist_erlangfunction to generate integer numbers) that form an Erlang distribution.

$rdist_erlang ( seed , k , mean ) ;$dist_erlang ( seed , k , mean ) ;

seed is a scalar integer variable used to initialize the sequence of generated numbers. seed must be a variable because the function updates the value of seed at each iteration. To ensure generation of an Erlang distribution, change the value of seed only when initializing the sequence.

k is an integer value greater than zero. Using a larger value for k decreases the variance of the distribution.

mean is an integer value greater than zero. mean specifies the value to be approached by the mean value of the generated numbers. For example, the following module returns a series of real numbers that together form an Erlang distribution.

Example

module erlang_check(outpin);electrical outpin;integer seed, k, mean;real rand_num;analog begin @(initial_step) begin seed = 25; k = 15; mean = 10; end rand_num = $rdist_erlang(seed, k, mean); $display("Random number is %g", rand_num); V(outpin) <+ rand_num;end

endmodule



9.7: Silvaco System FunctionsSilvaco provides system functions that are not defined in the OVI 2.0 standard. They have been added to the VERILOG-A interface, because from experience of transistor modeling at Silvaco, it has shown that they are very useful in helping the simulation of some models

Note: Because these tasks are not compliant with the OVI standard, they will not be recognized by Verilog-A compilers from other vendors.

9.7.1: $sit_get_prevReturns the value of a specified variable at a previous simulation point.

$sit_get_prev (variable, [iteration])

If the iteration argument is equal to zero (0), the value returned is the value from the previous iteration (during the same simulation point). If the iteration argument is equal to one (1), the value returned is the value from the previous simulation point.

If the iteration argument is omitted, the default value is zero (0).

Example

// We allow +/- 10V change between iterationsif (Vb2c1 - $sit_get_prev(Vb2c1, 1) > 10.0) begin Vb2c1 = $sit_get_prev(Vb2c1, 1) > 5.0; V(b2, c1) <+ Vb2c1;end // usage with no iteration argument Vds_prev = $sit_get_prev(Vds);

9.7.2: $sit_get_ddvReturns the derivative of an expression, with regard to a specific branch.

$sit_get_ddv (variable, branch_quality) ;

For each branch quantity expresions, the VERILOG-A compiler computes derivatives that are used to fill up the spice conductance matrix. These derivative values can be accessed through the internal task $sit_get_ddv.

Example

// $sit_get_ddv will return the value 5.0vds = 5 * V(d,s);Qds = $sit_get_ddv(vds, V(d,s));// $sit_get_ddv will return the value sin(V(d,s))vds = cos(V(d,s));Qds = $sit_get_ddv(vds, V(d,s));


Simulator Functions

9.8: Displaying ResultsVERILOG-A provides four tasks for displaying information: $strobe, $display, and $write.

$strobe

Use the $strobe task to display information on the screen. $strobe and $display use the same arguments, and are completely interchangeable.

strobe_task ::= $strobe [ ( list_of_arguments ) ]

list_of_arguments ::= argument | list_of_arguments , argument

The $strobe task prints a new-line character after the final argument. A $strobe task without any arguments prints only a new-line character.

Each argument is a quoted string or an expression that returns a value.

Each quoted string is a set of ordinary characters, special characters, or conversion specifications, all enclosed in one set of quotation marks. Each conversion specification in the string must have a corresponding argument following the string. One must ensure that the type of each argument is appropriate for the corresponding conversion specification.

An argument can be specified without a corresponding conversion specification. If you do, an integer argument is displayed using the %d format, and a real argument is displayed using the %g format.

Special Characters

Use the following sequences to include the specified characters and information in a quoted string.

Conversion Specifications

Conversion specifications have the form

Use this sequence To include

\n The new-line character

\t The tab character

\\ The backslash character, \

\” The quotation mark character, "

%% The percent character, %

%m or %M The hierarchical name of the current module, function, or named block



% [ flag ] [ field_width ] [ . precision ] format_character

where flag, field_width, and precision can be used only with a real argument.

flag is one of the three choices shown in the table:

field_width is an integer specifying the minimum width for the field.

precision is an integer specifying the number of digits to the right of the decimal point.

format_character is one of the following characters.

Examples of $strobe Formatting

The module is defined as:

module formatting_example;integer integer_val;real real_val;analog begin integer_val = 89; real_val = 125.456789; $strobe("Format D gives %D" , ival); $strobe("Format E (real) gives %E" , rval);

Flag Definition

- Left justify the output

+ Always print a sign

Blank space, or any character other than a sign.

Print a space

Format_character Type of Argument Output Example Output

c or C Integer ASCII character format

d or D Integer Decimal format 181, 42, -267

e or E Real Real, exponential format -1.0, 5E8, 36.669E-18

f or F Real Real, fixed-point format 101.04, -3.687

g or G Real Real, exponential, or decimal format, whichever format results in the shortest printed output

9.5001, 6.32E-7, -25.1E6

h or H Integer Hexadecimal format 2e, 252, a38, fff, 3E

o or O Integer Octal format 137, 777

s or S String Constant String format


Simulator Functions

$strobe("Format F (real) gives %F" , rval); $strobe("Format G (real)gives %G" , rval); end

endmodule

When one run format_module, it displays:

Format D gives 89Format E gives 1.254568e+02Format F gives 125.456789Format G gives 125.457

$display

Use the $display task to display information on the screen.

display_task ::= $display [ ( list_of_arguments ) ]


$display and $strobe use the same arguments and are completely interchangeable.

$write

Use the $write task to display information on the screen. This task is identical to the $strobe task, except that $strobe automatically adds a newline character to the end of its output, whereas $write does not.

write_task ::= $write [ ( list_of_arguments ) ]


The arguments one can use in list_of_arguments are the same as those used for $strobe.



9.9: Specifying Power ConsumptionUse the $pwr system task to specify the power consumption of a module. The $pwr task is supported only in analog contexts.

Note: The $pwr task is a nonstandard language extension, implemented for VERLIOG-A vendor compatiability.

pwr_task ::= $pwr( expr )

expr is an expression that specifies the power contribution. If more than one $pwr task is specified in a behavioral description, the result of the $pwr task is the sum of the individual contributions (See section 13.2.3:“The power function: $pwr”).

9.10: Working with FilesVERILOG-A provides several functions for working with files. $fopen prepares a file for writing. $fstrobe and $fdisplay write to a file. $fclose closes an open file.

9.10.1: Opening a FileUse the $fopen function to open a specified file.

fopen_function ::= multi_channel_descriptor = $fopen ( "file_name" ) ;

multi_channel_descriptor is a 32-bit unsigned integer that is uniquely associated with file_name. The $fopen function returns a multi_channel_descriptor value of zero if the file cannot be opened.

One can use a multi_channel_descriptor like a set of 32 flags, where each flag represents a single output channel. The least significant bit always refers to the standard output. The first time it is called, $fopen opens channel 1 and returns a descriptor value of 2 (binary 10). The second time it is called, $fopen opens channel 2 and returns a descriptor value of 4 (binary 100). Subsequent calls cause $fopen to open channels 3, 4, 5, and so on, and to return values of 8, 16, 32, and so on, up to a maximum of 32 open channels.

file_name is a string that can include the special commands described in "Special $fopen Formatting Commands". If file_name contains a path indicating that the file is to be opened in a different directory, the directory must already exist when the $fopen function runs.

The $fopen function reuses channels associated with any files that are closed.

For example, to open a file named my_file, use the code:

integer my_Chan_Descrip;my_Chan_Descrip = $fopen( "my_file" );


Simulator Functions

9.10.2: Special $fopen Formatting CommandsThe following special output formatting commands are available for use with the $fopen function.

The special output formatting commands can be followed by one or more modifiers, which extract information from UNIX filenames. (To avoid opening a file that is already open, the %C command must be followed by a modifier.) The modifiers are:

Any other character after a colon (:) signals the end of modifications. That character is copied with the previous colon.

The modifiers are typically used with the %C command, although they can be used with any of the commands. However, when the output of a formatting command does not contain a / and ".", the modifiers :t and :r return the whole name, and the :e and :h modifiers return ".". As a result, be aware that using modifiers with formatting commands other than %C might not produce the results one expect. For example, using the command:

$fopen("%I:h.freq_dat");

opens a file named ..freq_dat.

Use a concatenated sequence of modifiers. For example, if the design file name is res.ckt, and the statement:

Command Output Example

%C Design filename input.scs

%D Date (yy-mm-dd) 03-02-28

%H Host name my_computer

%S Simulator type smartspice

%P Process ID # 3781

%T Time (24hh:mm:ss) 15:41:25

%I Instance name opamp

%A Analysis name DC, TRAN, AC

Modifier Extracted information

:r Root (base name) of the path for the file

:e Extension of the path for the file

:h Head of the path for any portion of the file before the last /

:t Tail of the path for any portion of the file after the last /

:: The (:) character itself



$fopen("%C:r.freq_dat");

is used, then:

• %C is the design filename (res.ckt).

• :r is the root of the design filename (res).

• .freq_dat is the new filename extension.

As a result, the name of the opened file is res.freq_dat. The following table shows the various filenames generated from a design filename (%C) of /users/maxwell/circuits/opamp.ckt by using different formatting commands and modifiers.

9.10.3: Writing to a FileVERILOG-A provides three input/output functions for writing to a file: $fstrobe, $fdisplay, and $fwrite. The $fstrobe and $fdisplay functions use the same arguments and are completely interchangeable. The $fwrite function is similar, but does not insert automatic carriage returns in the output.

$fstrobe

Use the $fstrobe function to write information to a file.

Command and Modifiers Resulting Opened File

$fopen("%C"); None, because the design file cannot be overwritten.

$fopen("%C:r"); /users/maxwell/circuits/opamp

$fopen("%C:e"); ckt

$fopen("%C:h"); /users/maxwell/circuits

$fopen("%C:t"); opamp.ckt

$fopen("%C::"); /users/maxwell/circuits/opamp.ckt:

$fopen("%C:h:h"); /users/maxwell

$fopen("%C:t:r"); opamp

$fopen("%C:r:t"); opamp

$fopen("/tmp/%C:t:r.raw"); /tmp/opamp.raw

$fopen("%C:e%C:r:t"); ckt.opamp

$fopen("%C:r.%I.dat" ); /users/maxwell/circuits/opamp.opamp3.dat


Simulator Functions

fstrobe_function ::= $fstrobe (multi_channel_descriptor ,list_of_arguments )


The multi_channel_descriptor that is specified must have a value that is associated with one or more currently open files. The arguments that that can be used in list_of_arguments are the same as those used for $strobe. See "$strobe" for guidance.

For example, the following code fragment illustrates how may write simultaneously to two open files.

integer mcd1;integer mcd2;integer mcd;@(initial_step) begin mcd1 = $fopen("file1.dat"); mcd2 = $fopen("file2.dat");end ... mcd = mcd1 | mcd2; // Bitwise OR combines two channels $fstrobe(mcd, "This is written to both files");

$fdisplay

Use the $fdisplay function to write information to a file.

fdisplay_function ::= $fdisplay (multi_channel_descriptor ,list_of_arguments )


The multi_channel_descriptor that is specified must have a value that is associated with a currently open file. The arguments that used in list_of_arguments are the same as those used for $strobe. See "$strobe" for guidance.

$fwrite

Use the $fwrite function to write information to a file.

fwrite_function ::= $fwrite (multi_channel_descriptor ,list_of_arguments )




The multi_channel_descriptor that is specified must have a value that is associated with a currently open file. The arguments that one can use in list_of_arguments are the same as those used for $strobe. See "$strobe" for guidance.

The $fwrite function does not insert automatic carriage returns in the output.

9.10.4: Closing a FileUse the $fclose function to close a specified file.

file_close_function ::= $fclose ( multi_channel_descriptor ) ;

The multi_channel_descriptor that is specified must have a value that is associated with the currently open file that one want to close.

9.11: User-Defined FunctionsVERILOG-A supports user-defined functions. By defining and using your own functions, you can simplify code, and enhance readability and reuse.

9.11.1: Declaring an Analog User-Defined FunctionTo define an analog function, use this syntax:

Syntax

analog_function_declaration ::= analog function [ type ] function_identifier ; function_item_declaration function_item_declaration statement endfunction

type ::= integer | real

function_item_declaration ::= input_declaration | block_item_declaration

block_item_declaration ::= integer_declaration | real_declaration

type is the type of the value returned by the function. The default value is real. statement cannot include analog operators and cannot define module behavior.

Specifically, statement cannot include:

• ddt operator


Simulator Functions

• idt operator

• idtmod operator

• Access functions• Contribution statements• Event control statements• Simulator library functions, except that you can include the functions in the next list.

statement can include references to:

• $vt

• $vt(temp)

• $temperature

• $realtime

• $abstime

• analysis

• $strobe

• $display

• $write

• $fopen

• $fstrobe

• $fdisplay

• $fwrite

• $fclose

• All mathematical functions

All local variables can be declared and used in the function.

Each function that is defined must have at least one declared input. Each function must also assign a value to the implicitly defined internal variable with the same name as the function.

Example

analog function real chopper;input sw, in; // The function has two declared inputs.real sw, in; //The next line assigns a value to the implicit variable, chopper. chopper = ((sw > 0) ? in : -in);endfunction

The chopper function takes two variables, sw and in, and returns a real result. Use the function in any subsequent function definition or in the module definition.

9.11.2: Returning a Value from a User-Defined FunctionThe user-defined function definition implicitly declares a variable, internal to the analog function, with the same name as the analog function. This variable has the same type as the type specified in the analog function declaration. The analog function definition initializes the return value from the analog function by assigning the analog function result to the internal variable with the same name as



the analog function. This variable can be read and assigned within the flow; its last assigned value is passed back on the return call.

Example

The following line illustrates from the previous example, this concept:

chopper = ((sw > 0) ? in: -in);

If the internal variable is not assigned, the function shall return zero (0).

9.11.3: Calling a User-Defined Analog FunctionTo call a user-defined analog function, use the following syntax.

Syntax

analog_function_call ::= function_identifier ( expression , expression )

function_identifier must be the name of a defined function. Each expression is evaluated by the simulator before the function runs. However, do not rely on having expressions evaluated in a certain order because the simulator is allowed to evaluate them in any order.

• shall not call itself directly or indirectly, i.e., recursive functions are not permitted;• shall only be called within an analog block; and• can be called outside of their immediate scope.

The module phase_detector illustrates how the chopper function can be called.

module phase_detector(lo, rf, if0);inout lo, rf, if0;electrical lo, rf, if0;parameter real gain = 1;function real chopper; input sw, in; real sw, in; chopper = ((sw > 0) ? in : -in);endfunctionanalog V(if0) <+ gain * chopper(V(lo),V(rf)); //Call from within the analog block.

endmodule


Chapter 10:Instantiating Modules and Primitives

10.1: Instantiating Verilog-A ModulesUse the following syntax to instantiate modules in other modules.

module_instantiation ::= module_identifier [ parameter_value_assignment ] instance_list

instance_list ::= module_instance , module_instance ;

module_instance ::= name_of_instance ( [ list_of_module_connections ] )

name_of_instance ::= module_instance_identifier

list_of_module_connections ::= ordered_port_connection , ordered_port_connection

ordered_port_connection ::= [ net_expression ]

net_expression ::= net_identifier | net_identifier [ constant_expression ] | net_identifier [ constant_range ]

constant_range ::= constant_expression : constant_expression

The instance_list expression is discussed in the following sections. The parameter_value_assignment expression is discussed in Section 10.3: ‘Overriding Parameter Values in Instances” .

10.1.1: Creating and Naming InstancesThis section illustrates how to instantiate modules. Consider the following module, which describes a gain block that doubles the input voltage.

module vdoubler(in, out);input in;output out;electrical in, out;analog V(out) <+ 2.0 * V(in);

endmodule

Two of these gain blocks are connected, with the output of the first becoming the input of the second.



Figure 10-1: vquad

This higher-level component is described by module vquad, which creates two instances, named blk1and blk2, of module vdoubler. Module vquad also defines external ports corresponding to those shown in the schematic.

module vquad(din, dout);input din;output dout;electrical din, dout;wire blk1_blk2; vdoubler blk1(din, blk1_blk2); //By order vdoubler blk2(blk1_blk2, dout); //By order

endmodule

10.1.2: Mapping Instance Ports to Module PortsWhen instantiating a module, it must be specified how the actual ports listed in the instance correspond to the formal ports listed in the defining module. Module vquad, in the previous example, demonstrates one of the two methods provided in VERILOG-A. Module vquad uses an ordered list, where instance blk1’s first actual port name din maps to vdoubler’s first formal port name in. Instance blk1’s second actual port name blk1_blk2 maps to vdoubler’s second formal port name, and so on.

One can also map actual ports to the formal ports in the defining module explicitly using name pairs. If this approach is chosen, the order of the ports does not matter. Two kinds of mapping within a single instance cannot be mixed.

Mapping Ports with Ordered Lists

To use ordered lists to map actual ports listed in the instance to the formal ports listed in the defining module, ensure that the instance ports are in the same order as the defining module ports. For example, consider the following module child and the module instantiator that instantiates it.

module child(ina, inb, out);input [0:3] ina;input inb;output out;


Instantiating Modules and Primitives

electrical [0:3] ina;electrical inb;electrical out;

endmodule

module instantiator(conin, conout);input [0:6] conin;output conout;electrical [0:6] conin;electrical conout; child child1(conin[1:4], conin[6], conout);

endmodule

One can tell from the order of port names in these modules that port ina[0] in module child maps to port conin[1] in instance child1. Similarly, port inb in child maps to port conin[6] in instance child1. Port out in child maps to port conout in instance child1.

10.2: Connecting the Ports of Module InstancesDeveloping modules that describe components is an important step, and is the overall goal of simulating a system. But an equally important step is combining those components together so that they represent the system as a whole. This section discusses how to connect module instances, how to use their ports, and to describe the structure and behavior of the system being modeled.

Consider again the modules vdoubler and vquad, which describe this example.

Figure 10-2: vquad

module vdoubler(in, out);input in;output out;electrical in, out;analog V(out) <+ 2.0 * V(in);

endmodule



module vquad(din, dout);input din;output dout;electrical din, dout;wire blk1_blk2; vdoubler blk1(din, blk1_blk2); //By order vdoubler blk2(blk1_blk2, dout); //By order

endmodule

This time, note how the module instantiation statements in vquad use port names to establish a connection between output port blk1_blk2 of instance blk1 and input port blk1_blk2 of instance blk2.

One can establish the same connections by using name pairs, as illustrated in the following two instantiation statements:

vdoubler blk1(.out(blk1_blk2), .in(din)); //By namevdoubler blk2(.in(blk1_blk2), .out(dout)); //By name

Module instantiation statements like:

vdoubler blk1(din, dout);vdoubler blk2(din, dout);

establish different connections. These statements describe a system where the gain blocks are connected in parallel, see Figure 10-3.

Figure 10-3: Parallel vdoubler

10.2.1: Port Connection RulesIt is possible to connect the ports described in the vdoubler instances because the ports are defined with compatible disciplines, and are the same size.

• It is necessary to ensure that all ports connected to a net are compatible with each other. Ports of any analog discipline are compatible with a reference node (ground). You can connect the ports described in the vdoubler instances because the ports are defined with compatible disciplines and are the same size.



• It is necesary to ensure that the sizes of connected ports and nets match. In other words, you can connect a scalar port to a scalar net, and a vector port to a vector net or concatenated net expression of the same width.

10.2.2: Multilevel Hierarchal DesignsOne can use VERILOG-A modules inside a multilevel design hierarchy by instantiating Child Verilog.va files inside a Parent Verilog.va module using the following procedure.

inverter.va: (Child Verilog.va)

//inverter

‘include "discipline.h"‘include "constants.h"module inverter(in,out); input in; output out; electrical in,out;

//other parametrs that define the performance of the inverter gate parameter real vout_high = 5, vout_low = 0, vth = 1.4, tdelay = 2p from [0:inf), trise = 1p from [0:inf), tfall = 1p from [0:inf);analog begin if (V(in) > vth) ......end

endmodule

jk_ff.va: (Child Verilog.va)

//Clocked JK FlipFlop

‘include "discipline.h"‘include "constants.h"

module jk_ff(j, k, clk, q, qbar);inout clk, j, k, q, qbar;electrical q, qbar, clk, j, k;

// User defined parametersparameter real tdelay = 1n from [0:inf), ttransit = 1n from [0:inf), vout_high = 5, vout_low = 0 from (-inf:vout_high), vth = 1.4;



integer x; //Local variables

analog begin @(initial_step) x = 0; @(cross(V(clk) - vth, +1)) begin if (V(j) > vth) case (V(k) > vth) 1 : x = !x; 0 : x = 1; endcase ..... end

endmodule

serin_parout.va: (Parent Verilog.va)


‘include "inverter.va" “include definitions of Verilog-A modules inverter‘include "jk_ff.va" and jk_ff”

module serin_parout(d3, d2, d1, d0, din, clk); inout d3, d2, d1, d0, din, clk; electrical d3, d2, d1, d0, din, clk;

//Parametersparameter real trise = 10p from [0:inf);parameter real tfall = 10p from [0:inf);

//Internal electrical nodeselectrical dinbar, q0, qbar0, q1, qbar1, q2, qbar2, q3, qbar3;

//Structural declarationsinverter inverter0(din, dinbar);jk_ff jk_ff0(din, dinbar, clk, q0, qbar0); Instantiation of Verilog-A Child modules within Parent modulejk_ff jk_ff1(q0, qbar0, clk, q1, abar1); jk_ff jk_ff2(q1, qbar1, clk, q2, abar2);jk_ff jk_ff3(q2, qbar2, clk, q3, abar3);

analog begin V(d0) <+ transition(V(q0),trise,tfall); V(d1) <+ transition(V(q1),trise,tfall); V(d2) <+ transition(V(q2),trise,tfall); V(d3) <+ transition(V(q3),trise,tfall);

end

endmodule



10.3: Overriding Parameter Values in InstancesAs noted earlier, the syntax for the module instantiation statement is:

module_identifier [ parameter_value_assignment ] instance_list

The following sections discuss the parameter_value_assignment expression, which is further defined as

parameter_value_assignment ::= | #( named_param_override_list )

named_param_override_list ::= named_param_override , named_param_override

named_param_override ::= . parameter_identifier ( expression )

By default, instances of modules inherit any parameters specified in their defining module. To change any of the default parameter values, do so on the module instantiation statement itself, or from other modules and instances by using the defparam statement. The defparam statement is particularly useful if to change parameters throughout modules from a single location.

10.3.1: Overriding Parameter Values from the Instantiation StatementUsing the module instantiation statement, it is possible to assign values to parameters in two ways. You can assign values in the order the parameters are declared, or by explicitly referring to parameter names. The new values must be constant expressions.

Overriding Parameter Values with Ordered Lists

To override parameters using an ordered list of replacement values you must ensure that the list specifies replacement values in the same order that the parameters are defined in the defining module. It is not required to specify replacement values for every defined parameter, but if any value is omited you must omit every value from then on. In other words, you cannot skip over selected parameters. If a parameter does not need a new value, however, a replacement value equal to the default value can be specified.

Consider the two instances, weakp and plainp, instantiated within module m.

module m;voltage clk;electrical out_a, in_a; mosp #(2e-6, 1e-6) weakp(out_a, in_a, clk); mosp plainp(out_b, in_b, clk);

endmodule

The weakp module instantiation statement overrides the first two parameters given in the defining module, mosp, giving the first parameter the new value 2e-6 and the second parameter the value 1e-6. The plainp module instantiation statement has no parameter override expression, so the parameters assume their default values.



Overriding Parameter Values By Name

You can also override parameter values in an instantiated module by pairing the parameter names to be changed with the values they are to receive. A period and the parameter name come first in each pair, followed by the new value in parentheses. The parameter name must be the name of a parameter in the defining module of the module being instantiated. When parameter values are overridden by name, it is not required to specify values for every parameter.

Consider this modified definition of module vdoubler. This version has three parameters, parm1, parm2, and parm3.

Examples

module vdoubler(in, out);input in;output out;electrical in, out;parameter parm1=0.2, parm2=0.1, parm3=5.0;analog V(out) <+ (parm1+parm2+parm3) * V(in);

endmodule

module vquad(din, dout);input din;output dout; vdoubler #(.parm3(4.0)) blk1(din, blk1_blk2); // By name vdoubler #(.parm1(0.3), .parm2(0.2)) blk2(blk1_blk2, dout); // By name vdoubler #(0.3, 0.2) blk2(blk1_blk2, dout); // By order

endmodule

The module instantiation statement for instance blk1 overrides parameter parm3 by name to specify that the value for parm3 should be changed to 4.0. The other two parameters retain the default values 0.2 and 0.1. The module instantiation statement for blk2 uses an ordered list by name to override the first two parameters, parm1, and parm2. Parameter parm3 retains the default value 5.0.



10.4: Instantiating Analog PrimitivesThese sections describe how to instantiate some spice primitives in VERILOG-A code. For example, the following VERILOG-A module instantiates two VERILOG-A primitives: a resistor and an isource.

module R_C_Filter(in out)electrical in, out;electrical Tmp; analog begin resistor #(.r (100k) R1(in, Tmp); capacitor #(.c (20p)) C1(Tmp, out); end

endmodule

The following table shows the device available with their name, port names and parameter names.

10.4.1: B device

Example

with L and W parameters.

Spice Syntax

B8 net18 net011 net033 Depl_TOM2 L=800e-9 W=20e-6

Verilog-A Syntax

Depl_TOM2 #(.L(800e-9), .W(20e-6)) B8(net18,net011,net033);

Note: the Verilog-A module name for a B device must have a corresponding spice model card.

In the SMARTSPICE netlist, the model card for the previous example could be:

.MODEL Depl_TOM2 NMF ( LEVEL = 5 VERSION = 2 + BETA = 1.814862E-4 VTO = -0.3504765 ALPHA = 2.5848448 + GAMMA = 0.0225387 DELTA = 0 LAMBDA = 0 )

10.4.2: C device

Examplewith default parameter.

Spice Syntaxcf1 f2 0 500p

Verilog-A Syntaxcapacitor #(500p) cf1(f2,gnd);



Examplewith c,w,l,dtemp device parameters

Spice Syntaxc2 out gnd 1u l=10u w=1u dtemp=73

Verilog-A Syntaxcapacitor #(.c(1u), .l(10u), .w(1u), .dtemp(73)) c2(out, gnd);

Examplewith polynomial Capacitance

Spice Syntaxc3 in out POLY 2.0 0.5 0.01

Verilog-A Syntaxcapacitor #(.type("POLY"), [2.0,0.5,0.01]) c3(in, out);

10.4.3: D device

Example

Spice SyntaxD1 n2 n3 DIODE IC=0.3 DTEMP=0.5

Verilog-A Syntax diode #(.ic(0.3), .dtemp(0.5)) d1(n2, n3);

Note: the Verilog-A module name for a D device must have a corresponding spice model card.

10.4.4: E,F,G,H devices

Note: 1: Controlling nodes are specified in the port association list. ( See first example ). 2: Source types are specified by the parameter name type and with a string argument. Several types can be specified in the same statement. Example: ..., .type(“VCR”), .type(“POLY”), ... 3: coefficient vectors specified by position are processed following the source type. ( see next example ).

ExampleVCVC with polynomial source.

Spice Syntax



f12 n4 n7 POLY(2) vcc vee 0 0 0 0 1

Verilog-A Syntaxvcvc #(.type(“POLY(2)”),[0,0,0,0,1]) F12(n4,n7,vcc,vee);

Example

Linear VCVS source.

Spice Syntaxef f1 gnd s1 gnd 1+pp1+pp2-pp3

Verilog-A Syntaxvcvs #(.gain(1+pp1+pp2-pp3)) ef(f1,gnd,s1,gnd);

ExampleDelay Source.

Spice Syntaxedelay out gnd VCVS DELAY in gnd TD=0.01

Verilog-A Syntaxvcvs #(.type("VCVS"),.type("DELAY"),.TD(0.01)) edelay1(out,gnd,in,gnd);

ExampleTransformer source

Spice Syntaxew OUT 0 TRANSFORMER IN 0 10

Verilog-A Syntaxvcvs #(.type("TRANSFORMER"), 10) Ew(out, gnd, in, gnd);

Note: “TRANS” is also accepted.

ExampleDelay source with TD,TC1,TC2,NPDELAY parameters.

Spice SyntaxEtd out 0 DELAY in 0 td=1n tc1=1.1e-10 tc2=1.2e-10 npdelay=25



Verilog-A Syntaxvcvs #(.type("DELAY"),.td(1n),.tc1(1.1e-10), .tc2(1.2e-10), .npdelay(25)) edelay2(out,gnd,in,gnd);

ExampleCCCS source with default parameters.

Spice SyntaxVS1 s1 0 pwl( 0 1 3n 5v 23n 5 26n 1v ) ac 1VDS n1 0 1FF f2 f1 VS1 pp1F11 n3 0 vds 4

Verilog-A Syntaxvsource #(.pwl([0,1,3n,5,23n,5,26n,1]), .ac(1)) vs1(s1,gnd);vsource #(1) vds (n1,gnd);cccs #(.vcontrolname("vs1"), .gain(pp1)) ff(f2,f1);cccs #("vds",4) f11(n3,n0);

Example

CCVS source with and without default parameters.

Spice SyntaxHH h2 h1 HH pp1

Verilog-A Syntaxccvs #(.vcontrolname("hh"), .trres(pp1)) hh(h2,h1); ccvs #("hh), pp1) hh(h2,h1);

ExampleVCCS linear source with default parameter.

Spice SyntaxG1 0 ggout in in_1 10

Verilog-A Syntaxvccs #(10) g1(gnd, ggout, in, in_1);

ExampleVCCS Linear source.

Spice Syntaxgh1 h2 0 h1 0 1



Verilog-A Syntax vccs #(.gm(1)) gh1(h2,gnd,h1,gnd);

ExampleVCCS source with Polynomial coefficents.

Spice SyntaxGp 11 12 POLY(4) 5 0 6 0 7 0 8 0 0 1 1 1 1 0 0 0 0 0 0 -1

Verilog-A Syntaxvccs #(.type(“POLY(4)”),[0,1,1,1,1,0,0,0,0,0,0,-1]) Gp(n11,n12,n5,gnd,n6,gnd,n7,gnd,n8,gnd);

ExampleVCCS source with VCR and NAND parameters.

Spice SyntaxgAND d d1 VCR AND(3) g1 0 g2 0 g3 0+ delta=0.1 scale=2 m=2 tc1=1.1e-10 tc2=1.2e-10+ 0,1G 1,1G 2,1 5,1

Verilog-A Syntaxvccs #(.type("AND(3)"), type(“VCR”),[0,1G,1,1G,2,1,5,1],.m(2),.tc1(1.1e-10), .tc2(1.2e-10)) G1(d, d1, g1, gnd, g2, gnd, g3, gnd);

10.4.5: I, V devices

Examplecurrrent source with default parameter.

Spice SyntaxIee e 0 1m

Verilog-A Syntaxisource #(1m) Iee(e, gnd);

ExamplePWL current source.

Spice Syntaxi1 in1 0 1 pwl(0 0 1n 10 2n 0 4n 10 6n 0 r=2n)



Verilog-A Syntaxisource #(.dc(1), .pwl([0,1,1n,1.4,2n,2,3n,1,4n,4])) vds(in1,gnd);

ExampleSFFM voltage source.

Spice Syntax

v1 out1 0 sffm( 0 1M 20K 5 1K )

Verilog-A Syntaxvsource #(.sffm([0,1M,20K, 5, 1K])) v1(out1,gnd);

Spice SyntaxAM voltage source.

v1 out1 0 am( 10 1 100 1K 1m )

Verilog-A Syntaxvsource #(.am([10, 1, 100, 1k, 1m])) v1(out1,gnd);

Spice Syntax

PWL and AC voltage source.

vin1 in 0 AC 3 0 PWL 0 0 10n 5 25m 5 25.01M 0

Verilog-A Syntax vsource #(.ac(3,0), .pwl(0, 0, 10n, 5, 25m, 5, 25.01M,0 )) vin1(in, gnd);

ExampleVoltage SIN source.

Spice Syntax

vin1 source1 0 SIN(0 sqrt(2)*230 50 0 0 90)

Verilog-A Syntaxvsource #(.sin([0,sqrt(2)*230, 50, 0, 0, 90])) vin1(source1, gnd);

ExamplePWL source with input file.

Spice Syntax



V1 inp 0 0 PWLFILEDESC(2 0 1u 0 3.3 1n 1n) PWLFILE test3.dat

Verilog-A Syntaxvsource #(.dc(0), .pwlfiledesc([2, 0, 1u, 0, 3.3, 1n, 1n]), .pwlfile("test3.dat")) V1(inp, gnd);

Example

PWL source with input file and delay parameter.

Spice Syntax

V1 inp 0 0 PWLFILEDESC(2 0 1u 0 3.3 1n 1n) PWLFILE DigitalEndBy1.pwl TD=3n r=2n

Verilog-A Syntaxvsource #(0,.pwlfiledesc([2, 0, 1u, 0, 3.3, 1n, 1n]), .pwlfile("DigitalEndBy1.pwl"), .td(3n), .r(2n)) vin1(out, gnd);

10.4.6: J device

Spice Syntax:

j1 1 2 3 0 Depl l=0.8e-6 w=20e-6

Verilog-A Syntax Depl #(.l(0.8e-6), .w(20e-6)) j1(n1, n2, n3, gnd);

Note: the Verilog-A module name for a J device must have a corresponding spice model card.

10.4.7: K, L devices

Exampleinductor with polynomial coefficients.

Spice SyntaxL99 in out POLY 4.0 0.35 0.01 R = 10

Verilog-A Syntaxinductor #(.type("POLY"), [4.0,0.35,0.01], .r(10)) L99(in,out);

Exampleinductors and mutual inductors.



Spice SyntaxL_a n_0 p 6.0nL_b p pp 8.0nL_c pp 0 8.0nKK_A_B l_a l_b k=0.7

Verilog-A Syntaxinductor #(.l(6.0n)) L_a(n_0,p);inductor #(8.0n) L_b(p,pp);inductor #(.l(8.0n)) L_c(pp,n0); mutual #(.indnumber(2), .indnamen("l_a"), .indnamen("l_b"), .coefficient(0.7)) KK_A_B();

10.4.8: M device

Spice Syntaxmm 2 1 0 0 modd w=5u l=5u m=10

Verilog-A Syntaxmodd #(.w(5u),.l(5u),.m(10)) mm(n2, n1, gnd, gnd);

10.4.9: O device

Spice SyntaxO1 2 0 3 0 lline1 m=1O2 2 0 3 0 lline2 length=.6095

Verilog-A Syntaxlline1 #(.m(1)) o1(n2,n0,n3,n0);lline2 #(.length(0.6095)) o2(n2,n0,n3,n0);

Note: the Verilog-A module name for a O device must have a corresponding spice model card.

10.4.10: Q device

Spice SyntaxQ1 3 2 6 QNL IC=0.6,5.0 Q2 4 5 6 QNL OFF TEMP=50

Verilog-A Syntaxqnl #(.ic([0.6,5.0])) q1(n3,n2,n6);qnl #(.off(),.temp(50)) q2(n4,n5,n6);



Note: the Verilog-A module name for a Q device must have a corresponding spice model card.

10.4.11: R device

Spice Syntaxr1 in1 in2 50

Verilog-A Syntaxresistor #(.r(50)) r1 (in1,in2);

10.4.12: S device

Spice SyntaxS1 np nn ncp ncn swmod M=2

Verilog-A Syntaxswmod #(.m(2)) S1(n1, n2, n3, n4);

Note: the Verilog-A module name for a S device must have a corresponding spice model card.

10.4.13: T device

Spice SyntaxT1 In1 0 Out1 0 Z0=50 TD=10ns l=0.1

Verilog-A Syntaxtline #(.z0(50),.td(10n),.l(0.1)) T1(In1,gnd,Out1);

Note: the Verilog-A module name for a T device must have a corresponding spice model card.

10.4.14: U device

Spice Syntaxu6 2 0 3 0 lline6 l=0.6095

Verilog-A Syntaxlline6 #(.l(0.6095)) U6(n2,gnd,n3,gnd);



Note: the Verilog-A module name for a U device must have a corresponding spice model card.

10.4.15: W device

Example

Spice SyntaxS_w1 25 23 21 22 24 26 0 FQMODEL=w1 TYPE=Y

Verilog-A Syntax w1 #(.type("Y")) S_w1(n25, n23, n21, n22, n24, n26, gnd);

Note: the Verilog-A module name for a W device must have a corresponding spice model card.

10.4.16: SPICE Model Card PrimitivesThe new two listing show an example of how a model card can be instantiated from VERILOG-A.

Model card definition in the spice netlist file:

.model schot14v8x8 D( is=6.58e-14 n=1.008 nr=1.01+ ISR=1e-12+ ikf=6e-5 m=0.5 vj=0.65+ cjo=30ff xti=3.0 eg=0.82 )

Model card instantiation in the VERILOG-A source file:

module va_schot14v8x8(p, n);inout p,n;electrical p,n; schot14v8x8 diode1(p,n); schot14v8x8 #(.area(10u)) diode2(.a(p),.c(n));

endmodule

10.4.17: SPICE Subcircuit PrimitivesThe new two listing show an example of how a subcircuit can be instantiated from VERILOG-A.

Subcircuit definition in the spice netlist file:

.subckt inv in out l=10u w=10ump out in vdd vdd pmos l=’l’ w=’w’mn out in gnd gnd nmos l=’l’ w=’w’ .ends inv

Subcircuit instantiation in the Verilog-A source file:

module modva_inv(in, out);



inout in;electrical out;parameter real l=8u, w=8u;

// instantiates subcircuit ‘inv’ defined in the previous spice netlist. inv #(l,w) s1(in,out);

endmodule // modva_inv

10.4.18: Instantiating Analog Primitives that Use Array Valued ParametersSome analog primitives take array valued parameters. For example, one might instantiate the svcvsprimitive like this:

module fm_demodulator(vin, vout, vgnd);input vin, vgnd;output vout;electrical vin, vout, vgnd;parameter real gain = 1;

svcvs #(.gain(gain),.poles([-1M, 0, -1M, 0])) af_filter(vout, vgnd, vin, vgnd); //port orderanalog begin ...end

endmodule

This fm_demodulator module sets the array parameter poles to a comma-separated list enclosed by a set of square brackets.

10.4.19: Instantiating Modules that Use Unsupported Parameter TypesSome primitive modules also take parameter types that are not supported directly by the VERILOG-Alanguage. The following cases illustrate how to instantiate such modules. To set a string parameter in a primitive instance, set the parameter to a string constant.

Examples

The next fragment shows how one can set the pwl descriptor file name parameter to a vsource:

vsource #(.type(“pwl”)), .pwlfiledesc(“mydata.dat”) V1(src, gnd);

To set an enumerated parameter in a primitive instance, enclose the enumerated value in quotation marks.

The next fragment sets the parameter type to the value pulse:

vsource #(.type (“pulse”), .val1(5), .period(50u)) Vclk(clk, gnd);


Chapter 11:Grammar Summary

source_text ::=description

description ::=module_declaration | discipline_declaration | nature_declaration

module_declaration ::=module module_identifier [ list_of_ports ] ;[ module_items ]endmodule

list_of_ports ::=( port , port )

port ::=[ port_expression ]| . port_identifier ( [ port_expression ] )

port_expression ::=port_identifier| port_identifier [ constant_expression ]| port_identifier [ msb_constant_expression : lsb_constant_expression ]

module_items ::= module_item | analog_block

module_item ::=module_item_declaration| parameter_override| module_instantiation| analog_block

module_item_declaration ::=parameter_declaration| input_declaration| output_declaration| inout_declaration| integer_declaration| real_declaration| node_declaration| branch_declaration| genvar_declaration| analog_function_declaration

parameter_override ::=defparam list_of_param_assignments ;

nature_declaration ::=nature nature_name[ nature_descriptions ]endnature



nature_name ::=nature_identifier| nature_identifier : parent_identifier

parent_identifier ::=nature_identifier| discipline_identifier.flow| discipline_identifier.potential

nature_descriptions ::=nature_description| nature_description nature_descriptions

nature_description ::=attribute = constant_expression ;

attribute ::=abstol | access | ddt_nature | idt_nature | units | identifier | huge | blowup | maxdelta

discipline_declaration ::=discipline discipline_identifier[ discipline_descriptions ]enddiscipline

discipline_descriptions ::=discipline_description| discipline_description discipline_descriptions

discipline_description ::=nature_binding| attr_description

nature_binding ::=pot_or_flow nature_identifier ;

attr_description ::=pot_or_flow . attribute_identifier = constant_expression ;

pot_or_flow ::=potential | flowparameter_declaration ::=parameter [opt_type] list_of_param_assignments ;

opt_type ::=real | integer

list_of_param_assignments ::=declarator_init| list_of_param_assignments , declarator_init

declarator_init ::=parameter_identifier = constant_expression [ opt_range ]

opt_range ::=


Grammar Summary

from range_specifier| exclude range_specifier| exclude constant_expression

range_specifier ::=start_paren expression1 : expression2 end_parenstart_paren ::=[ | (

end_paren ::=] | )

expression1 ::=constant_expression | -inf

expression2 ::=constant_expression | inf

input_declaration ::=input [range] list_of_port_identifiers ;

output_declaration ::=output [range] list_of_port_identifiers ;

inout_declaration ::=inout [range] list_of_port_identifiers ;

list_of_port_identifiers ::=port_identifier , port_identifier

integer_declaration ::=integer list_of_identifiers ;

real_declaration ::=real list_of_identifiers ;

list_of_identifiers ::=var_name , var_name

var_name ::=variable_identifier| array_identifier range

node_declaration ::=discipline_identifier [range] list_of_nodes ;

list_of_nodes ::=node_identifier| node_identifier , list_of_nodes

branch_declaration ::=branch list_of_branches ;

list_of_branches ::=list_of_parallel_branches



| list_of_parallel_branches , list_of_brancheslist_of_parallel_branches ::=terminals list_of_branch_identifiers

terminals ::=( node_identifier )| ( node_identifier , node_identifier )

list_of_branch_identifiers ::=branch_identifier| branch_identifier , list_of_branch_identifiers

genvar_declaration ::=genvar list_of_genvar_identifiers ;

list_of_genvar_identifiers ::=genvar_identifier , genvar_identifier

analog_function_declaration ::=analog function [type] function_identifier ;function_item_declaration function_item_declaration statementendfunction

type ::=integer| real

function_item_declaration ::=input_declaration| block_item_declaration

block_item_declaration ::=parameter_declaration| integer_declaration| real_declaration

module_instantiation ::=module_identifier [ parameter_value_assignment ] instance_list

instance_list ::=module_instance , module_instance ;

module_instance ::=name_of_instance ( [ list_of_module_connections ] )

name_of_instance ::=module_instance_identifier

list_of_module_connections ::=ordered_port_connection , ordered_port_connection |named_port_connection , named_port_connection

ordered_port_connection ::=[ net_expression ]


Grammar Summary

named_port_connection ::=. port_identifier ( [ net_expression ] )

parameter_value_assignment ::=# ( ordered_param_override_list )| # ( named_param_override_list )

ordered_param_override_list ::=constant_expression , constant_expression

named_param_override_list ::=named_param_override , named_param_override

named_param_override ::=. parameter_identifier ( constant_expression )

net_expression ::=net_identifier| net_identifier [ expression ]| net_identifer [ msb_constant_expression : lsb_constant_expression ]

analog_block ::=analog statement

statement ::=null_statement| block_statement| branch_contribution| procedural_assignment| conditional_statement| loop_statement| case_statement| generate_statement| event_controlled_statement| last_crossing_function| system_task_enable

null_statement ::=;

block_statement ::=begin [ : block_identifier block_item_declaration ] statement end

branch_contribution ::=bvalue <+ expression ;

bvalue ::=access_identifier ( analog_signal_list )

analog_signal_list ::=



branch_identifier| node_or_port_identifier| node_or_port_identifier , node_or_port_identifier

nexpr ::=bvalue| ddt ( bvalue )| idt ( bvalue )| idtmod ( bvalue )

procedural_assignment ::=lexpr = expression ;

lexpr ::=integer_identifier| real_identifier| array_element

array_element ::=integer_identifier [ constant_expression ]| real_identifier [ constant_expression ]

conditional_statement ::=if ( expression ) statement [ else statement ]

case_statement ::=case ( expression )case_item case_itemendcase

case_item ::=expression , expression : statement| default [ : ] statementloop_statement ::=forever statement| repeat ( expression ) statement| while ( expression ) statement| for ( procedural_assignment ; expression ; procedural_assignment )statement

generate_statement ::=statement

start_expr ::=constant_expression

end_expr ::=constant_expression

incr_expr ::=constant_expression

event_controlled_statement ::=@ ( event_expression ) statement


Grammar Summary

event_expression ::=simple_event [ or event_expression ]

simple_event ::=global_event| event_function| identifier

global_event ::=initial_step [ ( analysis_list ) ]| final_step [ ( analysis_list ) ]

analysis_list ::=analysis_name , analysis_name

analysis_name ::=" analysis_identifier "

event_function ::=cross_function| timer_function

cross_function ::=cross ( expression [ , opt_args ] )

opt_args ::=direction [ , time_tol [ , expression_tol ] ]

direction ::=+1| -1

time_tol ::=expression

expression_tol ::=expression

timer_function ::=timer ( start_time [ , period ] )

start_time ::=expression

period ::=expressionlast_crossing_function ::=last_crossing ( expression [ , direction ] )

system_task_enable ::=system_task_name [ ( expression , expression ) ] ;

system_task_name ::= $strobe | $fstrobe | $write | $fwrite | $display |$fdisplay | $monitor | $fmonitor | $fclose | $finish | $stop | $fopen



range ::=[ constant_expression : constant_expression ]

constant_expression ::=constant_primary| string| unary_operator constant_primary| constant_expression binary_operator constant_expression| constant_expression ? constant_expression : constant_expression

constant_primary ::=number| parameter_identifier

expression ::=primary| unary_operator primary| expression binary_operator expression| expression ? expression : expression| function_call| access_function ( arg_list )| built-in_function ( arg_list )| system_function ( arg_list )

function_call ::=function_identifier ( expression , expression )

arg_list ::=expression , expression

access_function ::=bvalue

unary_operator ::=+ | - | ! | ~

binary_operator ::=+ | - | * | / | % | == | != | && | || | < | <= | > | >= | & | | | ^ |^~ | ~^ | >> | <<

primary ::=number | identifier | identifier [ expression ] | nexpr | ( expression )

number ::=decimal_number | real_number

decimal_number ::=[ sign ] unsigned_num

real_number ::=[ sign ] unsigned_num . unsigned_num| [ sign ] unsigned_num [ . unsigned_num ] e [ sign ] unsigned_num | [ sign ]unsigned_num [ . unsigned_num ] E [ sign ] unsigned_num| [ sign ] unsigned_num [ . unsigned_num ] unit_letter


Grammar Summary

sign ::=+ | -

unsigned_num ::=decimal_digit decimal_digit

decimal_digit ::=0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9

unit_letter ::=T | G | M | K | m | u | n | p | f | a

analog_function ::=ddt | idt | idtmod | absdelay | transition | slew | analysis | flicker_noise| noise_table | white_noise |laplace_zp | laplace_zd | laplace_np | laplace_nd |zi_zp | zi_zd | zi_np | zi_nd

built_in_function ::=ln | log | exp | sqrt | min | max | abs | pow | sin | cos | tan | asin |acos | atan | atan2 | sinh | cosh | tanh | asinh | acosh | atanh | hypot |limexp | ceil | floor

system_function ::=$realtime | $abstime | $temperature | $vt | $discontinuity | $bound_step

comment ::=short_comment| long_comment

short_comment ::=// comment_text \n

long_comment ::=/* comment_text */

comment_text ::= Any_ASCII_character

string ::=" Any_ASCII_character_except_newline "

identifier ::=simple_identifier| escaped_identifier

simple_identifier ::=[a-zA-Z]a-zA-Z_$0-9

escaped_identifier ::= Any_ASCII_character_except_white_space white_space

white_space ::=space | tab | newline


Chapter 12:Standard Definitions File

The following files, discipline.h and constants.h define the type of nature and discipline, including mathematical and physical constants. The file discipline.h declares standard natures and disciplines useful for analog systems. One can use these definitions as they are, change them, or override them. For further details of using these files, see Chapter 2: “Makeup of Modules” and Chapter 2: “The SmartSpice Verilog-A Simulation Flow”.

Abstol attribute redefinition

All abstol attributes defined in this file can be overidden by defining a macro with a name composed of the nature name and the string "_ABSTOL". To override an abstol value, the corresponding abstol macro must be redefined before the file discipline.h is included.

Example

In the VERILOG-A source file:

// redefine the abstol attribute for the current nature’define CURRENT_ABSTOL 2.0e-12

// include explicitly the standard file’include "discipline.h"module resistor(n,p);// now every nodes declared from a discipline with the nature Current will have the modified abstol...

12.1: “discipline.h” contentThe content of the file "discipline.h" is the following:

// Verilog-A standard definitions

//

// derived from Verilog-AMS Language Reference Manual version 2.0

//

// Natures and Disciplines

//

/*

* Default absolute tolerances may be overridden by setting the

* appropriate _ABSTOL prior to including this file

*

*/

// Electrical

// Current in amperes

nature Current

units = "A";

access = I;



idt_nature = Charge;

’ifdef CURRENT_ABSTOL

abstol = ’CURRENT_ABSTOL;

’else

abstol = 1.0e-12;

’endif

endnature

// Charge in coulombs

nature Charge

units = "coul";

access = Q;

ddt_nature = Current;

’ifdef CHARGE_ABSTOL

abstol = ’CHARGE_ABSTOL;

’else

abstol = 1e-14;

’endif

endnature

// Potential in volts

nature Voltage

units = "V";

access = V;

idt_nature = Flux;

’ifdef VOLTAGE_ABSTOL

abstol = ’VOLTAGE_ABSTOL;

’else

abstol = 1e-6;

’endif

endnature

// Flux in Webers

nature Flux

units = "Wb";

access = Phi;

ddt_nature = Voltage;

’ifdef FLUX_ABSTOL

abstol = ’FLUX_ABSTOL;

’else

abstol = 1e-9;

’endif

endnature

// Conservative discipline


Standard Definitions File

discipline electrical

potential Voltage;

flow Current;

enddiscipline

// Signal flow disciplines

discipline voltage

potential Voltage;

enddiscipline

discipline current

potential Current;

enddiscipline

// Magnetic

// Magneto_Motive_Force in Ampere-Turns

nature Magneto_Motive_Force

units = "A*turn";

access = MMF;

’ifdef MAGNETO_MOTIVE_FORCE_ABSTOL

abstol = ’MAGNETO_MOTIVE_FORCE_ABSTOL;

’else

abstol = 1e-12;

’endif

endnature


discipline magnetic

potential Magneto_Motive_Force;

flow Flux;

enddiscipline

// Thermal

nature Temperature

units = "C";

access = Temp;

’ifdef TEMPERATURE_ABSTOL

abstol = ’TEMPERATURE_ABSTOL;

’else

abstol = 1e-4;

’endif

endnature

// Power in Watts

nature Power

units = "W";

access = Pwr;



’ifdef POWER_ABSTOL

abstol = ’POWER_ABSTOL;

’else

abstol = 1e-9;

’endif

endnature


discipline thermal

potential Temperature;

flow Power;

enddiscipline

// Kinematic

// Position in meters

nature Position

units = "m";

access = Pos;

ddt_nature = Velocity;

’ifdef POSITION_ABSTOL

abstol = ’POSITION_ABSTOL;

’else

abstol = 1e-6;

’endif

endnature

// Velocity in meters per second

nature Velocity

units = "m/s";

access = Vel;

ddt_nature = Acceleration;

idt_nature = Position;

’ifdef VELOCITY_ABSTOL

abstol = ’VELOCITY_ABSTOL;

’else

abstol = 1e-6;

’endif

endnature

// Acceleration in meters per second squared

nature Acceleration

units = "m/s^2";

access = Acc;

ddt_nature = Impulse;

idt_nature = Velocity;



’ifdef ACCELERATION_ABSTOL

abstol = ’ACCELERATION_ABSTOL;

’else

abstol = 1e-6;

’endif

endnature

// Impulse in meters per second cubed

nature Impulse

units = "m/s^3";

access = Imp;

idt_nature = Acceleration;

’ifdef IMPULSE_ABSTOL

abstol = ’IMPULSE_ABSTOL;

’else

abstol = 1e-6;

’endif

endnature

// Force in newtons

nature Force

units = "n";

access = F;

’ifdef FORCE_ABSTOL

abstol = ’FORCE_ABSTOL;

’else

abstol = 1e-6;

’endif

endnature

// Conservative disciplines

discipline kinematic

potential Position;

flow Force;

enddiscipline

discipline kinematic_v

potential Velocity;

flow Force;

enddiscipline

// Angle in radians

nature Angle

units = "rads";

access = Theta;

ddt_nature = Angular_Velocity;

’ifdef ANGLE_ABSTOL



abstol = ’ANGLE_ABSTOL;

’else

abstol = 1e-6;

endnature

// Angular velocity in radians per second

nature Angular_Velocity

units = "rads/s";

access = Omega;

ddt_nature = Angular_Acceleration;

idt_nature = Angle;

’ifdef ANGULAR_VELOCITY_ABSTOL

abstol = ’ANGULAR_VELOCITY_ABSTOL;

’else

abstol = 1e-6;

endnature

// Angular acceleration in radians per seconds squared

nature Angular_Acceleration

units = "rads/s^2";

access = Alpha;

idt_nature = Angular_Velocity;

’ifdef ANGULAR_ACCELERATION_ABSTOL

abstol = ’ANGULAR_ACCELERATION_ABSTOL;

’else

abstol = 1e-6;

’endif

endnature

// Force in newtons

nature Angular_Force

units = "n/m";

access = Tau;

’ifdef ANGULAR_FORCE_ABSTOL

abstol = ’ANGULAR_FORCE_ABSTOL;

’else

abstol = 1e-6;

’endif

endnature

// Conservative disciplines

discipline rotational

potential Angle;

flow Angular_Force;

enddiscipline

discipline rotational_omega



12.1.1: "Constants.h" fileThe constants.h file defines mathematical and physical constants commonly used in an analog system. The constant.h file needs to be included explicitly with the following line:

‘ include "constants.h"

The content of the file is the following:

potential Angular_Velocity;

flow Angular_Force;

enddiscipline

// Mathematical and physical constants

’ifdef CONSTANTS_H

’else

’define CONSTANTS_H

// M_ is a mathematical constant

’define M_E 2.7182818284590452354

’define M_LOG2E 1.4426950408889634074

’define M_LOG10E 0.43429448100325182765

’define M_LN2 0.69314718055994530942

’define M_LN10 2.30258509299404568402

’define M_PI 3.14159265358979323846

’define M_TWO_PI 6.28318530717958647652

’define M_PI_2 1.57079632679489661923

’define M_PI_4 0.78539816339744830962

’define M_1_PI 0.31830988618379067154

’define M_2_PI 0.63661977236758134308

’define M_2_SQRTPI 1.12837916709551257390

’define M_SQRT2 1.41421356237309504880

’define M_SQRT1_2 0.70710678118654752440

// P_ is a physical constants

// charge of electron in coulombs

’define P_Q 1.6021918e-19

// speed of light in vacuum in meters/sec

’define P_C 2.997924562e8

// Boltzman’s constant in joules/Kelvin

’define P_K 1.3806226e-23

// Plank’s constant in joules*sec

’define P_H 6.6260755e-34

// permittivity of vacuum in farads/meter

’define P_EPS0 8.85418792394420013968e-12

// permeability of vacuum in henrys/meter

’define P_U0 (4.0e-7 * ’M_PI)



// zero celsius in kelvin

’define P_CELSIUS0 273.15

’endif


Chapter 13:The SmartSpice Verilog-A Simulation Flow

The main stages of the Verilog-A interface are described below:

1. A compilation phase: During the sourcing of a SMARTSPICE netlist, VERILOG-A files referred to by the .verilog command cards are compiled by the VERILOG-A SILVACO COMPILER. As a result of the compilation, a C file is produced for each module parsed.

2. A linkage phase: The generated C files are then automatically parsed by the SILVACO C-INTERPRETER, and transformed into an optimized pseudo-code that will be executed during the simulation. If the C files are compiled by a gcc or the native C compiler, a Dynamically Linkable Library (a .so file) is produced. This library is then linked to the SMARTSPICE

executable.3. A simulation phase: Once all VERILOG-A modules have been incorporated, the simulation in

SMARTSPICE is done as usual. The compilation, and the linkage are in fact transparent to the user. Simulating a netlist with VERILOG-A module is still done the same way as with a traditional netlist: first the netlist is sourced, then a simulation is run, and the results output in a text or graphical form.

The simulator flow with example of editing VERILOG file(s) and SMARTSPICE input deck, is shown in Figure 13-1.

Figure 13-1: Simulation Flow



13.1: Choosing the SILVACO C-INTERPRETER or a third-party C compiler• On Windows NT 4.0, Windows 2000 and XP platforms: The SILVACO C-INTERPRETER is automatically

used, and is, for the moment, the only solution available to execute VERILOG-A modules. The user does not need to setup anything.

• On Unix platforms: The GCC compiler is automatically used. The user needs to check that they have access to it. This solution will provide the best results in terms of CPU usage. If the user does not have a GCC, or a third-party C compiler installed on his platform, he can still switch to the SILVACO C-INTERPRETER.

There are 2 ways to specify the usage of the SILVACO C-INTERPRETER:

1. by setting the environment variable SMARTSPICE_VERILOGA_SCI to 1 with the following shell command: setenv SMARTSPICE_VERILOGA_SCI 1.

2. by setting the switch SCI to 1 in the smartspice.init_va config file.

The first way will have a global effect: everytime SMARTSPICE is run, the VERILOG-A INTERFACE will use the SILVACO C-INTERPRETER. In contrast the second implementation of, the switch will have an effect only on the netlists run from the same directory as the config file.

13.2: The SmartSpice Verilog-A interface

13.2.1: New Verilog-A Language Features Supported

Analog primitives

Analog primitives are SPICE devices, model cards or subcircuits that can be instantiated from a VERILOG-A module. These SPICE analog primitives are instantiated in the same way as any other VERILOG-A modules. The syntax of an analog primitive instantiation is the following:

Syntax

primitive_name #( parameter_override_list ) instance_name ( port_association_list );

Example

‘include "discipline.h"

// instantiate SPICE primitives resistor, tline and capacitor.module mva(in1,in2,out);inout in1,in2,out;electrical in1,in2,out;ground grnd; resistor #(.r(50)) r1(in1,in2); tline #(.z0(50), .td(10n), .l(0.1)) t1(in2,grnd,out); resistor #(.r(50)) r1out(out,grnd); capacitor #(.c(1pf)) c1(out,grnd);

endmodule // mva


The SmartSpice Verilog-A Simulation Flow

Example

vsource #(.type("sine"), .ampl(5), .freq(0.995e06)) vin1(out1,gnode);vpwl #(.wave([0, 2, 0.03u, 3])) vin2(out2,gnode);vsource #(.type("pulse"), .val0(5), .val1(-5), .td(10n), .rise(10n), .fall(10n), .width(40n), .period(100n)) vin3(out3,gnode);

13.2.2: Attributes HUGE, BLOWUP, MAXDELTA (Cadence Compatibility)The attributes Huge, Blowup and Maxdelta are now recognized by the simulator (see also Table 4-1). The meaning of theses attributes is the following:

• huge: bounds the change in value between iteration. This helps convergence when signal values are very large. Default: 45.036e06

• blowup: Exit the simulation with an error message when a value exceeds this attribute value.• maxdelta: bounds the change for voltage biases allowed on a Newton-Raphson iteration. Default:

0.0

13.2.3: The power function: $pwr The $pwr system task computes the power consumption of a module.

Note: The $pwr function is a nonstandard function.

Syntax

$pwr( expr )

where expr is an expression that specifies the power contribution.

Example

// Resistor with power contribution ‘include "discipline.h"

module Res(pos, neg);

inout pos, neg; electrical pos, neg; parameter real r=5;

analog begin V(pos,neg) <+ r * I(pos,neg); $pwr(V(pos,neg)*I(pos,neg)); end

endmodule

Access to the power consumption from the netlist is done by using the following syntax:

@YVLGinst_name[_pwr]



Example

YVLGr1 in1 out1 Res r=1e3YVLGr2 out1 0 Res r=1e3

.save @YVLGr1[_pwr] @YVLGr2[_pwr]

Futhermore, like any other devices, the power consumption is displayed for each instance and then added for each model. The following listing is the output after simulating a netlist with the 2 instances YVLGr1 and YVLGr2:

****** model type: VLG

subcktelement yvlgr2 yvlgr1model Res Res

_pwr 1.5625e-03 1.5625e-03

Total VLG:Res power dissipation = 3.1250e-03 Watts

13.2.4: The mathematical functions: hypot(x,y) and atan2(x,y)The function hypot(x,y) is equivalent to Sqrt(x^2 + y^2 ) and atan2(x,y) to the Arc-tangent of x/y.

13.2.5: Analysis ModeIn the current implementation, only DC, AC and transient and noise analysis are supported. Work will be done to support the noise analysis.

13.2.6: Usage of the .PRINT and .PLOT Smartspice commandsIt is possible to refer VERILOG-A objects from the netlist with the .PRINT or the .PLOT command. Objects that are accessible from the netlist are the following:

• sources and probes of all potential or flow quantities.• real variables.

Objects that are not yet accessible are:

• potential or flow quantities not used as a source or a probe.• objects in a module instantiated from another VERILOG-A module.

Example

In the module I_level_shift in the following listing, I(out) and I(in) are the only quantities to be available through the print command. The potential quantities V(out) and V(in) are not accessible.

Verilog-A module:

module I_level_shift(in,out);input in;



output out;electrical in,out;parameter real iout_offset = 0;analogI(out) <+ I(in) + iout_offset; // I(out) and I(in) can be used in the//.PRINT and .PLOT commands// V(out) and V(in) are not accessibleendmodule

13.2.7: Usage of the command .MODIFThe .MODIF command card can be used to refer VERILOG-A parameters. In the following example, the VERILOG-A parameter T is incremented by the value 1 for every new execution.

netlist:

* c sensor.verilog "c_sensor.va"vin 1 0 dc 0.1 PULSE (0 1 10n 10n 10n 20n 100n)YVLGlevelShift 1 2 I_level_shift iout_offser=1r2 2 0 1k.op.dc vin .1 10 1.tran 1n 200n 1n.print @YVLGlevelShift[I(out)].MODIF LOOP=2 YVLGlevelShift(iout_offset)+=1

13.2.8: Usage of the command .STA parameter sweep can be performed on VERILOG-A parameters with the control card .ST. In the following example, a sweep is performed on the parameter ’r’ of the VERILOG-A resistor module.

Example

.verilog "resistor.va"vin 1 0 1YVLGrin 1 2 resistorcin 2 0 1p.TRAN 1n 10n UIC.LET v1=v(1).LET v2=v(2).ST LIST YVLGrin(r) 1k 2k 5k

13.3: The Verilog-A compiler configuration fileA configuration file can be used to customize the execution of the VERILOG-A compiler. The name of the configuration file is smartspice.init_va. It has to be located in the current working directory, and/or the user home directory. Options set in the file located in the current working directory will override the ones set in the file located in the home directory. The commands available in a configuration file are described below.



Examples

set_c_compiler_path /main/frlocal/sparc-solaris2/binadd_include_path ../include/The switches available are described in the next table.Configuration commands for The VerilogA compilerCommand name arguments Descriptionset_switch <switch-name> <value> set a switchadd_include_path <path-name> add an include pathset_c_compiler_path <path-name> set path for the ccompilerSwitches for the VerilogA compilerSwitch Switch Name Values DefaultVerilog Preprocessor Output VPP 0 | 1 0SmartSpice User’s Manual - Volume 2

The switch VPP (Verilog Preprocessor Output Switch) is 1, the result of the preprocessor will be stored in a file with the same name as the input file but with the extension vpp.

The switch GCC (Gnu C Compiler switch) indicates to use gcc instead of the native C compiler. By default, GCC is set to 1.

The switch SCI (SILVACO C-INTERPRETER) indicates to use the SILVACO C-INTERPRETER instead of a C compiler.

Gnu C Compiler GCC 0 | 1 1Silvaco C Interpreter SCI 0 | 1 1 on Windows0 on UnixSwitches for the VerilogA compilerSwitch Switch Name Values Default

13.4: The .verilog cardVERILOG-A source files are compiled with the same command card .verilog. All the VERILOG-A modules instantiated in the SMARTSPICE netlist need to have their corresponding source files compiled with the .verilog card.

The .verilog card takes a single argument, which is the name of the VERILOG-A file. Several .verilog cards can be used in the same netlist. The file name could have a relative or absolute path name. If the filename has a relative path name, the directory of reference is the directory where the SMARTSPICE

netlist file is located.

Examples

.verilog “resitor.va”

.verilog “../capacitor/capacitor.va”

.verilog “/export/home/lionelk/myLib/inductor/inductor.va”

13.5: Module instantiationVERILOG-A modules can be instantiated with a syntax similar to any other device. Also, a model card can be created using an existing module. The syntax for a Verilog-A module instantiation is the following:



YVLG<instance-name> <interface-node> <module-name> (<param-name=paramvalue>)*

The following restrictions apply during a VERILOG-A module instantiation:

• <module-name> must have the same as a VERILOG-A module name or a model defined in a model card.

• <interface-node> is the list of node instantiation. The number of nodes must match the number of nodes declared in the VERILOG-A module. For parsing reason, the number of ports must be fixed at instantiation time. Because of this, it is not possible to assign a value to a parameter that defines the bounds of a vector port. The resizing of the bounds of a vector port must be done in a model card definition.

• <param-name> must be a parameter declared in the VERILOG-A module. If a parameter has no value assigned, the default value specified in the VERILOG-A module will be used.

Example

* instantiation of the module resistor. vss and gnd* are the port names. The parameter resistance is* assigned the value 1k

YVLGr1 vss gnd resistor resistance=1k

13.6: Model Card with Verilog-A moduleAs for other devices, it is possible to create a model card from a VERILOG-A module. The syntax is the following:

.model <model-name> VLG MODULE= <module-name> (<param-name=param-value>)*

Example

* declares a VLG model card m_resistor that uses the Verilog-A module* ’resistor’ and assign.model m_resistor VLG MODULE=resistor thermal_resistance=4 and assign the value 4 to the parameter thermal_resistance

Netlist Example

The following netlist shows an RLC circuit. The VERILOG-A files containing the resistor, inductor and capacitor modules are included with the .verilog card. The modules:

netlist:* RLC circuit using Verilog-A modules.verilog "resistor.va".verilog "inductor.va".verilog "capacitor.va"VIN1 1 0 PWL 0 0 10n 5 25m 5 25.01M 0YVLGr1 1 tmp resistor r=200



YVLGl1 tmp 2 inductor l=125mYVLGc1 2 0 capacitor c=1u.tran.2M 50M.print v(1) v(2).end

The next netlist shows a circuit where the same VERILOG-A module is instantiated several times, but with a different number of ports. A model card is created for each value of the parameter size. Only the relevant parts are shown in the listing.

netlist:.verilog "and.va"YVLGand1 1 2 3 4 and_3YVLGand2 4 5 6 and_2.......model and_3 VLG MODULE = V_and size=3.model and_2 VLG MODULE = V_and size=2

In this netlist, nodes 1, 2, 3 and 4 are assigned to node in[0], in[1], in[2] and in[3] respectively. The following listing shows the code for the Verilog-A module V_and:

module V_and(in,out);parameter real size = 2 from [2:inf);input [0:size-1] in;output out;voltage in,out;......endmodule

The modules resistor, inductor and capacitor are instantiated respectivly with the names YVLGr1, YVLGl1, YVLGc1

13.7: The Smartspice Verilog-A interface

13.7.1: DLL support for Windows platforms with the compiler VC++The DLL ( Dynamic Linkage Library ) mechanism allows SMARTSPICE to run VERILOG-A devices faster than with the SILVACO C-INTERPRETER. DLLs are produced by a C/C++ compiler, and for the moment, only the C/C++ compiler from the Microsoft Visual Studio 6.0 environment ( VC++ ), is supported. If you wish to use another C compiler, please contact SILVACO at [email protected].

The following section describes the necessary steps to check that your system is ready to execute VERILOG-A devices with VC++.

1. First, you will need to check that the following system variables PATH, INCLUDE and LIB are correctly set so VC++ can run correctly. To access system variables, right click the Icon “My Computer”, select “Properties” then check that the system variables described in the following table are correctly set. (For the variable PATH, the value %PATH% refers to the previous value of PATH that have to be kept)



You can also set variables in the AUTOEXEC.BAT files through the following commands:

rem we supposed that Visual Studio has been installed in the directoryrem C:\Program Files\Microsoft\Visual Studio

set MSVC_ROOT = C:\Program Files\Microsoft\Visual Studio

set PATH=%PATH%;%MSVC_ROOT%\Common\Tools;set PATH=%PATH%;%MSVC_ROOT%\Common\MSDEV98\BIN;set PATH=%PATH%;%MSVC_ROOT%\VC98\BIN;

set INCLUDE=%MSVC_ROOT%\VC98\INCLUDEset LIB=%MSVC_ROOT%\VC98\LIB

2. To set the SMARTSPICE VERILOG-A interface to use DLL with VC++ instead of the SILVACO C-INTERPRETER, the user variable SMARTSPICE_VERILOGA_VCC has to be set 1. You can set it through the “Properties” windows or with the following command in the AUTOEXEC.bat:set SMARTSPICE_VERILOGA_VCC=1

3. To double check now that your system is correctly configured, you can execute the following command in a MS-DOS prompt windows: Microsoft(R) Windows NT(TM)(C) Copyright 1985-1996 Microsoft Corp.

C:\>echo %PATH%C:\Program Files\Microsoft Visual Studio\Common\Tools;C:\Program Files\Microsoft Visual Studio\Common\Msdev98\BIN;C:\WINNT\system32;C:\WINNT;c:\Program files\microsoft visual studio\vc98\bin;c\silvaco\bin;

C:\>clMicrosoft (R) 32-bit C/C++ Optimizing Compiler Version 12.00.8168 for 80x86Copyright (C) Microsoft Corp 1984-1998. All rights reserved.

usage: cl [ option... ] filename... [ /link linkoption... ]

C:\>echo %SMARTSPICE_VERILOGA_VCC%1

Variables Suggested Value

PATH %PATH%;C:\Program Files\Microsoft Visual Studio\Com-mon\Tools;C:\Program Files\Microsoft Visual Studio\Com-mon\Msdev98\BIN;

INCLUDE C:\Program Files\Microsoft Visual Studio\VC98\INCLUDE

LIB C:\Program Files\Microsoft Visual Studio\VC98\LIB



13.8: Verilog-A error and warning messagesThe following section is a list of messages displayed when encountering errors. Only a subset of the error and warning messages are listed and explained. Examples are given to clarify the warning or error messages, but are not the only situation for which the message might occur. These messages are listed in alphabetical order.

Two types of error messages might occur:

• Parsing Errors (or warnings): they are syntax or semantic errors related to the VERILOG-Alanguage. They have the following format:<file name> at line <number>: Error:<error message>

Example

"test1.va" at line 16: Error: Unknown system task ’$last_cross’.

Once the error has been fixed, (here in the previous example, ‘$last_cross’ should have been changed to ‘last_crossing’ ), re-source the netlist so SMARTSPICE will re-compile the VERILOG-Asource file.

• Simulation Errors (or warnings): run-time errors found during the SMARTSPICE simulation. Some of these errors are domain or range checks that indicate that some VERILOG-A equations are incomplete for some specific input values. It is the responsability of the user to create a model where all possible input values are processed correctly. These error messages have the following format:Error: (VERILOGA): <error message>

Example

Error: (VERILOGA): Can not access verilog input file : ’test9.va’

13.8.1: Parsing errors• “’analysis’ analog function requires string arguments.”

Example

if ( analysis(AC) ) // ERROR: argument must be “AC”

• “Argument <number> of the concatenation operation has an unmatched type.”

Concatenation element type does not match the other element types.

Example

reg [8*14:1] stringvar;stringvar = "!!!",25; // ERROR: string type expected for argument 2.

• “Assignment statement type mismatch.”

The type of a right hand-side does not match the type of a left hand-side for a variable procedural assignment.



Example

integer val1;val1 = “string val”; // ERROR: integer type expected in the right hand-side.

• “Cannot assign value to genvar <name>.”

genvar variables can only be incremented in for-loops.

• “Can not evaluate size of vector <identifier> for port association.”

Expression of a vector range definition must be a constant expression ( numbers or parameters ).

• “Can not redeclare access attribute in a derived nature.”

Access attributes can only be declared in a base nature.

• “Domain error with constant argument for operator <operator name>.”

Argument is outside the domain of a mathematical operator.

• “Formal parameter <parameter name> not found in module instantiation.”

A parameter does not exist in the instantiated module.

• “Illegal type expression for parameter initialisation.”

Real or integer type are only supported for parameter.

• “Implicit node <node name> cannot be a vector.”

Implicit nodes ( nodes referenced in module instantiation statement that are not declared ) can only be scalar.

• “Invalid access <function name> for branch <branch name>.”

Example

electrical node1;F(node1) <+ R*I(node1); // ERROR: access function F is not valid.

• “No Branch quantity expression found.”

Internal compiler error. See previous VERILOG-A parsing errors. If not, contact [email protected].

• “No Code Generation Method for Expression <expression>.”

Internal compiler error. See previous VERILOG-A parsing errors.If not, contact [email protected].

• “Node <node name> is a vector. Index expression required.”

Access to a vector element requires a bracket operator.



• “Nodes <node name> and <node name> are not compatible.”

Two nodes referenced in a branch do not have the same discipline.

Example

electrical node1;thermal node2;V(n1,n2) <+ cos(ph); // ERROR: n1 and n2 have incompatible disciplines.

• “Ordered parameter assignment in analog primitive instance <instance name> not allowed.”

Example

resistor #(200)r1(in,tmp); // ERROR:parameter assignment must be by name // ex:.p(200)

• “Parameter <name> not found in analog primitive <name> for instance <name>.

Parameter not found in an analog primitive ( spice primitive, spice subcircuit, spice model card ).

Example

$ Smartspice netlist.SUBCKT srlc2 in out w=10uR1 in tmp 200L1 tmp out 125mC1 out 0 1u.ENDS srlc// Verilog-A source filesrlc1 #(.c(1u)) s1(out, grnd);

"wrongSubcircuit.va" at line 12: Error: Parameter ’c’ not found in analog primitive ’srlc1’ for instance ’s1’.

• “Port <port name> can not be declared as ground node.”

• “Preprocessor Error : Arguments mismatched for macro <macro name>

The number of actual arguments does not match the number of arguments specified during a macro function defintion.

Example

‘define MY_MAX(x,y,z) if(x > y) then x + z else y + zval = ‘MY_MAX(val0, val1); //ERROR: 3 arguments expected.

• “Preprocessor Error : Can not redefine <macro name>, already used as directive name.”

The macro name specified in the ‘define directive is already used. Rename macro name.

• “Preprocessor Error : Could not find file <file name>.”

The compiler could not add the file specified in the ‘include directive. Check file name.



• “Preprocessor Error : No arguments found during macro expansion.”

The number of actual arguments does not match the number of arguments specified during a macro function defintion.

Example

‘define MY_MAX(x,y,z) if(x > y) then x + z else y + zval = ‘MY_MAX; //ERROR: 3 arguments expected.

• “Recursivity loop found in instantiation statement for module <module name>.”

A module can not have a statment that instantiates itself.

• “Right operand of bitwise operator <operator name> should be integer.”

• “Seed argument must be an integer variable.”

The seed argument of random number generator functions must be an integer.

• “Syntax error near <character>.”

This means that the compiler is unable to determine the exact cause of the error. To find the problem, look at the referenced line syntax. Look also at the preceding line to see if there is anything wrong with it, such as a missing semicolon. For example, the following module is missing a semicolon in line 9.

Example

‘include "discipline.h"module probe_v2(vout, vin_p, vin_n);input vin_p, vin_n;output vout;electrical vout, vin_p, vin_n;analog begin$strobe("hi") // ERROR! Missing semicolon.$strobe("lo");V(vout) <+ V(vin_p,vin_n);endendmodule

• “<task name> system task requires a string as first argument.”

Wrong type for the first argument of a task.

Example

$strobe(int_val); // ERROR: string argument expected instead of integer

• “<task name> system task requires an integer variable as first argument (channel id).”

Wrong type for the first argument of a task. Example:

$fstrobe("=== first line ==="); // ERROR: missing channel id argument



• “Range error with constant argument for operator <operator name>.

• “Redefinition of nature <nature name>.”

Nature name must be unique.

• “Unexpected character <character>.”

Lexical error. Non-valid character found.

• “Unknown discipline or type ’electrical’. To use ’electrical’ as a discipline, please include the standard file ’discipline.h’.”

The line ‘include "discipline.h" has to be added at the beginning of the file so standard disciplines can be referenced.

• “Wrong keyword in domain specification.”

• “Wrong number of arguments during function call.”

In an user analog function call, the actual arguments number does not match the number of formal arguments.

Example

analog function real chopper; input sw, in;V(if0) <+ gain * chopper(V(rf)); // ERROR: 2 arguments expected.

13.8.2: Parsing warnings• “Contribution statement inside analog event block. Results may be incorrect.”

To avoid convergence problems, contribution statements should to be executed at each iteration of the SMARTSPICE simulation. For this reason, it is preferable to set only variables in event blocks or if-then statements.

Example

if ( V(Control) > 1 ) I(a_T,b_T) <+ V(a_T,b_T)/Ron; // WARNING

• “Internal node <node name> not used. The design might not converged.”

Every internal nodes must be referenced at least once in a contribution statement. This will avoid having a Spice singular matrix. In a hierarchical design, the condition has be true only at one hierarchy level.

• “No instance name in hierarchical name <name>. Ignored.”

No instance name found in defparam statement.



Example

defparam top.p = 2; // WARNING: top is not an instance name.

• “’$fmonitor’ system task has no string as second argument. Ignored. “

• Unknown command line switch type <line> ignored.

Unknown command in the init file smartspice.init_va.

13.8.3: Simulation errors• (VERILOGA): <file name> <line number>: Array index out of bound, index value is <number> for a

range definition [<number>:<number>]

This Run-time check failed because of an out-of-bound access to a vector element. Make sure the array index is within the range definition.

• (VERILOGA): Can not access verilog input file: <file name>

A file specified in a .verilog SMARTSPICE card could not be found.

• (VERILOGA): Compilation of <file name> ... failed

The VERILOG-A compilation of a file failed. Check previous parsing error messages.

• (VERILOGA): error in absdelay for <expression>: delay amount argument has to be a positive number (was <number>)

Delay argument in the absdelay analog function must be a positive number.

• (VERILOGA): <file name>, line <number>: Argument to <function name> function outside domain range (<number>), returning sqrt(0.0)

Run-time domain error, make sure that arguments are within the function’s domain.

• (VERILOGA): <file name>, line <number>: division operand equals zero, returning 1.0

Run-time check for division operand.

• (VERILOGA): Failed finding model <ident name>.

See previous parsing error messages.

• (VERILOGA): in instance <name>, parameter <name> outside its validity range.

Run-time check for the parameter value inside its validity range.

Example

parameter real param1 = 5.0;// ERROR : default value is outside validity range.



parameter real param2 = param1 exclude [-50.0:50);

• (VERILOGA): Model <ident name> from file <file name> already exits as a model card.

Duplicate model name. Look at all VERILOG-A module names declared in the used VERILOG-A files and at all VLG model cards. Supress or rename duplicates.

• (VERILOGA): Model <ident name> initialization FAILED (see previous messages).

See previous parsing error messages.

• (VERILOGA): model <model name> of analog primitive not found.

See previous VERILOG-A parsing error messages. See previous simulation error messages.

• (VERILOGA): Not enough channel files to open file: <file name>. Limit is 31.

Too many opened files.

• (VERILOGA): when setting real parameter id <number> with value <value> for analog primitive <name>: <error message>

• (VERILOGA): While parsing model <model name> declaration: No ’MODULE’ parameter specified.

The keyword MODULE is missing during a VLG model card declaration.

• Error: (VERILOGA): Wrong number of ports in input deck for instance <ident name>. Model <ident name> requires <number> port(s). <number> found(s).

The number of ports in the netlist for a YVLG device does not match the number of ports in the corresponding VERILOG-A module definition.

Example

$ In the smartspice netlistYVLGper 1 2 zero_div $ ERROR: Only 1 port expected.

// In the verilog-A source filemodule zero_div(in);input in;

13.8.4: Simulation Warnings• (VERILOGA): the previous warning(s) on line <number> occured in a derivative expression

automaticaly generated by the compiler. Results might be incorrect.

Since the VERILOG-A SMARTSPICE interface uses the derivative method to fill in the Spice conductance matrix, only mathematical expressions that contain derivate values within the function’s domain should be used. This avoids convergence problems during simulation.



Example

p1B1 = W*cos(a1)*pow((fi_d-fi_sl),2.0)/ (pow(d_dep,2.0)*(tan(a1)+tan(a2)))*miu_sa1_var*eps_ox;

Warning: (VERILOGA): ’B2_pondere_5_temp.2.va’, line 247 : Division operand equals zero, returning 1.0Warning: (VERILOGA): the previous warning(s) on line ’247’ occured in a derivative expression automaticaly generated by the compiler.Results might be incorrect.


Chapter 14:Device Modeling in Verilog-A

14.1: Device Modeling This chapter will explain the development of semiconductor device models within the SMARTSPICE VERILOG-A framework. We will cover the main aspects of semiconductor device modeling, discuss some important modeling terminology, and give some examples for Bipolar and MOS technologies.

What are models?

Models, as implemented in SPICE simulators are a set of implemented model equations, which allow the user to access and define the parameter values externally. The definition of the model equations and the method for extracting the parameters is called modeling.

Many different device models, also termed Compact Models (CMs), have been developed, at universities and through internal company research efforts, over the years for various technologies, some of these models when parameterized match devices produced by manufacturers. It is these models that eventually become “industry standards”.

It is these “industry standard” CMs that get implemented within the SPICE simulation program. Two issues arise from this process. The first is no documented agreements containing the technical specifications or other criteria used such as guidelines, definitions, and application domain. The second issue is that the user must wait for commercial SPICE vendors to implement these compact models within their respective codes.

VERILOG-A compact models open many areas of simulation to SPICE users that were formally closed due to the above process.



14.2: MOSFET Model Tutorial for Verilog-AThis section describes modeling a MOS device, model parameters, and the physical basis for mathematical formulations.

14.2.1: MOSFET Model Parameter DefinitionsThe MOSFET LEVEL 3 parameters are discussed below:

TOX - Oxide Thickness

TOX, one of the most important MOSFET parameters, is used to calculate gate oxide capacitance (COX). The COX parameter may be specified instead of TOX.

RD and RS - Drain and Source Ohmic Resistance

The drain and source ohmic resistances, RD and RS, may be specified for all models. If they are not specified, they are defaulted to zero values for both models.

LD - Lateral Diffusion Coefficient

The lateral diffusion coefficient, LD, may be specified for all MOSFET models. As discussed in the section Metallurgical Junction Depth, LD is used to define the effective channel length. Failure to specify either LD results in the use of the mask-defined channel length throughout the model.

VTO - Zero Bias Threshold Voltage

In addition to determining the boundary between the off region and the linear region of transistor operation, the value of VTO is used to calculate substrate bias effects, weak inversion effects, mobility degradation, and temperature effects.

If a value for VTO is not specified and NSUB is specified, then threshold voltage is calculated from the equation:

where:

vfb = flatband voltage

type =1 for NMOS and -1 for PMOS

PHI (2φf ) is the surface potential

KP - Intrinsic Transconductance

The intrinsic transconductance, KP, may be specified. A specified value overrides any calculation or default value in the model. If KP is not specified, but U0 and TOX (COX) are specified, then:

VTO vfb type2qεsiNSUB PHI⋅

COX----------------------------------------------------- PHI+

+=


Device Modeling in Verilog-A

GAMMA - Bulk Threshold Parameter

GAMMA is the coefficient of the terms which account for substrate bias effects in the equation for drain current. If GAMMA is not specified, it is calculated from NSUB as:

PHI (2φf) - Surface Potential at Strong Inversion

The surface potential at strong inversion, PHI, may be specified. If the value is specified, it is assumed to be equal to twice the Fermi level.

The value of PHI is used in threshold voltage equations.

NSUB - Effective Substrate Doping Concentration

If GAMMA is specified and NSUB is not specified, then NSUB is calculated from GAMMA. If neither parameter is specified, then the defaults are used.

U0, UCRIT, and UEXP - Surface Mobility and Degradation Coefficient

UO is the surface mobility. If both KP and U0 are specified, KP causes U0 to be ignored. If neither KP nor U0 are specified, default values of 600 for NMOS and 250 for PMOS are assumed.

UCRIT and UEXP account for the modeling of mobility degradation due to the vertical electric field:

If values for UCRIT and UEXP are not specified, default values of 1.0E4 V/cm and 0, respectively, are assigned. A zero value for UEXP effectively removes all variable mobility effects from the model.

LAMBDA - Channel Length Modulation Parameter

The channel length modulation parameter, LAMBDA, may be specified.

LAMBDA is used to calculate the effective electrical channel length as the depletion region spreads into the channel. The expression used for the effective electrical channel length is:

where Leff = Lmask - - the effective topological channel length.

KP U0 COX⋅U0 εox⋅TOX

--------------------= =

GAMMA2 q εsi NSUB⋅ ⋅ ⋅

COX-------------------------------------------------=

PHI 2kTq

----------- 1n NSUBni

------------------ ⋅=

US U0UCRIT εsi⋅

COX vgs von–( )⋅-------------------------------------------------

⋅=

Lelectrical Leff 1 LAMBDA vds⋅–( )⋅=

2 LD⋅



XJ - Metallurgical Junction Depth

The metallurgical junction depth, XJ, may be specified. If not specified, a zero value is assigned. The value of XJ can determine the effective channel length. The default value of the lateral diffusion coefficient, LD, is calculated by the formula:

LD is also used to calculate short-channel effects.

IS - Bulk Junction Reverse Saturation Current

The junction reverse saturation current, IS, may be specified in either the analytical or empirical models. The parameter represents the coefficient of the diode equation which simulates the current/voltage characteristics of the drain to substrate and source to substrate diodes. The diode equation for bulk-source diode is given below:

where x = S or D

The substrate to source and substrate to drain diode models contain a resistance in parallel with the current generator described above. This shunt resistance has a default value of 1.0E12 ohms.

NSS - Effective Surface State Density

The effective surface state density, NSS, should be specified only if the empirical model is to be used. No errors result if NSS is specified in the analytical model, but NSS will not be used in any of the calculations, and it could lead to some confusion if it is needlessly specified.

NFS - Effective Fast Surface State Density

The effective fast surface state density, NFS, may be specified for either the analytical or empirical model. If not specified, a zero default value is assigned. The parameter is used in both models for the weak inversion characteristics. If NFS equals zero, the weak inversion effects section of the model is bypassed. A non-zero value of NFS produces some drain current for values of vgs < VTO.

TPG - Type of Polysilicon

The type of polysilicon, TPG, should be specified only if the empirical model is used. Specification of silicon-type parameters in the analytical model will not result in an error, but they will not be used in any calculations. For the analytical model, the value of VTO will not be modified further by the specification of TPG.

PHIMS = TPG · FERMIG - FERMIS

FERMIG = Fermi level of the polysilicon gate

LD 0.75 XJ⋅=

Leff Lmask 2 0.75 XJ⋅ ⋅–=

ibx IS evbxVT

---------1–

⋅=

VT Vthermal( ) KTq

---------=



FERMIS = Fermi level of the substrate

where:

TPG = +1 for gate material opposite doping from NSUB

TPG = -1 for same doping as NSUB

Thus, the two Fermi levels are additive if the gate doping is of opposite polarity to the substrate, and they are subtractive if the gate and substrate are of the same doping polarity.

If VTO is not specified then:

else

where

CGDO and CGSO - Drain and Source Overlap Capacitance

The gate to source and gate to drain capacitances, CGSO and CGDO, may be specified. Failure to specify the parameter results in a zero value. If values are specified, they must be in units of F/m of channel width.

CGBO - Gate Bulk Overlap Capacitance

The gate bulk overlap capacitance, CGBO, may be specified. Failure to specify the parameter results in a zero value. If the value is specified, it must be in units of F/m of channel length. The quantity by the channel length to determine total capacitance.

CBD and CBS - Zero Bias Substrate to Drain and Substrate to Source Junction Capacitance

The zero bias substrate to drain and substrate to source capacitance may be specified or calculated:

where X = S or D.

If CBS or CBD is specified the CJ is overridden. The depletion capacitors are a function of the voltage across the PN junction. The expression of this junction capacitance is divided into two regions:

and to account for the high injection effects.

PB - Bulk Junction Potential

The bulk junction potential, PB, may be specified. If not specified, it assumes the default value of 0.8 volts. The parameter represents the PN junction contact potential for the source to substrate and drain to substrate junctions.

Vbi VFB Flat Band Voltage( ) PHI+=

Vbi VTO GAMMA PHI1 2⁄⋅–=

VFB PHIMS QiCox-----------–

1εox------- ρox x( )x xd

0

tox

∫–=

CBX CJ AX⋅=

VBX X = S or D( ) FC PB⋅≥ VBX FC PB⋅≤



FC - Forward Bias Non-Ideal Junction Capacitance Coefficient

The forward bias non-ideal junction capacitance coefficient, FC, may be specified. Along with PB, it determines the transition between the use of the reverse bias junction capacitance equation and a forward bias diffusion capacitance equation. The appropriate equations were previously defined. If no value is specified, the default value of 0.5 is used. For most cases, the default gives satisfactory performance.



14.3: Temperature CompensationThe following parameters are used for compensation of temperature-dependant parameters.

14.3.1: Temperature Model EquationsThese equations model the temperature dependence of various model parameters.

Energy Gap:

The energy gap width is defined by the expression:

Saturation Current Density

The source/drain diode saturation current IS and densities JS and JSW as:

Define:

Drain and Source Junction Potential

The temperature effects of the contact potentials of source and drain diodes:

Intrinsic Carrier Concentration

EG t( ) 1.16 7.02E 4–t2

t 1108+--------------------⋅–=

f EGvt tnom( )--------------------------

EGvt t( )-------------–=

IS t( ) IS efN----

⋅=

JS t( ) JS efN----

⋅=

JSW t( ) JSW efN----

⋅=

VJ t( ) VJ ttnom--------------- vt t( ) 3 1n t

tnom---------------

EG tnom( )vt tnom( )

-----------------------------EG t( )vt t( )

----------------–+⋅⋅–⋅=

CJ t( ) CJ 1 MJ 4 10e 4 ∆t VJ t( )VJ

---------------– 1+⋅–⋅ ⋅+⋅=

CJSW t( ) CJSW 1 MJSW 4 10e 4 ∆t VJSW t( )VJSW

-------------------------– 1+⋅–⋅ ⋅+⋅=

ni t( ) 1.45E16t

tnom---------------

3 2⁄EG t

tnom--------------- 1–

12 vt t( )⋅--------------------

⋅ ⋅exp⋅ ⋅=



Surface Potential

Threshold Voltage

Figure 14-1: Large Signal Model for the MOS Transistor

The capacitance of Figure 14-1 is separated into three types. The first type includes the capacitors CBD and CBS which are associated with the back biased depletion region between the drain and substrate, and the source and the substrate. The second type includes CGD, CGS and CGB which are all common to the gate and are dependent upon the operating capacitor of the transistor. The third type includes parasitic capacitors which are independent of the operating conditions.

PHI t( ) PHI ttnom---------------

vt t( ) 3t

tnom---------------

lnEG tnom( )vt tnom( )

-----------------------------⋅ EG t( )vt t( )

----------------–⋅⋅–⋅=

VTO t( ) VTO EG tnom( ) EG t( )–2

---------------------------------------------------- type PH t( ) PHI–2

-----------------------------------⋅+ +=



The resistors RD and RS (Figure 14-1) represent the ohmic resistance of the drain and source respectively. These resistors are transformed into conductances by taking their reciprocals:

drain conductance = 1.0/RD

and

source conductance = 1.0/RS

Figure 14-2: Large Signal Charge Storage Capacitors of the MOS Device

Figure 14-2 can also represent diodes, the pn junctions between the source and substrate, and the drain and substrate. For proper transistor operation these diodes are always reversed biased. Their purpose in the dc model is primarily to model leakage currents. These currents are expressed as:

Table 14-1: Constants for Silicon

Constant Symbol Constant Description Value Units

k Boltzmann’s constant 1.381 x 10-23 J/K

ni Intrinsic carrier concentration (27°C) 1.45 x 1010 cm-3

ε0 Permittivity of free space 8.854 x 10-14 F/cm

εsi Permittivity of silicon 11.7 εo F/cm

εox Permittivity of SiO2 3.9 εo F/cm

iBD IS VBDKT

-------------- 1–exp=



and

where IS is the reverse saturation current of a pn junction, K is Boltzmann’s constant and T is temperature in Kelvin units.

The depletion capacitors are a function of the voltage across the pn junction. The expression of this junction - depletion capacitance is divided into two regions in order to account for the high injection effects. The first is given as:

for where:

X = D for CBD and VBD, and S for CBS and VBS

AX = area of source (X = S) or drain (X = D)

CJ = zero bias (VBX = O) junction capacitance per unit area

where:

PB = bulk junction Potential

FC = forward bias non-ideal junction capacitance coefficient

MJ = bulk junction grading coefficient

If then:

To more closely model the depletion capacitance, break it into bottom and side wall components.

For :

and for :

+

iBS IS VBSKT

------------- 1–exp=

CBX CJ AX 1VBXPB

-------------–MJ–

⋅ ⋅=

VBX FC PB⋅≤

CJqεsiNSUB

ZDPB-----------------------------≅

VBX FC PB⋅>

CBX CJ AX⋅1 FC–( )1 MJ+

----------------------------------- 1 1 MJ+( )FC– MJ VBXPB

------------- +=

VBX FC PB⋅≤

CBX CJ AX⋅

1VBXPB

------------- –

MJ----------------------------------------

CJSW PX⋅

1VBXPB

------------- –

MJSW------------------------------------------------+=

VBX FC( ) PB( )≥

CBX CJ AX⋅1 FC–( )1 MJ+

----------------------------------- 1 1 MJ+( )FC– MJ VBXPB

------------- +=

CJSW PX⋅1 FC–( )1 MJSW+

------------------------------------------- 1 1 MJSW+( )FC–VBXPB

------------- MJSW+



where:

AX = area of source (X = S) or drain (X = D)

PX = perimeter of source (X = S) or drain (X = D)

CJSW = zero bias bulk-source/drain sidewall capacitance

MJSW = bulk - source/drain sidewall grading coefficient

MJ = bulk junction grading coefficient

CGXO (X = S or D) is the overlap capacitance in f/m for the gate - source or gate - drain overlap. The difference between the mask W and the actual W is due to the encroachment of the field oxide under the silicon nitride. The expressions for gate - source/drain overlap capacitance are:

where LD is the lateral diffusion component, Weff is the effective channel width, and CGXO (X = S or D) is the overlap capacitance in F/M for the gate - source or gate - drain overlap.

A third overlap capacitance that can be significant is the overlap between the gate and the bulk. This gate - bulk overlap capacitance is a function of the effective length of the channel. The gate - bulk overlap capacitance is expressed by:

The gate - channel capacitance is given as:

The term Leff is the effective channel length resulting from the mask - defined length being reduced by the amount of lateral dopant diffusion. The channel to bulk, C4, capacitance is a depletion capacitance that will vary with voltage as CBS and CBD capacitances.

14.3.2: DC Current Equations LEVEL 3 models drain current for all operating bias regions, and is computed as:

Cutoff Region

ids = 0 for

Turn-on Region

for vgs > vth

where:

vde = min (vds, vdsat)

C1 C2 LD( ) Weff( )Cox CGXO( ) Weff⋅== =

CGB CGBO Leff⋅=

C3 Weff L 2LD–( ) Cox Weff Leff Cox⋅ ⋅=⋅=

vgs vth≤

ids beta vgs vth–1 fb+

2--------------- vde⋅–

vde⋅ ⋅=

beta KPWeff

Leff----------- ueff COX

Weff

Leff-----------⋅ ⋅=⋅=

Leff L 2 LD( )–= Weff W=



and

The narrow width effect is modeled by the parameter fn:

where DELTA is the narrow width threshold adjust factor parameter.

The short channel effects are modeled by:

Threshold Voltage

where vbi = vgb + PHI

or

Saturation Voltage

Saturation voltage is controlled by the parameter VMAX:

where

Effective Surface Mobility

for vgs > vth

fb fn GAMMA fs⋅4 PHI vsb+( )1 2⁄⋅------------------------------------------------+=

fnεsi π DELTA⋅ ⋅2 COX Weff⋅ ⋅

-----------------------------------------=

fs 1XJscaled

Leff---------------------

LDscaled wc+

XJscaled------------------------------------ 1

wpXJscaled wp+------------------------------------

2–

1 2⁄ LDscaled

XJscaled----------------------–

–⋅

⋅–=

wp xd PHI vsb+( )1 2⁄⋅=

xd2 εsi⋅

q NSUB⋅--------------------------

1 2⁄

=

wc XJscaled 0.63135 0.08013929wp

XJscaled---------------------

0.0111077wp

XJscaled---------------------

2⋅–⋅+⋅=

vth vbi 8.14e 22 ETA⋅–

COX L3eff⋅

------------------------------------------- vds GAMMA fs PHI vsb+( )1 2⁄ fn PHI vsb+( )⋅+⋅⋅+⋅–=

vbi VTO GAMMA PHI1 2⁄⋅–=

vsat vgs vth–1 fb+

-------------------------=

vdsat vsat vc vsat2 vc2+( )1 2⁄

–+=

vcVMAX Leff⋅

usurf---------------------------------=

usurf U01 THETA vgs vth–( )⋅+-------------------------------------------------------------------=



If VMAX is specified:

for VMAX > 0

Channel Length Modulation

The channel length reduction, , is computed as:

for VMAX = 0,

for VMAX > 0

where cef is the critical electric field at the pinch-off point. It is computed as:

The drain current ids in saturation region is computed as:

Subthreshold Current

In the subthreshold region of operation, the subthreshold current is dominated by the fast surface state parameter NFS.

Define:

von = vth + fast for NFS > 0

where:

The drain ids current is:

Ids = Ids at Von, Vdmin,

and

= (Vgs - Von)/fast for Vgs < Von

where:

vdmin = min (vds, vdsat)

ueffusurf

1vdevc

----------+--------------------=

∆L

∆L xd KAPPA vds vdsat–( )⋅[ ] 1 2⁄⋅=

∆L cef xd2⋅2

----------------------–cef xd2⋅

2----------------------

2

KAPPA xd2 vds vdsat–( )⋅ ⋅( )⋅1 2⁄

+=

cef vc vc vdsat+( )⋅Leff vdsat⋅

--------------------------------------------=

ids ids

1∆LLeff---------–

-------------------=

fast KTq

--------- 1q NFS⋅

COX---------------------

GAMMA fs PHI vsb+( )1 2⁄ fn PHI vsb+( )⋅+⋅ ⋅2 PHI vsb+( )⋅

-----------------------------------------------------------------------------------------------------------------------------------+ +⋅=

Vsb e⋅



14.3.3: Capacitance Calculations

Figure 14-3: Overlap Capacitances of a MOS Transistor and the imact on L and W

The five capacitance elements associated with the MOSFET model topology are described here. The capacitances CBS and CBD are standard voltage variable junction capacitances. The remaining three elements represent various gate capacitances, and contain both fixed and variable terms. The fixed terms are specified as the parameters CGSO, CGDO, and CGBO in the model variable list. They represent metallization overlap capacitances, as described in Figure 14-3. A variable portion of the gate to channel capacitance is added to each of these fixed values, depending upon the region of transistor operation. In the region below cutoff, the entire gate to channel capacitance is assigned to CGB. As the device operation transitions into the saturated region, up to two-thirds of the channel capacitance is transferred to CGS. The equation governing the transition is:

The transition from saturated into linear operation is governed by:

CGB von vgs–PHI T( )

-------------------------- COX W L CGB0 Leff⋅+⋅ ⋅( )⋅=

CGS vgs von–PHI T( )

-------------------------- COX W L 23--- CGS0 Weff⋅⋅+⋅ ⋅

⋅=

CGS Weff CGS023--- COX W L 1 vgd von––

vgs von vgd von–+–----------------------------------------------------------------

⋅ ⋅ ⋅ ⋅+⋅=

CGD Weff CGD023--- COX W L 1 vgd von––

vgs von vgd von–+–----------------------------------------------------------------

⋅ ⋅ ⋅ ⋅+⋅=



14.4: MOSFET Model LEVEL=3

14.4.1: Model Parameters

Parameter Description Units Default

TOX Oxide thickness m 1.0E-7

NSUB Substrate doping 1/cm3 1E15

GAMMA Bulk threshold parameter V0.5 calculated

PHI Surface potential (2φf) V

VTO Zero-bias threshold voltage V 0

U0 Bulk mobility cm2/ V-s 600

VMAX Maximum drift velocity of carriers m/s 0

THETA Mobility modulation 0

ETA Static feedback 0

KAPPA Saturation field factor 0.2

DELTA Narrow width threshold adjusting factor 0

KP Transconductance parameter A/V2 2.0E-5

RD Drain ohmic resistance Ohm 0

RS Source ohmic resistance Ohm 0

IS Bulk junction saturation current A 1.0E-14

JS Bulk junction saturation current per unit area A/m2 0

JSW Sidewall junction saturation current per periphery length

A/m 0

NSS Surface state density 1/cm2 0

NFS Fast surface state density 1/cm2 0

TPG Type of gate material:+1 opposite to substrate -1 same as substrate0 Al gate

1.0

XJ Metallurgical junction depth m 0

LD (DLAT, LADT)

Lateral diffusion for length m 0

LAMDA Channel length modulation v-1 0

CGDO Gate-drain overlap capacitance F/m 0



14.4.2: MOS_LEVEL 3 Verilog-A ModelOne can download Silvaco’s Verilog-A implementation of this MOS_LEVEL 3 Verilog-A Model at www.silvaco.com.

14.4.3: EKV MOSFET Model - using Silvaco Verilog-A

Figure 14-4: Intrinsic EKV Model Elements

CGSO Gate-source overlap capacitance F/m 0

CGBO Gate-bulk overlap capacitance F/m 0

CJ Zero-bias area capacitance per junction area F/m2 0

VJ Bottom junction built-in potential V 0.75

MJ Bulk junction grading coefficient 0.33

FC Forward-bias depletion junction capacitance coefficient

0.5

CJSW Zero-bias sidewall capacitance per junction perimeter

F/m 0

MJSW Sidewall junction grading coefficient 0.33

CBD Zero-bias B-D junction capacitance F 0

CBS Zero-bias B-S junction capacitance F 0




14.5: EKV MOSFET ModelThe EKV (Enz, Krummenacher, Vittoz) MOSFET model has been developed in EPFL (“Ecole Polytechnique Federale de lausanne” - Switzerland). The model is dedicated to the simulation of low voltage, low current analog and mixed signal circuits using submicron CMOS technologies.

The EKV model equation is based on a single expression, which preserves continuity of first and higher order derivatives.

The Silvaco VERILOG-A implementation is based on Version 2.6, Revision II. For more information, please refer to the EKV Web Page at: http: //legwww.epfl.ch/ekv/.

One can download Silvaco’s Verilog-A implementation of this EKV MOSFET Model at www.silvaco.com.

14.5.1: Geometry Device ParametersThe MOSFET geometry device parameters supported by the EKV model are:

14.5.2: Effective Channel Length and Width CalculationsThe basic equation set in original EPFL implementation is:


Geometry Model Parameters

Name Description Units Default Scaling

L Channel length m - SCALE

W Channel width m - SCALE

M Parallel multiple device factor - 1 -

NS Series multiple device factor - 1 -

AD/AS D/S diffusion junction area m2 0.0 SCALE2

PD/PS D/S diffusion junction perimeter m 0 -

NRD/NRS D/S number of squares - 0 -

GEO D/S geometry selector - 0 -

Leff Lscaled DLscaled+=

Weff Wscaled DWscaled+=



Setup Parameters

Process Related Parameters

Name Description Units Defaults Scaling

DW (DWO) Channel width correction m 0.0 SCALM

DL (DLO) Channel length correction m 0.0 SCALM

XJ Metallurgical junction depth m 0.1E-6 SCALM

LD (DLAT, LATD, LAP)

Lateral diffusion into channel from D/S m 0.75 XJ SCALM

WD (WOT) Lateral diffusion into channel from Bulk m 0.0 SCALM

LDIF Lateral diffusion beyond the gate m 0.0 SCALM

HDIF Heavily doped diffusion length m 0.0 SCALM

XL Masking and etching effects on length m 0.0 SCALM

XW Masking and etching effects on width m 0.0 SCALM

METO Fringing factor m 0.0 SCALM

GEO D/S geometry selector - 0 -

ACM Area Calculation Method selector - 2 -

SCALM Scale factor for model parameters - 1.0 -

Name Description Default

NQS Non-Quasi-Static operation switch 0

SATLIM Ratio defining the saturation limit if/ir exp (4)

SCALM Model parameter scaling factor 1

XQC Charge/Capacitance model selector 1

IIRAT Impact ionization ratio 0

Name Description Units Default

COX Gate oxide capacitance per unit area F/m2 7.0E-4

DW Channel width correction m 0.0

DL Channel length correction m 0.0

XJ Metallurgical junction depth m 0.1E-6



Basic Parameters

Channel Length Modulation and Charge Sharing Parameters

Reverse Short-Channel Effect Parameters

Impact Ionization Related Parameters

Intrinsic Model Temperature Parameters


VTO Long-channel threshold voltage V 0.5

GAMMA Body effect parameter 1.0

PHI Bulk Fermi potential V 0.7

KP Transconductance parameter A/V2 50E-6

UCRIT Longitudinal critical field V/m 2E+6

EO Mobility reduction coefficient V/m 1E+12

THETA Mobility reduction coefficient (former model) 1/V 0.0


LAMBDA Depletion length coefficient (channel length modulation) - 0.5

WETA Narrow-channel effect coefficient - 0.25

LETA Short-channel effect coefficient - 0.1


QO Peak charge density A.s/m2 0.0

LK Characteristic length m 0.29E-6


IBA First impact ionization coefficient 1/m 0.0

IBB Second impact ionization coefficient 1/m 3E8

IBN Saturation voltage factor for impact ionization - 1.0

V



Matching Parameters

Noise Parameters


TNOM (TREF, TEMPM)

Parameter measurement temperature C 0.0

TCV Threshold voltage temperature coefficient V/K 1.0E-3

BEX Mobility temperature exponent - -1.5

UCEX Longitudinal critical field temperature exponent - 0.8

IBBT Temperature coefficient for IBB 1/K 9.0E-4


AVTO Threshold voltage mismatch parameter V.m 0.0

AKP Gain mismatch parameter m 0.0

AGAMMA Body effect mismatch parameter .m 0.0

Name Description Units Defaults

KF Flicker noise coefficient - 0.0

AF Flicker noise exponent - 0.0

V



LEVEL 2/3 Parameters

14.5.4: Handling of LEVEL 2/3 ParametersIf missing, some EKV parameters can be internally estimated from the value of supported LEVEL2/3 parameters using the following rules:

If TOX is given and COX is missing, the oxide capacitance is evaluated using:

If UO is given and KP is missing, the transconductance parameter is evaluated using:

If VMAX and U0 are given and UCRIT is missing, the longitudinal critical field is evaluated using:

If NSUB is given and GAMMA is missing, the body effect parameter is evaluated using:

If NSUB is given and PHI is missing, the bulk Fermi-potential is evaluated using:

If VFB is given and VTO is missing, the long-channel threshold voltage is evaluated using:

14.5.5: Temperature Compensation EquationsDefine T as the device operating temperature


TOX Oxide thickness m

VMAX Maximum drift velocity m/s -

UO Surface mobility cm2/(Vs) -

NSUB Substrate doping cm-3 -

VFB Flat-Band voltage V -

εox COX⁄

COX εox TOX⁄=

KP COX U0⋅=

UCRIT VMAX U0⁄=

GAMMA 2qεoxNSUB COX⁄=

PHI 2 Vt NSUB ni⁄( )ln⋅ ⋅=

VTO VFB PHI GAMMA PHI⋅+ +=

VTO T( ) VTO TCV T TNOM–( )⋅–=

KP T( ) KP TTNOM--------------------

BEX⋅=

UCRIT T( ) UCRIT TTNOM--------------------

UCEX⋅=

PHI T( ) PHI TTNOM--------------------⋅ 3 Vt

TTNOM--------------------

Eg TNOM( ) TTNOM--------------------⋅ Eg T( )+–ln⋅ ⋅–=



where and are the energy gap of silicon evaluated at T and TNOM respectively.

14.5.6: DC Current EquationsAll intrinsic voltages are referred to the substrate and are defined by:

The related transconductances are obtained through derivation of the drain current:

The “standard” transconductances (related to the voltages where the source is taken as reference) are evaluated using the following relationships:

Drain to Source Current

The drain current expression is a single equation, valid in all operating region and given by:

where:

is the thermal voltage at the device operating temperature, n is the slope factor, is the transconduc-tance factor, is the forward normalized current and is the reverse normalized current.

Short Distance Matching

The basic idea is to take into account the influence of geometry on random mismatch between identical transistors close to each other. This effect is described by the following relationships:

IBB T( ) IBB 1 IBBT T TNOM–( )⋅+[ ]⋅=

Eg T( ) Eg TNOM( )

VG VGB VGS VBS–= =

VS VSB VBS–= =

VD VDB VDS VBS–= =

gmg VG∂∂IDS=

gms VS∂∂IDS

–=

gmd VD∂∂IDS=

gm VGS∂∂IDS gmg= =

gmbs VBS∂∂IDS gms gmg gmd––= =

gds VDS∂∂IDS gmd= =

IDS 2 n β Vt2 if i ′ r–( )⋅ ⋅ ⋅ ⋅=

Vtk T⋅

q------------=

βif i ′ r



Effective Gate Voltage including Reverse Short-Channel Effect

where:

Effective Substrate Factor Accounting for Charge-Sharing

where:

and

To prevent the effective substrate factor from becoming negative, the following equation is used:

VTOa VTO AVTONP Weff NS Leff⋅ ⋅ ⋅

---------------------------------------------------------+=

KPa KP 1AKP

NP Weff NS Leff⋅ ⋅ ⋅---------------------------------------------------------+

⋅=

GAMMAa GAMMA AGAMMANP Weff NS Leff⋅ ⋅ ⋅

---------------------------------------------------------+=

VG ′ VG VTOa– ∆VRSCE– PHI GAMMAa PHI⋅+ +=

∆VRSCE2 Q0⋅COX--------------

1

112--- ξ ξ 2 Cε++( )⋅+

2-------------------------------------------------------------⋅=

ξ CA 10Leff

LK---------⋅ 1–

⋅=

Cε 4 22 10 3–×( )2

⋅=

CA 0.028=

γo GAMMAaεsi

COX-------------

LETALeff

----------------- V ′D V ′S+( )⋅ 3 WETA⋅Weff

--------------------------- VP0 PHI+⋅–⋅–=

V ′S D( )12--- VS D( ) PHI VS D( ) PHI+( )2 4 Vt⋅( )2++ +[ ]⋅=

VP0VG ′ PHI– GAMMAa VG ′

GAMMAa

2----------------------------

2

+GAMMAa

2----------------------------–

⋅– VG ′ 0>( )

PHI– VG ′ 0≤( )

=

γ′ 12--- γo γo2 0.1 Vt⋅++( )⋅=



Pinch-Off Voltage including Short- and Narrow-Channel

Slope Factor

Large Signal Interpolation Function

The EKV MOSFET model is based on the normalized transconductance-to-current characteristic that can be expressed by a simple and accurate analytical expression:

Integrating this equation yields the relation:

with

which cannot be inverted analytically. Currently a simplification of this algorithm that avoids Newton-Raphson iterations is used, leading to a continuous expression for the large signal interpolation func-tion F(v).

Forward Normalized Current

Drain-to-Source Saturation Voltage for Reverse Normalized Current

VPVG ′ PHI– γ′ VG ′

γ′2----

2

+γ′2----–

⋅– VG ′ 0>( )

PHI– VG ′ 0≤( )

=

n 1GAMMAa

2 VP PHI 4 Vt⋅+ +⋅---------------------------------------------------------+=

G i( )gms Vt⋅

IDS----------------------

di dv⁄i

----------------1

i 0.25+ 0.5+------------------------------------= = =

v 2 y⋅ y( )ln+= y i 0.25+ 0.5–=

z0

21.3 v v 1.6+( )ln–+-------------------------------------------------- v 0.35–≥( )

1.55 v–( )exp+ 15– v 0.35–<≤( )

=

z1

2 z0+

1 v z0( )ln+ +----------------------------------=

y

1 v z1( )ln+ +

2 z1+---------------------------------- v 15–>( )

12 v–( )exp+------------------------------ v 15–≤( )

=

F v( ) y 1 y+( )⋅=

if FVP VS–

Vt--------------------

=

V ′DSS VC14---

Vt

VC------- if

34--- if( )ln⋅–

⋅+12---–⋅ Vt

VC

2 Vt⋅-------------

ln 0.6–⋅+=



where

Reverse Normalized Current

where:

and:

The variable VDSS used in this formulation corresponds approximately to half the value of the actual saturation voltage. However, the related output variable is estimated with a different expression which gives more realistic values in weak inversion region.

Equivalent Channel Length

where:

and:

Transconductance Factor

where:

VC UCRIT NS Leff⋅ ⋅=

i ′ r FVP Vds VS V ′DSS

2 ∆V2+– Vds V ′DSS–( )2 ∆V2++––

Vt--------------------------------------------------------------------------------------------------------------------------------------------------

=

VdsVD VS–

2---------------------=

∆V 4 Vt1

64------ LAMBDA if

VDSS

Vt-------------–

⋅+⋅ ⋅=

VDSS VC14---

Vt

VC------- if⋅+

12---–⋅=

Leq12--- L ′ L ′2 Lmin

2++( )⋅=

Lmin NS Leff 10⁄⋅=

L ′ NS Leff⋅ ∆LVds Vip+

UCRIT------------------------+–=

Vip VDSS2 ∆V2+ Vds VDSS–( )2 ∆V2+–=

LCεsi

COX------------- XJ⋅=

∆L LAMBDA LC 1Vds Vip–

LC UCRIT⋅---------------------------------+

ln⋅ ⋅=

ββ′0

1COX

E0 εsi⋅------------------ Vt qB η qI⋅+⋅ ⋅+------------------------------------------------------------------------=



The normalized depletion and inversion charges ( and respectively) are defined in the Charge

Equations section above.

For compatibility with EKV model versions prior to v2.6, the former mobility reduction model which uses the parameter THETA is also available as an option. When THETA is given and E0 is not given, the simpler expression is used:

where:

Impact Ionization Current

This effect was not taken into account in versions prior to 2.3. The impact ionization current flows from Drain (or Source is Vds < 0.0) to the Bulk for a N-type MOS transistor and is expressed by:

IIRAT model parameter leads to direct a portion of the substrate current from the drain to the source.

14.5.7: Charge EquationsBoth a charge conservative model and a simpler capacitance model are available. The selected model depends on the value of the parameter XQC. Note that a simplified formulation is used for the reverse normalized current instead of the expression given in the DC Current Equations section.

Define:

β′0 β0 1COX

E0 εsi⋅------------------ qB0⋅+ ⋅=

β0 KPaNP Weff⋅

Leq-------------------------⋅=

qB0 GAMMAa PHI⋅=

η1 2⁄ NMOS( )1 3⁄ PMOS( )

=

qB qI

ββ0

1 THETA V ′P⋅+----------------------------------------------=

V ′P12--- VP VP

2 2 Vt2⋅++( )⋅=

Vib VD VS– IBN 2 VDSS⋅ ⋅–=

IDB

IDSIBAIBB----------- Vib

IBB– LC⋅Vib

-------------------------- exp⋅ ⋅ ⋅ Vib 0>( )

0 Vib 0≤( )

=

ir FVP VD–

Vt---------------------

=

xf14--- if+=

xr14--- ir+=



and:

Intrinsic Node Charges (XQC=0)

The expression for the total charge of the Drain, Source, Gate, and Bulk nodes can be expressed by:

where:

and are the normalized intrinsic node charges defined as follows.

The normalized inversion charge is given by the equation:

Intrinsic Capacitances (XQC=1)

A simplified capacitance model is obtained by neglecting the slight bias dependence of the slope factor n, resulting in the following expressions for the 5 total intrinsic capacitances:

where

nq 1GAMMAa

2 VP PHI 10 6–+ +⋅------------------------------------------------------+=

Q D S G B, , ,( ) Cox Vt q D S G B, , ,( )⋅ ⋅=

Cox COX NP Weff NS Leff⋅ ⋅ ⋅ ⋅=

q D S G B, , ,( )

qD nq–415------

3 xr3⋅ 6 xr

2 xf⋅ ⋅ 4 xr xf2⋅ ⋅ 2 xf

3⋅+ + +

xf xr+( )2--------------------------------------------------------------------------------------------------⋅ 1

2---–

⋅=

qS nq–4

15------

3 xf3⋅ 6 xf

2 xr⋅ ⋅ 4 xf xr2⋅ ⋅ 2 xr

3⋅+ + +

xf xr+( )2--------------------------------------------------------------------------------------------------⋅ 1

2---–

⋅=

qB

GAMMAa VP PHI 10 6–+ +⋅Vt

--------------------------------------------------------------------------------

–nq 1–

nq---------------

qI⋅– V ′G 0>( )

V ′GVt

--------- – V ′G 0≤( )

=

qG qI– qB–=

qI qS qD+ nq–43---

xf2 xf xr⋅ xr

2+ +

xf xr+------------------------------------------⋅ 1–

⋅= =

C gs gd gb sb db,, , ,( ) Cox c gs gd gb sb db,, , ,( )⋅=

cgs23--- 1

xr2 xr xf 2⁄+ +

xf xr+( )2-------------------------------------–

⋅=

cgd23--- 1

xf2 xf xr 2⁄+ +

xf xr+( )2-------------------------------------–

⋅=



This model is suitable for High Frequency analysis ( GHz).

14.5.8: Noise Model Equations

Thermal Noise

A new expression has been implemented which is valid in all regions of operation, including for small Vds:

Flicker Noise

The expression is similar to the standard NLEV=2 flicker noise model:

cgbnq 1–

nq--------------- 1 cgs cgd––( )⋅=

csb nq 1–( ) cgs⋅=

cdb nq 1–( ) cgd⋅=

f 109>

Sthermal 4kT β qI⋅ ⋅=

SflickerKF gm

2⋅

NP Weff NS Leff COX fAF⋅ ⋅ ⋅ ⋅ ⋅------------------------------------------------------------------------------------=



14.6: Berkeley BSIM3v3 MOSFET Model

14.6.1: IntroductionBSIM3v3 is the industry-standard, physics-based, deep-submicron MOSFET model for digital and analog circuit designs from the Device Group at the University of California at Berkeley.

14.6.2: Model ParametersThe foundation of the BSIM3 model is a coherent pseudo 2-D approach. Major short-channel effects and high-field effects such as threshold voltage reduction, effects due to non-uniform doping in direc-tions perpendicular or parallel to the surface, mobility reduction due to vertical field, carrier velocity saturation, channel length modulation, drain induced barrier lowering (DIBL), substrate current induced body effects (SCBE), subthreshold conduction, parasitic resistance effects, and LDD effects are included.

Care has been taken to retain the physical functional forms while improving model accuracy and com-putational efficiency. Model equations have been formed to simplify parameter extraction. The param-eter set is small. Every parameter has physical meaning, and the effects of the parameters are predictable. This feature makes it feasible to perform a statistical study of the impact of fabrication processes on device characteristics. Drain current and its first derivative in all operating regions, and the boundaries between regions are continuous, and convergence in circuit simulation is easy to obtain.

Control Parameters

All binnable model parameters are internally calculated using the same expression:

As an example, for the parameter K1: P0=K1, PL=LK1, PW=WK1, Pp=PK1.

If BINUNIT=1, the values of Leff and Weff used in the binning equation above are in microns. Otherwise, they are in meters. For a device with Leff=0.5 and Weff=10 : if BINUNIT=1, the parameter values for VSAT, LVSAT, WVSAT and PVSAT are lE5, lE4, 2E4 and 3E4, respectively. Therefore, the effective value of VSAT for this device is:

Vsat = lE5 + lE4/0.5 + 2E4/10 + 3E4/(0.5 * 10) = 1.28E5

To get the same effective value of VSAT for BINUNIT=0, the values of VSAT, LVSAT, WVSAT and PVSAT would be lE5, lE-2, 2E-2 and 3E-8, respectively. Thus,

Vsat = lE5 + lE-2/0.5E6 + 2E-2/10e-6 + 3E-8/(0.5E-6 * 10E-6) = 1.28E5

The parameters used in dW and dL equations cannot be binned.

If the model parameter BINFLAG is specified with a value greater than 0.9 and LREF, WREF are set to non-zero values, parameter values are then interpolated as:

Parameter Description Default

MOBMOD Mobility model selector 1

CAPMOD Flag for the short channel capacitance model

NQSMOD Flag for NQS model

BINUNIT Bin unit selector 1

P P0

PL

Leff---------

PW

Weff-----------

PP

Leff Weff×---------------------------+ + +=

µm µm



The effective values of LREF and WREF are computed in a manner consistent with the effective channel width and length (XW and XL are replaced by XWREF and XLREF, respectively).

DC Parameters


VTH0 Threshold voltage @Vbs=0 for large L 0.7 (NMOS)-0.7 (PMOS)

VFB Flat-band voltage

DELVTO Zero-bias threshold voltage shift 0.0

K1 First-order body effect coefficient 0.53

K2 Second-order body effect coefficient - -0.0186

K3 Narrow width coefficient - 80.0

K3B Body effect coefficient of K3 0.0

W0 Narrow width parameter 2.5E-6

NLX Lateral non-uniform doping coefficient 1.74E-7

DVT0W First coefficient of narrow width effect on Vth at small L

- 0

DVT1W Second coefficient of narrow width effect on Vth at small L

5.3E6

DVT2W Body-bias coefficient of narrow width effect on Vth at small L

-0.032

DVT0 First coefficient of short-channel effect on Vth - 2.2

DVT1 Second coefficient of short-channel effect on Vth - 0.53

DVT2 Body-bias coefficient of short-channel effect on Vth

-0.032

VBM Maximum applied body bias in Vth calculation

U0 Mobility at nominal temperature 670 (NMOS)250 (PMOS)

UA First-order mobility degradation coefficient 2.25E-9

UB Second-order mobility degradation coefficient 5.87E-19

P P0 PL1

Leff---------

1LREFeff-----------------------–

⋅ PW1

Weff-----------

1WREFeff-------------------------–

⋅ PP1

Leff---------

1LREFeff-----------------------–

1Weff-----------

1WREFeff-------------------------–

⋅ ⋅+ + +=

V

V

V

V1 2⁄

V 1–

m

m

m 1–

V 1–

V 1–

V

cm2 V 1– s 1–⋅ ⋅

m V 1–⋅

m2 V 2–⋅



UC Body-effect of mobility degradation coefficient -4.65E-11MOBMOD=1,2

-0.0465MOBMOD=3

VSAT Saturation velocity at nominal temperature 8.0E4

A0 Bulk charge effect coefficient for channel length - 1.0

AGS Gate bias coefficient of the Abulk 0.0

B0 Bulk charge effect coefficient for channel width 0.0

B1 Bulk charge effect width offset 0.0

KETA Body-bias coefficient of the bulk charge effect -0.047

A1 First non-saturation factor 0.0

A2 Second non-saturation factor - 1.0

RDSW Width coefficient of parasitic resistance 0.0

PRWG Gate bias coefficient of RDSW 0.0

PRWB Body effect coefficient of RDSW 0.0

WR Width offset from Weff for Rds calculation - 1.0

WINT Width offset fitting parameter from I-V without bias

0.0

LINT Length offset fitting parameter from I-V without bias

0.0

DWG Coefficient of Weff’s gate dependence 0.0

DWB Coefficient of Weff’s substrate body bias depen-dence

0.0

VOFF Offset voltage in the subthreshold region at large W and L

-0.08

NFACTOR Subthreshold swing factor - 1.0

ETA0 DIBL coefficient in subthreshold region - 0.08

ETAB Body-bias coefficient for the subthreshold DIBL effect

-0.07

DSUB DIBL coefficient exponent in subthreshold region

- DROUT

CIT Interface trap capacitance 0.0


m V 2–⋅

V 1–

m s 1–⋅

V 1–

m

m

V 1–

V 1–

Ω µmWR⋅

V 1–

V 1– 2⁄

m

m

m V 1–⋅

m V 1 2⁄–⋅

V

V 1–

F m 2–⋅



AC and Capacitance Parameters

The following parameters: CIT, CDSC, CDSCD, CDSCB, PCLM, PDIBLC1, PDIBLC2, PDIBLCB, DROUT, PSCBE1 and PBSCE2 are common to DC and AC equations. They are described in the pre-ceding table.

Only model parameters specific to AC equations are listed below. These model parameters are used in Intrinsic and Extrinsic Capacitance Models.

CDSC Drain/Source to channel coupling capacitance 2.4E-4

CDSCD Drain-bias sensitivity of CDSC 0.0

CDSCB Body-bias sensitivity of CDSC 0.0

PCLM Channel length modulation parameter - 1.3

PDIBLC1 First output resistance DIBL effect correction parameter

- 0.39

PDIBLC2 Second output resistance DIBL effect correction parameter

- 0.0086

PDIBLCB Body effect coefficient of DIBL correction param-eters

0.0

DROUT L dependence coefficient of the DIBL correction parameter in ROUT

- 0.56

PSCBE1 First substrate current body-effect parameter 4.24E8

PSCBE2 Second substrate current body-effect parameter 1.0E-5

PVAG Gate dependence of Early voltage - 0.0

DELTA Effective Vds parameter 0.01

ALPHA0 First impact ionization current parameter 0.0

ALPHA1 Impact ionization current parameter for length scaling (introduced in version 3.2 but supported in all versions in SmartSpice)

0.0

BETA0 Second impact ionization current parameter 30

NGATE Poly gate doping concentration (a zero value means infinity) (Note 5)

0.0


F m 2–⋅

F V 1– m⋅2–

⋅

F V 1– m⋅2–

⋅

V 1–

V m 1–⋅

m V 1–⋅

V

m V 1–⋅

V 1–

V

cm 3–




XPART Charge partitioning rate flag - 0

CGSO Non-LDD region source-gate overlap capacitance per unit channel length

CGD0 Non-LDD region drain-gate overlap capacitance per unit channel length

CGB0 Gate bulk overlap capacitance per unit channel length

CGSL Light doped source-gate region overlap capaci-tance

0.0

CGDL Light doped drain-gate region overlap capacitance 0.0

CKAPPA Coefficient for lightly doped region overlap capaci-tance

0.6

CF Fringing field capacitance

CLC Constant term for the short channel model 0.1E-6

CLE Exponential term for the short channel model - 0.6

DLC Length offset fitting parameter from C-V LINT

DWC Width offset fitting parameter from C-V WINT

VFBCV Flat-band voltage parameter -1

NOFF CV parameter in Vgsteff, CV for weak to strong inversion

- 1.0

VOFFCV CV parameter in Vgsteff, CV for week to strong inversion

0.0

ACDE Exponential coefficient for charge thickness in CAPMOD=3 for accumulation and depletion regions

1.0

MOIN Coefficient for the gate-bias dependent surface potential

15.0

F m 1–⋅

F m 1–⋅

F m 1–⋅

F m 1–⋅

F m 1–⋅

F m 1–⋅

F m 1–⋅

m

m

m

V

V

m V 1–⋅

V



MOS Diode and Access Resistance Model Parameters


RSH Source/Drain sheet resistance in ohms per square 0.0

JS Bottom junction saturation current per unit area 1.E-4

JSW Side wall junction saturation current density per unit length

0.0

IJTH Diode limiting current 0.1

NJ Emission coefficient of junction - 1.0

CJ Bottom junction capacitance per unit area at zero-bias 5.0E-4

MJ Bottom junction capacitance grading coefficient - 0.5

PB Bottom junction built-in potential 1.0

CJSW Sidewall junction capacitance per unit length at zero-bias

5.0E-10

MJSW Sidewall junction capacitance grading coefficient - 0.33

PBSW Sidewall junction built-in potential 1.0

CJSWG Gate sidewall junction capacitance per unit length at zero-bias

CJSW

MJSWG Gate sidewall junction capacitance grading coefficient - MJSW

PBSWG Gate sidewall junction built-in potential PBSW

METO Fringing factor 0

RD Drain ohmic resistance 0

RS Source ohmic resistance 0

RDC Drain contact resistance 0

RSC Source contact resistance 0

IS Bulk junction saturation current 1e-14

N Bulk diode emission coefficient - 1

NDS Reverse bias slope factor‘- 1 1.0

VNDS Reverse slope transition voltage -1.0

LD Lateral diffusion for length

WD Lateral diffusion for width 0

Ω sq 1–⋅

A m 2–⋅

A m 1–⋅

A

F m 2–⋅

V

F m 1–⋅

V

F m 1–⋅

V

m

Ω

Ω

Ω

Ω

A

V

m

m



NQS Model Parameters

Temperature Effect Parameters

LDIF Lateral diffusion beyond the gate 0

HDIF Heavily doped diffusion length 0

X Masking and etching effects on L 0

XW Masking and etching effects on W 0

LMLT Length multiplier - 1.0

WMLT Width multiplier - 1.0

SCALM Model parameter scaling factor - 1.0

FC Coefficient for the forward-bias depletion junction capac-itance formula

- 0.5

CJGATE Gate edge capacitance CJSW

CBD Total zero bias B-D junction capacitance 0

CBS Total zero bias B-S junction capacitance 0

BULK Substrate node name String “0”


ELM Elmore constant of the channel - 5


TNOM Temperature at which parameters are extracted oC 27

PRT Temperature coefficient for RDSW 0

UTE Mobility temperature exponent - -1.5

KT1 Temperature coefficient for threshold voltage -0.11

KT1L Channel length sensitivity of temperature coeffi-cient for threshold voltage

0.0

KT2 Body-bias coefficient of the Vth temperature effect - 0.022

UA1 Temperature coefficient for UA 4.31E-9

UB1 Temperature coefficient for UB -7.61E-18


m

m

m

m

F m 1–⋅

F

F

Ω µm⋅

V

V m⋅

m V 1–⋅

m2 V 2–⋅



UC1 Temperature coefficient for UC Mobmod=1,2:-5.6E-11Mobmod=3:-0.056

AT Temperature coefficient for saturation velocity 3.3E4

XTI Junction current temperature exponent coefficient - 3.0

TPB Temperature coefficient of PB 0.0

TPBSW Temperature coefficient of PBSW 0.0

TPBSWG Temperature coefficient of PBSWG 0.0

TCJSW Temperature coefficient of CJSW 0.0

TCJSWG Temperature coefficient of CJSWG 0.0

TCJ Bottom junction capacitance temperature coeffi-cient

0.0

TVJ Bottom junction potential temperature coefficient 0.0

TMJ1 Linear MJ temperature coefficient 0.0

TMJ2 Parabolic MJ temperature coefficient 0.0

TCJSW Sidewall junction capacitance temperature coeffi-cient

0.0

TVJSW Sidewall junction potential temperature coefficient 0.0

TMJSW1 Linear MJSW temperature coefficient 0.0

TMJSW2 Parabolic MJSW temperature coefficient 0.0

TTT1 Linear TT temperature coefficient 0.0

TTT2 Parabolic TT temperature coefficient 0.0

TRD1 Linear temperature coefficient for drain resistance 0.0

TRD2 Parabolic temperature coefficient for drain resis-tance

0.0

TRS1 Linear temperature coefficient for source resistance 0.0

TRS2 Parabolic temperature coefficient for source resis-tance

0.0


m V 2–⋅

V 1–

m s 1–⋅

V K 1–⋅

V K 1–⋅

K 1–

K 1–

K 1–

K 1–

V K 1–⋅

K 1–

K 2–

K 1–

V K 1–⋅

K 1–

K 2–

K 1–

K 2–

K 1–

K 2–

K 1–

K 2–



W and L Parameters

EG Energy gap at 300 K 1.16

GAP1 First bandgap correction factor 7.02e-4

GAP2 Second bandgap correction factor 1108


WL Coefficient of length dependence for width offset 0.0

WLN Power of length dependence of width offset - 1.0

WW Coefficient of width dependence for width offset 0.0

WWN Power of width dependence of width offset - 1.0

WWL Coefficient of length and width cross term for width offset

0.0

LL Coefficient of length dependence for length offset 0.0

LLN Power of length dependence for length offset - 1.0

LW Coefficient of width dependence for length offset 0.0

LWN Power of width dependence for length offset - 1.0

LWL Coefficient of length and width cross term for length offset

0.0

LLC Coefficient of length dependence for CV channel length offset (version 3.2)

LL

LWC Coefficient of width dependence for CV channel length offset (version 3.2)

LW

LWLC Coefficient of length and width dependence for CV channel length offset (version 3.2)

LWL

WLC Coefficient of length dependence for CV channel width offset (version 3.2)

WL

WWC Coefficient of width dependence for CV channel width offset (version 3.2)

WW

WWLC Coefficient of length and width dependence for CV channel width offset (version 3.2)

WWL

WREF Reference channel width 0.0


eV

eV K⋅ 1–

K

mWLN

mWWN

mWWN WLN+

mLLN

mLWN

mLWN LLN+

mLLN

mLWN

mLWN LLN+

mWLN

mWWN

mWWN WLN+

m



Bound Parameters

Process Parameters

LREF Reference channel length 0.0

XWREF Difference between physical and drawn reference width

0.0

XLREF Difference between physical and drawn reference length

0.0


LMIN Minimum channel length 0.0

LMAX Maximum channel length 1.0

WMIN Minimum channel width 0.0

WMAX Maximum channel width 1.0

TMIN Minimum temperature °C -273.15

TMAX Maximum temperature °C -273.15


COX Gate oxide capacitance

TOX Gate oxide thickness 1.5E-8

TOXM Gate oxide thickness at which parameters are extracted

TOX

XJ Junction depth 1.5E-7

GAMMA1 Body-effect coefficient near the surface

GAMMA2 Body-effect coefficient in the bulk

NCH Channel doping concentration 1.7E17

NSUB Substrate doping concentration 6.0E16

VBX Vbs at which the depletion width equals XT

XT Doping depth 1.55E-7


m

m

m

m

m

m

m

F m 2–⋅

m

m

m

V1 2⁄

V1 2⁄

cm 3–

cm 3–

V

m



14.6.3: Effective Channel Length and WidthDefine

(for ACM equations)

IV Model

Bias-Independent Quantities:

where

Bias-Dependent Effective Channel Width (for Vdsat, Vasat, Vdseff, and Idso equations):

CV Model

where

14.6.4: Temperature EquationsDefine

where T is the instance temperature and TNOM is a model parameter corresponding to the temperature at which model parameters have been extracted,

and

Lscaled L SCALE XL SCALM⋅+⋅=

Wscaled W SCALE⋅ XW SCALM⋅+=

WeffA W SCALE WMLT⋅ ⋅ XW SCALM⋅+=

Leff L SCALE LMLT⋅ XL SCALM⋅+⋅ 2 dL⋅–=

W ′eff WeffA 2 dW ′⋅–=

dW ′ WINT WL

LscaledWLN

-----------------WW

WscaledWWN

-------------------WWL

LscaledWLN W⋅ scaled

WWN------------------------------------------+ + +=

dL LINT LL

LscaledLLN

-----------------LW

WscaledLWN

-------------------LWL

LscaledLLN Wscaled

LWN⋅------------------------------------------+ + +=

Weff W ′eff 2 DWG Vgsteff⋅ DWB φs Vbseff– φs–(⋅+( ) )⋅–=

Lactive L SCALE LMLT⋅ XL SCALM⋅+⋅ 2 δLeff⋅–=

Wactive WeffA 2 δWeff⋅–=

δWeff DWC WL

LscaledWLN

-----------------WW

WscaledWWN

-------------------WWL


WWN------------------------------------------+ + +=

δLeff DLC LL

LscaledLLN

-----------------LW

WscaledLWN

-------------------LWL

LscaledLLN Wscaled

LWN⋅------------------------------------------+ + +=

TratioT

TNOM--------------------=

VtkB T⋅

q---------------= Vtnom

kB TNOM⋅q

-------------------------------=



as the thermal voltage at device and nominal temperature, respectively.

Model parameter temperature scaling

In order to account for temperature effects, several model parameters are temperature-scaled:

14.6.5: I-V Model Equations

Threshold Voltage

where

VTH0 T( ) VTH0 KT1 KT1L LLeff---------⋅ KT2 Vbseff⋅+ +

Tratio 1–( )⋅⋅=

U0 T( ) U0 Tratio( )UTE⋅=

VSAT T( ) VSAT AT Tratio 1–( )⋅–=

RDSW T( ) RDSW PRT Tratio 1–( )⋅+=

UA T( ) UA UA1 Tratio 1–( )⋅+=

UB T( ) UB UB1 Tratio 1–( )⋅+=

UC T( ) UC UC1 Tratio 1–( )⋅+=

Vth VTH0 K1 Φs⋅– K1ox φs Vbseff–⋅ K2ox Vbseff

K1ox 1NLXLeff

-------------+ 1– φs K3 K3b Vbseff⋅+( ) TOX

W′eff W0+---------------------------- φs

DVT0 D– VT1Leff

2lt---------⋅

exp 2 D– VT1Leff

lt---------⋅

exp⋅+ Vbi φs–( )

DSUB–Leff

2lt0---------⋅

exp 2 DSUB–Leff

lt0---------⋅

exp⋅+ ETA0 ETAB Vbseff⋅+( ) Vds⋅ ⋅–

⋅ ⋅–

DVT0W D– VT1WLeff Weff⋅

2ltw-------------------------⋅

exp 2 D– VT1WLeff Weff⋅

ltw-------------------------⋅

exp⋅+ Vbi φs–( )⋅ ⋅–

⋅ ⋅+⋅ ⋅+

⋅–+=

ltεsi Xdep⋅

COX---------------------- 1 DVT2 Vbseff⋅+( )⋅=

ltwεsi Xdep⋅

COX---------------------- 1 DVT2W Vbseff⋅+( )⋅=

Xdep2 ε⋅ si φs Vbseff–( )⋅

q NCH⋅-------------------------------------------------=

lt0

εsi Xdep0⋅COX

-------------------------=

Xdep0

2 ε⋅ si φs⋅q NCH⋅-----------------------=

Vbseff Vbc 0.5 Vbs Vbc– δ1 Vbs Vbc– δ1–( )2 4 δ1 Vbc⋅ ⋅( )–+–[ ]⋅+=



In version 3.0, is computed as follows:

if K2 > 0, otherwise

In version 3.1 and 3.2, it is computed as follows:

if K2 < 0, otherwise

In version 3.2, the following intermediate variables are computed to account for TOXM:

and

The expressions of and are given in the paragraph related to temperature dependence.

Effective Vgs - Vth

Mobility

MOBMOD = 1

MOBMOD = 2

δ1 0.001=

Vbc

Vbc 0.9 φsK12

4 K22⋅-----------------–

⋅= Vbc 10–=

Vbc 0.9 φsK12

4 K22⋅-----------------–

⋅= Vbc 30–=

K1ox K1TOX

TOXM-------------------⋅= K2ox K2

TOXTOXM-------------------⋅=

Vbi φs

Vgsteff

2 n V⋅ ⋅ t 1Vgs Vth–

2 n V⋅ ⋅ t------------------------

exp+ln⋅

1 2 n COX2 φs⋅

q ε⋅ si NCH⋅---------------------------------

Vgs Vth– 2 VOFF⋅–

2 n V⋅ ⋅ t-------------------------------------------------------–

exp⋅ ⋅ ⋅ ⋅+

----------------------------------------------------------------------------------------------------------------------------------------------------------------=

n 1 NFACTORCd

COX-------------⋅

CDSC CDSCD Vds⋅ CDSCB Vbseff⋅+ +( ) D– VT1Leff

2 l⋅ t-----------⋅

exp 2 DVT1Leff

lt---------⋅–

exp+ ⋅

COX--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

CITCOX-------------

+

+

+

=

Cdεsi

Xdep------------=

µeffU0

1 UA UC Vbseff⋅+( )Vgsteff 2 Vth⋅+

TOX---------------------------------------

⋅ UBVgsteff 2 Vth⋅+

TOX---------------------------------------

2

⋅+ +

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

µeffU0

1 UA UC Vbseff⋅+( )Vgsteff

TOX----------------

⋅ UBVgsteff

TOX----------------

2

⋅+ +

-----------------------------------------------------------------------------------------------------------------------------------=



MOBMOD = 3

Drain Saturation Voltage

For Rds > 0 or

For Rds = 0,

Effective Vds

Drain Current

µeffU0

1 UAVgsteff 2Vth+

TOX-----------------------------------

⋅ UBVgsteff 2Vth+

TOX-----------------------------------

⋅2

1 UC V⋅ bseff+( )⋅+ +

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

λ 1≠

Vdsatb b2 4 a c⋅ ⋅–––

2 a⋅----------------------------------------------=

a Abulk2 W⋅ eff VSAT⋅ C⋅ OX Rds⋅ 1

λ--- 1–

Abulk⋅+=

b Vgsteff 2 V⋅ t+( ) 2λ--- 1–

Abulk E⋅ sat L⋅ eff

3 A⋅ bulk Vgsteff 2 V⋅ t+( ) W⋅ eff VSAT COX R⋅ ds⋅ ⋅ ⋅

+

+

⋅

–=

c Vgsteff 2 V⋅ t+( ) E⋅ sat Leff⋅ 2 Vgsteff 2 V⋅ t+( )2 W⋅ eff VSAT COX Rds⋅ ⋅ ⋅ ⋅+=

λ A1 Vgsteff⋅ A2+=

λ 1=

VdsatEsat Leff Vgsteff 2 V⋅ t+( )⋅ ⋅

Abulk Esat Leff⋅ ⋅ Vgsteff 2 V⋅ t+( )+--------------------------------------------------------------------------------------------=

Abulk 1K1

2 φs Vbseff–⋅--------------------------------------

A0 L⋅ eff

Leff 2 XJ X⋅ dep⋅+----------------------------------------------------

1 AGS V⋅ gsteffLeff

Leff 2 XJ X⋅ dep⋅+----------------------------------------------------

⋅2

–⋅ B0Weff B1+-------------------------

+

⋅+

11 KETA Vbseff⋅+-----------------------------------------------⋅

=

Esat2 VSAT⋅

µeff-------------------------=

Vdseff Vdsat12--- Vdsat Vds– DELTA– Vdsat Vds– DELTA–( )2 4 DELTA Vdsat⋅ ⋅++( )⋅–=

IdsIdso

1Rds I⋅ dso

Vdseff-----------------------+

--------------------------------- 1Vds Vdseff–

VA------------------------------+

1Vds Vdseff–

VASCBE------------------------------+

⋅ ⋅=

Idso

Weff µ⋅ eff COX Vgsteff 1 AbulkVdseff

2 Vgsteff 2 V⋅ t+( )⋅-------------------------------------------------⋅–

Vdseff⋅⋅ ⋅ ⋅

Leff 1 Vdseff Esat L⋅ eff( )⁄+[ ]⋅----------------------------------------------------------------------------------------------------------------------------------------------------------------------------=



Substrate Current

Polysilicon Depletion Effect

Drain/Source Resistance

VA VAsat 1PVAG Vgsteff⋅

Esat L⋅ eff---------------------------------------+

1VACLM------------------

1VADIBLC-----------------------+

⋅1–

+=

VACLMAbulk Esat Leff Vgsteff+⋅ ⋅PCLM Abbulk Esat litl⋅ ⋅ ⋅-------------------------------------------------------------------- Vds Vdseff–( )⋅=

VADIBLCVgsteff 2 V⋅ t+( )

θrout 1 PDIBLCB Vbseff⋅+( )⋅--------------------------------------------------------------------------------- 1

Abulk Vdsat⋅Abulk Vdsat⋅ Vgsteff 2 V⋅ t+ +----------------------------------------------------------------------------–

⋅=

θrout PDIBLC1 DROUTLeff

2 l⋅ t0-------------⋅–

exp 2 DROUTLeff

lt0---------⋅–

exp⋅+⋅ PDIBLC2+=

1VASCBE--------------------

PSCBE2Leff

-------------------------PSCBE1 litl⋅–

Vds Vdseff–----------------------------------------

exp⋅=

VAsat

Esat L⋅ eff Vdsat 2 R⋅ ds+ VSAT C⋅ OX Weff Vgsteff 1Abulk Vdsat⋅

2 Vgsteff 2 V⋅ t+( )⋅-------------------------------------------------–⋅ ⋅ ⋅ ⋅+

2 λ 1 Rds VSAT C⋅ OX Weff Abulk⋅ ⋅ ⋅+–⁄-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

litlεsi TOX XJ⋅ ⋅

εox-------------------------------------=

IsubALPHA0

Leff-------------------------- ALPHA1+

Vds Vdseff–( ) BETA0Vds Vdseff–------------------------------–

expIdso

1Rds I⋅ dso

Vdseff-----------------------+

--------------------------------- 1Vds Vdseff–

VA------------------------------+

⋅ ⋅ ⋅ ⋅=

Vpoly12--- Xpoly E⋅ poly

q N⋅ GATE Xpoly2⋅

2 ε⋅ si-------------------------------------------------=⋅=

εox E⋅ ox εsi E⋅ poly 2 q ε⋅ ⋅ si N⋅ GATE V⋅ poly==

Vgs VFB φs Vpoly Vox+=––

εox2

2 q ε⋅ si N⋅ GATE TOX2⋅ ⋅---------------------------------------------------------------------- Vgs VFB– φs– Vpoly–( )2⋅ Vpoly 0=–

Vgseff VFB φsq ε⋅ si N⋅ GATE TOX2⋅

εox2

-------------------------------------------------------------- 12 ε⋅ ox

2 Vgs VFB– φs–( )⋅q ε⋅ si N⋅ GATE TOX2⋅--------------------------------------------------------------+ 1–

⋅+ +=

RdsRDSW 1 PRWG Vgsteff⋅ PRWB φs Vbseff– φs–( )⋅+ +[ ]⋅

106 W ′⋅ eff( )WR

-----------------------------------------------------------------------------------------------------------------------------------------------------------------=



14.6.6: Capacitance Model Equations

Overlap Capacitances

The following expressions corespond to a NMOS device.

• Source Overlap Charge

CAPMOD=0

CAPMOD=1

if (Vgs < 0)

else

CAPMOD=2

where

• Drain Overlap Charge

The expresssion of can be easily obtained from the preceding equations by replacing Vgs,

CGSO and CGSL, by Vgd, CGDO and CGDL, respectively.

• Gate Overlap Charge

Instrinsic Charges

CAPMOD=0

• Accumulation region (Vgs < VFBCV + Vbs)

• Subthreshold region (Vgs < Vth)

Qoverlap s,

Wactive------------------------- CGSO CF+( ) V⋅ gs=

Qoverlap s,

Wactive------------------------- CGSO CF+( ) V⋅ gs

CKAPPA CGSL⋅2

------------------------------------------------- 14 V⋅ gs

CKAPPA---------------------------– 1–

⋅–=

Qoverlap s,

Wactive------------------------- CGSO CF CKAPPA CGSL⋅+ +( ) V⋅ gs=

Vgs overlap,12--- Vgs δ+( ) Vgs δ+( )2 4 δ⋅+–

⋅= δ 0.02=

Qoverlap s,

Wactive------------------------- CGSO CF+( ) V⋅ gs CGSL Vgs Vgs overlap,

CKAPPA2

--------------------------- 14 V⋅ gs overlap,

CKAPPA-----------------------------------– 1–

⋅––

⋅+=

Qoverlap d,

Wactive-------------------------

Qoverlap g, Qoverlap s, Qoverlap d,+( )–=

Qg Wactive L⋅ active COX⋅ Vgs Vbs VFBCV––( )⋅=

Qsub Qg–=

Qinv 0=



• Strong inversion region (Vgs > Vth)

(i) 50/50 Charge partition

if Vds < Vdsat

Otherwise,

Qb Wactive L⋅ active COX⋅–K12

2---------- 1 1

4 Vgs Vbs– VFBCV–( )⋅

K12-----------------------------------------------------------------++–

⋅ ⋅=

Qg Qb–=

Qinv 0=

Vdsat cv,Vgs Vth–

A ′bulk------------------------=

A ′bulk Abulk0 1CLCLeff

------------- CLE

+ ⋅=

Abulk0 1K1

2 φs Vbseff–⋅--------------------------------------

A0 Leff⋅

Leff 2 XJ X⋅ dep⋅+----------------------------------------------------

B0W′eff B1+---------------------------+

⋅+ 1

1 KETA V⋅ bs+-----------------------------------------⋅=

Vth VFBCV φs K1 φs Vbseff–⋅+ +=

Qg Wactive L⋅ active C⋅ OX Vgs VFBCV– φs–Vds

2---------

A ′bulk V⋅ ds2

12 Vgs Vth–A ′bulk V⋅ ds

2-----------------------------–

⋅----------------------------------------------------------------------------+–⋅=

Qinv Wactive L⋅ active C⋅ OX– Vgs Vth–A ′bulk V⋅ ds

2-----------------------------

A ′bulk2 V⋅ ds

2

12 Vgs Vth–A ′bulk

2---------------- V⋅

ds–

⋅----------------------------------------------------------------------------+–⋅=

Qb Wactive L⋅ active C⋅ OX VFBCV Vth– φs

1 A ′bulk–( ) V⋅ ds

2-------------------------------------------

1 A ′bulk–( ) A ′⋅ bulk V⋅ ds2


2---------------- Vds⋅–

⋅----------------------------------------------------------------------------+ + +⋅=

Qs Qd 0.5 Q⋅ inv

W–= active L⋅ active C⋅ OX Vgs Vth–A ′bulk V⋅ ds

2-----------------------------

A ′bulk2 V⋅ ds

2


2---------------- Vds⋅–

⋅----------------------------------------------------------------------------+–⋅

= =

Qg Wactive L⋅ active C⋅ OX Vgs VFBCV– φs–Vdsat

3-------------–

⋅=



(ii) 40/60 channel-charge Partition

if (Vds < Vdsat)

otherwise,

(iii) 0/100 Channel-charge Partition

if Vds < Vdsat

Qs Qd13--- Wactive⋅ Lactive⋅ C⋅ OX Vgs Vth–( )⋅–= =

Qb W– active Lactive COX⋅ ⋅ VFBCV φs Vth–1 A ′bulk–( ) V⋅ dsat

3------------------------------------------------+ +

⋅=


2---------

A ′bulk V⋅ ds2


2-----------------------------–

⋅----------------------------------------------------------------------------+–⋅=

Qinv W– active L⋅ active C⋅ OX Vgs Vth–A ′bulk V⋅ ds

2-----------------------------

A ′bulk2 V⋅ ds

2


2---------------- Vds⋅–

⋅----------------------------------------------------------------------------+–⋅=



2-------------------------------------------



2---------------- Vds⋅–

⋅----------------------------------------------------------------------------–+ +⋅=

Qd W– active L⋅ active C⋅ OX

Vgs Vth–

2------------------------

A ′bulk

2---------------- Vds⋅

A ′bulk V⋅ ds

Vgs Vth–( )2

6-------------------------------

A ′bulk V⋅ ds Vgs Vth–( )⋅8

---------------------------------------------------------------A ′bulk Vds⋅( )2

40-------------------------------------+–⋅

Vgs VthA ′bulk

2---------------- Vds⋅––

2

----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+–⋅

=

Qs Qg Qb Qd+ +( )–=


3-------------–

⋅=

Qd4

15------ Wactive L⋅ active C⋅ OX Vgs Vth–( )⋅ ⋅–=

Qb Wactive L⋅ active C⋅ OX– VFBCV φs Vth

1 A ′bulk–( ) V⋅ dsat

3------------------------------------------------+–+

⋅=




otherwise

CAPMOD=1

Define

in version 3.0 and 3.1,

and

in version 3.2,

where Vth0 corresponds to the bias-independent threshold voltage.

if Vgs < (Vfb + Vbs + Vgsteffcv)

else


2---------

A ′bulk V⋅ ds2


2-----------------------------–

⋅----------------------------------------------------------------------------+–⋅=

Qinv Wactive L⋅ active C⋅ OX– Vgs Vth–A ′bulk V⋅ ds

2-----------------------------

A ′bulk2 V⋅ ds

2


2---------------- Vds⋅–

⋅----------------------------------------------------------------------------+–⋅=



2-------------------------------------------



2---------------- Vds⋅–

⋅----------------------------------------------------------------------------–+ +⋅=

Qd W– active L⋅ active C⋅ OXVgs Vth–

2------------------------

A ′bulk

4---------------- Vds⋅

A ′bulk V⋅ ds( )2


2---------------- Vds⋅–

⋅----------------------------------------------------------------------------–+⋅=



3-------------–

⋅=

Qb W– active L⋅ active C⋅ OX VFBCV φs Vth

1 A ′bulk–( ) V⋅ dsat

3------------------------------------------------+–+

⋅=

Qd 0=

Qs Qg Qb+( )–=

Vfb Vth φs K1 φs Vbseff–⋅––=

Vfb Vth0 φs K1ox φs Vbseff–⋅––=

Qg1 Wactive L⋅ active C⋅ OX Vgs Vfb– Vbs– Vgsteffcv–( )⋅–=

Qg1 Wactive L⋅ active C⋅ OX K12

2---------- 1 1

4 Vgs Vfb– Vgsteffcv V– bs–( )⋅

K12------------------------------------------------------------------------------++–

⋅ ⋅=

Qb1 Qg1–=



In version 3.0 and 3.1,

In version 3.2, the model parameters NOFF and VOFFCV are supported:

if Vds <= Vdsat

(i) 50/50 Channel-charge Partition

(ii) 40/60 channel-charge Partition


Vdsat cv,Vgsteffcv

A ′bulk---------------------=

A ′bulk Abulk0 1CLCLeff

------------- CLE

+ ⋅=

Abulk0 1K1

2 φs Vbs–----------------------------

A0 Leff⋅

Leff 2 XJ Xdep⋅⋅+----------------------------------------------------

B0Weff B1+-------------------------+

⋅+ 1

1 KETA Vbs⋅+-----------------------------------------⋅=

Vgsteffcv n V⋅ t 1Vgs Vth–

n V⋅ t------------------------

exp+ln⋅=

Vgsteffcv NOFF n V⋅ ⋅ t 1Vgs Vth– VOFFCV–

NOFF n V⋅ t⋅---------------------------------------------------------

exp+ln⋅=

Qg Qg1 Wactive L⋅ active C⋅ OX VgsteffcvVds

2---------

A ′bulk V⋅ ds2

12 VgsteffcvA ′bulk

2---------------- Vds⋅–

⋅-------------------------------------------------------------------------+–

⋅+=

Qb Qb1 Wactive L⋅ active C⋅ OX1 A ′bulk–

2------------------------- V⋅

ds



2---------------- Vds⋅–

⋅-------------------------------------------------------------------------–

⋅+=

Qs Qd

Wactive L⋅ active C⋅ OX2

----------------------------------------------------------- VgsteffcvA ′bulk

2---------------- Vds⋅

A ′bulk V⋅ ds2


2---------------- Vds⋅–

⋅-------------------------------------------------------------------------+–

⋅–==

Qs

Wactive L⋅ active C⋅ OX


2---------------- Vds⋅–

2

⋅-------------------------------------------------------------------------

Vgsteffcv3 4

3--- Vgsteffcv

2 A ′bulk Vds⋅ ⋅ ⋅–23--- Vgsteffcv A ′bulk V⋅ ds( )2 2

15------ A ′bulk V⋅ ds( )3⋅–⋅ ⋅+

–=

Qd Qg Qb Qs+ +( )–=

Qs


----------------------------------------------------------- VgsteffcvA ′bulk

2---------------- Vds⋅

A ′bulk V⋅ ds( )2


2---------------- Vds⋅–

⋅-------------------------------------------------------------------------–+

⋅–=



if Vds > Vdsat


(ii) 40/60 Channel-charge Partition


capmod=2

The definition of Vfb is the same as in CAPMOD=1.

where and


Qg Qg1 W+ active L⋅ active C⋅ OX VgsteffcvVdsat

3-------------–

⋅=

Qb Qb1 W– active L⋅ active C⋅ OXVgsteffcv Vdsat–( )

3----------------------------------------------⋅=

Qs Qd


----------------------------------------------------------- Vgsteffcv⋅–= =

Qs

2 Wactive L⋅ active C⋅ OX⋅5

------------------------------------------------------------------- Vgsteffcv⋅–=


Qs

2 Wactive L⋅ active C⋅ OX⋅3

------------------------------------------------------------------- Vgsteffcv⋅–=


Qg Qinv Qacc Qsub0 δQsub+ + +( )–=

Qb Qacc Qsub0 δQsub+ +=

Qinv Qs Qd+=

VFBeff Vfb 0.5 V3 V32 4 δ⋅ 3 Vfb⋅++

⋅–= V3 Vfb Vgb δ3––= δ3 0.02=

Qacc Wactive L⋅ active C⋅ OX VFBeff Vfb–( )⋅–=

Qsub0 W– active L⋅ active C⋅ OX K12

2---------- 1– 1

4 Vgs VFBeff– Vgsteffcv– Vbseff–( )⋅

K12--------------------------------------------------------------------------------------------++

⋅ ⋅=

Vdsat cv,Vgsteff cv,

A ′bulk-----------------------=

A ′bulk Abulk0 1CLC

Lactive-----------------

+ ⋅

CLE=

Abulk0 1K1

2 φs Vbseff–⋅--------------------------------------

A0 L⋅ eff

Leff 2 XJ Xdep⋅⋅+----------------------------------------------------

B0W′eff B1+---------------------------+

⋅+ 1

1 KETA Vbseff⋅+-----------------------------------------------⋅=



where and


(ii) 40/60 Channel-charge Partition


Vgsteffcv NOFF n V⋅ ⋅ t 1Vgs Vth– VOFFCV–

NOFF n V⋅ t⋅---------------------------------------------------------

exp+ln⋅=

Vcveff Vdsat cv, 0.5 V4 V42 4 δ⋅ 4 V⋅ dsat cv,++

⋅–= V4 Vdsat cv, Vds δ4––= δ4 0.02=

Qinv W– active L⋅ active C⋅ OX VgsteffcvA ′bulk

2---------------- Vcveff⋅–

A ′bulk2 V⋅ cveff

2


2---------------- Vcveff⋅–

⋅-------------------------------------------------------------------------------+

⋅=

δQsub Wactive L⋅ active C⋅ OX1 A– ′bulk

2---------------------- Vcveff⋅

1 A ′bulk–( ) A ′⋅ bulk V⋅ cveff2


2---------------- Vcveff⋅–

⋅-------------------------------------------------------------------------------+

⋅=

Qs Qd 0.5 Q⋅ inv


-----------------------------------------------------------– VgsteffcvA ′bulk

2---------------- Vcveff⋅

A ′bulk2 Vcveff⋅

2


2---------------- Vcveff⋅–

⋅-------------------------------------------------------------------------------+–

⋅

= = =

Qs



2----------------Vcveff–

2

⋅--------------------------------------------------------------------------

Vgsteffcv3 4

3--- Vgsteffcv⋅

2A ′bulk Vcveff⋅ ⋅–

23--- V⋅

gsteffA ′bulk Vcveff⋅( )2⋅ 2

15------ A ′bulk Vcveff⋅( )3⋅–+

–=

Qd



2----------------Vcveff–

2

⋅--------------------------------------------------------------------------

Vgsteffcv3 5

3--- Vgsteffcv⋅

2A ′bulk Vcveff⋅ ⋅– Vgsteff A ′bulk Vcveff⋅( )2⋅ 1

5--- A ′bulk Vcveff⋅( )3⋅–+

–=

Qs W– active L⋅ active C⋅ OXVgsteffcv

2---------------------

A ′bulk Vds⋅4

-----------------------------A ′bulk V⋅ ds( )2


2---------------- Vcveff⋅–

⋅-------------------------------------------------------------------------------–+

⋅=



CAPMOD=3 (available in version 3.2 only)

CAPMOD=3 only supports zero biased Vfb, i.e., Vfb is calculated from bias independent Vth regardless of the version number. This is different from CAPMOD=1 and 2.

where and

(i) 50/50 Charge Partition

Qd W– active L⋅ active C⋅ OXVgsteffcv

2---------------------

3 A ′bulk Vcveff⋅ ⋅4

------------------------------------------A ′bulk Vcveff⋅( )2


2---------------- Vcveff⋅–

⋅----------------------------------------------------------------------------–+

⋅=

Vfb Vth0 φs K1ox φs Vbseff–––=

Qacc Wactive L⋅ active C⋅ OXeff Vgbacc⋅=

Vgbacc12--- V0 V0

2 4 δ⋅ 3 V⋅ fb++[ ]⋅=

V0 Vfb Vbseff Vgs δ3––+=

VFBeff Vfb 0.5 V3 V32 4 δ⋅ 3 Vfb⋅++

⋅–= V3 Vfb Vgb δ3––= δ3 0.02=

COXeffCOX Ccen⋅COX Ccen+--------------------------------=

Ccen εsi XDC⁄=

Φδ VtVgsteff cv, Vgsteff cv, 2 K⋅ lox 2ΦB⋅+( )⋅

moin K⋅ lox Vt2⋅

-----------------------------------------------------------------------------------------------------

ln⋅=

Qsub0 Wactive L⋅ active C⋅ OXeff–Klox

2

2------------- 1– 1

4 Vgs VFBeff– Vbseffs– Vgsteff cv,–( )⋅

Klox2

------------------------------------------------------------------------------------------------++⋅ ⋅=

Vcveff Vdsat12--- V1 V1

2 4 δ⋅ 3 V⋅ dsat++( )⋅–=

V1 Vdsat Vds δ3––=

VdsatVgsteff cv, ϕδ–

A ′bulk-----------------------------------=

Qinv Wactive L⋅ active C⋅ OXeff–

Vgsteff cv, ϕδ12--- Abulk⋅ ′ Vcveff

A ′bulk2 V⋅ cveff

2

12 Vgsteff cv, ϕδ A ′bulk V⋅ cveff 2⁄––( )⋅---------------------------------------------------------------------------------------------------+⋅

––

⋅=

δQsub Wactive L⋅ active C⋅ OXeff–1 A ′bulk–

2------------------------- Vcveff⋅

1 A ′bulk–( ) A⋅ ′bulk V⋅ cveff2

12 Vgsteff cv, ϕδ A ′bulk V⋅ cveff 2⁄––( )⋅---------------------------------------------------------------------------------------------------–⋅=



(ii) 40/60 Charge Partition

(iii) 0/100 Charge Partition

Intrinsic Capacitances (with Body bias and DIBL)

Capacitance Model Implementation

The charge conservative capacitance model is evaluated in three steps:

• The variable gate, bulk and drain charges, qg, qb and qd respectively, are calculated as functions of the gate, drain, source and bulk voltages. The charge contribution of the overlap, bulk-drain and bulk-source capacitances are not added to qg and qb at this step. The partitioning ratio of qd to qs is determined using the XPART model parameter. Nine basic “capacitances” (partial derivatives of the qg, qd and qb charges with respect to Vgb, Vdb and Vsb) are calculated as follows;

QS QD12--- Q⋅

inv

Wactive L⋅ active C⋅ OXeff

2-----------------------------------------------------------------–=

Vgsteff cv, ϕδ12--- A ′bulk Vcveff

A ′bulk2 Vcveff

2⋅12 Vgsteff cv, ϕδ A ′bulk Vcveff⋅ 2⁄––( )⋅---------------------------------------------------------------------------------------------------+⋅ ⋅––

⋅= =

Qs


2 Vgsteff cv, ϕδ– A ′bulkVcveff 2⁄–( )2------------------------------------------------------------------------------------------ Vgsteff cv, ϕδ–( )3 4

3--- Vgsteff cv, ϕδ–( )2A ′bulkVcveff–

23--- Vgsteff cv, ϕδ–( ) A ′bulkVcveff( )2 2

15------ A ′bulkVcveff( )3 ]–

+–=

QD


2 Vgsteff cv, ϕδ– A ′bulkVcveff 2⁄–( )2------------------------------------------------------------------------------------------ Vgsteff cv, ϕδ–( )3 5

3--- Vgsteff cv, ϕδ–( )2A ′bulkVcveff–

Vgsteff cv, ϕδ–( ) A ′bulkVcveff( )2 15--- A ′bulkVcveff( )3 ]–

+–=

QS


2-----------------------------------------------------------------– Vgsteff cv, ϕδ

12---A ′bulkVcveff

A ′bulk2Vcveff

2

12 Vgsteff cv, ϕδ A ′bulkVcveff 2⁄––( )⋅-----------------------------------------------------------------------------------------------–+–⋅=

QD


2-----------------------------------------------------------------– Vgsteff cv, ϕδ

32---– A ′bulkVcveff

A ′bulk2Vcveff

2

12 Vgsteff cv, ϕδ A ′bulkVcveff 2⁄––( )⋅-----------------------------------------------------------------------------------------------+–⋅=

C s d g b, , ,( ) g,∂Qs d g b, , ,

∂Vgsteffcv------------------------

∂Vgsteffcv

∂Vgt------------------------⋅=

C s d g b, , ,( ) s,∂Qs d g b, , ,

∂Vds-----------------------

∂Qs d g b, , ,

∂Vgsteffcv------------------------

∂Vgsteffcv

∂Vgt------------------------

∂Vth

∂Vds------------

∂Vth

∂Vbs------------+

⋅ ⋅+=

C s d g b, , ,( ) d,∂Qs d g b, , ,

∂Vds-----------------------

∂Qs d g b, , ,

∂Vgsteffcv------------------------

∂Vgsteffcv

∂Vgt------------------------

∂Vth

∂Vds------------⋅ ⋅+=

C s d g b, , ,( ) b,∂Qs d g b, , ,

∂Vbs-----------------------

∂Qs d g b, , ,

∂Vgsteffcv------------------------

∂Vgsteffcv

∂Vgt------------------------

∂Vth

∂Vbs------------⋅ ⋅+=

cggb ∂qg ∂Vgb⁄= cdgb ∂qd ∂Vgb⁄= cbgb ∂qb ∂Vgb⁄=



• The total gate, drain and bulk charges (Qg, Qd and Qb respectively) are calculated. These charges contain the variable gate (qg), drain (qd) and bulk (qb) charges as well as the charge contribution of the overlap, bulk-drain and bulk-source capacitances.

• Sixteen derivatives of the terminal charges with respect to the terminal voltages are computed as follows:

where n and m are gate, source, drain or bulk. These derivatives are used as transcapacitances for small signal AC analysis.

The following BSIM3v3 device parameters can be stored, printed and/or measured using the .save, .probe, .print and .measure statements (see the table listing all output variables)

• The variable intrinsic transcapacitances:cggb cdgb cbgbcgdb cddb cbdbcgsb cdsb cbsb

• The variable bulk-drain and bulk-source capacitances: capbd and capbs

• The total gate, drain and bulk charges Qg, Qd and Qbcapgdo, gate-drain overlap capacitancecapgso, gate-source overlap capacitancecapgbo, gate-bulk overlap capacitancecapgg, total gate capacitance (cggb + capgdo + capgso + capgbo)

Capacitances listed in the above table are used in .AC analysis. The capacitance matrix used in all types of simulation in the frequency domain is shown in following table.

Node Gate Drain Source Bulk

Gate

+cggb+capgdo+capgso+capgbo

+cgdb-capgdo

+cgsb-capgso

-(cggb+cgdb+cgsb)-capgbo

Drain+cdgb-capgdo

+cddb+capgdo+capbd

+cdsb -(cdgb+cddb+cdsb)-capbd

Source

-(cggb+cdgb+cbgb)-capgso

-(cgdb+cddb+cbdb) -(cgsb+cdsb+cbsb)+capgso+capbs

+(cggb+cgdb+cgsb)+(cdgb+cddb+cdsb)+(cbgb+cbdb+cbsb)-capbs

Bulk

+cbgb-capgbo

+cbdb-capbd

+cbsb-capbs

-(cbgb+cbdb+cbsb)+capgbo+capbd+capbs

cgdb ∂qg ∂Vdb⁄= cddb ∂qd ∂Vdb⁄= cbdb ∂qb ∂Vdb⁄=

cgsb ∂qg ∂Vsb⁄= cdsb ∂qd ∂Vsb⁄= cbsb ∂qb ∂Vsb⁄=

∂Qn∂Vm-------------



14.6.7: NQS Model EquationsThe charge-deficit NQS model can be turned on by setting NQSMOD=1 (default 0 =OFF). An enhanced version of Berkeley NQS model can also be invoked by setting NQSMOD=5.

Quasi-static equilibrium channel charge:

Actual channel charge and Qdef obtained from subcircuit:

with

and

where,

Elmore Constant (default=5)

(default = 0.5)

Qeq Qg Qb+( )–=

Qch Qeq Qdef–=

gτ1τ---

1τdrift------------

1τdiff----------+= =

τdiffq L⋅ eff

2

16 µ⋅ eff KT⋅---------------------------------=

τdrift

COX Weff L⋅ eff3⋅

µeff ε Qeq α Q⋅ def–⋅ ⋅-----------------------------------------------------------

ζQeq------------≈=

ε ≡

0.0 α 1.0≤ ≤

ζCOX Weff L⋅ eff

3⋅µeff ε⋅

----------------------------------------------=



14.7: Berkeley MOSFET Model BSIM4

14.7.1: IntroductionBSIM4 model is developed to explicitely address many issues in modeling sub-0.13 microns CMOS technology and RF high-speed CMOS circuit simulation

The Silvaco Verilog-A implementation is based on the most recent Berkeley release of May, 09 2003, namely BSIM4 version 3.0.

14.7.2: Instance ParametersBesides standard instance parameters L, W, ... supported by all MOSFET devices, the following BSIM4-specific parameters can be specified on the device statement:

Control Parameters


NF Number of device fingers - 1

SA Distance between OD edge to poly of one side 0

SB Distance between OD edge to poly of the other side 0

SD Distance between neighbour fingers 0

MIN Minimize either D or S in area/perimeter equations - 0

RBPB Resistance connected between BP and B nodes

RBPD Resistance connected between BP and DB nodes

RBPS Resistance connected between BP and SB nodes

RBDB Resistance connected between DB and B nodes

RBSB Resistance connected between SB and B nodes

ACNQSMOD AC NQS model selector -

RBODYMOD Substrate resistance network model selector -

RGATEMOD Gate resistance network model selector -

GEOMOD Geometry dependent parasitics model selector -

RGEOMOD S/D resistance and contact model selector - 0


MOBMOD Mobility model selector 0

RDSMOD Bias-dependent S/D resistance model selector 0

IGCMOD Global model selector for Igs, Igd, Igcs and Igcd 0

m

m

m

Ω

Ω

Ω

Ω

Ω



Threshold Voltage Parameters

IGBMOD Global model selector for Igb 0

RGATEMOD Gate-resistance model selector 0

RBODYMOD Model selector for distributed substrate resistance network 0

DIOMOD Junction Diode IV model selector 1

CAPMOD Capacitance model selector 2

GEOMOD Geometry dependent parasitics model selector 0

PERMOD Source/Drain perimeter model selector 0

TEMPMOD Temperature model selector 0


VTH0 Long-channel threshold voltage at Vbs=0 V 0.7 (NMOS)-0.7 (PMOS)

VFB Flat-band voltage (see note below) V -1.0

PHIN Non-uniform vertical doping effect V 0.0

K1 First body bias coefficient 0.5

K2 Second body bias coefficient - 0.0

K3 Narrow width coefficient - 80.0

K3B Body effect coefficient of K3 0.0

W0 Narrow width parameter m 2.5E-6

LPE0 Non-uniform lateral doping parameter at Vbs=0 m 1.74E-7

LPEB Non-uniform lateral doping effect on K1 m 0.0

VBM Maximum applied body bias in Vth calculation V -3.0

DVT0 First coefficient of short channel effect on Vth - 1.0

DVT1 Second coefficient of short channel effect on Vth - 1.0

DVT2 Body-bias coefficient of short channel effect on Vth -0.032

DVT0W First coefficient of narrow width effect on Vth for small channel length

0.0

DVT1W Second coefficient of narrow width effect on Vth for small channel length

5.3E6


V

V 1–

V 1–

m 1–

m 1–



Moderate Inversion Parameters

Mobility Parameters

DVT2W Body-bias coefficient of narrow width effect on Vth for small channel length

-0.032

DVTP0 First coefficient of pocket implant effect on Vth for long channel effect

m 0.0

DVTP1 Second coefficient of pocket implant effect on Vth for long channel effect

0.0


VOFF Offset voltage in moderate inversion region for large width and length

V -0.08

VOFFL Coefficient for gate length dependence of VOFF m 0.0

MINV Coefficient of moderate inversion - 0.0


U0 Low field mobility 0.067 (NMOS)0.025 (PMOS)

UA Coefficient of first-order mobility degra-dation due to vertical field

1.0E9(MODMOD=0,1)1.0E-15 (MODMOB=2)

UB Coefficient of second-order mobility deg-radation due to vertical field

1.0E-19

UC Coefficient of mobility degradation due to body-bias effect (MODMOD=1)

(MODMOB=0,2)

-0.0465(MODMOD=1)-0.0465E-9(MODMOB=0,2)

EU Exponent for mobility degradation of MODMOB=2

- 1.67 (NMOS)1.0 (PMOS)


V 1–

V 1–

m2 Vs⁄

m V⁄

m2 V2⁄

V 1–

m2 V⁄



Unified Current Saturation Parameters

Output Resistance Parameters


LAMBDA Velocity overshoot coefficient 0.0

VTL Thermal velocity 2.0E5

LC Velocity back scattering coefficient 0.0

XN Velocity back scattering coefficient - 3.0


PCLM Channel length modulation parameter - 1.0

PDIBLC1 First output resistance DIBL effect correction param-eter

- 0.39

PDIBLC2 Second output resistance DIBL effect correction parameter

- 0.0001

PDIBLCB Body effect coefficient of DIBL correction parameters 0.0

DROUT L dependence coefficient of the DIBL correction parameter in Rout

- 1.0

PSCBE1 First substrate current body-effect parameter 4.24E8

PSCBE2 Second substrate current body-effect parameter 1.0E-5

PVAG Gate dependence of Early voltage - 0.0

DELTA Effective Vds parameter V 0.01

FPROUT Pocket degradation parameter in Rout 0.0

PDITS Magnitude of DITS on Rout 0.0

PDITSL L dependence of DITS on Rout 0.0

PDITSD Vds dependence of DITS on Rout 0.0

m3 Vs⁄

m s⁄

m

V 1–

V m⁄

m V⁄

V m⁄

V 1–

m 1–

V 1–



Asymmetric and Bias-Dependent Rds Parameters

Quantum-Mechanical Inversion-Layer Thickness and High-k Gate Dielectrics Parameters


RDSW Zero-bias LDD resistance per unit width (RDS-MOD=0)

200.0

RDSWMIN LDD resistance per unit width at high Vgs and zero Vbs (RDSMOD=0)

0.0

RDW Zero bias lightly-doped drain resistance Rd(V) per unit width (RDSMOD=1)

100.0

RDWMIN Lightly-doped drain resistance per unit width at high Vgs and zero Vbs (RDSMOD=1)

0.0

RSW Zero bias lightly-doped source resistance Rs(V) per unit width (RDSMOD=1)

100.0

RSWMIN Lightly-doped source resistance per unit width at high Vgs and zero Vbs (RDSMOD=1)

0.0

PRWG Gate bias dependence of LDD resistance 1.0

PRWB Body bias dependence of LDD resistance 0.0

WR Width dependence parameter of LDD resis-tance

- 1.0


EPSROX Gate dielectric constant relative to the vacuum - 3.9 (SiO2)

TOXE Electrical gate equivalent oxide thickness m 4.0E-9

TOXP Physical gate equivalent oxide thickness m TOXE

TOXM TOXE at which BSIM4 parameters are extracted m TOXE

DTOX Defined as TOXE-TOXP m 0.0

Ω µmWR⋅

Ω µmWR⋅

Ω µmWR⋅

Ω µmWR⋅

Ω µmWR⋅

Ω µmWR⋅

V 1–

V 0.5–



Gate-Induced Drain Leakage (GIDL) Current Parameters

Gate Tunneling Current Parameters


AGIDL Pre-exponential coefficient for GIDL 0.0

BGIDL Exponential coefficient for GIDL 2.3E9

CGIDL Parameter for the body bias effect on GIDL 0.5

EGIDL Fitting parameter for band bending V 0.8


AIGBACC Parameter for Igb in accumulation 0.43

BIGBACC Parameter for Igb in accumulation 0.054

CIGBACC Parameter for Igb in accumulation 0.075

NIGBACC Parameter for Igb in accumulation(Note 1)

- 1.0

AIGBINV Parameter for Igb in inversion 0.35

BIGBINV Parameter for Igb in inversion 0.03

CIGBINV Parameter for Igb in inversion 0.006

EIGBINV Parameter for Igb in inversion V 1.1

NIGBINV Parameter for Igb in inversion(Note 1)

- 3.0

AIGC Parameter for Igs, Igd, Igcs and Igcd 0.43 (NMOS)0.31 (PMOS)

BIGC Parameter for Igcs and Igcd 0.054 (NMOS)0.024 (PMOS)

CIGC Parameter for Igcs and Igcd 0.075 (NMOS)0.03 (PMOS)

AIGSD Parameter for Igs and Igd 0.43 (NMOS)0.31 (PMOS)

BIGSD Parameter for Igs and Igd 0.054 (NMOS)0.024 (PMOS)

Ω 1–

V m⁄

V3

F s2⋅ g⁄ m 1–⋅

F s2⋅ g⁄ m 1– V 1–⋅ ⋅

V 1–

F s2⋅ g⁄ m 1–⋅

F s2⋅ g⁄ m 1– V 1–⋅ ⋅

V 1–

F s2⋅ g⁄ m 1–⋅

F s2⋅ g⁄ m 1– V 1–⋅ ⋅

V 1–

F s2⋅ g⁄ m 1–⋅

F s2⋅ g⁄ m 1– V 1–⋅ ⋅



Electrode Gate, Intrinsic-Input Resistance and NQS Model Parameters

Substrate Resistance Network Parameters

CIGSD Parameter for Igs and Igd 0.075 (NMOS)0.03 (PMOS)

DLCIG S/D overlap length for Igs/Igd m LINT

NIGC Parameter for Igs, Igd, Igcs and Igcd(Note 1)

- 1.0

POXEDGE Factor for the gate oxide thickness in the S/D overlap regions (Note 1)

- 1.0

PIGCD Vds dependence of Igcs and Igcd(Note 1)

- (Note 2)

NTOX Exponent for the tox ratio - 1.0

TOXREF Nominal gate oxide thickness(Note 1)

A 30.0


RSHG Gate-electrode sheet resistance /square 0.1

XGW Distance from the gate contact to the channel edge m 0.0

XGL Difference between Ldrawn and physical gate lenght m 0.0

XRCRG1 Parameter for distributed channel-resistance effect - 12.0

XRCRG2 Parameter to account for the excess channel diffusion conductance

- 1.0


GBMIN Minimum conductance for the substrate resistance model 1.0E-12

RBPB Resistance connected between BP and B nodes 50.0

RBPD Resistance connected between BP and DB nodes 50.0

RBPS Resistance connected between BP and SB nodes 50.0

RBDB Resistance connected between DB and B nodes 50.0

RBSB Resistance connected between SB and B nodes 50.0


V 1–

Ω

Ω 1–

Ω

Ω

Ω

Ω

Ω



Stress Effect Parameters


SAREF Reference distance between OD edge to poly of one side

0.0

SBREF Flicker noise frequency exponent 0.0

WLOD Width parameter 0.0

KU0 Mobility degradation/enhancement coefficient 0.0

KVSAT Saturation velocity degradation/enhancement parameter

0.0

TKU0 Temperature coefficient of KU0 - 0.0

LKU0 Length dependence of KU0 0.0

WKU0 Width dependence of KU0 0.0

PKU0 Cross-term dependence of KU0 0.0

LLODKU0 Length parameter for U0 stress effect - 0.0

WLODKU0 Width parameter for U0 stress effect - 0.0

KVTH0 Threshold shift parameter 0.0

LKVTH0 Length dependence of KVTH0 0.0

WKVTH0 Width dependence of KVTH0 0.0

PKVTH0 Cross-term dependence of KVTH0 0.0

LLODVTH Length parameter for Vth stress effect - 0.0

WLODVTH Width parameter for Vth stress effect - 0.0

STK2 K2 shift factor related to Vth0 change 0.0

LODK2 K2 shift modification factor - 1.0

STETA0 ETA0 shift factor related to Vth0 change 0.0

LODETA0 ETA0 shift modification factor - 1.0

m

m

m

m

m

mllodku0

mw lodku0

mw lodku0+llodu0

V m⋅

V m llodku0⋅

V mw lodku0⋅

V mw lodku0+llodu0⋅

m

m



Asymmetric Source/Drain Junction Diode Parameters


NJS Junction emission coefficient (Source side) - 1.0

NJD Junction emission coefficient (Drain side) - NJS

XITS Junction current temperature exponent (Source side) - 3.0

XITD Junction current temperature exponent (Drain side) - XITD

IJTHSREV Limiting current in reverse bias region (Source side) A 0.1

IJTHDREV Limiting current in forward bias region (Drain side) A IJTHSREV

IJTHSFWD Limiting current in forward bias region (Source side) A 0.1

IJTHDFWD Limiting current in reverse bias region (Drain side) A IJTHSFWD

XJBVS Fitting parameter for diode breakdown (Source side) - 1.0

XJBVD Fitting parameter for diode breakdown (Drain side) - XJBVS

BVS Breakdown voltage (Source side) V 10.0

BVD Breakdown voltage (Drain side) V BVS

JSS Bottom junction reverse saturation current density (Source side)

1.0E-4

JSD Bottom junction reverse saturation current density (Drain side)

JSS

JSWS Isolation-edge sidewall reverse saturation current den-sity (Source side)

0.0

JSWD Isolation-edge sidewall reverse saturation current den-sity (Drain side)

JSWS

JSWGS Gate-edge sidewall reverse saturation current density (Source side)

0.0

JSWGD Gate-edge sidewall reverse saturation current density (Drain side)

JSWGS

CJS Bottom junction capacitance per unit area (Source side)

5.0E-4

CJD Bottom junction capacitance per unit area (Drain side) CJS

PBS Bottom junction built-in potential (Source side) V 1.0

PBD Bottom junction built-in potential (Drain side) V PBS

MJS Bottom junction grading coefficient (Source side) - 0.5

MJD Bottom junction grading coefficient (Drain side) - MJS

A m2⁄

A m2⁄

A m⁄

A m⁄

A m⁄

A m⁄

F m2⁄

F m2⁄



Series/Parallel Devices Modeling Parameters

CJSWS Isolation-edge sidewall junction capacitance per unit lenght (Source side)

5.0E-10

CJSWD Isolation-edge sidewall junction capacitance per unit length (Drain side)

CJSWS

PBSWS Isolation-edge sidewall junction built-in potential (Source side)

V 1.0

PBSWD Isolation-edge sidewall junction built-in potential (Drain side)

V PBSWS

MJSWS Isolation-edge sidewall junction grading coefficient (Source side)

- 0.33

MJSWD Isolation-edge sidewall junction grading coefficient (Drain side)

- MJSWS

CJSWGS Gate-edge sidewall junction capacitance per unit lenght (Source side)

CJSWS

CJSWGD Gate-edge sidewall junction capacitance per unit length (Drain side)

CJSWS

PBSWGS Gate-edge sidewall junction built-in potential (Source side)

V PBSWS

PBSWGD Gate-edge sidewall junction built-in potential (Drain side)

V PBSWS

MJSWGS Gate-edge sidewall junction grading coefficient (Source side)

- MJSWS

MJSWGD Gate-edge sidewall junction grading coefficient (Drain side)

- MJSWS


DMCG Distance from the contact center to the gate edge m 0.0

DMCI Distance in the channel length direction from the contact center to the isolation edge

m DMCG

DMDG Same as DMCG but for merged devices only m 0.0

DMCGT DMCG in test structures m 0.0

DWJ Offset of the S/D junction width due to variations m DWC

XGW Distance from the gate contact to the channel edge m 0.0

XGL Offset of the gate length due to variations in patterning m 0.0

NGCON Number of gate contacts (1 or 2 only) - 1


F m⁄

F m⁄

F m⁄

F m⁄



Charge-Voltage (CV) Parameters

Three capacitance models are available in BSIM4 and come from BSIM3v3.2.2. The BSIM3v3.2.2 capacitance model parameters are used without any change in BSIM4, with one exception: CKAPPA is separated into CKAPPAS and CKAPPAD for the source side and the drain side diodes, respectively.

W and L Parameters


CKAPPAS* Coefficient for Source/Gate overlap capacitance F/m 0.6

CKAPPAD* Coefficient for Drain/Gate overlap capacitance F/m CKAPPAS


WINT Channel width offset parameter m 0.0

LINT Channel length offset parameter m 0.0

WL Coefficient of length dependence for width offset 0.0

WLN Power of length dependence of width offset - 1.0

WW Coefficient of width dependence for width offset 0.0

WWN Power of width dependence of width offset - 1.0

WWL Coefficient of length and width cross term for width offset

0.0

LL Coefficient of length dependence for length offset 0.0

LLN Power of length dependence for length offset - 1.0

LW Coefficient of width dependence for length offset 0.0

LWN Power of width dependence for length offset - 1.0

LWL Coefficient of length and width cross term for length offset

0.0

LLC Coefficient of length dependence for CV channel length offset

LL

LWC Coefficient of width dependence for CV channel length offset

LW

LWLC Coefficient of length and width dependence for CV channel length offset

LWL

WLC Coefficient of length dependence for CV channel width offset

WL

mWLN

mWWN

mWWN WLN+

mLLN

mLWN

mLWN LLN+

mLLN

mLWN

mLWN LLN+

mWLN



14.7.3: Effective Channel Length and WidthDefine

IV model

Bias-Independent Quantities:

Bias-Dependent Effective Channel Width:

Weff is used in Vdsat, Vasat, Vdseff, and Idso equations.

BSIM4 uses the effective source/drain diffusion width for modeling parasitics, such as source/

drain resistance, gate electrode resistance and gate-induced drain leakage (GIDL) current.

WWC Coefficient of width dependence for CV channel width offset

WW

WWLC Coefficient of length and width dependence for CV channel width offset

WWL

DLC Length offset fitting parameter for C-V model m LINT

DWC Width offset fitting parameter for C-V model m WINT

DWG Coefficient of Weff gate bias dependence 0.0

DWB Coefficient of Weff body bias dependence 0.0

XW Offset for channel width due to mask/etch effect (Note 1)

m 0.0

XL Offset for channel length due to mask/etch effect(Note 1)

m 0.0


mWWN

mWWN WLN+

m V 1–⋅

m V 1 2⁄–⋅

Lscaled L SCALE XL+⋅=

WscaledW SCALE⋅

NF-------------------------------- XW+=

Leff Lscaled 2 LINT LL

LscaledLLN

-----------------LW

WscaledLWN

-------------------LWL

LscaledLLN Wscaled

LWN⋅------------------------------------------+ + +

⋅–=

W ′eff Wscaled 2 WINT WL

LscaledWLN

-----------------WW

WscaledWWN

-------------------WWL


WWN------------------------------------------+ + +

⋅–=

Weff W ′eff 2 DWG Vgsteff⋅ DWB φs Vbseff– φs–(⋅+( ) )⋅–=

Weffcj

Weffcj Wscaled 2 DWJ WLC

LscaledWLN

-----------------WWC

WscaledWWN

-------------------WWLC

LscaledWLN Wscaled

WWN⋅------------------------------------------+ + +

⋅–=



CV model

14.7.4: Gate Dielectric ModelBSIM4 accounts for the finite charge-layer thickness effect in both IV and CV models. For this pur-pose, BSIM4 accepts the electrical gate oxide thickness TOXE and/or the physical gate oxide thickness TOXP, or their difference DTOX = TOXE - TOXP, as model parameters.

BSIM4 also allows to specify a gate dielectric constant (EPSROX) different from 3.9 (SiO2) for high-k dielectrics modeling. This is an alternative to the “equivalent oxide” approach.

14.7.5: Temperature EquationsDefine

where T is the instance temperature and TNOM is a model parameter corresponding to the tempera-ture at which model parameters have been extracted,

and

as the thermal voltage at device and nominal temperature, respectively.

Model parameter temperature scaling

In order to account for temperature effects, several model parameters are temperature-scaled:

Lactive Lscaled 2 DLC LLC

LscaledLLN

-----------------LWC

WscaledLWN

-------------------LWLC

LscaledLLN Wscaled

LWN⋅------------------------------------------+ + +

⋅–=

Wactive Wscaled 2 DWC WLC

LscaledWLN

-----------------WWC

WscaledWWN

-------------------WWLC

LscaledWLN Wscaled

WWN⋅------------------------------------------+ + +

⋅–=

CoxeEPSROX ε0⋅

TOXE------------------------------------=

CoxpEPSROX ε0⋅

TOXP------------------------------------=

TratioT

TNOM--------------------=

VtkB T⋅

q---------------= Vtnom

kB TNOM⋅q

-------------------------------=

KT1 T( ) KT1 Tratio 1–( )⋅=

KT1L T( ) KT1L Tratio 1–( )⋅=

KT2 T( ) KT2 Tratio 1–( )⋅=

U0 T( ) U0 Tratio( )UTE⋅=

UA T( ) UA UA1 Tratio 1–( )⋅+=

UB T( ) UB UB1 Tratio 1–( )⋅+=

UC T( ) UC UC1 Tratio 1–( )⋅+=

VSAT T( ) VSAT AT Tratio 1–( )⋅–=



RdsMod=0 (internal source/drain LDD resistance)

RdsMod=1 (external source/drain LDD resistance)

Junction Diode IV and CV parameters

In the following equations, x stands for S or D, depending if the parameter is related to the source side or the drain side, respectively.

Energy gap calculation

The energy gap width at device and nominal temperature is defined by the expressions, respectively:

RDSW T( ) RDSW PRT Tratio 1–( )⋅+=

RDSWMIN T( ) RDSWMIN PRT Tratio 1–( )⋅+=

RDW T( ) RDW PRT Tratio 1–( )⋅+=

RDWMIN T( ) RDWMIN PRT Tratio 1–( )⋅+=

RSW T( ) RSW PRT Tratio 1–( )⋅+=

RSWMIN T( ) RSWMIN PRT Tratio 1–( )⋅+=

Jsx T( ) JSx

Eg TNOM( )Vtnom

--------------------------------Eg T( )

Vt---------------- XTIx Tratio( )ln⋅+–

NJx---------------------------------------------------------------------------------------------------------

exp⋅=

Jsswx T( ) JSSWx

Eg TNOM( )Vtnom

--------------------------------Eg T( )

Vt---------------- XTIx Tratio( )ln⋅+–

NJx---------------------------------------------------------------------------------------------------------

exp⋅=

Jsswgx T( ) JSSWGx

Eg TNOM( )Vtnom

--------------------------------Eg T( )

Vt---------------- XTIx Tratio( )ln⋅+–

NJx---------------------------------------------------------------------------------------------------------

exp⋅=

CJx T( ) CJx 1 TCJ T TNOM–( )⋅+[ ]⋅=

CJSWx T( ) CJSWx 1 TCJSW T TNOM–( )⋅+[ ]⋅=

CJSWGx T( ) CJSWGx 1 TCJSWG T TNOM–( )⋅+[ ]⋅=

PBx T( ) PBx TPB T TNOM–( )⋅–=

PBSWx T( ) PBSWx TPBSW T TNOM–( )⋅–=

PBSWGx T( ) PBSWGx TPBSWG T TNOM–( )⋅–=

Eg T( ) 1.16 7.02 10 4– T2

T 1108.0+--------------------------⋅ ⋅–=

Eg TNOM( ) 1.16 7.02 10 4– TNOM2

TNOM 1108.0+-------------------------------------------⋅ ⋅–=



Intrinsic carrier concentration, surface potential and built-in potential calculation

Flat-Band Voltage (for Tunneling Current Equations)

if NGATE > 0.0

otherwise

14.7.6: I-V Model Equations

Threshold Voltage

In addition to all the features of the BSIM3v3 model, the BSIM4 threshold voltage model can more accurately model devices with non-uniform doping profile in both vertical and lateral directions. It also removes a phantom second roll-up when in BSIM3v3. A new long channel DIBL model

for pocket devices is also implemented.

The complete equation implemented in BSIM4 is

ni 1.45 1010 TNOM300.15

-------------------- ⋅

1.5

21.5565981Eg TNOM( )

2 Vtnom⋅--------------------------------–

exp⋅ ⋅=

φs 0.4 PHIN Vtnom+ +NDEP

ni------------------

ln⋅=

Vbi VtnomNDEP NSD⋅

ni2

------------------------------------- ln⋅=

Vfbsd VtnomNGATE

NSD-----------------------

log⋅=

Vfbsd 0=

Vth L Lmin<

Vth

Vth VTH0 KT1 KT1L LLeff---------⋅ KT2 Vbseff⋅

K1ox φs Vbseff–⋅ K1 φs⋅–( ) 1LPEB

Leff-----------------+⋅ K2ox Vbseff

K1ox 1LPE0Leff

----------------+ 1– φs K3 K3B Vbseff⋅+( ) φs

TOXEW′eff W0+----------------------------⋅

0.5DVT0W

DVT1WLeff W ′eff⋅

ltw---------------------------⋅

cosh 1–

----------------------------------------------------------------------------------DVT0

DVT1Leff

lt---------⋅

cosh 1–

----------------------------------------------------------+ Vbi φs–( )

0.5

DSUBLeff

lt0---------⋅

cosh 1–

----------------------------------------------------------- ETA0 ETAB Vbseff⋅+( ) Vds⋅ ⋅–

⋅ ⋅–

⋅+⋅ ⋅+

⋅–

+ + +

+

=



where

and

In version 3.0 and later, a smoothing function is added to set an upper bound for the body bias:

and all equations are evaluated with instead of .

V

if K2 < 0, otherwise

The expressions of the built-in voltage of the source/drain junctions and the surface potential

are given in the paragraph related to temperature dependence.

Poly-Silicon Gate Depletion Effect

Improved Effective (Vgs-Vth)

In BSIM3v3, there is no parameter dedicated to the moderate inversion region. In BSIM4, two model parameters, VOFFL and MINV, are introduced to improve the model accuracy in this region.

For non-uniform channel doping profiles, VOFF has the following length dependence:

MINV is incorporated to improve the accuracy of , and in the moderate inversion region via:

K1ox K1TOXETOXM-------------------⋅= K2ox K2

TOXETOXM-------------------⋅=

Vbseff Vbc 0.5 Vbs Vbc– δ1 Vbs Vbc– δ1–( )2 4 δ1 Vbc⋅ ⋅( )–+–[ ]⋅+=

V ′bseff 0.95 φs⋅ 0.5 0.95 φs⋅ Vbseff δ1 0.95 φs⋅ Vbseff– δ1–( )2 4 δ1 0.95 φs⋅ ⋅ ⋅++––( )⋅–=

V ′bseff Vbseff

δ1 0.001=

Vbc 0.9 φsK12

4 K22⋅-----------------–

⋅= Vbc 30–=

ltwεsi TOXE Xdep⋅ ⋅

EPSROX--------------------------------------------- 1 DVT2W Vbseff⋅+( )⋅=

ltεsi TOXE Xdep⋅ ⋅

EPSROX--------------------------------------------- 1 DVT2 Vbseff⋅+( )⋅=

Xdep2 ε⋅ si φs Vbseff–( )⋅

q NDEP⋅-------------------------------------------------=

lt0

εsi TOXE X⋅ dep0⋅EPSROX

------------------------------------------------=

Xdep0

2 ε⋅ si φs⋅q NDEP⋅--------------------------=

Vbi φs

Vgseff VFB φsq ε⋅ si N⋅ GATE TOXE2⋅

EPSROX2------------------------------------------------------------------- 1

2 EPSROX2⋅ Vgs VFB– φs–( )⋅

q ε⋅ si N⋅ GATE TOXE2⋅--------------------------------------------------------------------------------------+ 1–

⋅+ +=

V ′off VOFF VOFFLLeff

----------------------+=

gmgm

Id-------

gm2

Id-------



to improve parameter optimization process.

The expression of the effective (Vgs-Vth) reads:

where the sub-threshold swing n is written as

Mobility

Mobmod = 0

Mobmod = 1

Mobmod = 2

where for NMOS and for PMOS.

Bulk Charge Effect

m* 0.5MINV( )atanπ

----------------------------------+=

Vgsteff

n V⋅ t 1 m* Vgseff Vth–

n V⋅ t------------------------------⋅

exp+ln⋅

m* n Coxe2 φs⋅

q ε⋅ si NDEP⋅-------------------------------------

1 m*–( ) Vgseff Vth–( )⋅ V ′off–

n V⋅ t------------------------------------------------------------------------------–

exp⋅ ⋅ ⋅+

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

n 1 NFACTORCdep

Coxe------------⋅

Cdsc CIT+

Coxe-----------------------------+ +=

CdscCDSC CDSCD Vds⋅ CDSCB Vbseff⋅+ +( ) 0.5⋅

DVT1Leff

lt---------⋅

cosh 1–

-------------------------------------------------------------------------------------------------------------------------------=

Cdepεsi

Xdep------------=

µeffU0

1 UA UC Vbseff⋅+( )Vgsteff 2 Vth⋅+

TOXE---------------------------------------

⋅ UBVgsteff 2 Vth⋅+

TOXE---------------------------------------

2

⋅+ +

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

µeffU0

1 UAVgsteff 2Vth+

TOXE-----------------------------------

⋅ UBVgsteff 2Vth+

TOXE-----------------------------------

⋅2

1 UC V⋅ bseff+( )⋅+ +

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

µeffU0

1 UA UC Vbseff⋅+( )Vgsteff C0 VTH0 VFB– φs–( )⋅+

TOXE---------------------------------------------------------------------------------------

EU

⋅+

--------------------------------------------------------------------------------------------------------------------------------------------------------------------=

C0 2= C0 2.5=

Abulk 1 FdopingA0 L⋅ eff

Leff 2 XJ X⋅ dep⋅+----------------------------------------------------

1 AGS V⋅ gsteffLeff

Leff 2 XJ X⋅ dep⋅+----------------------------------------------------

⋅2

–⋅ B0W ′eff B1+---------------------------

+

⋅+

11 KETA Vbseff⋅+-----------------------------------------------⋅

=



where

Asymmetric and Bias-Dependent Drain/Source Resistances

Rdsmod = 0 (internal Rds(V))

Rdsmod = 1 (external Rd(V) and Rs(V))

where is the flat-band voltage between gate and source/drain calculated in the “Tunneling Cur-

rents” section.

Drain Saturation Voltage

Define

For Rds > 0 or (extrinsic case)

Fdoping

1LPEB

Leff-----------------+ K1ox⋅

2 φs Vbseff–⋅------------------------------------------------- K2ox K3B TOXE

W ′eff W0+----------------------------- φs⋅ ⋅–+=

Rds

RDSWMIN R+ DSW PRWB φs Vbseff– φs–( ) 11 PRWG Vgsteff⋅+--------------------------------------------------+⋅⋅

106 W⋅ effcj( )WR

----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

Rd

RDWMIN R+ DW P– RWB Vbd1

1 PRWG Vgd Vfbsd–( )⋅+-------------------------------------------------------------------+⋅⋅

106 W⋅ effcj( )WR

NF⋅-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

Rs

RSWMIN RSW+ P– RWB Vbs1

1 PRWG Vgs Vfbsd–( )⋅+-------------------------------------------------------------------+⋅⋅

106 W⋅ effcj( )WR

NF⋅--------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

Vfbsd

λ A1 Vgsteff⋅ A2+=

λ 1≠

Vdsatb b2 4 a c⋅ ⋅–––

2 a⋅----------------------------------------------=

a Abulk2 W⋅ eff VSAT⋅ Coxe⋅ Rds⋅ 1

λ--- 1–

Abulk⋅+=



For Rds = 0 and (intrinsic case)

where

corresponds to the critical electrical field at which the carrier velocity becomes saturated.

To account for velocity overshoot:

where and are defined in following paragraphs.

As GAMMA defaults to 0 and so ensures backward compatibility, this equation is supported by all ver-sions of BSIM4.

Effective Vds

An effective Vds is used to ensure a smooth transition near Vdsat from electrode to saturation regions:

Drain Current

The current equation for both linear and saturation regions is expressed by

where

b Vgsteff 2 V⋅ t+( ) 2λ--- 1–

Abulk E⋅ sat L⋅ eff

3 A⋅ bulk Vgsteff 2 V⋅ t+( ) W⋅ eff VSAT Coxe R⋅ ds⋅ ⋅ ⋅

+

+

⋅

–=

c Vgsteff 2 V⋅ t+( ) E⋅ sat Leff⋅ 2 Vgsteff 2 V⋅ t+( )2 W⋅ eff VSAT Coxe Rds⋅ ⋅ ⋅ ⋅+=

λ 1=

VdsatEsat Leff Vgsteff 2 V⋅ t+( )⋅ ⋅

Abulk Esat Leff⋅ ⋅ Vgsteff 2 V⋅ t+( )+--------------------------------------------------------------------------------------------=

Esat2 VSAT⋅

µeff-------------------------=

E ′ sat Esat 1LAMBDALeff µeff⋅--------------------------

1Vds Vdseff–

Esat litl⋅------------------------------+

2

1–

1Vds Vdseff–

Esat litl⋅------------------------------+

2

1+

---------------------------------------------------------⋅+

⋅=

litl Vdseff

Vdseff Vdsat12--- Vdsat Vds– DELTA– Vdsat Vds– DELTA–( )2 4 DELTA Vdsat⋅ ⋅++( )⋅–=

IdsIds0 NF⋅

1Rds I⋅ ds0

Vdseff-----------------------+

--------------------------------- 11

Cclm------------

VA

VAsat--------------

ln⋅+ 1Vds Vdseff–

VADIBL------------------------------+

1Vds Vdseff–

VADITS------------------------------+

1Vds Vdseff–

VASCBE------------------------------+

⋅ ⋅ ⋅ ⋅=

Idso

Weff µ⋅ eff Coxeff Vgsteff 1 AbulkVdseff

2 Vgsteff 2 V⋅ t+( )⋅-------------------------------------------------⋅–

Vdseff⋅⋅ ⋅ ⋅

Leff 1 Vdseff Esat L⋅ eff( )⁄+[ ]⋅-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

VA VAsat Cclm Vds Vdseff–( )⋅+=

Cclm1

PCLM------------------- F FPVAG 1

Rds I⋅ ds0

Vdseff-----------------------+

LeffVdsat

Esat-------------+

1litl-------⋅ ⋅ ⋅ ⋅ ⋅=



A source end velocity limit model is introduced to account for the current saturation mechanism due to the high electric field and strong velocity overshoot in nanoscale MOSFETs. It is supported in all ver-sions of BSIM4 and is turned on if the model parameter VTL is set to a positive value. VTL defaults to 0:

where

and

F 1

1 FPROUTLeff

Vgsteff 2 V⋅ t+-------------------------------------⋅+

------------------------------------------------------------------------------=

FPVAG 1 PVAGVgsteff

Esat Leff⋅-------------------------⋅+ =

VADIBLVgsteff 2 V⋅ t+( )

θrout 1 PDIBLCB Vbseff⋅+( )⋅--------------------------------------------------------------------------------- 1Abulk Vdsat⋅

Abulk Vdsat⋅ Vgsteff 2 V⋅ t+ +----------------------------------------------------------------------------–

FPVAG⋅ ⋅=

θroutPDIBLC1

2 DROUTLeff

lt0---------⋅

cosh 1– ⋅

----------------------------------------------------------------------------- PDIBLC2+=

1VASCBE--------------------

PSCBE2Leff

-------------------------PSCBE1 litl⋅–

Vds Vdseff–----------------------------------------

exp⋅=

VAsat

Esat L⋅ eff Vdsat 2 R⋅ ds+ VSAT Coxe⋅ Weff Vgsteff 1Abulk Vdsat⋅

2 Vgsteff 2 V⋅ t+( )⋅-------------------------------------------------–⋅ ⋅ ⋅ ⋅+

2 λ 1 Rds VSAT Coxe⋅ Weff Abulk⋅ ⋅ ⋅+–⁄---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

litlεsi TOXE XJ⋅ ⋅

EPSROX-----------------------------------------=

VADITS1

PDITS-------------------- F 1 1 PDITSL Leff⋅+( ) PDITSD Vds⋅( )exp⋅+[ ]⋅ ⋅=

CoxeffCoxe Ccen⋅Coxe Ccen+-----------------------------=

Ccenεsi

XDC-----------=

XDC1.9 10 9–×

1Vgsteff 4 VTH0 VFB– φs–( )⋅+

2 TOXP⋅-----------------------------------------------------------------------------------

0.7

+

--------------------------------------------------------------------------------------------------------=

I ′dsIds

1νsHD

νsBT------------

2 MM⋅+

1 2 MM⋅( )⁄---------------------------------------------------------------------=

νsHDIds

Vgsteff Coxeff Weff⋅ ⋅----------------------------------------------------=

νsBT1 r–1 r+------------ VTL⋅= r

Leff

XN Leff⋅ LC+--------------------------------------=



is a constant value.

Substrate Currents

Impact Ionization Current

Gate-Induced Drain Leakage (GIDL) Current

The equivalent expression for the Gate-Induced Source Leakage (GISL) current has been added to make the gate induced leakage component of the substrate current symmetric:

Gate Direct Tunneling Currents (optional)

Two global selectors are provided to turn on/off the tunneling components. Igcmod=1 turns on Igcs, Igcd, Igs and Igd. Igbmod=1 turns on Igb.

Voltage Across Oxide

where

MM 2=

IsubALPHA0

Leff-------------------------- ALPHA1+

Vds Vdseff–( ) BETA0Vds Vdseff–------------------------------–

exp IdsNoSCBE⋅ ⋅ ⋅=

IdsNoSCBEIds0 NF⋅

1Rds I⋅ ds0

Vdseff-----------------------+

--------------------------------- 11

Cclm------------

VA

VAsat--------------

ln⋅+ 1Vds Vdseff–

VADIBL------------------------------+

1Vds Vdseff–

VADITS------------------------------+

⋅ ⋅ ⋅=

IGIDL AGIDL Weffcj NFVds Vgseff– EGIDL–

3 TOXE⋅--------------------------------------------------------- 3 TOXE BGIDL⋅ ⋅

Vds Vgseff– EGIDL–---------------------------------------------------------–

expVdb

3

CGIDL Vdb3+

-------------------------------------⋅ ⋅ ⋅ ⋅ ⋅=

IGISL AGIDL Weffcj NFV– ds Vgdeff– EGIDL–

3 TOXE⋅------------------------------------------------------------- 3 TOXE BGIDL⋅ ⋅

Vds– Vgdeff– EGIDL–--------------------------------------------------------------–

expVsb

3

CGIDL Vsb3+

-------------------------------------⋅ ⋅ ⋅ ⋅ ⋅=

Vox Voxacc Voxdepinv+=

Voxacc Vfbzb VFBeff+=

Voxdepinv K1ox Φs⋅ Vgsteff+=

VFBeff Vfbzb12--- Vfbzb Vgb– δ– Vfbzb Vgb– δ–( )2 4 δ Vfbzb⋅ ⋅++( )⋅–= δ 0.02=( )



( is the threshold voltage at Vbs=0 and Vds=0)

Gate-to-Substrate Current

where

A=4.97232e-7 and B=7.45669e11

and

A=3.75956e-7 and B=9.82222e11

Gate-to-Channel Currents

where

A=4.97232e-7 for NMOS and A=3.42537e-7 for PMOS

B=7.45669e11 for NMOS and B=1.16645e12 for PMOS

The model parameter PIGCD is not specified, it is calculated by:

Vfbzb Vth0 Φs– K1 Φs⋅–= Vth0

ΦsK1ox

2------------ 1

4

K1ox2

------------ Vgseff Vgsteff– VFBeff– Vbseff–( )⋅+ 1–⋅=

Igb Igbacc Igbinv+=

Igbacc Weff Leff A ToxRatio Vgb VauxB– TOXE AIGBACC BIGBACC Voxacc⋅–( ) 1 CIGBACC Voxacc⋅+( )⋅ ⋅ ⋅[ ]exp

⋅ ⋅ ⋅ ⋅ ⋅⋅

=

A V 2–⋅ g Fs2( )⁄( )0.5

ToxRatioTOXREF

TOXE---------------------------

NTOX 1

TOXE2--------------------⋅=

Vaux NIGBACC Vt 1Vgb Vfbzb–

NIGBACC Vt⋅------------------------------------------–

exp+ log⋅ ⋅=

Igbinv Weff Leff A ToxRatio Vgb VauxB– TOXE AIGBINV BIGBINV Voxdepinv⋅–( ) 1 CIGBINV Voxdepinv⋅+( )⋅ ⋅ ⋅[ ]exp

⋅ ⋅ ⋅ ⋅ ⋅⋅

=

A V 2–⋅ g Fs2( )⁄( )0.5

Vaux NIGBINV Vt 1Voxdepinv EIGBINV–

EIGBINV Vt⋅-----------------------------------------------------------

exp+ log⋅ ⋅=

Igcs IgcPIGCD Vds⋅ PIGCD Vds⋅–( )exp 1 10 4–+–+

PIGCD Vds⋅( )2 2.0 10 4–×+------------------------------------------------------------------------------------------------------------------------⋅=

Igcd Igc1 PIGCD Vds⋅ 1+( ) PIGCD Vds⋅–( )exp⋅– 10 4–+

PIGCD Vds⋅( )2 2.0 10 4–×+-------------------------------------------------------------------------------------------------------------------------------------⋅=

Igc Weff Leff A ToxRatio Vgseff VauxB– TOXE AIGC BIGC Voxdepinv⋅–( ) 1 CIGC Voxdepinv⋅+( )⋅ ⋅ ⋅[ ]exp

⋅ ⋅ ⋅ ⋅ ⋅⋅

=

A V 2–⋅ A V 2–⋅

g Fs2( )⁄( )0.5

g Fs2( )⁄( )0.5

Vaux NIGC Vt 1Vgseff VTH0–

NIGC Vt⋅--------------------------------------

exp+ log⋅ ⋅=



The Gate-to-Channel currents are expressed as functions of instead of to account for the

saturation effect observed at high Vds:

Gate-to-S/D Currents

and

where

A=4.97232e-7 for NMOS and A=3.42537e-7 for PMOS

B=7.45669e11 for NMOS and B=1.16645e12 for PMOS

the expression of is given in the “Temperature Equations” section.

14.7.7: Capacitance Model EquationsBSIM4 provides three options for selecting intrinsic and overlap/fringing capacitance models. Those three capacitance models come from BSIM3v3.2.2.

The following table maps the BSIM4 CV models to those implemented in BSIM3v3.2.2:

CAPMOD in BSIM4Matched Intrinsic CAPMOD in BSIM3v3.2.2

Matched Overlap/fringing CAPMOD in BSIM3v3.2.2

0 0 0

1 2 2

2 (default) 3 2

PIGCD B TOXE⋅Vgsteff

2--------------------------- 1

Vdseff

2 Vgsteff⋅------------------------– ⋅=

Vdseff Vds

Igcs IgcPIGCD Vdseff⋅ PIGCD Vdseff⋅–( )exp 1 10 4–+–+

PIGCD Vdseff⋅( )2 2.0 10 4–×+------------------------------------------------------------------------------------------------------------------------------------⋅=

Igcd Igc1 PIGCD Vdseff⋅ 1+( ) PIGCD Vdseff⋅–( )exp⋅– 10 4–+

PIGCD Vdseff⋅( )2 2.0 10 4–×+------------------------------------------------------------------------------------------------------------------------------------------------⋅=

Igs Weff DLCIG A ToxRatioEdge Vgs V ′gsB– TOXE POXEDGE AIGSD BIGSD V ′gs⋅–( ) 1 CIGSD V ′gs⋅+( )⋅ ⋅ ⋅ ⋅[ ]exp

⋅ ⋅ ⋅ ⋅ ⋅⋅

=

Igd Weff DLCIG A ToxRatioEdge Vgd V ′gdB– TOXE POXEDGE AIGSD BIGSD V ′gd⋅–( ) 1 CIGSD V ′gd⋅+( )⋅ ⋅ ⋅ ⋅[ ]exp

⋅ ⋅ ⋅ ⋅ ⋅⋅

=

A V 2–⋅ A V 2–⋅

g Fs2( )⁄( )0.5

g Fs2( )⁄( )0.5

ToxRatioEdgeTOXREF

TOXE POXEDGE⋅-------------------------------------------------------

NTOX 1

TOXE POXEDGE⋅( )2---------------------------------------------------------------⋅=

V ′gd Vgd Vfbzd–( )2 10 4–+=

V ′gs Vgs Vfbzd–( )2 10 4–+=

Vfbsd



Gate Electrode and Intrinsic-Input Resistance

In BSIM4, four options are available:

RgateMod = 0 (zero-resistance)

In this case, no gate resistance is generated.

RgateMod = 1 (constant-resistance)

RgateMod = 2 (IIR model with variable resistance)

RgateMod = 3 (IIR model with two nodes)

RgeltdRSHG XGW

Weffcj

3 NGCON⋅--------------------------------+

⋅

NGCON Ldrawn XGL–( ) NF⋅ ⋅-------------------------------------------------------------------------------------=

1Rii------- XRCRG1

Ids

Vdseff--------------- XRCRG2

Weff µeff Coxeff Vt⋅ ⋅ ⋅Leff

-------------------------------------------------------⋅+ ⋅=



For these two latter cases, NQS models should be deactivated (TrnqsMod=0 and AcnqsMod=0).

Substrate Resistance Network

The model selector RbodyMod can be used to turn on/off the resistance network.

RbodyMod = 0 (Off)

No substrate resistance network is generated.

RbodyMod = 0 (On)

All five resistances in the substrate network are present simultaneously:

14.7.8: Asymmetric MOS Junction Diode ModelsIn this section, x stands for S or D because expressions are similar for the source and drain sides.

Effective Junction Area and Perimeter

If Ax is given

otherwise

is computed from NF, DWJ, GeoMod, DMCG, DMCI, DMDG, DMCGT and MIN.

Axeff Ax=

Axeff



If Px is given

if (PerMod = 0) else

otherwise

is computed from NF, DWJ, GeoMod, DMCG, DMCI, DMDG, DMCGT and MIN.

Junction Diode IV Model

Saturation Current

DioMod=0 (resistance-free)

where

DioMod=1 (breakdown-free)

(Current limiting feature)

Define

If

otherwise

(resistance- and breakdown-free model)

DioMod=2 (resistance and breakdown)

In this case, the expressions corresponding to noimod=0 are used along with the exponential term lin-earization in the forward-bias mode ( ) and in the reverse-bias mode ( ), as described in the preceding paragraph.

Pxeff Px= Pxeff Px NF Weffcj⋅–=

Pxeff

Isbx Jsx T( ) Axeff Jsswx T( ) Pxeff Jsswgx T( ) NF Weffcj⋅ ⋅+⋅+⋅=

Ibx IsbxVbx

NJx Vtnom⋅--------------------------------

1–exp fbreakdown⋅ ⋅ Vbx GMIN⋅+=

fbreakdown 1 XJBVxBVx Vbx+

NJx Vtnom⋅--------------------------------–

exp⋅+=

IJTHxFWD 0>

Vjxm NJx Vtnom 1IJTHxFWD

Isbx-----------------------------------+

ln⋅ ⋅=

Vbx Vjxm<

Ibx IsbxVbx

NJx Vtnom⋅--------------------------------

1–exp⋅ Vbx GMIN⋅+=

Ibx IJTHxFWDIJTHxFWD Isbx+

NJx Vtnom⋅--------------------------------------------------- Vbx Vjxm–( )⋅+=

IJTHxFWD 0≤

Ibx IsbxVbx

NJx Vtnom⋅--------------------------------

1–exp⋅ Vbx GMIN⋅+=

IJTHxFWD IJTHxREV



Junction Diode CV Model

If

otherwise

14.7.9: Source/Drain Diffusion ResistanceIf RgeoMod=0, the source diffusion resistance is not generated.

If NRS is given,

otherwise

is computed from NF, DWJ, GeoMod, DMCG, DMCI, DMDG, DMCGT, RSH and MIN.

If RgeoMod=0, the drain diffusion resistance is not generated.

If NRD is given,

otherwise

is computed from NF, DWJ, GeoMod, DMCG, DMCI, DMDG, DMCGT, RSH and MIN.

Cbx Cjbx Axeff Cjbxsw Pxeff Cjbxswg N⋅ F Weffcj⋅+⋅+⋅=

Vbx 0<

Cjbx CJx T( ) 1Vbx

PBx T( )---------------------–

MJx–

⋅=

Cjbxsw CJSWx T( ) 1Vbx

PBSWx T( )-------------------------------–

MJSWx–

⋅=

Cjbxswg CJSWGx T( ) 1Vbx

PBSWGx T( )------------------------------------–

MJSWGx–

⋅=

Cjbx CJx T( ) 1 MJxVbx

PBx T( )---------------------⋅+

⋅=

Cjbxsw CJSWx T( ) 1 MJSWxVbx

PBSWx T( )-------------------------------⋅+

⋅=

Cjbxswg CJSWGx T( ) 1 MJSWGxVbx

PBSWGx T( )------------------------------------⋅+

⋅=

Rsdiff NRS RSH⋅=

Rsdiff

Rddiff NRD RSH⋅=

Rddiff



14.8: BJT Modeling

14.8.1: Gummel-Poon BJT Model Equations

DC Current EquationsThe “eff” suffix on a parameter indicates that the parameter is temperature and geometry scaled. See the temperature effects equations below.

The DC characteristics of the BJT transistor are determined by 20 model parameters.

Define:

Forward diffusion current:

The current equations for the collector current (ic) and the base current (ib) are:

Base Charge EquationsThe parameters VAF and VAR represent the forward and reverse Early voltages. The parameters IKF and IKR determine the high current BF roll-off. ISE, NI, ISC, and NC determine the low current BF roll-off.

Base charge factor qb is determined as follows:

Substrate Current EquationsThe substrate current flows from the substrate to the collector for vertical transistors and substrate to base for lateral transistors.

For vertical transistors:

when vbs > -10 · NS · vt

and:

when vbs ≤ -10 · NS · vt

ibfISeff

BF------------ e

vbeNF vt⋅--------------------

1– ⋅=

ib ibf=

q11

1vbc

VAF-------------

vbeVAR-------------––

------------------------------------------------=

ibs ISSeff e

vbsNS vt⋅-------------------

1–

⋅=

ibs I– SSeff=



Variable Base Resistance EquationsSMARTSPICE incorporates the well known variable base resistance model. There are three parameters in the model: RB, IRB, and RBM. RB is base resistance for low currents (low injection level). RBM is base resistance for high base currents (high injection level). IRB is the base current at which the base resistance equals (RB + RBM)/2.

If IRB is not specified:

otherwise

where:

Capacitance EquationsThe total junction capacitance is computed as a sum of the depletion and diffusion capacitances. The depletion capacitance dominates low current behavior. The diffusion capacitance dominates high current behavior.

In the following equations, for depletion capacitance:

fc = FC

Base Emitter Capacitance Equations

The base-emitter capacitance is computed as a sum of diffusion and depletion capacitance.

cbe = cbediff + cbedep

Base-Emitter Diffusion Capacitance

Model parameters TF, XTF, ITF, and VTF can be used to modify the diffusion capacitance:

for ibe ≤ 0

for ibe > 0

where:

rbb RBMeff RBeff RBMeff–qb

---------------------------------------------- +=

rbb RBMeff 3 RBeff RBMeff z( ) z–tanz z( ) z( )tan⋅tan⋅-------------------------------------------⋅–⋅+=

z1 1 144

ibπ2 IRBeff⋅------------------------------⋅+

1 2⁄+–

24

n2------

ibIRBeff( )

------------------------ 1 2⁄

⋅------------------------------------------------------------------------------=

cbediff ∂∂vbe------------- TF ibe

qb--------⋅

=

cbediff ∂∂vbe------------- TF TF 1 tfarg+( ) ibe

qb--------⋅ ⋅=



Internal base-emitter current is determined by:

Base-Emitter Depletion Capacitance

The following equations model the base-emitter depletion capacitance.

for vbe < fc · VJE

for vbe ≥ fc · VJE

Base-Collector Capacitance Equations

The base-collector capacitance is computed as a sum of the depletion and diffusion capacitances.

cbc = cbcdiff + cbcdep

Base-Collector Diffusion Capacitance

The diffusion capacitance is modeled by model parameter TR:

where:

Base-Collector Depletion Capacitance

The following equations model the base-collector depletion capacitance.

for vbc < fc · VJC

for vbc ≥ fc · VJC

tfarg XTF ibeibe ITF+--------------------------

2

e

vbc1.44 VTF⋅----------------------------

⋅ ⋅=

ibe ISeff e

vbeNE vt⋅--------------------

1– ⋅=

cbedep CJEeff 1vbeVJE------------–

MJE–⋅=

cbedep CJEeff1 fc 1 MJE+( ) MJE vbe

VJE------------⋅+⋅–

1 fc–( ) 1 MJE+( )------------------------------------------------------------------------------------⋅=

cbcdiff ∂∂vbc------------- TR ibc⋅( )=

ibc ISeff e

vbcNR vt⋅--------------------

1– ⋅=

cbcdep XCJC CJCeff 1vbcVJC------------–

MJC–⋅ ⋅=

cbcdep XCJC CJCeff1 fc 1 MJC MJC vbc

VJC------------⋅+ +⋅–

1 fc–( ) 1 MJC+( )-------------------------------------------------------------------------------⋅ ⋅=



External Base-Internal Collector Junction Capacitance

Parameter XCJC is used to model the base-collector capacitance as a distributed capacitance. When XCJC is set to one, the entire base-collector capacitance is connected to the internal base node.

for vbcx < fc · VJC

for vbcx ≥ fc · VJC

Substrate Capacitance

for vs < fc · VJS

for vs ≥ fc · VJS

where:

ccs = cs

vs = vsc

Temperature Effects EquationsSMARTSPICE contains a number of temperature equations. These equations model the temperature dependence of various model parameters. Temperature model selection parameters TEMPLEV and TEMPLEVC can be used to select different temperature models.

For energy gap width:

where:

EG(0) = 1.16, gap1 = 7.02E-4, gap2 =1108.0

Define:

Saturation Currents and Current Gain

cbcx CJCeff 1 XCJC–( ) 1vbcxVJC-------------–

MJC–⋅ ⋅=

cbcx CJCeff 1 XCJC–( )1 fc 1 MJC+( ) MJC vbcx

VJC-------------⋅+⋅–

1 fc–( ) 1 MJC+( )-------------------------------------------------------------------------------------⋅ ⋅=

cs CJSeff 1vs

VJS------------–

MJS–⋅=

cs CJSCeff1 fc 1 MJS MJS vs

VJS------------⋅+ +⋅–

1 fc–( ) 1 MJS+( )------------------------------------------------------------------------------⋅=

EG t( ) EG 0( ) gap1t2

t gap2+( )---------------------------⋅–=

f EGvt tnom( )--------------------------

EGvt t( )-------------– XTI 1n t

tnom---------------

⋅+=

BF t( ) BF ttnom---------------

XTB⋅=



Capacitance Temperature EquationsSMARTSPICE uses different sets of equations to model the temperature effects of the contact potential.

In the following equations, “X” stands for E, C, or S (emitter, collector, or substrate).

BR t( ) BR ttnom---------------

XTB⋅=

ISE t( ) ISEt

tnom---------------

XTB------------------------------ e

fNE---------

⋅=

ISC t( ) ISCt

tnom---------------

XTB------------------------------ e

fNC---------

⋅=

ISS t( ) ISSt

tnom---------------

XTB------------------------------ e

fNS---------

⋅=

IS t( ) IS ef⋅=

IBE t( ) IBE e

fNF---------

⋅=

IBC t( ) IBC e

fNR---------

⋅=

IKF t( ) IKF 1 TIKF1 ∆t TIKF2 ∆t2⋅+⋅+( )⋅=

IKR t( ) IKR 1 TIKR1 ∆t TIKR2 ∆t2⋅+⋅+( )⋅=

IRB t( ) IRB 1 TIRB1 ∆t TIRB2 ∆t2⋅+⋅+( )⋅=

IKF t( ) IKF 1 TIKF1 ∆t TIKF2 ∆t2⋅+⋅+( )⋅=

IKR t( ) IKR 1 TIKR1 ∆t TIKR2 ∆t2⋅+⋅+( )⋅=

IRB t( ) IRB 1 TIRB1 ∆t TIRB2 ∆t2⋅+⋅+( )⋅=

VJX t( ) VJX ttnom--------------- vt t( ) 3 1n t

tnom--------------- EG tnom( )

vt tnom( )-----------------------------

EG t( )vt t( )

----------------–+⋅⋅–⋅=

CJX t( ) CJXO 1 MJX 4 10e 4 ∆t VJX t( )VJX

--------------------– 1+⋅–⋅ ⋅+⋅=

CJSW t( ) CJSW 1 MJSW 4 10e 4 ∆t VJSW t( )VHSW

-------------------------– 1+⋅–⋅ ⋅+⋅=



Basic DC Model Parameters

Low Current Beta Degradation Parameters

Parameter Description Units Default Area

(TYPE) +1 for NPN -1 for NPN

IS Saturation current A 1.0E-16 *

BF Maximum forward current gain 100

NF Forward current emission coeffi-cient

1.0

BR Maximum reverse current gain 1.0

NR Reverse current emission coefficient 1.0


ISE B-E leakage saturation current A 0 *

NE B-E leakage emission coefficient 1.5

ISC B-C leakage saturation current A 0 *

NC B-C leakage emission coefficient 1.5



Base Width Modulation Parameters (Early Effect)

High Current Beta Degradation Effect Parameters

Parasitic Resistor Parameters

Junction Capacitor Parameters


VAF Forward early voltage V infinite

VAR Reverse early voltage V infinite


IKF Forward knee current A infinite *

IKR Reverse knee current A infinite *

NK (NKF) Knee current roll-off coefficient 0.5

Parameters Description Units Default Area

RB Low bias base resistance Ohm 0 *

RBM High bias base resistance Ohm RB *

IRB Current where base resistance equals (RB + RBM)/2

A infinite *

RE Emitter resistance Ohm 0 *

RC Collector resistance Ohm 0 *


CJE B-E zero-bias depletion capacitance F 0 *

VJE B-E built-in potential V 0.75

MJE B-E junction exponential factor 0.33

FC Coefficient for forward-bias depletion capacitance formula

0.5

CJC B-C zero-bias depletion capacitance F 0 *

VJC B-C built-in potential V 0.75

MJC B-C junction exponential factor 0.33



Substrate Current Parameters

Transit Time Parameters


One can download Silvaco’s Verilog-A implementation of the Gummel-Poon BJT Model at www.silvaco.com.

XCJC Fraction of B-C depletion capacitance connected to internal base node

1

CJS (CJB) Zero-bias substrate junction capacitance F 0 *

VJS (VJB) Substrate junction built-in potential V 0.75

MJS(MJB) Substrate junction exponential factor 0.5

Parameters Description Units Default Area

ISS Substrate saturation current A 0 *

NS Substrate current emission factor 1.0


TF Forward transit time sec 0

XTF Fitting coefficient for TF 0

ITF Coefficient for TF current dependence A 0 *

VTF Coefficient for TF voltage dependence V infinite

TR Reverse transit time sec 0


Xtb Forward and Reverse Temperature exponent

0

Eg Energy Gap eV 1.16

XTi Temperature component of IS 3

TNOM Nominal Temperature K 300 Ti




14.9: Mextram Transistor Model (LEVEL=504)Mextram level 504 is implemented to be compliant to the Philips Nat. lab unclassified report, “The Mextram Bipolar Transistor Model LEVEL 504”, issued in December 2002.

Details and news on Mextram are available on Philips Semiconductors web site (http://www.semiconductors.philips.com/Philips_Models/).

The large signal equivalent circuit is shown below (please note the addition of overlap capacitances QBCO and QBEO):

Figure 14-5: Equivalent Circuit for Large Signal Analysis

E CC2

B

E1 C1

B2

B1

In RCC

RBC

RBV

RE Ic1c2

ISb1Ib1b2

Ib1+Ib2

Iex+Isub+Ib3 Isub+XIsub-Isf

XIex+XIsub

Iavl

Qte+Qbe+Qn Qtc+Qbc+Qepi

Qb1b2

QtsSQte Qtex+Qex

XQtex+XQex

S

Qbeo Qbco



14.9.1: Model Parameters .


MULT Multiplication factor - 1

TREF Reference temperature 27

DTA Difference of the device temp. to ambient temperature 0

EXMOD Flag for extended modelling of the reverse current gain - 1

EXPHI Flag for the distributed high frequency effects in transient - 1

EXAVL Flag for extended modelling of avalanche currents - 0

IS Collector-emitter saturation current A 22E-18

IK Collector-emitter high injection knee current A 0.10

VER Reverse Early voltage V 2.50

VEF Forward Early voltage V 44.00

BF Ideal forward current gain - 215.00

IBF Saturation current of the non-ideal forward base current A 2.7E-15

MLF Non-ideality factor of the non-ideal forward base current - 2.00

XIBI Part of ideal base current taht belongs to the sidewall - 0.00

BRI Ideal reverse current gain - 7.00

IBR Saturation current of the non-ideal reverse base current A 1.0E-15

VLR Cross-over voltage of the non-ideal reverse base current V 0.20

XEXT Part of IEX, QEX, QTEX and ISUB that depends on the base-collector voltage VBC1 instead of VB1C1

- 0.63

WAVL Epilayer thickness used in weak-avalanche model m 1.1E-6

VAVL Voltage determining curvature of avalanche model V 3.00

SFH Current spreading factor of avalanche model (Used if EXAVL=1)

- 0.30

RE Emitter resistance 5.00

RBC Constant part of the base resistance 23.00

RBV Variable part of the base resistance at zero bias 18.00

RCC Constant part of the collector resistance 12.00

RCV Resistance of the unmodulated epilayer 150.00

°C

°C

Ω

Ω

Ω

Ω

Ω



SCRCV Space charge resistance of the epilayer 1250.0

IHC Critical current for velocity saturation in the epilayer A 4.0E-3

AXI Smoothness parameter for the onset of quasi-saturation - 0.30

CJE Zero bias emitter-base depletion capacitance F 73E-15

VDE Emitter-base diffusion voltage V 0.95

PE Emitter-base grading coefficient - 0.40

XCJE Fraction of the emitter-base depletion capacitance that belongs to the sidewall

- 0.40

CJC Zero bias collector-base depletion capacitance F 78E-15

VDC Collector-base diffusion voltage V 0.68

PC Collector-base grading coefficient - 0.5

XP Constant part of CJC - 0.35

MC Collector current modulation coefficient - 0.5

XCJC Fraction of the collector-base depletion capacitance under the emitter area

- 32.0E-3

MTAU Non-ideality factor of the emitter stored charge - 1.00

TAUE Minimum transit time of stored emitter charge s 2.0E-12

TAUB Transit time of stored base charge s 4.2E-12

TEPI Transit time of stored epilayer charge s 41E-12

TAUR Transit time of reverse extrinsic stored base charge s 520E-12

DEG Bandgap difference over the base eV 0.0

XREC Pre-factor of the recombination part of IB1 - 0.0

AQB0 Temperature coefficient of the zero bias base charge - 0.30

AE Temperature coefficient of the resistivity of the emitter - 0.0

AB Temperature coefficient of the resistivity of the base - 1.00

AEPI Temperature coefficient of the resistivity of the epilayer - 2.50

AEX Temperature coefficient of the resistivity of the extrinsic base

- 0.62

AC Temperature coefficient of the resistivity of the buried layer - 2.00

DVGBF Bandgap voltage difference of forward current gain V 50.0E-3

DVGBR Bandgap voltage difference of reverse current gain V 45.0E-3

VGB Bandgap voltage of the base V 1.17


Ω



14.9.2: Model constants

Constants A and B for impact ionization depend on transistor type:

For NPN:

MC_An = 7.03 · 105 cm-1

MC_Bn = 1.23 · 106 V · cm-1

For PNP:

MC_An = 1.58 · 106 cm-1

MC_Bn = 2.04 · 106 V · cm-1

VGC Bandgap voltage of the collector V 1.18

VGJ Bandgap voltage recombination emitter-base junction V 1.15

DVGTE Bandgap voltage difference of emitter stored charge V 0.05

AF Flickernoise exponent - 2.00

KF Flickernoise coefficient ideal base current - 20E-12

KFN Flickernoise coefficient non-ideal base current - 20E-12

ISS Base-substrate saturation current A 48E-18

IKS Base-substrate high injection knee current A 250E-6

CJS Zero bias collector-substrate depletion capacitance F 315E-15

VDS Collector-substrate diffusion voltage V 0.62

PS Collector-substrate grading coefficient - 0.34

VGS Bandgap voltage of the substrate V 1.20

AS For a closed buried layer : AS = ACFor an open buried layer : AS = AEPI

- 1.58

RTH Thermal resistance /W 300.00

CTH Thermal capacitance J/ 3.00E-9

CBEO Emitter-base overlap capacitance F 0.0

CBCO Collector-base overlap capacitance F 0.0


°C

°C

MC_AJE 3.0=

MC_AJC 2.0=

MC_AJS 2.0=



14.9.3: Temperature scaling

The reference temperature is TREF (in ). The simulation temperature is computed from TEMP

and DTEMP (instance parameters), and from the model parameter DTA (all values specified in ).

Temperature conversions

TK = TEMP + DTA + 273.15 + VdT

(VdT is the voltage of the thermal node, if used)

TRK = TREF + 273.15

(Thermal voltage)

Resistances

The various parameters A describe the mobility of the corresponding regions : . The

temperature dependence of the zero-bias charge goes as .

RBCT = RBC · TNAEX

RBVT = RBV · TNAB

RCCT = RCC · TNAC

RCVT = RCV · TNAEPI

Depletion Capacitances

The junction diffusion voltage VDX with respect to temperature is:

where:

for the base-emitter junction:

°C

°C

TNTK

TRK-------------=

VTkq--- TK⋅=

VTRkq--- TRK⋅=

1V∆T----------

1VT-------

1VTR----------–=

µ tNA–∼

QB0T QB0⁄ tAQB0N=

VDXT 3kq---

TK ln TN( ) VDX TN 1 TN–( ) VGAP⋅+⋅+⋅ ⋅ ⋅–=

VGAP VGB=

X E=



for the base-collector junction:

for the collector-substrate junction:

The temperature scaling rule is the same for depletion capacitances CJE and CJS:

where PX is the grading coefficient.

The collector depletion capacitance is divided up in a variable and constant part. The constant part is temperature independent.

Current Gain

Currents and Voltages

VGAP VGC=

X C=

VGAP VGS=

X S=

CJXT CJX VDXVDXT----------------

PX⋅=

CJCT CJC 1 XP–( ) VDCVDCT-----------------

PCXP+⋅

⋅=

XPT XP CJCCJCT---------------⋅=

BFT BF TNAE AB– AQB0–( ) DVGBF

V∆T-----------------------–

exp⋅⋅=

BRIT BRI DVGBRV∆T

-----------------------–

exp⋅=

IST IS TN4 AB– AQB0–( ) V– GB V∆T⁄ exp⋅⋅=

IKT IK TN1 AB–( )⋅=

IBFT IBF TN6 2 MLF⋅–( )

VGJ–( ) MLF V∆T⋅( )⁄ exp⋅ ⋅=

IBRT IBR TN2 VGC–( ) 2 V∆T⋅( )⁄ exp⋅⋅=

VEFT VEF TNAQB0( )

1 XP–( ) VDCVDCT-----------------

PC⋅ XP+

1–⋅=

·



VLR and VLF are assumed temperature independant.

When either IS = 0 or ISST = 0 then .

Transit Times

Avalanche constant

Note that this temperature rule is independent of TREF since we take MC_BN as a material constant.

Heterojunction features

14.9.4: Geometry scalingThe parameter MULT can be used to put transistors in parallel. The following parameters are affected by the value of MULT :

IS, IK, IBF, IBR, IHC, ISS, IKS, CJE, CJC, CJS, CTH, CBEO, CBCO are multiplied by MULT

RE, RBC, RBV, RCC, RCV, SCRCV, RTH are divided by MULT

and the flicker-noise coefficients are scaled as :

VERT VER TNAQB0( ) VDE

VDET-----------------

PE–⋅=

ISST ISS TN4 AS–( ) V– GS( ) V∆T⁄ exp⋅⋅=

IKST IKS TN1 AS–( ) IST

IS---------

ISSISST-------------⋅ ⋅ ⋅=

IKST IKS TN1 AS–( )

⋅=

TAUET TAUE TNAB 2–( )

DVGTE–( ) V∆T⁄ exp⋅⋅=

TAUBT TAUB TNAQB0 AB 1–+( )

⋅=

TEPIT TEPI TNAEPI 1–( )

⋅=

TAURT TAURTAUBT TEPIT+

TAUB TEPI+----------------------------------------------⋅=

BnT MC_BN 1 7.2 10 4– TK 300–( ) 1.6 10 6– TK 300–( )2⋅–⋅+[ ]=

DEGT DEG TNAQB0( )

⋅=

KF KF MULT 1 AF–( )⋅→

KFN KFN MULT1 2 MLF 1–( ) AF 2 MLF–( )+[ ]–⋅→



14.9.5: DC current Equations

Ideal forward and reverse current

Model parameter: IS

The value of is not always the same as the node voltage VB2C2. The expression for

will be given in variable collector resistance section.

Main Current INThe Moll-Ross or integral charge-control relation is used to take into account high injection in the base. To avoid dividing by zero at punch-through, the depletion charge term q0 is modified.

Forward Base Currents

The total ideal base current is separated into a bulk and sidewall component. The bulk component depends on voltage VB2E1 and the sidewall component on voltage VB1E1. The separation is given by parameter XIBI.

Bulk component:

Sidewall component:

The non-ideal base current is given by:

IF ISTVB2E1

VT--------------

exp⋅=

IR ISTV∗ B2C2

VT------------------

exp⋅=

V∗ B2C2

V∗ B2C2 VT⁄( )exp

qI0 1

VTEVERT----------------

VTCVEFT----------------+ +=

qI1

qI0 qI

0( )2 0.01++2

-------------------------------------------------=

qIB qI

1 112---n0

12---nB+ +

⋅=

INIF IR–

qIB

-----------------=

IB1 1 XIBI–( )IST

BFT-----------

VB2E1

VT---------------

exp 1–

⋅ ⋅=

IB1S XIBI

IST

BFT-----------

VB1E1

VT---------------

exp 1–

⋅ ⋅=



Model parameters: IS, BF, XIBI, IBF and MLF.

Reverse Base Currents

The substrate current (holes injected from base to substrate), including high injection is given by:

The current with substrate bias in forward is only included as a signal to the designer :

The extrinsic base current (electrons injected from collector to extrinsic base, similar to IB1) is given by:

derivatives are computed from an approximated equation :

Model parameters: IBR, VLR, ISS, IKS, BRI, IS, IK

Weak Avalanche Current

In reverse mode IC1C2 < 0 or hard saturation the avalanche current is zero.

IAVL = 0

IB2 IBFTVB2E1

MLF VT⋅-------------------------- 1–exp

GMIN VB2E1⋅+⋅=

IB3 IBRT

VB1C1

VT---------------

exp 1–

VB1C1

2 VT⋅---------------

expVLRT

2 VT⋅----------------

exp+

---------------------------------------------------------------------

GMIN VB1C1⋅+⋅=

ISUB

2 ISSTVB1C1

VT---------------

exp 1–

⋅ ⋅

1 1 4IST

IKST--------------

VB1C1

VT---------------

exp

⋅ ⋅++

---------------------------------------------------------------------------------------=

ISF ISSTVSC1

VT------------

exp 1–

⋅=

g1

4 ISTVB1C1

VT---------------

exp⋅ ⋅

IKT----------------------------------------------------=

nBEXg1

1 1 g1++( )---------------------------------=

nBEX nBex 1 g1+ 1+≈

IEX1

BRIT--------------

12--- IKT nBEX IST–⋅ ⋅

⋅=

VB2C1 VDCT≥



In forward mode we have the following gradient of the electric field for zero bias :

The depletion layer thickness becomes :

The current ICAP will be given in Intrisic collector depletion charge section.

The generation of avalanche current increases at high current levels. This is only taken into account when flag EXAVL = 1.

When EXAVL = 0, then the effective thickness of the epilayer is :

WEff = WAVL

When EXAVL = 1, then :

For either value of EXAVL the thickness over which the electric field is important is :

The average electric field and the field at the base-collector junction are :

When EXAVL = 0, then the maximum of the electric field is :

EM = E0

When EXAVL = 1, then

The injection thickness Xi / WEPI is given in Variable collector resistance section.

dEdx02VAVL

WAVL2---------------------=

XD2

dEdx0-----------------

VDCT VB2C1–

1 ICAP IHC⁄–--------------------------------------⋅=

Weff WAVL 1Xi

2 WEPI⋅---------------------–

2

⋅=

WDxD Weff⋅

x2D W2

eff+---------------------------------=

EAVVDCT VB2C1–

WD--------------------------------------=

E0 EAV12--- WD dEdx0 1

ICAP

IHC------------–

⋅ ⋅ ⋅+=

SHW 1 2 SFH 12 Xi⋅WEPI--------------+

⋅ ⋅+=

Efi1 SFH+

1 2 SFH⋅+------------------------------=

EW EAV12--- WD dEdx0 Efi

IC1C2

IHC SHW⋅------------------------------–

⋅ ⋅ ⋅–=

EM12--- EW E0 EW E0–( )2 0.1 E2

AV ICAP IHC⁄⋅ ⋅++ +( )⋅=



For either value of EXAVL the intersection point and the generation factor GEM are :

When the expression for will diverge. Hence for (1-EAV/EM) < 10-7 we need to take the appropriate analytical limit and get :

The generation factor may not exceed 1 and may not exceed

The variable base resistance RB2 at the end of section Variable base resistance. The base base charge

term was given in section Main current IN. The avalanche current then is :

Series resistances:

emitter: RET = constant

base : RBCT = constant

collector: RCCT = constant

Variable Base Resistance

The variable part of the base resistance is modulated by the base charges and takes into account the base current crowding:

Model parameters : RBV, VER, VEF.

λD

λDEM WD⋅

2 EM EAV–( )⋅-------------------------------------=

GEMAn

BnT---------- EM λD

BnT–

EM-------------

expBnT–

EM------------- 1

Weff

λD-----------+

⋅exp–

⋅ ⋅ ⋅=

EM EAV≈ λD

GEM An WeffBnT–

EM-------------

exp⋅ ⋅=

GMAXVT

IC1C2 RBCT RB2+( )⋅----------------------------------------------------------

qIB

BFT-----------

RET

RBCT RB2+-----------------------------------+ +=

qIB

IAVL IC1C2

GEM GMAX⋅GEM 1 GMAX+( ) GMAX+⋅--------------------------------------------------------------------⋅=

qQ0 1

VTE

VERT----------------

VTC

VEFT----------------+ +=

qQ1

qQ0 qQ

0( )2

0.01++2

-----------------------------------------------------=

RB23 RBVT⋅

qQB

------------------------=

IB1B2

2 VT⋅RB2--------------

VB1B2

VT---------------

exp 1– VB1B2

RB2---------------+⋅=



Variable Collector Resistance

This model of the epilayer resistance takes into account:

• The decrease in resistance due to carriers injected from the base if only the internal base-collector junction is forward biased (quasi-saturation) and if both the internal and external base-collector junctions are forward biased (hard saturation and reverse mode of operation).

• Ohmic current flow at low current densities.• Space charge limited current flow at high current densities (Kirk effect, only in forward mode).

The current through the epilayer is given by :

For numerical reasons, when pW < e-40 then .

In version 1, derivatives are computed from an approximated equation :

In reverse mode the node voltage difference VB2C2 is the quantity that we use in further calculations. In forward mode the relation between the voltage difference VB2C2 and the current IC1C2 is not smooth

enough. We will instead calculate that is to be used in subsequent calculations. It has smoother properties than VB2C2 itself. In forward mode the node voltage VC2 is only used for K0 and IC1C2. For the rest of the quantities in the epilayer model a distinction must be made between forward and reverse mode.

Forward mode (IC1C2 > 0)

The voltage and current at which quasi-saturation or Kirk effect start are :

K0 1 4 VB2C2 VDCT–( ) VT⁄[ ]exp⋅+=

KW 1 4 VB2C1 VDCT–( ) VT⁄[ ]exp⋅+=

pW2 VB2C1 VDCT–( ) VT⁄[ ]exp⋅

1 KW+-----------------------------------------------------------------------------=

pW 0→

pW pW12--- KW 1–( )⋅≈

EC VT K0 KWK0 1+

KW 1+------------------

ln––⋅=

IC1C2

EC VC1C2+

RCVT-----------------------------=

V∗ B2C2

Vthqs VDCT 2 VT

IC1C2 RCVT⋅2 VT⋅

----------------------------------- 1+ ln⋅ ⋅ VB2C1–+=

Vqs12--- Vth

qs Vthqs( )

24 0.1 VDCT⋅( )2⋅++

=

IqsVqs

SCRCV----------------------

Vqs IHC SCRCV⋅+

Vqs IHC RCV⋅+-------------------------------------------------------⋅=



We need to solve :

which leads to

The injection thickness is given by :

The hole density at the base-collector junction is

For numerical reasons, when then

Reverse mode (IC1C2 < 0)

The hole density at the base-collector junction is :


The injection thickness is :

α1 AXI 1 IC1C2 Iqs⁄ 1–( ) AXI⁄[ ]exp+ ln⋅+

1 AXI 1 1– AXI⁄[ ]exp+ ln⋅+--------------------------------------------------------------------------------------------------------------------=

α Iqs⋅Vqs

SCRCV y2i⋅

----------------------------------Vqs SCRCV IHC yi⋅ ⋅+

Vqs RCV IHC⋅+----------------------------------------------------------------⋅=

vVqs

IHC SCRCV⋅---------------------------------------=

yi1 1 4 α v 1 v+( )⋅ ⋅ ⋅++

2 α 1 v+( )⋅ ⋅---------------------------------------------------------------=

xi

WEPI-------------- 1

yi

1 pW yi⋅+--------------------------–=

p∗ 0

gIC1C2 RCV⋅

2 VT⋅--------------------------------

xi

WEPI--------------⋅=

p∗ 0g 1–

2------------

g 1–2

------------ 2

2g pW pW g 1+ +( )⋅+ ++=

p∗ 0 e 40–< p∗ 0 0→

eV∗ B2C2 VT⁄

p∗ 0 p∗ 0 1+( ) VDCT VT⁄( )exp⋅ ⋅=

p∗ 02 VB2C2 VDCT–( ) VT⁄ exp⋅

1 K0+------------------------------------------------------------------------------=

p∗ 0 p0∗ 1

2--- K0 1–( )⋅≈

V∗ B2C2 VT⁄( )exp VB2C2 VT⁄( )exp=

xi

WEPI--------------

EC

EC VB2C2 VB2C1–+---------------------------------------------------=



Numerical problems might arise for . When or approximate

14.9.6: Description of charges

Emitter depletion charges

The total base-emitter depletion capacitance is separated into a bulk and sidewall component. The bulk component is located between node E1 and node B2 and the sidewall component between nodes B1 and E1 (see Fig. 2-19).

The bulk component is :

The sidewall component is :

Intrinsic collector depletion charge

In forward mode (IC1C2 > 0) then

In reverse mode (IC1C2 < 0) then

IC1C2 0≈ VC1C2 10 5– VT⋅< EC e 40– VT K0 KW+( )⋅ ⋅<

pavp∗ 0 pW+

2----------------------=

xi

WEPI--------------

pav

pav 1+-----------------=

VFE VDET 1 a 1– PE⁄jE–( )⋅=

VjE VB2E1 0.1VDET 1 VB2E1 VFE–( ) 0.1VDET⁄[ ]exp+ ln⋅–=

VTEVDET

1 PE–----------------- 1 1 VjE VDET⁄–( )1 PE––[ ] ajE VB2E1 VjE–( )⋅+⋅=

QTE 1 XCJE–( ) CJET VTE⋅ ⋅=

VSjE VB1E1 0.1VDET 1 VB1E1 VFE–( ) 0.1VDET⁄[ ]exp+ ln⋅–=

QSTE XCJE CJET

VDET

1 PE–----------------- 1 1 VS

jE VDET⁄–( )1 PE–

–[ ] ajE VB1E1 VSjE–( )⋅+⋅

⋅ ⋅=

B112---SCRCV IC1C2 IHC–( )⋅=

B2 SCRCV RCVT IHC IC1C2⋅ ⋅ ⋅=

Vxi 0= B1 B21 B2++=



Vxi=0 = VC1C2

The junction voltage for the capacitance is given by

Extrinsic collector depletion charges

The extrinsic collector depletion charge is partitioned between nodes B1 and C1 and nodes B and C1 respectively, independent of flag EXMOD.

Vjunc VB2C1 Vxi 0=+=

Vch

0.1VDCT IC1C2 0≤

VDCT 0.1 2IC1C2

IC1C2 Iqs+---------------------------⋅+

⋅ IC1C2 0>

=

bjcajc XPT–

1 XPT–------------------------=

VFC VDCT 1 b 1– PC⁄jc–( )⋅=

Vjc Vjunc Vch 1 Vjunc VFC–( ) Vch⁄[ ]exp+ ln⋅–=

ICAP

IHC IC1C2⋅IHC IC1C2+-------------------------------- IC1C2 0>

IC1C2 IC1C2 0≤

=

fI 1ICAP

IHC------------–

MC

=

VCVVDCT

1 PC–----------------- 1 fI 1 Vjc VDCT⁄–( )1 PC–⋅–[ ] fI bjc Vjunc Vjc–( )⋅ ⋅+⋅=

VTC 1 XPT–( ) VCV⋅ XPT VB2C1⋅+=

QTC XCJC CJCT VTC⋅ ⋅=

VjCEXVB1C1 0.1VDCT 1 VB1C1 VFC–( ) 0.1VDCT⁄[ ]exp+ ln⋅–=

VTEXVVDCT

1 PC–----------------- 1 1 VjCEX

VDCT⁄–( )1 PC––[ ] bjc VB1C1 VjCEX–( )⋅+⋅=

QTEX CJCT 1 XPT–( ) VTEXV⋅ XPT VB1C1⋅+[ ] 1 XCJC–( ) 1 XEXT–( )⋅ ⋅ ⋅=

XVjCEXVBC1 0.1VDCT 1 VBC1 VFC–( ) 0.1VDCT⁄[ ]exp+ ln⋅–=

XVTEXVVDCT

1 PC–----------------- 1 1 XVjCEX

VDCT⁄–( )1 PC––[ ] bjc VBC1 XVjCEX–( )⋅+⋅=

XQTEX CJCT 1 XPT–( ) XVTEXV⋅ XPT VBC1⋅+[ ] 1 XCJC–( ) XEXT⋅ ⋅ ⋅=



Depletion charge

Stored emitter charge

Stored base charges



VFS VDST 1 a 1– PS⁄js–( )⋅=

VjS VSC1 0.1VDST 1 VSC1 VFS–( ) 0.1VDST⁄[ ]exp+ ln⋅–=

QTS CJSTVDST

1 PS–----------------- 1 1 VjS VDCT⁄–( )1 PS––[ ] ajs VSC1 VjS–( )⋅+⋅

⋅=

QE0 TAUET IKTIST

IKT----------

1 MTAU⁄⋅ ⋅=

QE QE0 eVB2E1 MTAU VT⋅⁄

1–( )⋅=

QB0 TAUBT IKT⋅=

f1

4 IST⋅IKT

-----------------VB2E1

VT--------------

exp⋅=

n0

f1

1 1 f1++---------------------------=

n0 n0 1 f1+ 1+≈

QBE12--- QB0 n0 qQ

1⋅ ⋅ ⋅=

f2

4 IST⋅IKT

-----------------V∗ B2C2

VT-----------------

exp⋅=

nBf2

1 1 f2++---------------------------=

nB nB 1 f2+≈ 1+

QBC12--- QB0 nB qQ

1⋅ ⋅ ⋅=



The expression for was given in section Variable collector resistance.

Stored epilayer charge

Stored extrinsic charges


The electron density nBEX was given in section Reverse base currentsExtended Modeling of the Reverse Current Gain EXMOD = 1.

14.9.7: Extended Modeling of the Reverse Current Gain EXMOD = 1

Currents

The base currents IEX and ISUB are redefined:

A part XEXT of the base current of the extrinsic transistor is connected to the base terminal:

V∗ B2C2

VT------------------

exp

QEPI0

4 TEPIT VT⋅ ⋅RCVT

--------------------------------------=

QEPI12--- QEPI0

xi

WEPI-------------- p∗ 0 pW 2+ +( )⋅ ⋅ ⋅=

g2 4VB2C1 VDCT–

VT--------------------------------------

exp⋅=

pWEXg2

1 1 g2++----------------------------=

pWEX pWex 1 g2+ 1+≈

QEXTAURT

TAUBT TEPIT+----------------------------------------------

12--- QB0 nBEX⋅ ⋅ 1

2--- QEPI0 pWEX⋅ ⋅+

⋅=

IEX 1 XEXT–( ) IEX⋅=

ISUB 1 XEXT–( ) IEX⋅=

XIMSUB XEXT

2 ISSTVBC1

VT-------------

exp 1–

⋅⋅

1 1 4IST

IKST--------------

VBC1

VT-------------

exp

++

-----------------------------------------------------------------------------⋅=




To improve convergency behavior the conductivity of branch B-C1 is limited by a resistance of value RCCT :

In version 1, the expression for is different :

Charges

The charge QEX is redefined:

Xg1

4 ISTVBC1

VT-------------

exp⋅ ⋅

IKT--------------------------------------------------=

XnBEXXg1

1 1 Xg1++( )-------------------------------------=

XnBEX XnBex 1 Xg1+ 1+≈

XIMEXXEXTBRIT

-----------------12--- IKT XnBEX⋅ ⋅ IST–

⋅=

VEX VT 2VT

XEXTIST

BRIT-------------- ISST⋅

RCCT⋅ ⋅----------------------------------------------------------------------------------

ln+

=

VBEXVBC1 VEX–( ) VBC1 VEX–( )2 0.0121++

2----------------------------------------------------------------------------------------------------------=

FEXVBEX

RCCT XIMEX XIMSUB+( ) VBEX+⋅-------------------------------------------------------------------------------------------------=

FEX

FEXVBEX

XEXTIST

BRIT-------------- ISST+

RCCT⋅ ⋅ XIMEX XIMSUB+( ) RCCT⋅ VBEX+ +

-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

XISUB FEX XIMSUB⋅=

XIEX FEX XIMEX⋅=

QEX 1 XEXT–( ) QEX⋅=

Xg2 4VBC1 VDCT–

VT------------------------------------

exp⋅=

XpWEXXg2

1 1 Xg2++---------------------------------=




Model parameters : XEXT, TAUR, TAUB, TEPI

14.9.8: Distributed High Frequency Effects In the Intrinsic BaseDistributed high frequency effects are modeled, in first order approximation, both in lateral direction (current crowding) and in vertical direction (excess phase-shift). The distributed effects are an optional part of the Mextram model and can be switched on and off by flag EXPHI (on: EXPHI = 1 and off: EXPHI = 0). The high frequency current crowding is modeled by:

In version 1, the expression for is different :

Moreover, version 1 accounts for all derivatives of . In version 0, only was computed.

For reasons of simplification, only the forward depletion and diffusion charges are taken into account. The partial derivative of QB1B2 with respect to VB2E1 has to be neglected in the AC analysis. In transient analysis the convergency behavior may be improved by approximating this derivative with:

In vertical direction (excess phase-shift) base-charge-partioning is used. For reasons of simplification it is only implemented for the forward base charge (QBE) and for low level injection. Now QBE and QBC are redefined according to:

with

XpWEX XpWex 1 Xg2+ 1+≈

XQEX FEX XEXTTAURT

TAUBT TEPIT+----------------------------------------------

12--- QB0 XnBEX⋅ ⋅ 1

2--- QEPI0 XpWEX⋅ ⋅+

⋅ ⋅ ⋅=

CB15---

∂QTE

∂QB2E1-----------------------

∂QBE

∂VB2E1-----------------------

∂QE

∂VB2E1-----------------------+ +

⋅=

CB

CB15---

∂QTE

∂QB2E1-----------------------

12--- QB0 qQ

1 VB2E1∂∂n0⋅ ⋅ ⋅

∂QE

∂VB2E1-----------------------+ +

⋅=

QB1B2

∂QB1B2

∂VB2E1-----------------------

QB1B2 CB VB1B2⋅=

∂QB1B2

∂VB2E1-------------------

∂QBE

∂VB2E1-------------------

∂QE

∂VB2E1-------------------+

VB1B2

5 VT⋅---------------- ⋅=

QBE 1 qC–( ) QBE⋅=

QBC qC QBE QBC+⋅=

qC13---=



14.9.9: Heterojunction featuresThe most important difference between SiGe and pure Si transistors is the functional difference between hole charges and Gummel number. When the Ge concentration has a non-zero slope

we redefine the describing the Early effect for the currents (the remains unchanged).

Another feature that might be needed for SiGe transistors is recombination in the base. This changes the forward ideal base current (when ).

The last term also describes Auger recombination in high injection.

14.9.10: Noise ModelFor noise analysis noise current sources are added to the small signal equivalent circuit.

Thermal noise:

For the variable part of the base resistance a different formula is used, taking into account the effect of current crowding on noise behavior.

For the variable part of the collector resistance we take base-widening into account :

Collector current shot noise:

Forward base current shot noise and 1/f noise:

dEg 0≠

qI0 qQ

0

qI0

VTE

VERT---------------- 1+

DEGT

VT-----------------⋅

expVTC–

VEFT----------------

DEGT

VT-----------------⋅

exp–

DEGT

VT-----------------

1–exp

---------------------------------------------------------------------------------------------------------------------------------→

XREC 0≠

IB1

IST

BFT----------- 1 XIBI–( ) 1 XREC–( )

VB2E1

VT--------------

1–exp

XRECVB2E1

VT--------------

V∗ B2C2

VT------------------

exp 2–

+exp

1VTC

VEFT----------------+

1 nBn0+( )⋅ ⋅ ⋅

+⋅⋅ ⋅→

iNRE

2 4 k TK⋅ ⋅RET

----------------------- ∆f⋅=

iNRBC

2 4 k TK⋅ ⋅RBCT

----------------------- ∆f⋅=

iNRCC

2 4 k TK⋅ ⋅RCCT

----------------------- ∆f⋅=

iNRBV

24 k TK⋅ ⋅

RB2-----------------------

4VB1B2

VT---------------

5+exp

3------------------------------------------- ∆f⋅⋅=

iNRCV

24 k TK⋅ ⋅RCVT

----------------------- 1QEPI

QEPI0---------------+

∆f⋅ ⋅=

iNC

2 2 qIf Ir+

qIB

-------------- ∆f⋅ ⋅ ⋅=



Emitter-base sidewall current shot noise and 1/f noise :

Reverse base current shot noise and 1/f noise:

Extrinsic current shot noise and 1/f noise:

When EXMOD = 0 we have :

If EXMOD = 1 we have :

Substrate current shot noise (between nodes B1 and S, respectively B and S) :

14.9.11: Self-heating featureTo enable self-heating capability, set instance parameter SELFT to 1.

Power dissipation is given by :

One can download Silvaco’s Verilog-A implementation of the Mextram Model at www.silvaco.com.

iNB

2 2q IB1 IB2+[ ] KFf

--------- 1 XIBI–( )IB1

1 XIBI–-----------------------

AF

⋅ ⋅

KFNf

-------------- IB22 MLF 1–( )⋅ AF 2 MLF–( )⋅+⋅

+ +⋅

∆f⋅

=

iNBS

2 2 q ISB1

KFf

--------- XIBI ISB1

XIBI--------------

AF

⋅ ⋅+⋅ ⋅

∆f⋅=

iNB32 2 q IB3

KFf

--------- IB3( )AF⋅+⋅ ⋅

∆f⋅=

iNIEX2 2 q IEX

KFf

--------- IEX( )AF⋅+⋅ ⋅

∆f⋅=

iNIEX2 2 q IEX

KFf

--------- 1 XEXT–( )IEX

1 XEXT–--------------------------

⋅AF

⋅+⋅ ⋅

∆f⋅=

iNXIEX2 2 q XIEX

KFf

--------- XEXTXIEX

XEXT-----------------

⋅AF

⋅+⋅ ⋅

∆f⋅=

iNISUB2 2 q ISUB ∆f⋅ ⋅ ⋅=

iNXISUB2 2 q XISUB ∆f⋅ ⋅ ⋅=

Pdiss IN VB2E1 V∗ B2C2–( ) IC1C2 V∗ B2C2 VB2C1–( ) Iavl V∗ B2C2⋅–⋅+⋅=

V2EE1 RET⁄ V2

CC1 RCCT⁄ V2BB1 RBCT⁄+ + +

IB1B2 VB1B2⋅ IB1 IB2+( ) VB2E1 ISB1 VB1E1⋅+⋅+ +

IEX IB3 ISUB+ +( ) VB1C1⋅ XIEX XISUB+( ) VBC1⋅+ +

XISUB ISUB ISF–+( ) VC1S⋅+



14.10: The HICUM Bipolar Transistor ModelThe HIgh CUrrent Model (HICUM) is an advanced transistor model for bipolar transistors with main emphasis on circuit design for high-speed applications. This model has been developed and continuously improved for about 15 years. Work started about 1982 at Ruhr-University Bochum, Germany, with major emphasis on high-speed ECL-type circuits for fibre-optic applications.

The model has been extended to high-speed small-signal applications since 1989, as well as to SiGe HBTs since 1993. HICUM development resulted from the experience that the SPICE Gummel-Poon model (SGPM) is not accurate enough for high-speed large-signal transient applications and the required high collector current densities. Other major disadvantages of the SGPM are lack of sufficient physical background, poor description of base resistance and (quasi-)saturation effects.

Silvaco Verilog-A implementation of HICUM complies with version 2.1 of the model.



Equivalent Circuit

Figure 2-6: Equivalent circuit for DC and transient analysis.

Figure 2-7: Equivalent circuit for AC and noise analysis.


General Parameters


BULK Name of the global node used to connect the substrate when the terminal ns of the device is unspecified.

- “0”(gnd)



Transfer Current Parameters


C10 ICCR constant A.C 3.76e-32

MCF Ideality factor - 1.0

IS Collector saturation current A

QP0 Zero bias hole charge C 2.78e-14

ICH High-current correction term for 2D/3D-ICCR A 2.09e-2

HJEI Base-Emitter depletion charge weighting factor (HBTs) - 1.0

HJCI Base-Collector depletion charge weighting factor (HBTs) - 1.0

HFE Emitter minority charge weighting factor (HBTs) - 1.0

HFC Collector minority charge weighting factor (HBTs) - 1.0

Internal Junction Capacitances Parameters


CJEI0 B-E zero-bias depletion capacitance F 8.11e-15

VDEI B-E built-in voltage V 0.95

ZEI B-E exponent coefficient - 0.5

ALJEI B-E ratio of maximum to zero-bias value - 1.8

CJCI0 B-C zero-bias depletion capacitance F 1.16e-15

VDCI B-C built-in voltage V 0.8

ZCI B-C exponent coefficient - 0.333

VPTCI B-C punch-through voltage (a zero value means infinity) V 0.0

ZCIR B-C exponent coefficient under punch-through condi-tions

- (*)

Transit Time and Minority Charge Parameters


T0 Low-current forward transit time at Vbci=0 s 4.75e-12

DT0H Time constant for base and BC SCR width modulation s 2.1e-12

TBVL Time constant for modeling carrier jam at low Vcei s 4.0e-12



TEF0 Storage time in neutral emitter s 1.8e-12

GTFE Exponent coefficient for current dependence of TEF0 - 1.4

THCS Saturation time constant at high current densities s 3.0e-11

ALHC Smoothing factor for normalized injection width - 0.75

FTHC Partitioning factor between Base and Collector - 0.6

TR Reverse transit time s 0.0

Critical Current Parameters


RCI0 Internal collector resistance at low electric fields 1.278e+2

VLIM Voltage defining the limit between high and low electric fields in the collector

V 0.7

VPT Epilayer punch-through voltage of B-C SCR V 5.0

VCES Internal C-E saturation voltage V 0.1

Excess Phase Parameters


ALIT Transfer current additional delay time factor - 0.45

ALQF Minority charge additional delay time factor - 0.225

Lateral Scaling Parameters


LATB Scaling factor for QfC in bE direction - 3.765

LATL Scaling factor for QfC in lE direction - 0.342

Transit Time and Minority Charge Parameters


Ω



Base Current Components Parameters


IBEIS Bottom B-E saturation current A 1.16e-20

MBEI Bottom B-E non-ideality factor - 1.015

IREIS Bottom B-E recombination saturation current A 1.16e-16

MREI Bottom B-E recombination non-ideality factor - 2.0

IBEPS Peripheral B-E saturation current A 3.72e-21

MBEP Peripheral B-E non-ideality factor - 1.015

IREPS Peripheral B-E recombination saturation current A 1.0e-30

MREP Peripheral B-E recombination non-ideality factor - 2.0

IBCIS Internal B-C saturation current A 4.39e-20

MBCI Internal B-C non-ideality factor - 1.03

IBCXS External B-C saturation current A 1.16e-20

MBCX External B-C non-ideality factor - 1.015

Peripheral/External Capacitances Parameters


CJEP0 Peripheral B-E zero-bias depletion capacitance F 2.07e-15

VDEP Peripheral B-E built-in voltage V 1.05

ZEP Peripheral B-E exponent coefficient - 0.4

ALJEP Peripheral B-E ratio of maximum to zero-bias value - 2.4

CJCX0 External B-C zero-bias depletion capacitance F 5.39e-15

VDCX External B-C built-in voltage V 0.7

ZCX External B-C exponent coefficient - 0.333

ZCXR External B-C exponent coefficient under punch-through conditions

- (*)

VPTCX External B-C punch-through voltage (a zero value means infinity)

V 100



CEOX B-E overlap capacitance F 1.13e-15

CCOX B-C overlap capacitance F 2.97e-15

FBC B-C external capacitance partitioning factor - 0.1526

Internal Base Resistance Parameters


RBI0 Zero-bias internal base resistance 71.76

FGEO Geometry factor for long emitter stripe - 0.73

FDQR0 Correction factor for modulation by SCRs - 0.0

FQI Ratio of internal to total minority charge - 0.9055

FCRBI Ratio of HF shunt to total internal capacitance - 0.0

External Series Resistances Parameters


RCX External collector resistance 9.165

RBX External base resistance 8.83


Substrate Networks Parameters


RSU Parasitic substrate series resistance 100.0

CSU Parasitic substrate capacitance F 1.0e-15

Peripheral/External Capacitances Parameters


Ω

Ω

Ω

Ω

Ω



Substrate Transistor Parameters


ITSS Transfer saturation current A 7.44e-21

MSF Forward non-ideality coefficient - 1.05

MSR Reverse emission coefficient - 1.01

TSF Forward minority charge transit time s 0.0

ISCS S-C diode saturation current A 8.62e-20

MSC S-C diode non-ideality factor - 1.1

Substrate-Collector Capacitance Parameters


CJS0 S-C zero-bias depletion capacitance F 3.64e-14

VDS S-C built-in voltage V 0.6

ZS S-C exponent coefficient - 0.447

VPTS S-C punch-through voltage (a zero value means infinity) V 0.0

Base-Collector Avalanche Parameters


FAVL Avalanche multiplication factor - 1.186

QAVL Avalanche exponent coefficient C 11.1e-15

Base-Emitter Breakdown Parameters


IBETS B-E tunneling saturation current A 1.0e-2

ABET B-E tunneling exponent coefficient - 40



Temperature Dependence Parameters


TNOM Reference temperature at which parameter measure-ment has been done

27

VGB Equivalent band-gap voltage V 1.17

GAP1 First bandgap correction factor.Recommended values:

7.02E-4 or 4.43E-4 - Silicon 4.56E-4 - Germanium 5.41E-4 - Gallium Arsenide

eV/K 7.02E-4

GAP2 First bandgap correction factor. Recommended values:

1108 or 636 - Silicon 210 - Germanium 204 - Gallium Arsenide

K 1108

ALB Relative temperature coefficient of current gain 6.3e-3

ALT0 First temperature coefficient of low-bias transit time 0.0

KT0 Second temperature coefficient of low-bias transit time 0.0

ALVS Relative temperature coefficient of VLIM 1.0e-3

ALCES Relative temperature coefficient of VCES 0.4e-3

ZETARCI Temperature exponent coefficient of RCI - 1.6

ZETARBI Temperature exponent coefficient of RBI - 0.588

ZETARCX Temperature exponent coefficient of RCX - 0.223

ZETARBX Temperature exponent coefficient of RBX - 0.206

ZETARE Temperature exponent coefficient of RE - 0.0

ALFAV Relative temperature coefficient of FAVL 8.25e-5

ALQAV Relative temperature coefficient of QAVL 1.96e-4

°C

K 1–

K 1–

K 2–

K 1–

K 1–

K 1–

K 1–



14.10.2: Temperature ScalingThe reference temperature at which the parameters are determined is TNOM (TREF) (in C). The actual device operating temperature depends on instance parameters TEMP and DTEMP (in C).

Intermmediate variables

All temperatures are internally converted to Kelvin:

Define the thermal voltage by:

and

Transfer Current

Thermal Network and Self-Heating Parameters


SELFT Turn on self-heating effect, 0 means OFF, other val-ues means ON (overrides the value of the option SHMOD).

0

RTH Thermal resistance K/W 0.0

CTH Thermal capacitance K/J 0.0

XRT Exponent for RTH temperature dependence - 0.0

DTMAX Maximum temperature rise above heatsink K 1000

°°

T TEMP 273.15+=

T0 TNOM 273.15+=

VTkq---

T⋅=

VT0kq---

T0⋅=

TrTT0------=

∆T T T0–=

C10 T( ) C10 TN3 VGB

VT-------------- Tr 1–( )⋅

exp⋅ ⋅=

QP0 T( ) QP0 1ZEI

2----------- 1

VDEI T( )VDEI

--------------------------–

⋅+⋅=



The expression of the built-in voltage VDEI(T) is defined below.

Saturation Currents

Define the correction term:

and the factor

saturation currents can be defined by the following expressions:

Saturation currents have been made temperature-dependent in version 2.1. This results in the division of the parameter ITSS (saturation current for the parasitic PNP device) into forward and reverse components :

Series Resistances

αT ALB ∆T⋅=

RTVGB

VT-------------- Tr 1–( )⋅=

IBEIS T( ) IBEIS Tr3 MBEI⁄ MCF R⋅ T

MBEI-------------------------- αT–

exp⋅ ⋅=

IBEPS T( ) IBEPS Tr3 MBEP⁄ MCF R⋅ T

MBEP-------------------------- αT–

exp⋅ ⋅=

IREIS T( ) IREIS Tr3 MREI⁄ MCF RT⋅

MREI--------------------------

exp⋅ ⋅=

IREPS T( ) IREPS Tr3 MREP⁄ MCF R⋅ T

MREP--------------------------

exp⋅ ⋅=

IBCIS T( ) IBCIS Tr3 MBCI⁄ MCF R⋅ T

MBCI--------------------------

exp⋅ ⋅=

IBCXS T( ) IBCXS Tr3 MBCX⁄ MCF R⋅ T

MBCX--------------------------

exp⋅ ⋅=

ITSFS T( ) ITSS T3 MSF⁄r

RT

MSF--------------

exp⋅ ⋅=

ITSRS T( ) ITSS T3 MSR⁄r

RT

MSR--------------

exp⋅ ⋅=

ISCS T( ) ISCS T3 MSC⁄r

RT

MSC--------------

exp⋅ ⋅=

RCI0 T( ) RCI0 TrZETARCI⋅=

RBI0 T( ) RBI0 TrZETARBI⋅=

RBX T( ) RBX TrZETARBX⋅=



Transit Time and Minority Charge

A smoothing function has been introduced in order to prevent VLIM(T) to become negative at very high temperature:

Depletion Capacitances

The junction diffusion voltage is defined by the classical expression:

with the bandgap voltage at device and nominal temperatures given by:

and

If the model parameter GAP1 is set to zero, the expression reduces to the original formulation:

Moreover, a smoothing function has been introduced in order to prevent VDx(T) to become negative at very high temperature:

with

If ALJx is not available as a model parameter, an internal built-in value (set to 2.4) is used.

RCX T( ) RCX TrZETARCX⋅=

RE T( ) RE TrZETARE⋅=

VLIM T( )unsmoothed VLIM 1 ALVS ∆T⋅–( ) TrZETARCI⋅ ⋅=

VLIM T( ) VT 1.0 1.0VLIM T( )unsmoothed

VT----------------------------------------------------- 1.0–

exp+ln+

⋅=

VCES T( ) VCES 1 ALCES ∆T⋅+( )⋅=

T0 T( ) T0 1 ALT0 ∆T⋅ KT0 ∆T2⋅+ +( )⋅=

THCS T( ) THCS TrZETARCI 1–( )⋅=

TEF0 T( ) TEF0Tr

1 ALB ∆T⋅+-----------------------------------⋅=

VDx T( ) VDx Tr VT 3 ln Tr( )⋅EG T0( )

VT0--------------------

EG T( )VT

------------------–+⋅–⋅=

EG T( ) VGB GAP1T2

T GAP2+( )--------------------------------⋅–=

EG T0( ) VGB GAP1T0

2

T0 GAP2+( )----------------------------------⋅–=

VDx T( ) VDx Tr⋅ VGB Tr 1–( )⋅– 3 VT ln Tr( )⋅ ⋅–=

VDx T( ) VDα VT 1.0VDx T( )unsmoothed VDα–

VT-------------------------------------------------------------------

exp+ln⋅+=

VDα 1.001VDxALJx---------------⋅=



The temperature scaling rule for depletion capacitances is:

with: x = EI, CI, EP, CX or S depending on the junction.

The control parameters used to limit the capacitance value at high forward bias are defined by:

Avalanche

Tunneling

All other parameters are assumed to be temperature independent.

14.10.3: DC Equations

Internal Voltages

Define:

Quasi-Static Transfer Current

CJx T( ) CJx0VDx

VDx T( )----------------------

Zx⋅=

ALJEI T( ) ALJEI VDEI T( )VDEI

--------------------------⋅=

ALJEP T( ) ALJEP VDEP T( )VDEP

---------------------------⋅=

FAVL T( ) FAVL ALFAV ∆T⋅( )exp⋅=

QAVL T( ) QAVL ALQAV ∆T⋅( )exp⋅=

IBETS T( ) IBETS VDEP T( )VDEP

--------------------------- 2 CJEP0 T( )

CJEP0-----------------------------⋅ ⋅=

ABET T( ) ABET VDEP T( )VDEP

---------------------------⋅=

Vbei V B ′( ) V E ′( )–=

Vbci V B ′( ) V C ′( )–=

Vbep V B*( ) V E′( )–=

Vbcp V B*( ) V C ′( )–=

Vsci V S ′( ) V C ′( )–=

IT ITf ITr–=



The main current can be mathematically split into a forward component:

with:

and an inverse component:

Model parameters: ICH, C10 and MCF.

The base charge is given by:

and are the depletion charges stored at the BE and BC junction,

and are weighted minority charges stored in the transistor.

In general, the minority charges and are non-linearly dependent on and . For this

case, the implicit equation involving the common variable is solved internally by using a simple iteration process.

Model parameters: QP0, HJEI and HJCI.

Critical Current for Onset of High Current Effects

with:

and the smoothed effective collector voltage:

with:

Model parameters: RCI0, VLIM and VPT.

Base-Emitter Voltage Controlled Minority Charge

corresponds to the low-current component and the other components correspond to the emitter,

base and collector contributions at high collector current densities. It is important to notice that is not the actual collector minority charge because it includes a bias-dependent weighting function due to the lateral current spreading.

ITf ITf1 1ITf1

ICH------------+

⋅= ITf1C10QpT----------

VbeiMCF V⋅ T--------------------------

exp⋅=

ITrC10QpT----------

VbciVT

------------- exp⋅=

QpT QP0 HJEI QjEI⋅ HJCI QjCI⋅ QfT QrT+ + + +=

QjEI QjCI

QfT QrT

QfT QrT ITf ITr

QpT

ICKVceff

RCI0 T( )------------------------

1

1Vceff

VLIM T( )--------------------------

2

+

------------------------------------------------ 1x x2 10 3–++

2------------------------------------+⋅ ⋅=

xVceff VLIM T( )–

VPT---------------------------------------------=

Vceff VT 1 1Vc

VT------- 1–

exp+ ln+⋅=

Vc Vbei Vbci– VCES T( )–=

QfT Qf0 HFE ∆QfE⋅ ∆QfB HFC QfCT⋅+ + +=

Qf0

QfCT



Model parameters: HFE and HFC.

Low Current Density Component

with the current-independent transit time given by:

with as the internal Base-Collector depletion capacitance (evaluated without punch-through effect to cover all regions).

Model parameters: T0, DT0H and TBVL.

High Current Density Base Component

with the normalized injection width:

and

Model parameters: THCS, FTHC and ALHC.

High Current Density Emitter Component

Model parameters: TEF0 and GTFE.

High Current Density Collector Component

Define the normalized current:

with

Two cases have to be considered:

•


Qf0 τ f0 ITf⋅=

τ f0 T0 DT0H CJCI0 T( )CjCI

---------------------------- 1– ⋅ TBVL

CjCI

CJCI0 T( )---------------------------- 1–

⋅+ +=

CjCI

∆QfB 1 FTHC–( ) THCS T( ) w2 ITf⋅ ⋅ ⋅=

w i i2 ALHC++

1 1 ALHC++-----------------------------------------= i 1

ICK

ITf---------–=

∆QfE TEF0 T( )ITf

ICK---------

GTFE ITf

1 GTFE+---------------------------⋅ ⋅=

QfCT FTHC THCS T( ) ITf fCT⋅ ⋅ ⋅=

ick 1i i2 ALHC++

1 1 ALHC++-----------------------------------------–= i 1

ICK

ITf---------–=

LATB LATL>

fCT2

LATB LATL–----------------------------------------- 1 LATL w⋅+( )ln

LATL----------------------------------------------

1 LATB w⋅+( )lnLATB

----------------------------------------------–⋅=

w κ 1–LATB κ LATL⋅–------------------------------------------------=



and the intermediate variable:

•

with

and the normalized injection width:

Model parameters: FTHC, THCS, ALHC, LATB and LATL.

Base-Collector Voltage Controlled Minority Charge

Model parameters: TR.

Static Base Current Components

Internal Base Resistance

The DC internal resistance is modeled by:

with the current crowding factor

( is the base current component previously calculated).

and the conductivity modulated internal resistance,

κ 1 LATL+1 LATB+---------------------------

ick 1–

=

LATB LATL=

fCT2

LATB2 z⋅--------------------------- z z( )ln⋅ LATB w⋅–[ ]⋅=

z 1 LATB w⋅+( )=

w1 ick–

1 LATB ick⋅+--------------------------------------=

Qr TR ITr⋅=

IjBEI IBEIS T( ) VbeiMBEI VT⋅-----------------------------

exp 1– IREIS T( ) VbeiMREI VT⋅-----------------------------

exp 1–⋅+⋅=

IjBEP IBEPS T( ) VbepMBEP VT⋅-------------------------------

exp 1– IREPS T( ) VbepMREP VT⋅-------------------------------

exp 1–⋅+⋅=

IjBCI IBCIS T( ) VbciMBCI VT⋅-----------------------------

exp 1–⋅=

IjBCX IBCXS T( ) VbcpMBCX VT⋅-------------------------------

exp 1–⋅=

rBI ri1 η+( )lnη

-----------------------⋅=

η FGEOri IjBEI⋅

VT---------------------⋅= IjBEI

ri RBI0 T( )Q0

Q0 ∆Qp+------------------------ fp⋅ ⋅=



with:

and the periphery correction factor.

The depletion charges, , and the actual minority charge, are described in the charge section below.

Model parameters: RBI0, FGEO, FDQR0, FCRBI, FQI and QR0.

Collector-Base Breakdown: Avalanche Current

with:

Emitter-Base Breakdown: Tunneling Current

Parasitic Substrate Transistor

14.10.4: Description of Charges

Actual Base-Emitter Voltage Controlled Minority Charge

The terms , and have been already defined in DC equations.

The collector component is defined by:

Define the normalized current:

with

and the intermediate variable:

Q0 QP0 T( ) 1 FDQR0+( )⋅=

∆Qp QjEI QjCI Qf+ +=

fpQjEI Qf FQI⋅+

QjEI Qf+----------------------------------------=

QjEI QjCI Qf

IAVL ITf FAVL T( ) VCBeffQAVL T( )

CjCI VCBeff⋅--------------------------------–

exp⋅ ⋅ ⋅=

VCBeff VDCI T( ) Vbci–=

IBET IBETS T( ) Ve–( ) 1 Ve–( )1 ZEP– ABET T( )– 1 Ve–( )ZEP 1–⋅( )exp⋅ ⋅ ⋅=

ITS ITSS VbcpMSF VT⋅--------------------------

expVsci

MSR VT⋅--------------------------

exp–⋅=

ISC ISCS VsciMSC VT⋅--------------------------

exp 1–⋅=

Qf Qf0 ∆QfE ∆QfB QfC+ + +=

Qf0 ∆QfE ∆QfB

QfC FTHC THCS T( ) ITf fC⋅ ⋅ ⋅=

ick 1i i2 ALHC++

1 1 ALHC++-----------------------------------------–= i 1

ICK

ITf---------–=



as in DC equations.

Two cases have to be considered:

•

with:

with: ,

has the same form as but with and interchanged.

and the normalized injection width:

•


Model parameters: FTHC, THCS, ALHC, LATB and LATL.

Emitter-base depletion charges and capacitances

Define the (forward) voltage at which the classical expression intercepts the maximum constant value.

and the auxiliary voltage:

with

the internal Base-Emitter capacitance is defined by:

and the corresponding charge reads:

κ 1 LATB+1 LATL+---------------------------

ick 1–

=

LATB LATL>

fC2

LATB LATL–----------------------------------------- fCi

1 LATB+1 LATL+---------------------------

ln⋅ fCb fCl+–⋅=

fCi w LATL LATB+2

----------------------------------------- w2⋅ LATL LATB⋅3

--------------------------------------- w3⋅+ +=

fCb 1LATLLATB-----------------–

z2 2 z( )ln⋅ 1– ⋅ 1+4 LATB⋅

-------------------------------------------------------LATLLATB-----------------

z3 3 z( )ln⋅ 1– ⋅ 1+9 LATB⋅

-------------------------------------------------------⋅+⋅=

z 1 LATB w⋅+=

fCl fCb LATB LATL

w 1 κ–LATB κ LATL⋅–------------------------------------------------=

LATB LATL=

fC w2 1 LATB w⋅ 3⁄+1 LATB w⋅+

-------------------------------------------⋅=

w1 ick–

1 LATB ick⋅+--------------------------------------=

Vf VDEI T( ) 1 ALJEI T( )1

ZEI-----------–

–⋅=

ν j Vf VT 1 e+( )ln⋅–= eVf Vbei–

VT-------------------------

exp=

CjEICJEI0 T( )

1 ν j VDEI T( )⁄–( )ZEI--------------------------------------------------------

ee 1+------------⋅ ALJEI T( ) CJEI0 T( ) 1

e 1+------------⋅ ⋅+=



Model parameters: CJEI0, VDEI, ZEI and ALJEI.

The expressions of the peripheral Base-Emitter capacitance and corresponding charge are

obtained by inserting the related model parameters as well as the voltage Vbep in the previous equations.

Model parameters: CJEP0, VDEP, ZEP and ALJEP.

Base Collector Depletion Charges and Capacitances

The model is similar to that used for Base Emitter junction modeling. However, a punch-through effect at large reverse bias is accounted for.

Define the (forward) voltage at which the classical expression intercepts the maximum constant value

the auxiliary voltages:

with

and

with:

and the voltage at which the transition from medium to large reverse bias starts.

The capacitance consists of three components:

with the term corresponding to the classical equation at medium bias and

the term corresponding to the maximum value at large forward bias,

and the term corresponding to the large reverse bias region beyond punch-through;

with:

QjEICJEI0 T( ) VDEI T( )⋅

1 ZEI–---------------------------------------------------------- 1 1

νj

VDEI T( )--------------------------–

1 ZEI–( )

– ALJEI T( ) CJEI0 T( ) Vbei ν j–( )⋅ ⋅+⋅=

CjEP QjEP

VfCI VDCI T( ) 1 2.4

1ZCI-----------–

–⋅=

νjr VfCI VT 1 er+( )ln⋅–= erVfCI Vbci–

VT------------------------------

exp=

νjm VPTCI VDCI T( )–( )– Vr 1 em+( )ln⋅+=

emVPTCI VDCI T( )– νjr+

Vr-----------------------------------------------------------------

exp=

Vr 0.1 VPTCI VDCI T( )–( )⋅ 4 VT⋅+=

CjCI CjCIcl CjCIpt CjCIfb+ +=

CjCIclCJCI0 T( )

1 ν jm VDCI T( )⁄–( )ZCI------------------------------------------------------------

em

em 1+----------------

er

er 1+--------------⋅ ⋅=

CjCIfb 2.4 CJCI0 T( ) 1er 1+--------------⋅ ⋅=

CjCIptCjCI0r

1 ν jr VDCI T( )⁄–( )ZCIR--------------------------------------------------------------

1em 1+----------------⋅=



The corresponding charge is obtained by integration of the capacitance.

with the component at medium bias:

the component at large reverse bias

the component at large forward bias:

and a correction component resulting from the integration process:

Model parameters: CJCI0, VDCI, VPTCI, ZCI and ZCIR.

Substrate-Collector Depletion Charge and Capacitance

The expressions of the Substrate-Base capacitance and corresponding charge are obtained by inserting the related model parameters as well as the voltage Vsci in the equations used for the Base-Collector junction.

Model parameters: CJS0, VDS, ZS and VPTS0.

New temperature mappings

The temperature dependence of junction diffusion voltages VDx (x = EI, CI, EP, CX or S) is now expressed by the classical expression:

with the bandgap voltage at device and nominal temperatures given by:

and

EG is now defined as an alias for VGB.

CjCI0r CJCI0 T( ) VDCI T( )VPTCI

-------------------------- ZCI ZCIR–( )

⋅=

QjCI QjCIm QjCIr QjCIf QjCIc–+ +=

QjCImCJCI0 T( ) VDCI T( )⋅

1 ZCI–---------------------------------------------------------- 1 1

νjm

VDCI T( )--------------------------–

1 ZCI–( )–⋅=

QjCIrCjCI0r

1 ZCIR–------------------------ 1 1

νjr

VDCI T( )--------------------------–

1 ZCIR–( )–⋅=

QjCf 2.4 CJCI0 T( ) Vbci νjr–( )⋅ ⋅=

QjCIcCjCI0r VDCI T( )⋅

1 ZCIR–-------------------------------------------------- 1 1

ν jm

VDCI T( )--------------------------–

1 ZCIR–( )

–⋅=

CjS QjS

VDx T( ) VDx Tr VT 3 Tr( )ln⋅EG T0( )

VT0--------------------

EG T( )VT

------------------–+⋅–⋅=

EG T( ) VGB GAP1T2

T GAP2+( )--------------------------------⋅–=

EG T0( ) VGB GAP1T0

2

T0 GAP2+( )----------------------------------⋅–=



14.11: The VBIC Bipolar Transistor Model (LEVEL=5)The Vertical Bipolar Inter-Company (VBIC) model was defined by a group of IC and CAD industry representatives, to provide a public domain, standard BJT model.

The model is based upon Kull’s enhancements to the Spice Gummel-Poon (SGP) bipolar model, with extensions to incorporate the physical effects characteristic of modern bipolar transistors.

Equivalent circuit

Figure 2-8: Equivalent Circuit of the VBIC Bipolar Model (large signal)

14.11.1: VBIC Model ParametersFor parameters noted with an asterisk (*), a zero value means infinity.

General Parameters


LEVEL Model selector (must be set to 5 for VBIC) - 1

VERSION Version parameter. Only 1.1 (if REV=5) and 1.2 (if REV= 0) are permitted, otherwise 1.2 is assumed.

- 1.2

REVISION Revision parameter. Only 0 (if VERS=1.2) and 5 (if VERS=1.1) are permitted, otherwise 0 is assumed.

- 0

Itxf−Itzr

c

e

b

RCX

RE

RBX

Ibc−Igc

Ibe

Qbc

Qbe

Itfp−Itrp

Ibcp

Ibep

Qbcp

Qbep

RS

Qbcx

RBIP/qbp

RBI/qb

Ibex

Qbex

CBEO

s CBCO

bx bi

ei

cx

ci

bp

si

RCI

IthCTH

RTH

dt

ItzfQcxf

Flxf

1Ω

xf1 xf2

thermal networktl

excess phase network



BULK Name of the global node used to connect the substrate when the terminal ns of the device is unspecified.

- “0”(gnd)

QBM Selector for SGP qb formulation (v1.2) - 0.0

SELFT Self-heating effect switch, 0 means OFF, other values mean ON (the value of SHMOD option is overridden).

- 0

Saturation Current Parameters


IS Transport saturation current A 1e-16

ISRR Reverse saturation current factor for HBTs (v1.2)

- 1.0

IBEI Ideal B-E saturation current A 1e-18

IBEN Non-ideal B-E saturation current A 0.0

IBCI Ideal B-C saturation current A 1e-16

IBCN Non-ideal B-C saturation current A 0.0

ISP Transport saturation current of the para-sitic device

A 0.0

IBEIP Ideal B-E saturation current of the parasitic device

A 0.0

IBENP Non-ideal B-E saturation current of the par-asitic device

A 0.0

IBCIP Ideal B-C saturation current of the parasitic device

A 0.0

IBCNP Non-ideal B-C saturation current of the par-asitic device

A 0.0

Emission Coefficient Parameters


NF Forward emission coefficient - 1.0

NR Reverse emission coefficient - 1.0

NEI Ideal B-E emission coefficient - 1.0

NEN Non-ideal B-E emission coefficient - 2.0

NCI Ideal B-C emission coefficient - 1.0

General Parameters




NCN Non-ideal B-C emission coefficient - 2.0

NFP Forward emission coefficient of the parasitic device

- 1.0

NCIP Ideal B-C emission coefficient of the parasitic device

- 1.0

NCNP Non-ideal B-C emission coefficient of the para-sitic device

- 2.0

Partioning Parameters


WBE Portion of IBEI from Vbei, 1-WBE from Vbex

- 1.0

WSP Portion of ICCP from Vbep, 1-WSP from Vbci

- 1.0

High Current Beta Degradation Effect Parameters


IKF Forward knee current A 0.0

IKR Reverse knee current A 0.0

NKF High current roll-off coefficient (v1.2) - 0.5

IKP Parasitic knee current A 0.0

Early Voltage Parameters


VEF Forward Early voltage V 0.0

VER Reverse Early voltage V 0.0

Emission Coefficient Parameters




Weak Avalanche Parameters


AVC1 B-C weak avalanche parameter 1 - 0.0

AVC2 B-C weak avalanche parameter 2 - 0.0

Resistance Parameters


RCX Extrinsic collector resistance 0.0

RCI Intrinsic collector resistance 0.0

RBX Extrinsic base resistance 0.0

RBI Intrinsic base resistance 0.0


RS Substrate resistance 0.0

RBP Parasitic base resistance 0.0

RTH Thermal resistance of device. K/W 0

XRT Exponent for RTH temperature dependence.

- 0

Overlap Capacitance Parameters


CBEO Extrinsic B-E overlap capacitance F 0.0

CBCO Extrinsic B-C overlap capacitance F 0.0

CCSO Fixed C-S capacitance (v1.2) F 0.0

Junction Capacitance Parameters


FC Forward bias depletion capacitance limit - 0.9

CJE B-E zero bias capacitance F 0.0

PE B-E built-in potential V 0.75

Ω

Ω

Ω

Ω

Ω

Ω

Ω



ME B-E grading coefficient - 0.33

AJE B-E capacitance smoothing factor - -0.5

CJC B-C intrinsic zero bias capacitance F 0.0

CJEP B-C extrinsic zero bias capacitance F 0.0

PC B-C built-in potential V 0.75

MC B-C grading coefficient - 0.33

AJC B-C capacitance smoothing factor - -0.5

VRT B-C capacitance limiting voltage (v1.2) V 0.0

ART B-C capacitance limiting smoothing fac-tor (v1.2)

V 0.1

CJCP S-C zero bias capacitance F 0.0

PS S-C built-in potential V 0.75

MS S-C grading coefficient - 0.33

AJS S-C capacitance smoothing factor - -0.5

CTH Thermal capacitance of device. K/J 0

Epilayer Parameters


VO Epi drift saturation voltage V 0.0

GAMM Epi doping parameter - 0.0

HRCF High current RC factor - 1.0

QCO Epi charge parameter - 0.0

Transit Time and Excess Phase Parameters


TF Forward transit time s 0.0

QTF Variation of TF with base-width modulation - 0.0

XTF Coefficient of TF bias dependence - 0.0

Junction Capacitance Parameters




VTF Coefficient of TF dependence on Vbc - 0.0

ITF Coefficient of TF dependence on Ic - 0.0

TR Reverse transit time s 0.0

TD Forward excess-phase delay time s 0.0



TNOM Nominal temperature (model parameter mea-surement temperature)

C 27

DTMAX Maximum temperature rise above heatsink. K 1000

XRE Temperature exponent of RE - 0.0

XRB Temperature exponent of RBI and RBX (v1.1.5)Temperature exponent of RBI (v1.2)

- 0.0

XRBX Temperature exponent of RBX (v1.2) - 0.0

XRC Temperature exponent of RCI and RCX (v1.1.5)Temperature exponent of RCI (v1.2)

- 0.0

XRCX Temperature exponent of RCX (v1.2) - 0.0

XRBP Temperature exponent of RBP (v1.2) - 0.0

XRS Temperature exponent of RS - 0.0

XVO Temperature exponent of VO - 0.0

EA Activation energy for IS V 1.12

DEAR Activation energy shift for ISRR (v1.2) V 0.0

EAP Activation energy for ISP (v1.2) V 1.12

EAIE Activation energy for IBEI V 1.12

EAIC Activation energy for IBCI/IBEIP V 1.12

EAIS Activation energy for IBCIP V 1.12

EANE Activation energy for IBEN V 1.12

EANC Activation energy for IBCN/IBENP V 1.12

EANS Activation energy for IBCNP V 1.12

XIS Temperature exponent of IS - 3.0

Transit Time and Excess Phase Parameters


°



14.11.2: DC Current EquationsThe VBIC expressions of base and collector currents are similar to SGP equations. The base current is divided into base-emitter and base-collector components.

It is assumed that geometry and/or temperature scaled values of model parameters are used in the following expressions.

XIKF Temperature exponent of IKF (v1.2) - 0.0

XISR Temperature exponent of ISRR (v1.2) - 0.0

XII Temperature exponent of IBEI/IBCI/IBEIP/IBCIP

- 3.0

XIN Temperature exponent of IBEN/IBCN/IBENP/IBCNP

- 3.0

TNF Temperature coefficient of NF - 0.0

TAVC Temperature coefficient of AVC2 - 0.0

TVBBE1 First temperature coefficient of VBBE (v1.2) 0.0

TVBBE2 Second temperature coefficient of VBBE (v1.2) 0.0

TNBBE Temperature coefficient of NBBE (v1.2) 0.0

Noise Parameters


KFN B-E flicker noise constant - 0.0

AFN B-E flicker noise exponent - 1.0

BFN B-E flicker noise 1/f dependence - 1.0

Base-Emitter Tunneling Parameters


IBBE B-E breakdown current (v1.2) A 1.0e-6

NBBE B-E breakdown emission coefficient (v1.2) - 1.0

VBBE B-E breakdown voltage (v1.2) V 0.0



V K 1–⋅

V K 2–⋅

K 1–



Define the branch voltages used in equations below:

Vbei = v(bi) - v(ei)

Vbex = v(bx) - v(ei)

Vbci = v(bi) - v(ci)

Vbcx = v(bi) - v(cx)

Vrci = v(cx) - v(ci)

Vrbi = v(bx) - v(bi)

Vbep = v(bx) - v(bp)

Vbcp = v(si) - v(bp)

Vrbp = v(cx) - v(bp)

Collector Current Contributions

The VBIC (zero excess phase) forward and reverse transport currents are:

and

where:

and are forward and reverse ideal currents and qb is the normalized base charge calculated as a function of applied bias.

Ideal Forward and Reverse Currents

The expression of ideal reverse current has been modified to account for a separate saturation current IS in reverse operation (HBTs).

(v1.1.5)

or

(v1.2)

Parameters: IS, ISSR (v1.2), NF, NR.

Base Charge

(v1.1.5)

with:

Itzf Itfiqb---------= Itzr Itri

qb----------=

Itfi Itri

Itfi IS VbeiNF Vtd⋅------------------------

exp 1.0– ⋅=

Itri IS VbciNR Vtd⋅------------------------

exp 1.0– ⋅=

Itri IS ISSR VbciNR Vtd⋅------------------------

exp 1.0– ⋅ ⋅=

qb q12

------q12 4 q2⋅+

2---------------------------------+=



(a zero value means infinity for VER and VEF)

(a zero value means infinity for IKR and IKF)

qdbe and qdbc are the normalized depletion charges.

if: (QBM < 0.5)

else,

(SGP)

Transport Current and Base Charge of the Parasitic Device

where:

(a zero value means infinity for IKP)

Parameters: ISP, WSP, NFP, IKP.

Currents in Modulated Resistors

The following currents are computed only if corresponding model parameters RBI, RCI and RBP have non-zero values (negative values are considered as zero). Otherwise, internal related nodes simply collapse.

Define:

q1 1.0qdbeVER--------------

qdbcVEF-------------+ +=

q2ItfiIKR------------

ItriIKF-----------+=

qb q12

------

q1

1.0NKF--------------

4 q2⋅+

NKF

2-----------------------------------------------------+=

qb q12

------ 1.0 1.0 4.0 q2⋅+( )NKF+[ ]⋅=

Iccp Itfp Itrp–qbp

-----------------------------=

Itfp ISP WSP VbepNFP Vtd⋅----------------------------

exp⋅ 1.0 WSP–( ) VbciNFP Vtd⋅----------------------------

exp⋅ 1.0–+ ⋅=

Itrp ISP VbcpNFP Vtd⋅----------------------------

exp 1.0– ⋅=

qbp 12---

1 4 q2p⋅+2

-------------------------------+=

q2p ItfpIKP-----------=

Kbci1.0 GAMM Vbci

Vtd-------------

exp⋅+ RCI 0.0>

0.0 RCI 0.0≤

=



Parameters: RCI, GAMM.

The intrinsic collector current is modeled with the enhanced Kull quasi-saturation model:

where:

with

VO and HRCF are model parameters for which a zero value means infinity.

A simple qb modulation model is used and leads to:

Parameter: RBI

A similar expression is used to model the qbp modulation in parasitic device:

Parameter: RBP

Intrinsic and Extrinsic Base-Emitter Current

The base-emitter current is partitioned between intrinsic and extrinsic contributions to account for the distributed nature of the base.

Parameters: WBE, IBEI, NEI, IBEN, NEN.

Base-Emitter Breakdown Current

In v1.2, a simple exponential model has been introduced to account for the base-emitter tunneling effect. New contributions, noted Ibebk and Ibexbk, are added to the intrinsic and extrinsic base-emitter currents Ibe and Ibex, respectively.

If: VBBE > 0.0

Kbcx1.0 GAMM Vbcx

Vtd--------------

exp⋅+ RCI 0.0>

0.0 RCI 0.0≤

=

Irci Iohm

1.0 derf2+--------------------------------=

Iohm Vrci Vtd Kbci Kbcx– rKp1( )log–( )⋅+RCI

-----------------------------------------------------------------------------------------------------------= rKp1Kbci 1.0+Kbcx 1.0+----------------------------=

derf RCI Iohm⋅

VO Vrci2 0.01+2.0 HRCF⋅

------------------------------------+

----------------------------------------------------=

Irbi Vrbi qb⋅RBI

------------------------=

Irbp Vrbp qbp⋅RBP

------------------------------=

Ibe WBE IBEI VbeiNEI Vtd⋅---------------------------

exp 1.0– ⋅ IBEN Vbei

NEN Vtd⋅------------------------------

exp 1.0– ⋅+⋅=

Ibex 1.0 WBE–( ) IBEI VbexNEI Vtd⋅---------------------------

exp 1.0– ⋅ IBEN Vbex

NEN Vtd⋅------------------------------

exp 1.0– ⋅+⋅=



(v1.2 only)

(v1.2 only)

else,

(v1.2 only)

(v1.2 only)

Parameters: WBE, IBBE (v1.2), NBBE (v1.2), VBBE (v1.2) and EBBE (v1.2).

Intrinsic Base-Collector Current

Parameters: IBCI, NCI, IBCN, NCN.

Base-Collector Weak Avalanche Current

If , a weak avalanche contribution is calculated and added to the base-collector current.

where:

Parameters: PC, MC, AVC1, AVC2.

Base-Emitter Current of the Parasitic Device

Parameters: IBEIP, NCI, IBENP, NCN.

Base-Collector Current of the Parasitic Device

Parameters: IBCIP, NCIP, IBCNP, NCNP.

Ibebk WBE IBBE VBBE– Vbei–NBBE Vtd⋅

------------------------------------------ exp EBBE–

⋅ ⋅–=

Ibexbk 1.0 WBE–( ) IBBE VBBE– Vbex–NBBE Vtd⋅

------------------------------------------- exp EBBE–

⋅ ⋅–=

Ibebk 0.0=

Ibexbk 0.0=

Ibc IBCI VbciNCI Vtd⋅---------------------------

exp 1.0– ⋅ IBCN Vbci

NCN Vtd⋅------------------------------ exp 1.0–

⋅+=

AVC1 0>

Igc Itzf Itzr– Ibc–( ) avalm⋅=

avalm AVC1 vl AVC2– vlMC 1.0–⋅( )exp⋅ ⋅=

vl PC Vbci–( )2 0.01+ PC Vbci–+2

------------------------------------------------------------------------------------------=

Ibep IBEIP VbepNCI Vtd⋅---------------------------

exp 1.0– ⋅ IBENP Vbep

NCN Vtd⋅------------------------------

exp 1.0– ⋅+=

Ibcp IBCIP VbcpNCIP Vtd⋅--------------------------------

exp 1.0– ⋅ IBCNP Vbcp

NCNP Vtd⋅----------------------------------

exp 1.0– ⋅+=



14.11.3: Charge and Capacitance Equations

Normalized Junction Depletion Charge

VBIC has two depletion charge models: the standard Gummel-Poon model and a single-piece model for which the capacitance is smoothly limited to a constant value for a forward biased junction.

In v1.2, new equations (and model parameters) have been added to account for reach-through limiting effect in the base-collector junction. These equations are used to evaluate normalized base-collector depletion charges qdbc and qdbep if the value of VRT is greater than zero. This effect is not accounted for in the calculation of qdbe and qdbex.

It is important to notice that the expressions of vl and vl0 are different in v1.2. The smoothing factor is 4*AJ*AJ, where AJ is expressed in volts.

Standard Gummel-Poon model

If the smoothing coefficient AJx (x=C,E or S) is less than or equal to zero, the regional depletion capacitance model is used to compute depletion charges.

Define

where:

V is the junction applied voltage,

Px (x=C,E or S) is the junction built-in potential and

FC is the forward bias depletion capacitance limit.

If:

else, if and (reach-through limiting)

(v1.2 only)

else,

where:

Mx (x=C,E or S) is the junction grading coefficient.

Single piece model

If the smoothing coefficient AJx (x=C,E or S) is positive, the single piece depletion capacitance model is used to compute depletion charges.

If and (reach-through limiting)

Define:

dvh V FC Px⋅–=

dvh 0.0>

qj Px 1.0 1.0 FC–( )1.0 Mx––1.0 Mx–

--------------------------------------------------------⋅ dvh1.0 FC dvh Mx⋅

2.0 Px⋅------------------------+–

1.0 FC–( )1.0 Mx+-----------------------------------------------------⋅+=

VRT 0.0> V VRT–<

qj Px1.0 Mx–---------------------- 1.0 1.0

VRTPx

-------------+ 1.0 Mx–

1.01.0 Mx–( ) V VRT+( )⋅

Px VRT+-------------------------------------------------------------–

⋅–⋅=

qj Px1.0 1.0

VPx-------–

1.0 Mx––

1.0 Mx–--------------------------------------------------------⋅=

VRT 0.0> ART 0.0>

dv0 FC– Px⋅=



(v1.2 only)

(v1.2 only)

(v1.2 only)

(v1.2 only)

(v1.2 only)

(v1.2 only)

(v1.2 only)

(v1.2 only)

(v1.2 only)

(v1.2 only)

(v1.2 only)

else,

Define:

(v1.1.5)

or:

(v1.2)

and:

(v1.1.5)

or:

(v1.2)

the depletion charge can be expressed by:

Parameters: AJx, Px, Mx (x=C,E or S), FC, VRT (v1.2), ART (v1.2).

vn0VRT dv0+VRT dv0–------------------------------=

vnl0 2 vn0⋅

vn0 1.0–( )24 AJx

2⋅+ vn0 1.0+( )24 ART2⋅++

----------------------------------------------------------------------------------------------------------------------------------------------=

vl0 0.5 vnl0 VRT dv0–( )⋅ VRT– dv0–( )⋅=

vn 2.0 V⋅ VRT dv0+ +VRT dv0–

----------------------------------------------------=

vnl 2 vn⋅

vn 1.0–( )24 AJx

2⋅+ vn 1.0+( )24 ART2⋅++

----------------------------------------------------------------------------------------------------------------------------------------=

vl0 0.5 vnl VRT dv0–( )⋅ VRT– dv0–( )⋅=

sel 0.5 vnl 1.0+( )⋅=

crt 1.0 VRTPx

-----------+ Mx–

=

cmx 1.0 FC–( ) Mx–=

cl 1.0 sel–( ) crt⋅ sel cmx⋅+=

qj Px1.0

vlPx-------–

1.0 Mx–

1.0 Mx–-------------------------------------------⋅ Px

1.0vl0Px--------–

1.0 Mx–

1.0 Mx–--------------------------------------------⋅– V vl– vl0+( ) cl⋅+=

vl 0.5 V FC Px⋅– V FC Px⋅–( )2 AJx+–( )⋅ FC Px⋅+=

vl 0.5 V FC Px⋅– V FC Px⋅–( )2 4 AJx2⋅+–( )⋅ FC Px⋅+=

vl0 0.5 FC Px⋅– FC Px⋅–( )2 AJx+–( )⋅ FC Px⋅+=

vl0 0.5 FC Px⋅– FC Px⋅–( )2 4 AJx2⋅+–( )⋅ FC Px⋅+=

qj Px–

1.0vlPx-------–

1.0 Mx–

1.0 Mx–-------------------------------------------⋅ V vl vl0+–

1.0 FC–( )Mx--------------------------------- Px

1.0vl0Px--------–

1.0 Mx–

1.0 Mx–--------------------------------------------⋅+ +=



Base-Emitter Charge

The base-emitter charge is partitioned between Qbe and Qbex.

Qbe contains also a diffusion charge component.

qdbe is the normalized depletion charge calculated using the algorithm described above:

tff is the forward transit time modeled as:

that reduces to:

if

Parameters: CJE, WBE, PE, ME, FC, AJE, TF, QTF, XTF, ITF (a zero value for ITF means infinity).

qdbex is the normalized depletion charge calculated using the algorithm described above:

Parameters: CJE, WBE, PE, ME, FC, AJE.

Base-Collector Charge

The intrinsic base-collector charge Qbc contains contributions of depletion and diffusion charges. As the extrinsic charge Qbcx, it also includes a term corresponding to the charge associated with the base pushout into the collector.

The intrinsic base-collector charge is

qdbc is the normalized depletion charge calculated using the algorithm described above:

Parameters: CJC, TR, QC0, PC, MC, FC, AJC.

The extrinsic base-collector charge is

Parameter: QC0.

Base-Emitter Charge of the Parasitic Device

qdbep is the normalized depletion charge calculated using the algorithm described above:

Qbe CJE qdbe WBE⋅ ⋅ tff Itzf⋅+=

qdbe qj Vbei PE ME FC AJE, , , ,( )=

tff TF 1.0 QTF q1⋅+( ) 1.0 XTF Vbci1.44 VTF⋅----------------------------

expItfi

Itfi ITF+---------------------------

2

⋅ ⋅+ ⋅ ⋅=

tff TF 1.0 QTF q1⋅+( )⋅= Itfi 0.0≤

Qbex CJE qdbex 1.0 WBE–( )⋅ ⋅=

qdbex qj Vbex PE ME FC AJE, , , ,( )=

Qbc CJC qdbc⋅ TR Itri⋅ QC0 Kbci⋅+ +=

qdbc qj Vbci PC MC FC AJC, , , ,( )=

Qbcx QC0 Kbcx⋅=

Qbep CJEP qdbep⋅ TR Itfp⋅+=

qdbep qj Vbep PC MC FC AJC, , , ,( )=



Parameters: CJEP, TR, PC, MC, FC and AJC.

Base-Collector Charge of the Parasitic Device

or:

The contribution of the fixed capacitance CCSO is added to the total base-collector charge.

qdbcp is the normalized depletion charge calculated using the algorithm described above:

Temperature dependence of thermal resistance

TNOM is the temperature at which the model parameters have been extracted. T corresponds to the dynamic temperature Td if self-heating is turned on. Otherwise, T corresponds to the operating temperature. The capacitance Cth is assumed to be temperature indepdendent.

14.11.4: Excess Phase NetworkIf the excess phase delay TD is set to a positive value then an internal network is created (nodes xf1 and xf2). The capacitance and inductance values are set to TD and TD/3 respectively and the value of the current source is set to Itzf. Finally, the collector current is calculated using the resulting current Itxf induced in the inductor.

14.11.5: Temperature ScalingTemperature effects are presented using the device temperature dynamically calculated during

iterations. If the self-heating calculation is not turned on is not taken into account in temperature

scaling and the device operating temperature is used instead.

The following abbreviations are defined for convenience:

and

Parasitic Resistors

Qbcp CJCP qdbcp⋅=

Qbcp CJCP qdbcp CCSO Vbcp⋅+⋅=

qdbcp qj Vbcp PS MS FC AJS, , , ,( )=

RTH T( ) RTH TTNOM--------------------

XRT⋅=

Icc Itxf Itzr–=

Td

Td

Top

Vtdkq--- Td⋅= Vtnom

kq--- Tnom⋅= rtd

Td

Tnom-------------=

RCX Td( ) RCX rtd( )XRC⋅=

RCI Td( ) RCI rtd( )XRC⋅=



(v1.1.5)

Saturation Currents

(v1.2 only)

RBX Td( ) RBX rtd( )XRB⋅=

RBI Td( ) RBI rtd( )XRB⋅=

RE Td( ) RE rtd( )XRE⋅=

RS Td( ) RS rtd( )XRS⋅=

RBP Td( ) RBP rtd( )XRC⋅=

IS Td( ) IS rtd( )XISNF----------- EA

NF---------–

1.0 rtd–

Vtd--------------------⋅

exp⋅ ⋅=

ISP Td( ) ISP rtd( )XISNFP------------- EA

NFP-------------–

1.0 rtd–

Vtd--------------------⋅

exp⋅ ⋅=

IKF Td( ) IKF rtd( )XIKF⋅=

ISRR Td( ) ISRR rtd( )XISRNR

---------------- DEARNR

------------------–1.0 rtd–

Vtd--------------------⋅

exp⋅ ⋅=

IBEI Td( ) IBEI rtd( )XIINEI------------ EAIE

NEI----------------–

1.0 rtd–

Vtd--------------------⋅

exp⋅ ⋅=

IBEN Td( ) IBEN rtd( )XINNEN--------------- EANE

NEN------------------–

1.0 rtd–

Vtd--------------------⋅

exp⋅ ⋅=

IBCI Td( ) IBCI rtd( )XIINCI------------ EAIC

NCI----------------–

1.0 rtd–

Vtd--------------------⋅

exp⋅ ⋅=

IBCN Td( ) IBCN rtd( )XINNCN--------------- EANC

NCN------------------–

1.0 rtd–

Vtd--------------------⋅

exp⋅ ⋅=

IBEIP Td( ) IBEIP rtd( )XIINCI------------ EAIC

NCI----------------–

1.0 rtd–

Vtd--------------------⋅

exp⋅ ⋅=

IBENP Td( ) IBENP rtd( )XINNCN--------------- EANC

NCN------------------–

1.0 rtd–

Vtd--------------------⋅

exp⋅ ⋅=

IBCIP Td( ) IBCIP rtd( )XII

NCIP----------------- EAIS

NCIP----------------–

1.0 rtd–

Vtd--------------------⋅

exp⋅ ⋅=

IBCNP Td( ) IBCNP rtd( )XIN

NCNP------------------- EANS

NCNP-------------------–

1.0 rtd–

Vtd--------------------⋅

exp⋅ ⋅=

VBBE Td( ) VBBE 1.0 TVBBE1 Td Tnom–( )⋅ TVBBE2 Td Tnom–( )2⋅+ +( )⋅=



Non-Ideality Factors and Weak Avalanche Model Parameters

Built-in Potentials

PE, PC and PS are scaled using the corresponding parameters EAIE, EAIC, EAIS, and the following algorithm (Px means PE, PC, or PS and EAIx means EAIE, EAIC, or EAIS).

where:

In v1.2, the expression psiio has been updated and reads now:

However the original expression is maintained when invoking:

Zero-Bias Capacitances

NBBE Td( ) NBBE 1.0 TNBBE Td Tnom–( )⋅+( )⋅=

EBBE Td( )VBBE Td( )

NBBE Td( ) Vtd⋅--------------------------------------------–

exp=

NF Td( ) NF 1.0 TNF Td Tnom–( )⋅+( )⋅=

NR Td( ) NR 1.0 TNF Td Tnom–( )⋅+( )⋅=

AVC2 Td( ) AVC2 1.0 TAVC Td Tnom–( )⋅+( )⋅=

Px Td( ) psiin 2.0 Vtd

1.0 1.0 4.0psiinVtd

---------------– exp⋅++

2.0-----------------------------------------------------------------------------

log⋅ ⋅+=

psiin psiio rtd⋅ 3.0 Vtd rtd( )log⋅ ⋅ EAIx rtd 1.0–( )⋅––=

psiio 2.0 VtnomPx

2.0 Vtnom⋅---------------------------

expPx

2.0 Vtnom⋅---------------------------–

exp– log⋅ ⋅=

psiio 2.0 VtdPx

2.0 Vtd⋅--------------------

expPx

2.0 Vtd⋅--------------------–

exp– log⋅ ⋅=

CJE Td( ) CJE PEPE Td( )--------------------

ME⋅=

CJC Td( ) CJC PCPC Td( )--------------------

MC⋅=

CJEP Td( ) CJEP PCPC Td( )--------------------

MC⋅=

CJCP Td( ) CJCP PSPS Td( )-------------------

MS⋅=



Epilayer Parameters

One can download Silvaco’s Verilog-A implementation of the VBIC Model at www.silvaco.com.

GAMM Td( ) GAMM rtd( )XIS EA–1.0 rtd–

Vtd--------------------⋅

exp⋅ ⋅=

VO Td( ) VO rtd( )XVO⋅=



14.12: Interfacing Verilog-A Compact Model Code to the Input DeckVERILOG-A models are identified by the YVLG prefix followed by the device name (e.g., YVLGmodel_name). The model_name.va file must also be referenced within the SPICE deck.

Syntax

.VERILOG "model_name.va" YVLGmodel_name < ports> params

14.13: .MODEL Card.Model cards are required in all spice decks containing YVLG modules, and supports external parameter settings.

Syntax

.VERILOG "model_name.va" YVLGmodel_name < ports> params

* Define the model card for the model_name module.MODEL params VLG MODULE = model_name + L = 10E-6, W = 20E-6 *** Process Related Model Parameters+ COX = 3.45E-3+ XJ = 0.15E-6*** Intrinsic Model Parameters+ VTO = 0.6+ GAMMA = 0.71+ PHI = 0.97+ KP = 150E-6+ E0 = 88.0E6+ UCRIT = 4.5E6+ DL = -0.05E-6+ DW = -0.02E-6+ LAMBDA = 0.23+ LETA = 0.28+ WETA = 0.05+ Q0 = 280E-6+ LK = 0.5E-6*** Substrate Current Parameters+ IBN = 1.0+ IBA = 200E6+ IBB = 350E6*** Intrinsic Model Temperature Parameters+ TNOM = 25.0+ TCV = 1.5E-3+ BEX = -1.5+ UCEX = 1.7+ IBBT = 0.0*** 1/f Noise Model Parameters+ KF = 1E-27+ AF = 1+ TYPE=1



The complete SPICE deck for a DC analysis of a VERILOG-A implemented EKV model with extrinsic capacitance is shown below.

14.14: Compiling Verilog-A Compact ModelsThe Silvaco VERILOG-A gives one the ability to compile the custom models developed by using VERILOG-Awith the native host C compiler. Since the VERILOG-A code accepted by the Interpreter is ANSI C, it can be compiled by using any C compiler. Compiled VERILOG-A models using the host C compiler will provide the fastest execution speed once a model has been fully developed within SMARTSPICE VERILOG-Aframework. Once this is performed, the provided models.c file should be modified (as described below) and the library libsmart.so should be built by using the provided Makefile.

Finally, the environment variable, LD_LIBRARY_PATH, should be set to reference the location of the file (libsmart).

14.15: Interfacing Verilog-A Compact Model Code to a Schematic SymbolCreate a symbol as specified within the SCHOLAR USER’S MANUAL. Using the SYMBOL EDITOR, press the SMARTSPICE button to access the SMART SPICE STRING EDITOR. Within this window, type the following string:

YVLGmodel_name @Path %P1 %P2 %P3…..%Pn <ParamsID> param1=@param1 param2=@param2 paramn=@paramn

Where %Pn represents pin names and paramn=@paramn allows values for paramn to be entered from the schematic.

The SPICE deck must contain the following:

.VERILOG "model_name.va"

and the

.MODEL ParamsID VLG MODULE = model_name *** Process Related Model Parameters+ COX = 3.45E-3+ XJ = 0.15E-6.....



14.16: Declaring Verilog-A Modules Within a SmartSpice Input DeckVERILOG-A modules can be used inside the input deck as following:

.verilog “file.va” name of the file that contains the Verilog-A module(s) that will be used within this input deck.

YVLGpart_name <port pins> module_name <parameter values> that is contained within file.va.

or

YVLGpart_name <port pins> model_card_ID_name

.MODEL model_card_ID_name VLG MODULE = module_name + <parameter values

Examples

*Spice deck no VLG Model Card

.verilog “resistor.va”

.verilog “inductor.va”

.verilog “capacitor.va”

*voltage sourcevin in 0 sin (0 5 10e06 0 0)

*SmartSpice Verilog-A module instantiantionYVLGres in 2 resistor r=200YVLGind 2 out inductor l=10uYVLGcap out 0 capacitor c=10p

.tran 1n 800n

.print v(in) v(out)

.end

or

*Spice deck with VLG Model Card

.verilog “resistor.va”

.verilog “inductor.va”

.verilog “capacitor.va”

*voltage sourcevin in 0 sin (0 5 10e06 0 0)

*SmartSpice Verilog-A module instantiantion



YVLGres in 2 paramsRYVLGind 2 out paramsLYVLGcap out 0 paramsC

*VLG model card.model paramsR VLG MODULE = resistor+ r = 200 $ optional, but it will override the first parameter..model paramsL VLG MODULE = inductor+ L = 10uh $ optional, but it will override the first parameter..model paramsC VLG MODULE = capacitor+ C = 10p $ optional, but it will override the first parameter.

.tran in 800n

.print v(in) v(out)

.end


Chapter 15:Verilog-A Examples

This chapter provides VERILOG-A examples from simple digital gates to complex behavioral models of a Phase Lock loop.

15.1: Digital circuitsThis section shows the following digital components, including primitive digital circuit components.

• Inverter• Buffer• Nand• Nor• Exor• DFF• Shift_registor• Counter

15.1.1: InverterFigure 15-1 shows the Inverter circuit symbol.

Figure 15-1: Inverter

Inverter behavior shows the following.

Logic Table

We can write VERILOG-A for inverter as such (inv.in):

‘Include "discipline.h"module inv(in, out); input in; output out;

IN OUT10

in out



electrical in,out;

parameter real vout_high = 5;parameter real vout_low = 0;parameter real vth = 2.5;parameter real tdelay = 5n; //propagation delayparameter real trise = 8.5n; //rise timeparameter real tfall = 10n; //fall timereal Val; analog begin @( initial_step ) begin // initial condition if ( V(in) > vth ) val = vout_low; else val = vout_high; end @( cross( V(in) - vth, +1) ) val = vout_low; // Vin>vth => vout_low @( cross( V(in) - vth, -1) ) val = vout_high; // Vin<vth => vout_high

V(out) <+ transition( val,tdelay,trise,tfall ); end

endmodule

Figure 15-2: Inverter Simulation Result

A Spice inputdeck can be described as the following (inv.va):

*----LOGIC ( inverter ) Circuit-----**.verilog "inv.va".options post probe iplot_one numdgt=10+ accuratev01 vcc 0 dc 5v02 in 0 pulse(0 5 1u 1n 1n 1u 2u)*YVLG_NOT in out inv.tran 1n 10u.iplot v(in)+ ’v(out)+10’.probe all.end


Verilog-A Examples

15.1.2: BufferFigure 15-3 is the Buffer circuit symbol.

Figure 15-3: Buffer

Buffer behavior shows the following.

Logic Table

We can write VERILOG-A for buffer as such (buff.va):


module inv(in,out); input in; output out; electrical in,out;

parameter real vout_high = 5;parameter real vout_low = 0;parameter real vth = 2.5;parameter real tdelay = 5; // propagation delay timeparameter real trise = 8.5n; // rise timeparameter real tfall = 11n; // fall timereal val; analog begin @( initial_step ) begin // initial condition if ( V(in) > vth ) val = vout_low; else val = vout_high; end @( cross( V(in) - vth, +1) ) val = vout_low; // Vin>vth => vout_low @( cross( V(in) - vth, -1) ) val = vout_high; // Vin<vth => vout_high

V(out) <+ transition( val,tdelay,trise,tfall ); end

endmodule

IN OUT0 01 1



Figure 15-4: Buffer Simulation Result

The Spice inputdeck describes the following (buf.in):

*----LOGIC ( Buffer ) Circuit-----**.verilog "buffer.va".options post probe iplot_one numdgt=10+ accuratev01 vcc 0 dc 5v02 in 0 pulse(0 5 1u 1n 1n 1u 2u)*YVLG_buf in out buffer.tran 1n 10u.iplot v(in)+ ’v(out)+10’.probe all.end

15.1.3: NandFigure 15-5 is a well known Nand circuit symbol.

Figure 15-5: Input Nand Circuit

2-input Nand behavior shows the following.

in1

in2

out


Verilog-A Examples

Logic Table

We can describe this as the following (nand.va)

‘include "discipline.h"module dnand(in,out);

parameter real size = 2 from [2:inf), vout_high = 5, vout_low = 0 from (-inf:vout_high), vth = 2.5, tdelay = 5n from [0:inf), trise = 10n from [0:inf), tfall =12n from [0:inf);

input [0:size-1] in; output out; voltage in,out;

integer in_state[0:size-1],i; integer out_state; real vout;

analog begin @(initial_step) for(i=0;i<size;i=i+1) in_state[i]=0;

generate i (0,size-1) begin @(cross(V(in[i]) - vth)) begin in_state[i] = V(in[i]) > vth; out_state = 1; for (i=0;i<size;i=i+1) if (!(out_state && in_state[i])) out_state = 0; if (out_state) vout = vout_low; // inversion of output else vout = vout_high; end end

V(out) <+ transition(vout,tdelay,trise,tfall); endendmodule

IN1 IN2 Out0 0 10 1 11 0 11 1 0



Figure 15-6: 2 - Input Nand Simulation Result

Spice inputdeck show the following(nand.in).

*----LOGIC ( NAND ) Circuit-----**.verilog "nand.va".options iplot_one

v01 in1 0 pulse(0 5 0u 1n 1n 1u 2u)v02 in2 0 pulse(0 5 1u 1n 1n 2u 4u)

YVLG_nand in1 in2 out nand

.tran 1n 40u

.iplot v(in1)+ ’v(in2)+10’+ ’v(out)+20’.probe all.end

The number of input is limited by size, so if you want more input, you had better set "size = number" as is needed.

Example

If you want 4 input nand,

‘include "discipline.h"module dnand(in,out); you don’t need change

parameter real size = 4 from [4:inf), you must change from 2 to 4

The Spice inputdeck is described: (4nand.in)

*----LOGIC ( 4 input NAND ) Circuit-----**.verilog "nand.va"


Verilog-A Examples

.options iplot_one

v01 in1 0 pulse(0 5 0u 1n 1n 1u 2u)v02 in2 0 pulse(0 5 1u 1n 1n 2u 4u)v03 in3 0 pulse(0 5 0u 1n 1n 4u 8u)v04 in4 0 pulse(0 5 1u 1n 1n 8u 16u)

YVLG_nand in4 in3 in2 in1 out nand size=4.tran 1n 40u

.iplot v(in1)+ ’v(in2)+10’+ ’v(in3)+20’+ ’v(in4)+30’+ ’v(out)+40’.probe all.end

Figure 15-7: 4 - Input Nand Simulation result

15.1.4: NORFigure 15-8 is a well known 2 input NOR circuit.

Figure 15-8: 2-Input NOR

2-input NOR circuit behavior shows the following LOGIC Table.

In1

in2

out



Logic Table

This circuit is described as the following (nor.va):

‘include "discipline.h"module dnor(in,out);

parameter real size = 2 from [2:inf), vout_high = 5, vout_low = 0 from (-inf:vout_high), vth = 2.5, tdelay = 5n from [0:inf), trise = 10n from [0:inf), tfall = 10n from [0:inf);

input [0:size-1] in; output out; voltage in,out;

integer in_state[0:size-1],i; integer out_state; real vout;

analog begin @(initial_step) for(i=0;i<size;i=i+1) in_state[i]=0;

generate i (0,size-1) begin @(cross(V(in[i]) - vth)) begin in_state[i] = V(in[i]) > vth; out_state = 0; for (i=0;i<size;i=i+1) if (in_state[i]) out_state = 1; if (out_state) vout = vout_low; else vout = vout_high; end end


IN1 IN2 Out0 0 10 1 01 0 01 1 0


Verilog-A Examples

Figure 15-9: 2- Input NOR Simulation Result

Spice inputdeck(nor.in):

*----LOGIC ( 2-Input NOR ) Circuit-----*.verilog "nor.va".option post probe iplot_one

v01 vcc 0 dc 5v02 in1 0 pulse(0 5 1u 1n 1n 1u 2u)v03 in2 0 pulse(0 5 2u 1n 1n 2u 4u)*YVLG_OR in1 in2 out dnor.tran 1n 20u.iplot v(in1)+’v(in2)+10’+’v(out)+20’.probe all.end

This example can also expand the number of input. If you want more (ex. the number is 3), change the VERILOG-A source and Spice inputdeck as follows.

Verilog-A source file (nor.va):

module dnor(in,out); you don’t need to changeparameter real size = 3 from [3:inf), you must change from 2 to 3

Spice inputdeck (3nor.in):

*----LOGIC ( 3-Input NOR ) Circuit-----*.verilog "nor.va"



.option post probe iplot_one

v01 in1 0 pulse(0 5 1u 1n 1n 1u 2u)v02 in2 0 pulse(0 5 2u 1n 1n 2u 4u)v03 in3 0 pulse(0 5 2u 1n 1n 4u 8u)

*YVLG_OR in1 in2 in3 out nor size=3.tran 1n 20u.iplot v(in1)+ ’v(in2)+10’+ ’v(in3)+20’+ ’v(out)+30’.probe all.end

Figure 15-10: 3-Input NOR Simulation Result

15.1.5: EXORFigure 15-11 is a well-known 2 input XOR circuit.

Figure 15-11: 2-Input XOR

2-input XOR circuit behavior show the following LOGIC Table.

in1

in2

out


Verilog-A Examples

Logic Table

This circuit is described as follows (xor.va).

Verilog-A Source file(xor.va):


module dxor(in,out);parameter real vh=5, vl=0, vth=1.5, tdelay=10n, trise=5n, tfall=5n;input [0:1] in;output out;voltage in,out;real vout;

analogbegin

if ( V(in[0])==V(in[1]) ) vout=vl; else vout=vh;

generate i (0,1) begin @(cross(V(in[i]) - vth)) begin if ( V(in[0])==V(in[1]) ) vout=vl; else vout=vh; end end


IN1 IN2 Out0 0 00 1 11 0 11 1 0



Figure 15-12: XOR Simulation Result

Spice inputdeck show the following(xor.in):

*----LOGIC ( 2-Input XOR ) Circuit-----**.verilog "xor.va".option post probe iplot_one method=gear

v01 vcc 0 dc 5v02 in1 0 pulse(0 5 1u 1n 1n 1u 2u)v03 in2 0 pulse(0 5 2u 1n 1n 2u 4u)*YVLG_OR in1 in2 out dxor.tran 10n 40u.iplotv(in1)+’v(in2)+10’+’v(out)+20’.probe all.end

15.1.6: DFF (D-type Flip Flop)Figure 15-13 is D type Flip Flop (RTL symbol)

Figure 15-13: D-Type Flip Flop

D

CLK Q

Q


Verilog-A Examples

Its behavior is shown in the following table.

Logic Table

VERILOG-A source file for DFF is described as follows:

Verilog-A source file(dff.va):


module vdff(q, qbar, clk, d); input clk,d; output q,qbar; voltage q, qbar, clk, d;

parameter real tdelay = 5n from [0:inf), ttransit = 5n from [0:inf), vout_high = 5, vout_low = 0 from (-inf:vout_high), vth= 2.5;

integer x; analog begin @(initial_step) x = 0;

@(cross(V(clk) - vth, +1 )) x = (V(d) > vth);

V(q) <+ transition( vout_high*x + vout_low*!x, tdelay, ttransit ); V(qbar) <+ transition( vout_high*!x + vout_low*x, tdelay, ttransit ); endendmodule

CLK D Q Q_bar0 0 0 10 1 0 11 1 1 0 (CLK:L - >H)1 0 0 1 (CLK:L - >H)



Figure 15-14: DFF Simulation Result

Spice inputdeck shows the following(dff.in):

*----LOGIC ( 4bit Shift Register ) Circuit-----**.verilog "dff.va".option post probe iplot_one

v02 d1 0 pwl(0 0 0.999u 0 1u 5 1.999u 5 2u 0 20u 0 R 0n)v03 clk 0 pulse(0 5 1u 1n 1n 2u 4u)*YVLGa_nd1 q1 q1b clk d1 VdffYVLGa_nd2 q2 q2b clk q1 VdffYVLGa_nd3 q3 q3b clk q2 VdffYVLGa_nd4 q4 q4b clk q3 Vdff

.tran 1n 50u*.probe all.let v1=’v(q1)+6’.let v2=’v(q2)+12’.let v3=’v(q3)+18’.let v4=’v(q4)+24’.iplot v(clk) v1 v2 v3 v4

.end


Verilog-A Examples

15.1.7: 4bit Shift RegisterFigure 15-15 4bit Shift_register is an example of using a DFF block This Shift Register is driven by Clock rise edge.

Figure 15-15: 4bitShift Resistor

Spice Inputdeck(4bit_shift_reg.in):

*----LOGIC ( 4bit Shift Register ) Circuit-----**.verilog "dff.va".option post probe iplot_one

v02 d1 0 pwl(0 0 0.999u 0 1u 5 1.999u 5 2u 0 20u 0 R 0n)v03 clk 0 pulse(0 5 1u 1n 1n 2u 4u)*YVLGa_nd1 q1 q1b clk d1 VdffYVLGa_nd2 q2 q2b clk q1 VdffYVLGa_nd3 q3 q3b clk q2 VdffYVLGa_nd4 q4 q4b clk q3 Vdff

.tran 1n 50u*.probe all.let v1=’v(q1)+6’.let v2=’v(q2)+12’.let v3=’v(q3)+18’.let v4=’v(q4)+24’.iplot v(clk) v1 v2 v3 v4

.end

D

CLK Q

Q D

CLK Q

Q D

CLK Q

Q D

CLK Q

Q

Q1 Q2 Q3

(sH

Data



Figure 15-16: 4bit Shift Resistor Simulation Result

15.1.8: 4bit Down CounterThe next example is a 4bit down counter using a DFF VERILOG-A module. 4bit down Counter spice netlist

Figure 15-17: 4bit Down Counter

4bit down counter netlist is shown as follows(4bit_counter.in).

Spice inputdeck(4bit_dcount.in):

*----LOGIC ( 4bit Down Counter ) Circuit-----**.verilog "dff.va".option post probe iplot_one

v01 d 0 pulse ( 0 5 5u 1n 1n 5u 10u)v02 clk 0 pulse(0 5 0u 1n 1n 2u 4u)*YVLGa_nd1 q1 d1 clk d1 VdffYVLGa_nd2 q2 d2 q1 d2 VdffYVLGa_nd3 q3 d3 q2 d3 VdffYVLGa_nd4 q4 d4 q3 d4 Vdff

.tran 1n 50u

D

CLK Q

Q

Q1

CL

D

CLK Q

Q

Q2

D

CLK Q

Q

Q3

D

CLK Q

CQ


Verilog-A Examples

.let v1=’v(q1)+10’

.let v2=’v(q2)+20’

.let v3=’v(q3)+30’

.let v4=’v(q4)+40’

.iplot v(clk) v1 v2 v3 v4

.probe all

.end

Figure 15-18: 4bit Down Counter Simulation Result

15.2: Analog FilterAnalog Filter is very important for analog Circuit design. In this section, we can learn basic filter description for VERILOG-A using transfer function.

This section describes the following filters.

• LPF: first order Low pass filter• HPF: first order High pass filter• BPF: first order Band pass filter

15.2.1: LPFLPF is called "differentialtor" (or differential circuit), as is shown as Figure 15-19.

Figure 15-19: RC Filter

Vin(t) Vout(t)

R



Transfer function for LPF is described in the following equation:

We can write this equation for VERILOG-A using Laplace function.

Laplace_nd means "n: numerator" and "d: dominator". The numerator of above transfer function is "1", and the dominator above transfer function are 1+(1/2pai*frq)*S

We can write:

laplace_nd(V(in), 1 , 1,1/(‘M_TWO_PI*freq_p1) )

See Figure 15-20 LPF characteristics.

*Freq_p1 is Cut off frequency.

Figure 15-20: LPF Characteristics

Verilog-A source file is the following (lpf.va):

‘include "discipline.h"‘include "Constants.h"

module lpf1(in,out); input in; output out; voltage in,out;

parameter real freq_p1 = 1M from (0:inf); analog V(out) <+ laplace_nd(V(in), 1 , 1,1/(‘M_TWO_PI*freq_p1) );

endmodule

H s( ) 11 1 2Π freq⁄( )S+---------------------------------------------=

Freq(Hz)

-3db


Verilog-A Examples

Spice inputdeck (lpf.in):

*----- Low pass filter -----*.verilog "lpf.va"

.option probe iplot_one

v01 in 0 2.5 ac 1YVLG_lpf in out lpfc01 out 0 1p.options use degrees .ac oct 10 1 1g

.let vdb=vdb(out)

.let vp=vp(out)

.iplot vdb

.end

Figure 15-21: LPF Simulation Results



15.2.2: HPFHPF can be described as an Integrate(C-R) circuit (see Figure 15-22).

Figure 15-22: Integrator

HPF also can be expressed by transfer function as the following.

We can write the above equation to VERILOG-A as follows:

laplace_nd(V(in), 0,1/(‘M_TWO_PI*freq_p1) , 1,1/(‘M_TWO_PI*freq_p1) )

Verilog-A source (hpf.va):


module hpf(in,out); input in; output out; voltage in,out;

parameter real freq_p1 = 1M from (0:inf);

analog V(out) <+ laplace_nd(V(in), 0,1/(‘M_TWO_PI*freq_p1) , 1,1/(‘M_TWO_PI*freq_p1) );

endmodule

Spice inputdeck (hpf.in):

*----- high pass filter -----*.verilog "hpf.va"

.option probe iplot_one

Vout(t)

R C

Vin(t)

Fig Error! No text of specified style in document..0.

H s( ) 1 2Π freq⁄( )S1 1 2Π freq⁄( )S+---------------------------------------------=


Verilog-A Examples

v01 in 0 2.5 ac 1YVLG_lpf in out hpf*c01 out 0 1p

.ac oct 10 1 1g

.let vdb=vdb(out)

.let vp=vp(out)

.iplot vdb*.iplot vp.end

Figure 15-23: HPF Simulation Result (freq v.s. gain)

15.2.3: BPFBPF can be described using LPF and HPF.

BPF characteristics are shown in Figure 15-24.

Figure 15-24: BPF Characteristics

Freq(Hz)

-3db

Frq_p1 Frq_p2



If the input signal Frequency is "f", then BPF behavior is shown as:

• f <Freq_p1: input signal can't through• Freq_p1 < f <Freq_p2: input signal can through• Freq_p2 < f: input signal can't through

BPF is described in two ways:

1. One is to describe it by the transfer function2. Or, description by LPF and HPF.

The later way can be described simply as the following

The former way is difficult unless you can understand transfer function.

BPF transfer function shows the following equation:

We can describe transfer function like the following using laplace function of VERILOG-A:

laplace_nd(V(in), 0,1/(‘M_TWO_PI*freq_p1) , 1,1/(‘M_TWO_PI*freq_p1),pow(1/(‘M_TWO_PI*freq_p2),2))

Verilog-A source (bpf.va):

‘include "discipline.h"module bpf(in,out); input in; output out; voltage in,out;

parameter real freq_p1 = 100k from (0:inf),freq_p2 = 1M from [freq_p1:inf);

analog V(out) <+ laplace_nd(V(in), 0,1/(‘M_TWO_PI*freq_p1) , 1,1/(‘M_TWO_PI*freq_p1),pow(1/(‘M_TWO_PI*freq_p2),2) );

endmodule

Spice inputdeck (bpf.in):

*----- band pass filter -----*.verilog "bpf.va"

.option probe iplot_one usedegrees=true

v01 in 0 2.5 ac 1YVLG_lpf in out bpfc01 out 0 1p

YVLG_LPF 2 IN LPFYVLG_HPF OUT 2 HPF

H s( ) 1 2Π freq⁄( )S1 1 2Π freq⁄( )S 1 2Π freq⁄( )S2+ +------------------------------------------------------------------------------------------=


Verilog-A Examples

.ac oct 10 10 1g

.let vdb=vdb(out)

.let vp=vp(out)

.iplot vdb

.end

Figure 15-25: BPF Characteristics

15.3: Analog CircuitThis section has analog circuit examples using VERILOG-A, although describing analog circuit behavior is difficult because the simple behavior is not the whole behavior of the analog circuit. If the user wants to describe VERILOG-A code for an analog circuit, one must know the analog specification and characteristics.

This section shows the following analog.

• Opamp• Sample hold • ADC• DAC• Delta-Sigma modulator

15.3.1: OPAMP (Operational Amplifier)Figure 15-26 is an example of an inverted operational amplifier (opamp). This opamp can be described in various ways. But, if the user wants to write this using VERILOG-A, the user must have a knowledge of the characteristics for opamp. Figure 15-26 opamp input is Vin, the output voltage is Vout, and Negative Feedback resistances are R1and R2.

This opamp gain shows the following equation:

We can also describe the following for Vout:

Gain R2R1-------=

Vout Vref–R2R1------- Vin Vref–( )×–=



Figure 15-26: Inverted Amplifier

In general, Vout is cramped by supply voltage, so we can describe this opamp using VERILOG-A.

Verilog-A source (amp.va):

// simple opamp‘include "descipline.h"module amp(in,out); input in; output out; electrical in,out;// parameter real gain=10;parameter avcc=5;//Analog supply voltage soruceparameter avss=0;//Analog ground referenceparameter vref=2.5;//input reference voltageparameter real R1=1k;//initial resistanceparameter real R2=1k;//initial resistancereal A,gain,vout;analog begin@(initial_step)begingain=R2/R1;A=-1*gain;//invert signalend vout=A*(V(in) - vref) + vref;if( vout > avcc ) vout=avcc;if( vout < avss ) vout=avss;

V(out) <+ vout; endendmodule


Verilog-A Examples

Spice inputdeck (opamp.in):

*---- ANALOG( OPAMP) Circuit-----**.verilog "amp.va".options iplot_one

v01 in 0 sin(2.5 0.1 1meg)

YVLG_amp in out amp R2=10k.tran 1n 10u

.iplot v(in) v(out)

.probe all

.end

As for the above Spice inputdeck, the amplitude of input signal is 0.1(V) and R2 is set to 10k, so Gain=R2/R1=10k/1k=10. We can expect Vout as 10 times of the INPUT signal voltage.

Running spice simulation above inputdeck by these conditions, we get Figure 15-27.

Figure 15-27: OPAMP Simulation Result



15.3.2: Sample holdAs for analog circuits design, sample hold circuit is used for various analog blocks. For example, ADC uses this to preserve input voltage (Vin).

A sample hold circuit is shown in Figure 15-28.

Figure 15-28: Sample Hold Circuit

Right Circuit behavior shows the following:

CLK: sampling clock signal

CLK=High, SW=ONCLK=LOW, SW OFF

In other words, when CLK is high at t, Vout(t) is Vin(t). When CLK changes high to low at t+dt, Vout(t+dt) is Vin(t)

We describe this using VERILOG-A:

Verilog-A source (sample_hold.va):

‘include "descipline.h"module sample_hold(in,out,clk); input in,clk; output out; voltage in,out,clk; parameter real clk_vth = 2.5; real v;

analog begin @(initial_step) v=V(in); if (analysis("static") || (V(clk) > clk_vth)) v = V(in); // passing phase @(cross(V(clk)-clk_vth,0)) v = V(in); // sampling phase V(out)<+v; endendmodule


Verilog-A Examples

Spice Inputdeck (shold.in):

*------ Sample Hold ----*.verilog "sample_hold.va".option probe iplot_onev01 in 0 sin(2.5 2.5 100k)v02 clk 0 pulse(0 5 0.2u 1n 1n 0.3u 0.6u)YVLG_sample_amp in out clk sample_hold c01 out 0 1p.probe all.iplot v(in) +v(clk)+’v(out)+10’.tran 1n 20u.end

Figure 15-29: Sample Hold Simulation Result



15.3.3: ADC (Pipelined ADC and user defined resolution)Analog to Digital Converter (ADC) is now used in various regions.

ADC behavior changes from analog signal to digital code with a resolution.

Analog signal input changes into 4bit digital code at the same time, and ADC is then called pipelined ADC.

As for Pipelined ADC, it is useful for Flash ADC.

Figure 15-30: *bit ADC Block

The ADC block has a sample hold circuit and a comparator. The Comparator compares input voltage with digital weighed (8bit).

Figure 15-31: ADC Simulation Result

Verilog-A source (adc.va)

//----- Pipelined ADC-----//‘include "discipline.h"‘include "Constants.h"module adc (in,out,clk);


Verilog-A Examples

parameter integer bit=10; // ADC resolution parameter real fullscale =5.0,//supply voltage vth=2.5,//threshold dly=10n, // transition delay ttime=1n; // transition rising time input in; // input analog voltage input clk; // input clock output [bit-1:0] out; // digital vector output

electrical in,clk; electrical [bit-1:0] out;

real sample; integer result[bit-1:0]; // integer array integer i; // index loop analog begin @( cross(V(clk)-vth, +1) ) begin sample = V(in); for( i=bit-1;i>=0;i=i-1 ) begin if( sample>vth ) begin result[i] = 5.0; sample = sample - vth; end else begin result[i] = 0.0; end sample = 2.0 * sample; end end

for(i=0;i<bit;i=i+1 ) begin V(out[i]) <+ transition(result[i], dly, ttime); end end endmodule

Spice inputdeck(adc.in):

*----- 8bit pipelined ADC -----*.verilog "adc.va".options iplot_one

* voltage sourcesvvin vin 0 sin (2.5 2.5 1meg 0 0 )vvclk vclk 0 PULSE (0 5 10n 1n 1n 5n 20n)

* Verilog-A adc module instantiationYVLGadc vin msb 7bit 6bit 5bit 4bit 3bit 2bit lsb vclk adc bit=8 fullScale=5

* analysis.tran 1n 1000n.let msb=’v(msb)/5+20’



.let7bit=’v(7bit)/5+18’






.letlsb=’v(lsb)/5+6’

.letclk=’v(vclk)/5’* save all data.iplot v(vin) clk msb 7bit 6bit 5bit 4bit 3bit 2bit lsb.end

DAC (pipelined DAC and User defined resolution):

DAC is a Digital to Analog converter, whose function is to put input digital signal change into an analog signal.

Figure 15-32 is an 8bit DAC, and the circuit behavior is ideal.

Figure 15-32: 8bit DAC

Simulation results show the following:


Verilog-A Examples

Figure 15-33: DAC Simulation Results

Verilog-A source (dac.va):

//----- DAC -----//‘include "discipline.h"‘include "Constants.h"module dacn(in,out) ; parameter real fullscale=5; //supply voltage parameter integer maxbit=10, bit=10; //Resolution input [0:bit-1] in ; output out; electrical out ; electrical [0:bit-1] in ; real vlump[maxbit:1]; real vout[maxbit:1]; //voltage real outv,vth; integer i; //index loop integer code[bit-1:0]; //digital code analog begin

analog begin @(initial_step) begin vth=fullscale/2 ; for( i=1;i <= maxbit; i=i+1) begin vlump[i]=fullscale/pow(2,i) ; end end for (i=1 ;i<= bit; i=i+1) begin if( V(in[i-1])>vth ) begin



code[i-1]=1 ; end else begin code[i-1]=0 ; end vout[i]=vlump[i]*code[i-1] ; end if (bit<maxbit) begin for( i=maxbit;i>bit;i=i-1 ) begin vout[i]=0 ; end end

outv=vout[1]+vout[2]+vout[3]+vout[4]+vout[5]+vout[6]+vout[7]+vout[9]+vout[10] ;

// V(out) <+ transition(outv,50n,50n,50n) ; V(out)<+outv;

endendmodule

Spice inputdeck:

*----- 8bit DAC -----*.verilog "dac.va".verilog "dff.va".options iplot_onev03 clk 0 pulse(0 5 0u 1n 1n 0.5u 1u)

*YVLG_dff1 q1 d1 clk d1 dffYVLG_dff2 q2 d2 q1 d2 dffYVLG_dff3 q3 d3 q2 d3 dffYVLG_dff4 q4 d4 q3 d4 dffYVLG_dff5 q5 d5 q4 d5 dffYVLG_dff6 q6 d6 q5 d6 dffYVLG_dff7 q7 d7 q6 d7 dffYVLG_dff8 q8 d8 q7 d8 dff

*YVLG_DAC d8 d7 d6 d5 d4 d3 d2 d1 out dac bit=8

.tran 1n 500u

.let LSB=’v(d1)/5+6’

.let BIT2=’v(d2)/5+8’

.let BIT3=’v(d3)/5+10’

.let BIT4=’v(d4)/5+12’

.let BIT5=’v(d5)/5+14’

.let BIT6=’v(d6)/5+16’

.let BIT7=’v(d7)/5+18’

.let MSB=’v(d8)/5+20’*.let BIT9=’v(d9)/5+22’*.let MSB=’v(d10)/5+24’


Verilog-A Examples

.iplot v(out) LSB BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 MSB

.probe all

.end

15.3.4: ADC to DAC Example:This section shows the previous example code (adc.va and dac.va). In this case, ADC resolution is set to 5bit, and DAC resolution is set to 5bit.

This circuit block is shown as:

Figure 15-34: 5bit ADC and 5bit DAC Block

The simulation result is shown in the Figure 15-35.

Figure 15-35: 5bit ADC/DAC Simulation Result



Spice inputdeck (adctodac.in):

*----- 5bit ADC to 5bit DAC -----*.verilog "dac.va".verilog "adc.va"*.options post probe+ iplot_onevvin vin 0 sin (2.5 2.5 0.1meg 0 0 -90 )vvclk vclk 0 PULSE (0 5 10n 1n 1n 100n 200n)**YVLGdac msb 3 2 1 out dacYVLGdac 5 4 3 2 1 out dac bit=5YVLGadc vin 5 4 3 2 1 vclk adc bit=5*.tran 1n 20u.probe all.let MSB=’0.2*v(5)+4’+ 4bit=’0.2*v(4)+6’+ 3bit=’0.2*v(3)+8’+ 2bit=’0.2*v(2)+10’+ LSB=’0.2*v(1)+12’.iplot v(vin) + v(out)+ LSB 2bit 3bit 4bit MSB.end

15.3.5: Delta-Sigma ModulatorDelta-Sigma consists of circuit blocks (see Figure 15-36). The first block is the summing block, and the second block is the integrator, but these blocks presently consist of SCF (switched capacitor filter). The "D" block is a quantizer in Feedback loop, and the final block is 1bit dac.

Figure 15-36: Delta-Sigma Modulator

All blocks are driven by sampling CLOCK (CLK).


Verilog-A Examples

Figure 15-37: Delta-Sigma Simulation Result

Verilog-A source(delta_sigma.va):

‘include "discipline.h"‘include "Constants.h"module delta_sigma(in,clk,out); input in,clk; output out; voltage in,clk,out; parameter real quantizer_vth=2.5; parameter real clk_vth=0; parameter real d2a_gain=1.0;

real vsum; real vd; real vint; real vout; real hi,lo;

analog begin @(initial_step) begin vd=0;vint=0;vout=0; hi = 5; lo = 0; end

@(cross(V(clk) - clk_vth,1)) begin// summing junction vsum = V(in) - vd ;// integrator vint = vint + vsum;// quantizer if (vint > quantizer_vth) vout = hi ;



else vout = lo ;// D to A vd = d2a_gain*vout ; end V(out) <+ vd ; endendmodule

Spice inpudeck ( sdelta.in):

**----- Analog (1st order Delta-Sigma modulator) circuit -----***.verilog "firstorder_sigmadelta.va"

.options iplot_one

v01 vcc 0 dc 5 v02 clk 0 pulse(0 5 10n 0.1n 0.1n 10n 20n)v03 in 0 SFFM (2.5 2.5 44.1k 1000 10 )*YVLG_sigmdelata in clk out delta_sigm*.tran 1n 20u.let vin=’v(in)+6’.let vout=’v(out)+6’.let vclk=v(clk).iplot vout vin vclk.end

15.4: Example 1: DFF with Spice PrimitivesThis example shows some techniques for creating an accurate VERILOG-A module of Data Flip-Flop cell. An accurate module can be realized by introducing complex delay and rise/fall time models, which are a function of the output load and ramp-time of the clock pulse. Another technique is the use of SPICE primitives such as capacitor, resistor, diode, BJT and MOSFET. In this example, capacitors are instantiated inside the module representing the load capacitance of module terminals.

A practical example of DFF module is shown below.

Example: DFF module description (dff_cl.va)

// D-FF with CLEAR// Tpd, Tr and Tf are optimized based on the result of device simulation// using BSIM3v3.2 default parameter set and nominal condition. //


module dff_cl (d, clk, clr, q) ; input d, clk, clr ; output q ; electrical d, clk, clr, q ;


Verilog-A Examples

parameter real VDD=3.3, THRESH=0.5, LO_THRESH=0.2, HI_THRESH=0.8, FO=2.0, SLOPE_IN=0.09n ; parameter real C_D=9.78e-15, C_CLK=9.98e-15, C_CLR=12.40e-15 ; parameter real TR_CLK_0=38.7647p, TR_CLK_1=244.058p, TF_CLK_0=259.585p, TF_CLK_1=128.525p, TF_CLR_0=276.347p, TF_CLR_1=122.161p, TD_L2H_0=937.706p, TD_L2H_1=-163.297p, TD_H2L_0=831.739p, TD_H2L_1=-76.1828p, TD_CLR_0=184.611p, TD_CLR_1=-67.1826p, SLOPE_COEF=0.33033, SLOPE_NOM=0.09n ;

/* following parameters are calculated internally */ parameter real delta_thresh=HI_THRESH-LO_THRESH, vth=VDD*THRESH, tr_clk = (TR_CLK_0+TR_CLK_1*FO)/delta_thresh, tf_clk = (TF_CLK_0+TF_CLK_1*FO)/delta_thresh, tf_clr = (TF_CLR_0+TF_CLR_1*FO)/delta_thresh, td_l2h = TD_L2H_0+TD_L2H_1*FO+SLOPE_COEF*(SLOPE_IN-SLOPE_NOM), td_h2l = TD_H2L_0+TD_H2L_1*FO+SLOPE_COEF*(SLOPE_IN-SLOPE_NOM), td_clr = TD_CLR_0+TD_CLR_1*FO+SLOPE_COEF*(SLOPE_IN-SLOPE_NOM) ;

real td, tr, tf ; integer state ;

/* SPICE primitives as input capacitor */ capacitor #(.c(C_D)) cdata(d) ; capacitor #(.c(C_CLK)) cclk(clk) ; capacitor #(.c(C_CLR)) cclr(clr) ;

/* Behavioral description of DFF with CLEAR */ analog begin @(initial_step) begin state=0 ; tr=tr_clk ; end

@(cross(V(clk)-vth,+1)) begin if(V(clr) < vth) state=0 ; else state=(V(d) > vth) ; if(state) td=td_l2h ; else begin td=td_h2l ; tf=tf_clk ; end end

@(cross(V(clr)-vth,-1)) begin state=0 ; td=td_clr ; tf=tf_clr ; end



V(q) <+ transition(VDD*state, td, tr, tf) ; endendmodule

In the module description, three capacitors are introduced to represent input capacitance of module ports; d, clk and clr. The capacitance values are derived from transistor level simulation, and should match to the equivalent gate capacitance of MOSFET at each module port. For rough estimation, the following capacitance equation can be used to calculate gate capacitance.

Cgate = EPSox*L*W/TOX where EPXox is gate oxide permittivity = 3.453143e-11 [F/m] L and W are channel length and width in meter TOX is gate oxide thickness in meter

Another technique for achieving accurate model is the introduction of complex formula to model delay time and rise/fall transition time of flip-flop. Generally, the delay time is the function of fanout and ramp-time of clock pulse, and can be formulated as follows;

Tdelay = T0 + T1*FANOUT + T2*SLOPE where FANOUT is number of fanout drived by DFF output SLOPE is ramp-time of clk pulse T0 is delay time at FANOUT=0 and SLOPE=0 T1 is coefficient of fanout dependency T2 is coefficient of ramp-time dependency

In this example, the parameter SLOPE is replaced by (SLOPE - SLOPEnom), where SLOPEnom is the nominal slope at which T0 and T1 are extracted.

The transition time is formulated in the same manner as delay time, except the fanout dependency term is excluded, and is defined as following formula;

Ttrans = TT0 + TT1*FANOUT where FANOUT is number of fanout drived by DFF output TT0 is transition time at FANOUT=0 TT1 is coefficient of fanout dependency

Note that since the delay time of high data and low data are not identical, the different delay parameters are introduced to calculate each delay formula of high and low data. In addition, the different delay parameters are introduced to calculate the clear time. Likely, the different transition parameters are introduced to calculate rise and fall time individually.


Verilog-A Examples

15.5: Simulation with SmartSpice8-bit shift resister circuit and input deck are shown in Figure 15-38 and the following Example, respectively.

Figure 15-38: 8 Bit Shift Resistor

Example: Input deck of 8-bit shift register

* 8-Bit Shift Register************************************ Netlist ********************************VCLR CLR 0 PWL(0 0 1N 0 1.09N VDD 102N VDD 102.09N 0)VCLK CLK 0 PULSE(0 VDD 5N SLOPE SLOPE 4.91N 10N)VDATA DATA 0 PULSE(0 VDD 3N SLOPE SLOPE 9.91N 20N)VDD VDD 0 DC 3.3XCLK CLK CLKB INVERTER PARAMS: WP=6.8U LP=0.5U WN=4.8U LN=0.5UXCLKB CLKB CLK_VA INVERTER PARAMS: WP=’6.8U*4’ LP=0.5U WN=’4.8U*4’ LN=0.5UXDATA DATA DATAB INVERTER PARAMS: WP=6.8U LP=0.5U WN=4.8U LN=0.5UXDATAB DATAB DATA_VA INVERTER PARAMS: WP=6.8U LP=0.5U WN=4.8U LN=0.5UXCLR CLR CLRB INVERTER PARAMS: WP=6.8U LP=0.5U WN=4.8U LN=0.5U



XCLRB CLRB CLR_VA INVERTER PARAMS: WP=’6.8U*4’ LP=0.5U WN=’4.8U*4’ LN=0.5UYVLG0 DATA_VA CLK_VA CLR_VA Q0 DFF_CL FO=2.03085 SLOPE_IN=SLOPE_VALYVLG1 Q0 CLK_VA CLR_VA Q1 DFF_CL FO=2.03085 SLOPE_IN=SLOPE_VALYVLG2 Q1 CLK_VA CLR_VA Q2 DFF_CL FO=2.03085 SLOPE_IN=SLOPE_VALYVLG3 Q2 CLK_VA CLR_VA Q3 DFF_CL FO=2.03085 SLOPE_IN=SLOPE_VALYVLG4 Q3 CLK_VA CLR_VA Q4 DFF_CL FO=2.03085 SLOPE_IN=SLOPE_VALYVLG5 Q4 CLK_VA CLR_VA Q5 DFF_CL FO=2.03085 SLOPE_IN=SLOPE_VALYVLG6 Q5 CLK_VA CLR_VA Q6 DFF_CL FO=2.03085 SLOPE_IN=SLOPE_VALYVLG7 Q6 CLK_VA CLR_VA Q7 DFF_CL FO=1.34995 SLOPE_IN=SLOPE_VALXOUT0 Q0 O0_VA INVERTER PARAMS: WP=6.8U LP=0.5U WN=4.8U LN=0.5UXOUT1 Q1 O1_VA INVERTER PARAMS: WP=6.8U LP=0.5U WN=4.8U LN=0.5UXOUT2 Q2 O2_VA INVERTER PARAMS: WP=6.8U LP=0.5U WN=4.8U LN=0.5UXOUT3 Q3 O3_VA INVERTER PARAMS: WP=6.8U LP=0.5U WN=4.8U LN=0.5UXOUT4 Q4 O4_VA INVERTER PARAMS: WP=6.8U LP=0.5U WN=4.8U LN=0.5UXOUT5 Q5 O5_VA INVERTER PARAMS: WP=6.8U LP=0.5U WN=4.8U LN=0.5UXOUT6 Q6 O6_VA INVERTER PARAMS: WP=6.8U LP=0.5U WN=4.8U LN=0.5UXOUT7 Q7 O7_VA INVERTER PARAMS: WP=6.8U LP=0.5U WN=4.8U LN=0.5UCL0 O0_VA 0 ’0.01PF*2’ CL1 O1_VA 0 ’0.01PF*2’ CL2 O2_VA 0 ’0.01PF*2’ CL3 O3_VA 0 ’0.01PF*2’ CL4 O4_VA 0 ’0.01PF*2’ CL5 O5_VA 0 ’0.01PF*2’ CL6 O6_VA 0 ’0.01PF*2’ CL7 O7_VA 0 ’0.01PF*2’ ***** Subcircuit Definitions.SUBCKT INVERTER IN OUTMP1 OUT IN GND GND NM L=LN W=WNMP2 OUT IN VDD VDD PM L=LP W=WP.ENDS INVERTER****************************** Control Deck ******************************.MODEL PM PMOS LEVEL=8.MODEL NM NMOS LEVEL=8.VERILOG ’dff_cl.va’.GLOBAL VDD GND .PARAM VDD=3.3 SLOPE=0.09N SLOPE_VAL=308p.SAVE V(CLK_VA) V(CLR_VA) V(DATA_VA)+ V(O0_VA) V(O1_VA) V(O2_VA) V(O3_VA) V(O4_VA) V(O5_VA) V(O6_VA) V(O7_VA).OPTIONS ACCT NOMOD.TRAN 1P 120N.END

Simulation Results:

Simulation results are shown in Figure 15-39 through Figure 15-41. These figures show that the waveforms obtained from VERILOG-A simulation (solid lines) are well matched to those obtained from transistor level simulation (dot lines).


Verilog-A Examples

Figure 15-39: CLK Signals Simulation Results

Figure 15-40: Output Signals (Rise) Simulation Results

Figure 15-41: Output Signals (Fall) Simulation Results

15.6: Example 2: PLLThe block diagram of PLL is shown in Figure 15-42. The PLL consists of digital blocks; Phase Detector (PD) and clock Divider, and analog blocks; Voltage Controlled Oscillator (VCO), Charge Pump (CP) and Loop Filter (LPF). Some of these blocks can be replaced by the VERILOG-A module for the purpose of reducing the simulation time.

In this example, the PD, VCO and Divider blocks are replaced by the VERILOG-A module, and perform a simulation to see the phase-lock characteristic of PLL.



Figure 15-42: PLL Block Diagram

The VERILOG-A module descriptions for each blocks are shown in List 2-1 through List2-3.

Example: Phase Detector module description (pll_pd.va)

// Phase Detector//


module pll_pd (in_ref, in_fb, out_up, out_dn); inout in_ref, in_fb, out_up, out_dn; electrical in_ref ,in_fb ,out_up, out_dn; parameter real vdd=3.3, ttol=10f, delay=1n, ttime=0.1n ; integer state; // state=1 for down, -1 for up

analog begin @(cross( V(in_ref) - vdd/2 , 1 , ttol )) state = state - 1; @(cross( V(in_fb) - vdd/2 , 1 , ttol )) state = state + 1; if ( state > 1 ) state = 1 ; if ( state < -1 ) state = -1; V(out_dn) <+ transition( (state + 1)/2*vdd , delay , ttime ); V(out_up) <+ transition( (state - 1)/2*vdd+vdd , delay , ttime ); endendmodule

Example: VCO module description (pll_vco.va)

// VCO//



Verilog-A Examples

module pll_vco ( in, out ) ; inout in, out ; electrical in, out ; parameter real vdd=3.3 ; parameter real amp = vdd/2, // amplitude of vout [V] offset = vdd/2, // offset of vout [V] gain = 464e6, // gain [Hz/V] vnom = 1.270, // nominal vin [V] fc = 400e6 ; // center frequency@vnom [Hz] real freq ;

analog begin freq = fc + gain * (V(in) - vnom) ; V(out) <+ amp * sin( 2 * ‘M_PI * idt(freq) ) + offset ; endendmodule

Example: Divider module description (divider.va)

// CLOCK DIVIDER//


module divider ( in, out ) ; inout in, out ; electrical in, out ; parameter integer num_div = 4 ; // number of divide parameter real vdd = 3.3 , delay = 2n , ttime = 0.1n ; integer count, state ;

analog begin @( cross( V(in) - vdd/2 , +1 ) ) begin if ( count >= div_num/2 ) begin state = !state ; count = 0 ; end count = count + 1 ; end V(out) <+ transition( state * vdd, delay , ttime ) ; endendmodule

Note that the parameters gain and vnom used in VCO module, are derived from transistor level simulation, therefore the phase-lock characteristic obtained from the VERILOG-A simulation would be matched to that obtained from transistor level simulation.

The input deck is shown in the following Example.



Example: Input Deck of PLL simulation

* PLL ; SPICE/Verilog-A Mixed Simulation**------------------ Verilog-A module file ------------------*.verilog "pll_pd.va" ; Phase Detector.verilog "pll_vco.va" ; VCO.verilog "divider.va" ; Clock Divider*------------------ SPICE Subcircuit file ------------------*.include "pll_cp.net" ; Charge Pump.include "pll_lpf.net" ; Loop Filter*-------------------- PLL Main Circuit ---------------------*YVLGpd ref fb up down pll_pdXcp up down lpf pll_cpXlpf lpf pll_lpfYVLGvco lpf ckout pll_vcoYVLGdiv ckout fb divider

vref ref 0 pulse(0 3.3 22.4n 0.1n 0.1n 4.9n 10n)vvdd vdd 0 3.3

.tran 1n 2u

.ic v(lpf)=1.1

.save v(ref) v(fb) v(up) v(down) v(lpf) v(ckout)

.end

Simulation Results:

Simulation results are shown in Figure 15-43 through Figure 15-45.

Figure 15-43 shows the phase-frequency difference between reference clock and feedback clock at time=0s. After 1.5us of transient simulation, the feedback clock is locked to the reference clock as shown in Figure 15-44. The VCO input voltage supplied from charge pump keeps constant value of 1.27v which is consistent with the given value of parameter vnom in VCO module.

Figure 15-45 shows the phase-lock characteristic of VERILOG-A mixed simulation and full transistor level simulation.

Figure 15-43: V(vco_in) at time=0 s Simulation Results


Verilog-A Examples

Figure 15-44: V(vco_in) at time=1.5 us Simulation Results

Figure 15-45: Comparison with transistor level Simulation Results


Index

Symbols$abstime Function............................................................... 9-8$display .......................................................................... 9-19

$fdisplay ......................................................................... 9-23$fstrobe .......................................................................... 9-22$fwrite ............................................................................ 9-23

$realtime Function .............................................................. 9-8$sit_get_ddv .................................................................... 9-16$sit_get_prev ................................................................... 9-16

$strobe ........................................................................... 9-17$write ............................................................................. 9-19*AE.............................................................................. 14-60

*AQB0.......................................................................... 14-60*AXI............................................................................. 14-59*CBCO ......................................................................... 14-61

*CBEO ......................................................................... 14-61*CTH ........................................................................... 14-61*DEG ........................................................................... 14-60

*DVGBF ....................................................................... 14-60*DVGBR ....................................................................... 14-60*DVGTE ....................................................................... 14-60

*HRCF ....................................................................... 14-126*IKF ........................................................................... 14-124*IKP........................................................................... 14-124

*IKR........................................................................... 14-124*ITF ........................................................................... 14-127*MLF............................................................................ 14-59

*RTH ........................................................................... 14-61*TAUB.......................................................................... 14-60*TAUE.......................................................................... 14-60

*TAUR.......................................................................... 14-60*TEPI ........................................................................... 14-60*VAVL .......................................................................... 14-59

*VBBE........................................................................ 14-128*VEF............................................................... 14-59, 14-124*VER .............................................................. 14-59, 14-124

*VO ........................................................................... 14-126*VRT.......................................................................... 14-126*VTF .......................................................................... 14-127

*WAVL ......................................................................... 14-59*XREC ......................................................................... 14-60

AAB............................................................................... 14-60Absolute Delay Operator .................................................... 6-14AC............................................................................... 14-60


ac.................................................................................... 9-1AEPI ............................................................................ 14-60

AEX ............................................................................. 14-60AF ............................................................................... 14-60AFN ........................................................................... 14-128

AJC ........................................................................... 14-126AJE ........................................................................... 14-126AJS ........................................................................... 14-126

Analog Conditional .............................................................. 5-5Analog Operators.............................................................. 6-11Analog Procedural Block....................................................... 5-1

Analog Signals ................................................................... 5-7Analysis ............................................................................ 9-1Arithmetic Operators............................................................ 6-4

Arrays .............................................................................. 4-5ART ........................................................................... 14-126AS ............................................................................... 14-61

Attributes HUGE, BLOWUP, MAXDELTA (Cadence Comparibility).................................................. 13-3

Avalanche constant ......................................................... 14-64AVC1 ......................................................................... 14-125AVC2 ......................................................................... 14-125

BBase Charge................................................................ 14-129Base Charge Equations.................................................... 14-41

Base Emitter Capacitance Equations ................................... 14-42Base Nature ...................................................................... 4-7base resistance model ..................................................... 14-42

Base Width Modulation Parameters (Early Effect)................... 14-47Base-Collector Capacitance Equations ................................ 14-43Base-Collector Charge ................................................... 14-135

Base-Collector Charge of the Parasitic Device ..................... 14-136Base-Collector Current of the Parasitic Device..................... 14-133Base-Collector Depletion Capacitance ................................. 14-43

Base-Collector Diffusion Capacitance .................................. 14-43Base-Collector Weak Avalanche Current ............................ 14-132Base-Emitter Breakdown Current...................................... 14-132

Base-Emitter Charge ..................................................... 14-135Base-Emitter Charge of the Parasitic Device ....................... 14-136Base-Emitter Current of the Parasitic Device ....................... 14-132

Base-Emitter Depletion Capacitance ................................... 14-43Base-Emitter Diffusion Capacitance .................................... 14-42Base-Emitter Tunneling Parameters .................................. 14-128

Basic DC Model Parameters.............................................. 14-45BF ................................................................... 14-46, 14-59BFN ........................................................................... 14-128

Index-1


Binary Operators................................................................. 6-5Binding Natures ................................................................ 4-10

BJT Modeling ................................................................. 14-41Block Names...................................................................... 5-2Block Statements ................................................................ 5-1

Bounding the Time Step ....................................................... 9-7BR............................................................................... 14-46Branches ........................................................................ 4-16

BRI .............................................................................. 14-59Built-in Potentials .......................................................... 14-138BULK (NSUB) .............................................................. 14-123

CCapacitance Equations..................................................... 14-42Capacitance Temperature Equations ................................... 14-45

Case ................................................................................ 5-5CBCO ........................................................................ 14-125CBEO......................................................................... 14-125

CCSO ........................................................................ 14-125Charge and Capacitance Equations .................................. 14-133Chi-Square Distribution ...................................................... 9-14

Circular Integrator Operator ................................................. 6-13CJC .................................................... 14-47, 14-60, 14-126CJCP ......................................................................... 14-126

CJE .................................................... 14-47, 14-59, 14-125CJEP ......................................................................... 14-126CJS ................................................................. 14-48, 14-61

Closing a File ................................................................... 9-24Collector Current Contributions ........................................ 14-129Collector Resistance ........................................................ 14-70

Compatibility of Disciplines .................................................. 4-11Compiler Directives ............................................................. 3-9Concatenations ................................................................ 6-10

Conditional Statement .......................................................... 5-4conservative system ............................................................ 1-3Control Flow .................................................................... 2-11

Converting Real Numbers to Integer Numbers ........................... 4-2Correlated noise ................................................................. 9-4cross function..................................................................... 8-4

current crowding ............................................................. 14-77Current Gain .................................................................. 14-63Currents and Voltages...................................................... 14-64

Currents in Modulated Resistors....................................... 14-130

Ddc.................................................................................... 9-1

DC Current Equations .................................................... 14-128DC current Equations....................................................... 14-65DEAR......................................................................... 14-127

Declaring .......................................................................... 2-2Depletion Capacitances.................................................... 14-63

Index-2

Depletion charge............................................................ 14-74Derived Nature .................................................................. 4-9

Description of charges..................................................... 14-72Differences between v1.1.5 and v1.2 ................................ 14-121diffusion capacitance ...................................................... 14-42

Discipline of Wires and Undeclared Nets ............................... 4-14Disciplines ...................................................................... 4-10Discontinuity ..................................................................... 9-5

Distributed High Frequency Effects In the Intrinsic Base..................................................... 14-77

DTA ............................................................................ 14-58

EEA ............................................................................ 14-127

EAIC ......................................................................... 14-127EAIE ......................................................................... 14-127EAIS ......................................................................... 14-127

EANC ........................................................................ 14-127EANE ........................................................................ 14-127EANS ........................................................................ 14-127

EAP .......................................................................... 14-127Early Voltage Parameters .............................................. 14-124EKV MOSFET Model ...................................................... 14-29

Emission Coefficient Parameters ..................................... 14-123Emitter depletion charges................................................. 14-72Empty Disciplines............................................................. 4-14

Epilayer Parameters ........................................ 14-126, 14-139Equivalent circuit.......................................................... 14-122Equivalent Circuit for Large Signal Analysis.......................... 14-58

Equivalent Circuit of the VBIC Bipolar Model (large signal)......................................... 14-122

Erlang Distribution ............................................................ 9-15Escaped........................................................................... 3-6Event Detection ................................................................. 8-1

Event OR Operator ............................................................. 6-9EXAVL......................................................................... 14-59Excess Phase Network.................................................. 14-136

exclude ............................................................................ 4-5EXMOD ....................................................................... 14-58EXPHI ......................................................................... 14-59

Exponential Distribution ..................................................... 9-12Extended Modeling of the Reverse

Current Gain EXMOD = 1 ............................................. 14-75External Base-Internal Collector

Junction Capacitance .................................................. 14-44Extrinsic collector depletion charges ................................... 14-73

FFC ................................................................. 14-47, 14-125flicker_noise...................................................................... 9-3For.................................................................................. 5-6


Index

Forward Base Currents .................................................... 14-66Forward mode (IC1C2 > 0)................................................ 14-70

from ................................................................................. 4-5

GGAMM........................................................................ 14-126

General Parameters ...................................................... 14-122Genvars............................................................................ 4-5GEOM (SUBS) ............................................................... 14-46

Geometry scaling............................................................ 14-65Ground ........................................................................... 4-15Gummel-Poon BJT Model Equations................................... 14-41

HHeterojunction features ......................................... 14-65, 14-78High Current Beta Degradation

Effect Parameters .......................................... 14-47, 14-124

IIBBE .......................................................................... 14-128IBCI ........................................................................... 14-123IBCIP ......................................................................... 14-123

IBCN.......................................................................... 14-123IBCNP........................................................................ 14-123IBEI ........................................................................... 14-123

IBEIP ......................................................................... 14-123IBEN.......................................................................... 14-123IBENP ........................................................................ 14-123

IBF .............................................................................. 14-59IBR.............................................................................. 14-59ic..................................................................................... 9-1

Ideal forward and reverse current ....................................... 14-65Ideal Forward and Reverse Currents ................................. 14-129Identifiers .......................................................................... 3-6

IHC.............................................................................. 14-59IK ................................................................................ 14-59IKF .............................................................................. 14-47

IKR.............................................................................. 14-47IKS .............................................................................. 14-61Implicit............................................................................ 4-17

Instantiating Analog Primitives that Use Array Valued Parameters .............................................. 10-19

Integer ............................................................................. 3-2integer.............................................................................. 4-3Integer Numbers................................................................. 4-1

Intrinsic and Extrinsic Base-Emitter Current ........................ 14-131Intrinsic Base-Collector Current........................................ 14-132Intrinsic collector depletion charge ...................................... 14-72

IRB.............................................................................. 14-47IS ....................................................... 14-46, 14-59, 14-123ISC.............................................................................. 14-46


ISE .............................................................................. 14-46ISP ............................................................................ 14-123

ISRR.......................................................................... 14-123ISS .................................................................. 14-48, 14-60ITF .............................................................................. 14-48

JJunction Capacitance Parameters..................................... 14-125Junction Capacitor Parameters .......................................... 14-47

KKeywords .......................................................................... 3-7KF ............................................................................... 14-60

KFN ............................................................... 14-60, 14-128Kirchoff ’s Potential Law (KPL) ............................................... 1-3Kirchoff’s Flow Law (KFL) ..................................................... 1-3

LLaplace Transform Filters ................................................... 6-22laplace_nd....................................................................... 6-24

laplace_np....................................................................... 6-24laplace_zd....................................................................... 6-23laplace_zp....................................................................... 6-23

LEVEL............................................................ 14-58, 14-122LEVEL 3 Verilog-A Model Listing ........................................ 14-16Limited Exponential ........................................................... 6-27

Logical Operators................................................................ 6-7Looping ............................................................................ 5-6Low Current Beta Degradation Parameters ........................... 14-46

MMain Current IN .............................................................. 14-65MC ................................................................ 14-60, 14-126

ME ............................................................................ 14-126MJC............................................................................. 14-47MJE ............................................................................. 14-47

MJS ............................................................................. 14-48Model constants ............................................................. 14-62Model Parameters........................................................... 14-58

Modella Bipolar Transistor............................................... 14-159module ............................................................................. 2-1Modules.......................................................................... 10-1

Creating and Naming ..................................................... 10-1Instantiating Analog Primitives.......................................... 10-9Multilevel Hierarchal Designs ........................................... 10-5Overriding Parameter Values ........................................... 10-7Overriding Parameter Values in Instances........................... 10-7Ports of Module Instances ............................................... 10-3

Monitored Events ................................................................ 8-4MOSFET Model LEVEL=3 ................................................ 14-15MOSFET model LEVEL=3

DC current equations ................................................... 14-11

Index-3


model parameters........................................................ 14-15MS ............................................................................ 14-126

MTAU........................................................................... 14-60MULT ........................................................................... 14-58

NName ............................................................................... 2-3Natures................................................................... 4-6, 4-15NBBE ......................................................................... 14-128

NC............................................................................... 14-46NCI ............................................................................ 14-123NCIP .......................................................................... 14-124

NCN .......................................................................... 14-124NCNP......................................................................... 14-124NE............................................................................... 14-46

NEI ............................................................................ 14-123NEN........................................................................... 14-123NF ................................................................. 14-46, 14-123

NFP ........................................................................... 14-124NK (NKF) ...................................................................... 14-47NKF ........................................................................... 14-124

Nodes ............................................................................ 2-14nodeset ............................................................................ 9-1Noise ............................................................................... 9-3

noise .................................................................... 9-1, 14-78Noise Model .................................................................. 14-78Noise Parameters ......................................................... 14-128

noise_table........................................................................ 9-3Non-Ideality Factors and Weak Avalanche

Model Parameters ..................................................... 14-138Normal (Gaussian) Distribution............................................. 9-12Normalized Junction Depletion Charge .............................. 14-133

NR................................................................. 14-46, 14-123NS............................................................................... 14-48Numbers ........................................................................... 3-2

OOperators.......................................................................... 3-2Ordinary............................................................................ 3-6

Overlap Capacitance Parameters ..................................... 14-125

PParameters................................................................ 2-5, 4-3

Parasitic Resistor Parameters ............................................ 14-47Parasitic Resistors ........................................................ 14-137Partioning Parameters.................................................... 14-124

PC................................................................. 14-60, 14-126PE ................................................................. 14-59, 14-125phase-shift .................................................................... 14-77

Poisson Distribution ........................................................... 9-13Port Declaration.................................................................. 2-4

Index-4

Port Direction .................................................................... 2-4Port Type ......................................................................... 2-4

Ports ............................................................................... 2-3Probes............................................................................. 5-9Probes and Sources ........................................................... 5-9

PS ................................................................. 14-61, 14-126

QQBM ......................................................................... 14-123

QCO ......................................................................... 14-126QTF .......................................................................... 14-126

RRandom Numbers .............................................................. 9-9RB .............................................................................. 14-47RBC ............................................................................ 14-59

RBI ........................................................................... 14-125RBM ........................................................................... 14-47RBP .......................................................................... 14-125

RBV ............................................................................ 14-59RBX .......................................................................... 14-125RC.............................................................................. 14-47

RCC............................................................................ 14-59RCI ........................................................................... 14-125RCV............................................................................ 14-59

RCX.......................................................................... 14-125RE ...................................................... 14-47, 14-59, 14-125Real ................................................................................ 3-3

real ................................................................................. 4-3Real Numbers ................................................................... 4-1Repeat and While............................................................... 5-6

Resistance Parameters ................................................. 14-125Resistances .................................................................. 14-62Reverse Base Currents ................................................... 14-66

Reverse mode (IC1C2 ...................................................................14-71REVISION (REV, VREV) ............................................... 14-122RS ............................................................................ 14-125

SSaturation Current Parameters ........................................ 14-123Saturation Currents ...................................................... 14-137

Saturation Currents and Current Gain ................................. 14-44SCRCV........................................................................ 14-59Self-heating feature ........................................................ 14-80

Sequential ........................................................................ 5-3Sequential Blocks............................................................... 5-1SFH ............................................................................ 14-59

Shift Operators .................................................................. 6-9Signal Access Functions ...................................................... 5-7Signal-flow systems ............................................................ 1-4

Silvaco System Functions .................................................. 9-16


Index

Single piece model........................................................ 14-134Slew Filter ....................................................................... 6-20

Sources ............................................................................ 5-9Special Characters.............................................................. 3-5Specified Distributions........................................................ 9-11

Standard Gummel-Poon model ........................................ 14-133Standard Mathematical Functions........................................... 7-1static ................................................................................ 9-1

Stored base charges ....................................................... 14-74Stored emitter charge ...................................................... 14-74Stored epilayer charge ..................................................... 14-75

Stored extrinsic charges ................................................... 14-75Strings.............................................................................. 3-5Student’s T Distribution ...................................................... 9-14

Substrate Capacitance ..................................................... 14-44substrate current............................................................. 14-41Substrate Current Equations ............................................. 14-41

Substrate Current Parameters ........................................... 14-48Survey of Modeled Effects ................................. 14-121, 14-159Survey of modeled Effects ................................................ 14-57

TTAVC ......................................................................... 14-128TD............................................................................. 14-127

temperature................................................................... 14-44Temperature conversions ................................................. 14-62Temperature dependence of thermal resistance................... 14-136

Temperature Effect Parameters ............................ 14-48, 14-127Temperature Effects Equations .......................................... 14-44Temperature scaling ........................................................ 14-62

Ternary Operator ................................................................ 6-9TF .................................................................. 14-48, 14-126The Improved Mextram Transistor

Model (LEVEL=504) .................................................... 14-57The power function

$pwr........................................................................... 13-3Thermal Voltage ................................................................. 9-9

Time Derivative Operator.................................................... 6-12Time Integral Operator ....................................................... 6-12timer function ..................................................................... 8-5

TNBBE ....................................................................... 14-128TNF ........................................................................... 14-128TNOM ........................................................................ 14-127

Tokens ............................................................................. 3-1TR.................................................................. 14-48, 14-127tran.................................................................................. 9-1

Transit Time and Excess Phase Parameters ....................... 14-126Transit Time Parameters .................................................. 14-48Transit Times ................................................................. 14-64

Transition Filter ................................................................ 6-15Transport Current and Base Charge


of the Parasitic Device ................................................ 14-130TREF ........................................................................... 14-58

Trigonometric and Hyperbolic Functions................................... 7-2TVBBE1...................................................................... 14-128TVBBE2...................................................................... 14-128

UUniform Distribution ........................................................... 9-11User-Defined Functions ...................................................... 9-24

VVAF ............................................................................. 14-47VAR............................................................................. 14-47

Variable Base Resistance ................................................. 14-69Variable Base Resistance Equations ................................... 14-41VBIC Bipolar Transistor .................................................. 14-121

Model Parameters ..................................................... 14-122Temperature Scaling .................................................. 14-136

VDC............................................................................. 14-60VDE............................................................................. 14-59

VDS............................................................................. 14-61VERSION (VERS)......................................................... 14-122VGB............................................................................. 14-60

VGC ............................................................................ 14-60VGJ ............................................................................. 14-60VGS............................................................................. 14-61

VJC ............................................................................. 14-47VJE ............................................................................. 14-47VJS ............................................................................. 14-48

VLR ............................................................................. 14-59VTF ............................................................................. 14-48

WWBE .......................................................................... 14-124Weak Avalanche Current .................................................. 14-67Weak Avalanche Parameters........................................... 14-125

White Space ...................................................................... 3-1white_noise ....................................................................... 9-3Writing to a File ................................................................ 9-22

WSP .......................................................................... 14-124

XX (Subcircuit Call) ........................................................... 10-18

XCJC ............................................................... 14-48, 14-60XCJE ........................................................................... 14-60XEXT ........................................................................... 14-59

XIBI ............................................................................. 14-59XII ............................................................................. 14-128XIKF .......................................................................... 14-128

XIN ............................................................................ 14-128XIS ............................................................................ 14-127

Index-5


XISR .......................................................................... 14-128XP ............................................................................... 14-60

XRB (XRBI) ................................................................. 14-127XRBP ......................................................................... 14-127XRBX ......................................................................... 14-127

XRC (XRCI) ................................................................. 14-127XRCX......................................................................... 14-127XRE ........................................................................... 14-127

XRS ........................................................................... 14-127XTF ............................................................... 14-48, 14-126XVO........................................................................... 14-127

ZZero-Bias Capacitances ................................................. 14-139zi_nd .............................................................................. 6-27

zi_np .............................................................................. 6-27zi_zd .............................................................................. 6-26zi_zp .............................................................................. 6-26

Z-Transform..................................................................... 6-25

Index-6

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