verifikation - metoder og libraries

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Presented byMartin Rønne, MR Logic

Slides prepared byJim Lewis, [email protected]

SynthWorks

Copyright © 2016 SynthWorks Design Inc.

Copyright © 2017 by SynthWorks Design Inc.Reproduction of this entire document in whole for individual usage is permitted. All other rights reserved.

In particular, without express written permission of SynthWorks Design Inc, You may not alter, transform, or build upon this work,You may not use any material from this guide in a group presentation, tutorial, training, or classroomYou must include this page in any printed copy of this document.

This material is derived from SynthWorks' Advanced VHDL Testbenches and Verification class

This material is updated from time to time and the latest copy of this is available at http://www.SynthWorks.com/papers

Contact InformationJim Lewis, PresidentSynthWorks Design Inc11898 SW 128th AvenueTigard, Oregon [email protected]

www.SynthWorks.com

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UartTbTxProc : processbegin. . .UartSend(UartTxRec, X"4A") ; UartSend(UartTxRec, X"4B") ;. . .

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architecture UartTx1 of TestCtrl is. . .

beginControlProc : processbegin

. . .WaitForBarrier(TestDone, 5 ms) ;ReportAlerts ; std.env.stop;

end process ;

CpuTestProc : processbegin

wait until nReset = '1' ;CpuWrite(. . .) ;Toggle(CpuRdy);. . .WaitForBarrier(TestDone) ;

end process ;

UartTbTxProc : processbegin

WaitForToggle(CpuRdy);UartSend(. . .) ;. . .WaitForBarrier(TestDone) ;

end process ; . . .

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UartSend(...)

type CpuRecType is recordRdy : std_logic_max ;Ack : std_logic_max ;

Data : unsigned_max(7 downto 0) ; ErrMode : unsigned_max(2 downto 0) ;

end record ;

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procedure UartSend (. . .

) isbegin-- Copy Transaction to RecordUartTxRec.Data <= . . . ; UartTxRec.ErrMode <= . . . ;

-- Handshake with UartTxRequestTransaction(. . .);

-- Copy results from Record. . .

end UartSend ;

entity UartTx isport (. . .) ;

end UartTx ;architecture Model of UartTx is. . .

begin

. . .

UartTxFunction : process-- declarations not shown

begin-- Handshake with UartSendWaitForTransaction(. . .);

-- Create UART waveforms. . .

end process ;

end Model ;

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Data1 := RV.RandInt(Min => 0, Max => 15) ;Data2 := RV.RandInt(0, 15, (5,11) ) ; -- except 5 & 11

Data3 := RV.RandInt( (1,2,3,5,7,11) ) ; Data4 := RV.RandInt( (1,2,3,5,7,11), (5,11) ) ;

. . . -- ((val1, wt1), (val2, wt2), ...)Data6 := RV.DistValInt( ((1,7), (3,2), (5, 1)) ) ;

Data5 := RV.DistInt ( (7, 2, 1) ) ;

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variable RV : RandomPType ;. . .

StimGen: while TestActive loop case RV.DistInt( (70, 10, 10, 5, 5) ) iswhen 0 => -- Nominal case 70% Operation := UARTTB_NO_ERROR ; Data := RV.RandSlv(0, 255, Data'length) ;

when 1 => -- Parity Error 10%Operation := UARTTB_PARITY_ERROR ; Data := RV.RandSlv(0, 255, Data'length) ;

when . . . -- (2, 3, and 4)

end case ;

UartRxScoreboard.Push( (Data, Operation) ) ;

UartSend(UartTxRec, Data, Operation) ; . . .

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function GenBin ( . . . ) return CovBinType ;

type CovPType is protectedprocedure AddBins ( CovBin : CovBinType ) ;procedure AddCross( Bin1, Bin2, ... : CovBinType ) ;procedure ICover ( val : integer ) ;procedure ICover ( val : integer_vector ) ;impure function IsCovered return boolean ;procedure WriteBin ; procedure WriteCovHoles ; procedure ReadCovDb ( FileName : string ) ;procedure WriteCovDb ( FileName : string; ... ) ;. . .

end protected CovPType ;

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architecture Test3 of tb isshared variable ACov : CovPType ;

beginCollectCov : process variable RV : RandomPType ; -- randomization objectvariable Src1, Src2 : integer ;

beginACov.SetName("TbAlu_ConstrainedRandom") ;

ACov.AddCross( GenBin(0,7), GenBin(0,7) );loopSrc1 := RV.RandInt(0, 7) ;Src2 := RV.RandInt(0, 7) ;

DoAluOp(TRec, Src1, Src2) ;

ACov.ICover( ( Src1, Src2 ) ) ;

exit when ACov.IsCovered ;

end loop ;ACov.WriteBin ; ReportAlerts ; std.env.stop ;

end process ;

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ACov.AddCross( GenBin(0,7), GenBin(0,7) );

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TestProc : process beginfor i in 0 to 7 loop for j in 0 to 7 loopif i /= j then -- non-diagonalACov.AddCross(2, GenBin(i), GenBin(j)) ;

else-- diagonalACov.AddCross(4, GenBin(i), GenBin(j)) ;

end if ; ...

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architecture Test3 of tb isshared variable ACov : CovPType ; -- Cov Object

begin

CollectCov : process variable Src1, Src2 : integer ;

beginSetAlertLogName("IntelligentCov1") ;

ACov.AddCross( GenBin(0,7), GenBin(0,7) );

loop

(Src1, Src2) := ACov.RandCovPoint ;

ACov.ICover( (Src1, Src2) ) ;

DoAluOp(TRec, Src1, Src2) ;

exit when ACov.IsCovered ;

end loop ;ACov.WriteBin ; ReportAlerts ; std.env.stop ;

end process ;

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while not ACov.IsCovered loop

(Src1, Src2) := ACov.RandCovPoint ;

if Src1 /= Src2 thenDoAluOp(TRec, Src1, Src2) ;ACov.ICover( (Src1, Src2) ) ;

else-- Do previous and following diagional DoAluOp(TRec, (Src1-1) mod 8, (Src1-1) mod 8) ; DoAluOp(TRec, Src1, Src1 ) ; DoAluOp(TRec, (Src1+1) mod 8, (Src1+1) mod 8) ;

-- Can either record all or select itemsACov.ICover( (Src1, Src1) ) ;

end if ;

end loop ;

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StimCov.AddBins( 70, NORMAL ) ;StimCov.AddBins( 10, PARITY ) ;StimCov.AddBins( . . . ) ; . . .loopiOperation := StimCov.RandCovPoint ;

case iOperation is when 1 => . . . -- Nominalwhen 3 => . . . -- Parity. . .

end case ;

UartRxScoreboard.Push( (Data, Operation) ) ;

UartSend(UartTxRec, Data, Operation) ;StimCov.Icover(iOperation) ;exit when StimCov.IsCovered ;

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SetAlertLogName("Test_Uart_Rx1") ;

signal CpuID : AlertLogIDType ;signal DataErrID : AlertLogIDType ;. . .

CpuID <= GetAlertLogID("Cpu_1") ; DataErrID <= GetAlertLogID("Cpu_1 Data Error", CpuID);

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Alert (CpuID, "Illegal State") ;AlertIfNot(CpuID, ReadValid, "Read Failed", FAILURE) ;AlertIfDiff(CpuID, "./File1.txt", "./File2.txt") ;

%% Alert ERROR In Cpu_1, Illegal State at 5000 ns

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Log("Test 1 Starting") ;Log(CpuID, "Entered Hold State", DEBUG) ;

%% Log ALWAYS Test 1 Starting at 1770 ns%% Log DEBUG In Cpu_1, Entered Hold State at 31000 ns

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AffirmIf(CpuID, Data = Expect, "Data: " & to_string(Data), " /= Expected: " & to_string(Expect)) ;

%% Alert ERROR In Cpu_1, Data: 5 /= Expected: 6 at ... ns

%% Log PASSED In Cpu_1, Data: 5 at 2150 ns

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ReportAlerts ;

%% DONE FAILED Test_UartRx_1 Total Error(s) = 10 Failures: 0Errors: 10 Warnings: 0 at 100100100 ns

%% DONE FAILED Test_UartRx_1 Total Error(s) = 10 Failures: 0Errors: 10 Warnings: 0 at 100100100 ns %% Default Failures: 0 Errors: 2 Warnings: 0%% OSVVM Failures: 0 Errors: 0 Warnings: 0%% Cpu_1 Failures: 0 Errors: 5 Warnings: 0%% Cpu_1 Data Error Failures: 0 Errors: 4 Warnings: 0%% Cpu_1 Protocol Error Failures: 0 Errors: 1 Warnings: 0%% UartTx_1 Failures: 0 Errors: 0 Warnings: 0

%% DONE PASSED Test_UartRx_1 at 100100100 ns

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SetAlertEnable(WARNING, FALSE) ; -- For all IDsSetAlertEnable(CpuID, WARNING, FALSE) ; -- For CpuID

SetAlertStopCount(ERROR, 20) ; -- For all IDsSetAlertStopCount(CpuID, ERROR, 20) ; -- CpuID

ClearAlerts ;

SetLogEnable(PASSED, TRUE) ; -- For all modelsSetLogEnable(CpuID, DEBUG, TRUE) ; -- For CpuID

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TranscriptOpen("./results/test1.txt") ;TranscriptClose ;

SetTranscriptMirror(TRUE) ; -- TRUE is the default

print("A String") ; -- Direct to file, newline addedprint("") ; -- Print a blank line

writeline( WriteBuf ) ; -- Using textio

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GenerateProc : processbeginSB.Push(X"10") ; UartSend(TRec, X"10") ;SB.Push(X"11") ; UartSend(TRec, X"11") ;SB.Push(X"12") ; UartSend(TRec, X"12") ;. . . Done <= TRUE ; wait ;

end process GenerateProc ;

ReceiveProc : processvariable ExpectD, RcvD : std_logic_vector(7 downto 0);

beginSetAlertLogName("SB_UART");while not Done loop UartGet(RRec, RcvD) ; SB.Check(RcvD) ;

end loop ; ReportAlerts ;

end process ReceiveProc ;

shared variable SB : ScoreboardPType ;

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type MemoryPType is protected

procedure MemInit ( AddrWidth, DataWidth : in integer ) ;

procedure MemWrite ( Addr, Data : in std_logic_vector ) ;

impure function MemRead ( Addr : in std_logic_vector ) return std_logic_vector ;

procedure FileReadH (FileName : string) ;procedure FileWriteH (FileName : string) ;

. . .

end protected MemoryPType ;

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