uvm: now or never? - test and verification solutions

Copyright © 2011-2012 by Doulos. All rights reserved. 1

UVM: Now or Never?

John Aynsley, Doulos

UVM: Now or Never?

• UVM: The Basic Facts

• Options for Interoperability and Migration

• Mixed Language UVM

• Final Remarks

Copyright © 2011-2012 by Doulos. All rights reserved.

Why UVM?

3

The big wins are

• Verification quality

• Testbench / VIP reuse

• Knowhow / skills reuse

Reusable Verification Environment


SystemVerilog


UVM

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• UVM is actively supported by all major vendors

UVM = Universal Verification Methodology

• Drives mutually consistent SystemVerilog implementations

• One standard enhances interoperability and ecosystem growth

• Increases confidence for SystemVerilog adoption


UVM: The Basic Facts

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• Open source (Apache) SystemVerilog Base Class Library

• Constrained random verification

• Configurable, flexible, test benches

• Mixed language vision

Still need a "methodology"


The Big Picture

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uvm_env

uvm_agent

A consistent spatial structure


UVM Highlights

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• Separation of tests from test bench

• Transaction-level communication (TLM)

• Sequences

• Factory and configuration

• Message reporting

• End-of-test mechanism

• Register layer

UVM: Now or Never?




• Final Remarks


UVM versus OVM versus VMM

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• UVM actively developed and promoted by all vendors

• OVM and VMM are not

• UVM adds new features to OVM

• Some OVM features now deprecated

• Advanced features of UVM still a work-in-progress (run-time phasing)

OVM VMM

UVM

OVM 2.1.1

Cadence & Mentor Synopsys

ASI


Interoperability and Migration

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• OVM-to-UVM Migration

www.uvmworld.org - ovm2uvm_migration.pdf

verificationacademy.com/verification-methodology

www.doulos.com/knowhow/sysverilog/uvm/ovm-to-uvm

• ASI: OVM<->VMM Interoperability Library

verificationacademy.com/verification-methodology - ovm_vmm_interop_1_0.tgz

• VMM / UVM Interoperability Kit

http://www.vmmcentral.org/cgi-bin/interopkit/req1.cgi

UVM: Now or Never?




• Final Remarks


Mixed Language Communication

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Wires

Vendor-specific

DPI Functions

Transactions

Vendor-specific

Cadence UVM-ML

Synopsys TLI

Mentor UVM Connect

UVM: Now or Never?




• Final Remarks


Don't Underestimate the Learning Curve

SystemVerilog for FPGA/ASIC Design

Nothing

RTL and test benches

UVM Adopter Class

Verilog

Comprehensive SystemVerilog

SV for Designers Class-based

verification

15


Easier UVM Coding Idioms

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class my_comp extends uvm_component;

ùvm_component_utils(my_comp)

function new(string name, uvm_component parent);

super.new(name, parent);

endfunction

function void build_phase(...);

...

endclass

Pattern 1

class my_seq extends uvm_sequence #(my_tx);

ùvm_object_utils(my_seq)

function new(string name = "");

super.new(name);

endfunction

...

task body;

...

endclass

Pattern 2b

class my_tx extends uvm_sequence_item;

ùvm_object_utils(my_tx)

function new (string name = "");

super.new(name);

endfunction

function string convert2string;

...

endclass

Pattern 2a


What Next?

17

http://www.doulos.com/knowhow/video_gallery

• First Steps with UVM video and source code examples

• Download UVM

http://www.accellera.org/downloads/standards/uvm

uvm: now or never? - test and verification solutions

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