using the mcbsp chapter 6 c6000 integration workshop copyright © 2005 texas instruments. all rights...

Using the McBSP

Chapter 6C6000 Integration Workshop

Copyright © 2005 Texas Instruments. All rights reserved. Technical Training

Organization

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Goals for Module 6…

CPUEDMA

RCVCHAN

gBufRcv

ADC

DAC

McBSPRcv

Xmt

XMTCHAN

gBufXmt

+

COPY

We will learn how to: Use the McBSP to communicate with an external codec Synchronize EDMA transfers with an event Read the position of DIP switch on the DSK

Technical TrainingOrganization

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Outline

McBSP Overview EDMA Synchronization Events DSK’s Serial Communications Initializing McBSP & AIC23 Using the AIC23 Lab 6: Audio Pass-Thru


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Could this be you?

That darn serial port betterbe able to support…

AC’97

SPIT1

E1ST-Bus

MVIP

IOM-2

IIS

Multi-

Channe

lu-Law/A-Law

Codecs

AICs

Full-duplexThe McBSP is an extremely

capable serial port


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Outline

McBSP Overview Block Diagram Data and Frame-Sync Timing McBSP Clock Generation Interrupt/Event Generation


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McBSP Block Diagram

CPU

EDMA

InternalBus

DXR

DXXSR

CLKR

FSR

CLKX

FSX

CLKS

RBR

DRR 32

DRRSRExpand(optional)

Compress(optional)

Let’s look at some basic definitions…

McBSP ControlRegisters SPCR

RCR

XCR PCR

SRGR


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Basic Definitions - Bit, WordCLK

b7 b6 b5 b4 b3 b2 b1 b0

Word

FS

a1 a0

Bit

D

“Word” or “channel” contains #bits specified by WDLEN1 (8, 12, 16, 20, 24, 32)

“Bit” - one data bit per SP clock period

SP Ctrl (SPCR)Rcv Ctrl (RCR)Xmt Ctrl (XCR)Rate (SRGR)

Pin Ctrl (PCR)

Serial Port

RWDLEN157

XWDLEN157

Basic Definitions - Frame


Pin Ctrl (PCR)

Serial Port

“Frame” - contains one or multiple words

w0 w1 w2 w3 w4 w5 w6 w7

FrameWord

w6 w7D

FS

RFRLEN1814

XFRLEN1814

FRLEN1 specifies #words per frame (1-128)

RWDLEN157

XWDLEN157

Outline



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CLK & FS Pins: Input or Output

McBSP

CLKRCLKX

Input or Output?

CLK/FS can be inputs or outputs


Pin Ctrl (PCR)

Serial Port

CLKRMFSRM10

FSXM11

CLKXM89

CLK/FS Mode0: Input1: Output

FSRFSX

If You Select CLK as Output …

McBSP


Pin Ctrl (PCR)

Serial Port

Sample Rate Generator (SRGR)

CLKRCLKX

Rate (SRGR)CLKSM29

CLKSM

(Internal Clock)

CLKOUT1

CLKS

CLKSM: selects clock src (CLKOUT1 or CLKS)

CLKGDV07

CLKGDV

CLKGDV: divide down (1-255) CLKG = (input clock) / (1 + CLKGDV) Max transfer rate is 100Mb/s (for most ‘C6x devices)

CLKG

FSRFSX

If You Select FS as Output …


Pin Ctrl (PCR)

Serial Port

CLKSM29

CLKGDV07

FSGM28

Frame Sync Gen Mode ( FSGM ): 0 = FSX gen’d on every DXR XSR copy

McBSPSample Rate Generator (SRGR)

FSRFSXCLKRCLKX

CLKSM

(Internal Clock)

CLKOUT1

CLKS

CLKGDVCLKG

Framing FSG

FWID815

FPER27 16

1 = FSX and/or FSR gen’d by “Framing” FPER: frame sync period (12 bits) FWID: frame sync pulse width (8 bits)

Outline



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EDMA Sync Events from McBSP

“Ready to Read”

EDMA

CODEC

REVT RRDY=1

DRR RBR RSR

DXR XSR

Receive Event (REVT) When value reaches DRR, sync event sent to EDMA. This can be used to trigger an EDMA transfer.


Pin Ctrl (PCR)

Serial Port

XRDY=1“Ready to Write”

XEVT

Transmit Event (XEVT) Sent to EDMA when DXR is emptied (and ready to

receive another value)

XRDY17

RRDY1

Outline

McBSP Overview EDMA Synchronization Events DSK’s Serial Communications Initializing McBSP & AIC23 Using the AIC 23 Lab 6: Audio Pass-Thru


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C6713 EDMA ChannelsEDMA Channel Event Description 0 DSPINT HPI to DSP interrupt1 TINT0 Timer 0 interrupt2 TINT1 Timer 1 interrupt3 SD_INT EMIF SDRAM timer interrupt4 EXT_INT4 External interrupt pin 45 EXT_INT5 External interrupt pin 56 EXT_INT6 External interrupt pin 67 EXT_INT7 External interrupt pin 78 EDMA_TCC8 9 EDMA_TCC9 10 EDMA_TCC1011 EDMA_TCC1112 XEVT0 McBSP0 transmit event13 REVT0 McBSP0 receive event14 XEVT1 McBSP1 transmit event15 REVT1 McBSP1 receive event

Each channel is associated with a specific sync event When a sync event is unused, that channel may still be programmed

for a simple block memory-copy operation

EDMA chaining


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EDMA Sync Events (ER)EDMA

Channels

15REVT1

14 XEVT1

...

0DSPINT

EDMA_setChannel(hMyChan)

EDMA Event Input

0

1

0

0

ER

XEVT1

REVT1

Previously, EDMA_setChannel() triggered an EDMA channel to run XEVT1 & REVT1 set the appropriate bits in the Event Register (ER),

rather than our code doing this manually

EDMA Sync Events (ER)EDMA

Channels

15REVT1

14 XEVT1

...

0DSPINT


EDMA Event Input

1

1

0

0

ER

DSPINT

XEVT1

REVT1


rather than our code doing this manually What if there is a sync event I don’t want the EDMA to respond to?

Say, DSPINT?

EDMA Sync Events (ER, EER)


rather than our code doing this manually What if there is a sync event I don’t want the EDMA to respond to?

Say, DSPINT? The Event Enable Register (EER) allows event inputs to be blocked.

EDMAChannels

15REVT1

14 XEVT1

...

0DSPINT


EDMA Event Input

1

1

0

0

ER

DSPINT

XEVT1

REVT1

EER0 = 0

EER... = 1

EER14 = 1

EER15 = 0

EER

Note: When setting an ER bit manually (e.g. EDMA_setChannel), the associated EER bit is ignored by the EDMA hardware.


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Outline

McBSP Overview EDMA Synchronization Events DSK’s Serial Communications

AIC23 Codec McBSP AIC23

Initializing McBSP & AIC23 Using the AIC 23 Lab 6: Audio Pass-Thru


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Control

Channel

Data

Channel(Left, Right)

24-bit resolution (90db SNR ADC, 100db SNR DAC) Multiple Digital transfer widths (16-bits, 20-bits, 24-bits, 32-bits) Programmable frequency (8K, 16K, 24K, 32K, 44.1K, 48K, 96K) AIC23 has two serial data pins:

Input for control – reads/writes AIC23’s control registers Bidirectional pin to transfer data to A/D and D/A converters

AIC23 Codec


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Control

Data

McBSP1 connected to program AIC23’s control registers McBSP2 is used to transfer data to A/D and D/A converters One McBSP could be made to handle the AIC23, but since multiple McBSP’s

were available, using two made the design easierOn the C6713 DSK…

C6416 DSK: McBSP Codec Interface

McBSP1

McBSP2


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Control

Data

McBSP0

McBSP1

McBSP0 connected to program AIC23’s control registers McBSP1 is used to transfer data to A/D and D/A converters One McBSP could be made to handle the AIC23, but since multiple McBSP’s

were available, using two made the design easier

C6713 DSK: McBSP Codec Interface


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Outline

McBSP Overview EDMA Synchronization Events DSK’s Serial Communications Initializing McBSP & AIC23

McBSP Init Codec Init

Using the AIC 23 Lab 6: Audio Pass-Thru


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AIC23Codec

Control McBSP

General Procedure to Initialize Codec

Since the AIC23 is connected to the McBSP, you must first initialize the McBSP, then the codec.

C6416 DSK McBSP1 used for

control channel

C6713 DSK McBSP0 used for

control channel

1. Setup McBSP

2. Setup Codec via McBSP

SPCRRCRXCR

SRGRPCRMCR

DXRDRR


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1. McBSP Setup#include <csl.h>#include <csl_mcbsp.h>MCBSP_Handle hMcbsp0;

MCBSP_Config mcbspCfgControl = { 0x00001000, // Serial Port Control Reg. (SPCR) 0x00000000, // Receiver Control Reg. (RCR) 0x00000040, // Transmitter Control Reg. (XCR) 0x20001363, // Sample-Rate Generator Reg. (SRGR) 0x00000000, // Multichannel Control Reg. (MCR) 0x00000000, // Receiver Channel Enable (RCER) 0x00000000, // Transmitter Channel Enable (XCER) 0x00000A0A // Pin Control Reg. (PCR)};

void initMcBSP(){ hMcbsp0 = MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET); MCBSP_config(hMcbsp0, &mcbspCfgControl ); MCBSP_start (hMcbsp0, MCBSP_XMIT_START | MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC, 100);}

1

3

45

Let's look more closely the McBSP configuration ...

2

6

1. McBSP Config (a)MCBSP_Config mcbspCfgControl = {

MCBSP_SPCR_RMK(MCBSP_SPCR_FREE_NO,MCBSP_SPCR_SOFT_NO,MCBSP_SPCR_FRST_YES,MCBSP_SPCR_GRST_YES,MCBSP_SPCR_XINTM_XRDY,MCBSP_SPCR_XSYNCERR_NO,MCBSP_SPCR_XRST_YES,MCBSP_SPCR_DLB_OFF,MCBSP_SPCR_RJUST_RZF,MCBSP_SPCR_CLKSTP_NODELAY,MCBSP_SPCR_DXENA_OFF,MCBSP_SPCR_RINTM_RRDY,MCBSP_SPCR_RSYNCERR_NO,MCBSP_SPCR_RRST_YES

),

Puts both transmit and rcv sides into reset upon config.

Previous slide shows config as 32-bit hex values (because it fit on 1 slide).

A better method uses _RMK macros. Improves: Readability Maintainability


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1. McBSP Config (b)

MCBSP_RCR_DEFAULT,MCBSP_XCR_RMK(

MCBSP_XCR_XPHASE_SINGLE, MCBSP_XCR_XFRLEN2_OF(0), MCBSP_XCR_XWDLEN2_8BIT, MCBSP_XCR_XCOMPAND_MSB, MCBSP_XCR_XFIG_NO, MCBSP_XCR_XDATDLY_0BIT, MCBSP_XCR_XFRLEN1_OF(0), MCBSP_XCR_XWDLEN1_16BIT, MCBSP_XCR_XWDREVRS_DISABLE

),

Default values provided in CSL for each register (or bit)


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Codec Initialization

Specify codec configuration

void initCodec(MCBSP_Handle hMcbsp){ short codecConfig[10] = { 0x0017, // 0 Left line input channel volume 0x0017, // 1 Right line input channel volume 0x01f9, // 2 Left channel headphone volume … }; for (i = 0; i < 10; i++) { … MCBSP_write(hMcbsp,(i << 9)|codecConfig[i]);}}

AIC23Codec

Control McBSP

1. Setup McBSP

2. Setup Codec via McBSP

SPCRRCRXCR

SRGRPCRMCR

DXRDRR

Write init values to codec

Outline

McBSP Overview EDMA Synchronization Events DSK’s Serial Communications Initializing McBSP & AIC23 Using the AIC23 (setup EDMA) Lab 6: Audio Pass-thru


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McBSP

Using the Codec (via EDMA)gBufXmt EDMA

ChanDXR

XEVT2

(… EDMA_OPT_SUM_INC, // Src update mode? EDMA_OPT_DUM_NONE, // Dest update mode? EDMA_OPT_TCINT_YES, // Cause EDMA interrupt? EDMA_OPT_TCC_OF(0), // Transfer complete code? EDMA_OPT_FS_NO), // Use frame sync? … EDMA_SRC_OF(gBufXmt), // src address? EDMA_DST_OF(0), … // dest address?

hEdmaXmt = EDMA_open(EDMA_CHA_XEVT2, EDMA_OPEN_RESET); gEdmaConfigXmt.dst = MCBSP_getXmtAddr(hMcbsp2);EDMA_intEnable(gTcc);

Note: McBSP1 and XEVT1 for C6713Technical Training

Organization

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Outline

McBSP Overview EDMA Synchronization Events DSK’s Serial Communications Initializing McBSP & AIC23 Using the AIC 23 Lab 6: Audio Pass-thru


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Lab 6 – Audio Pass Thru

CPUEDMA

RCVCHAN

gBufRcv

ADC

DAC

McBSPRcv

Xmt

XMTCHAN

gBufXmt

+

COPY

Goals:1. EDMA (RCV) copies values from DRR to gBufRcv2. CPU copies gBufRcv to gBufXmt3. EDMA (XMT) copies gBufXmt to DXR4. Opt: add sine to gBufRcv based on DIP switch


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Chapter 6: Optional Topic DMA Synchronization and

DMA Split Mode

Click Here for Chapter 7Channel Sorting


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ti


using the mcbsp chapter 6 c6000 integration workshop copyright © 2005 texas instruments. all rights...

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