Using Contrapositive Law to Enhance Implication Graphs of Logic Circuits

Kunal K Dave

Master’s Thesis

Electrical & Computer Engineering

Rutgers University

4/23/2004

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Talk Outline

Background

Oring Nodes

New Algorithms

Results

Conclusion and Future Work

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Background Implication graph-based ATPG techniques:

Larrabee et al. -- IEEE-TCAD, 1992 Chakradhar et al.-- IEEE-TCAD, 1993 Tafershofer et al. -- IEEE-TCAD, 2000

Implication based fault-independent redundancy identification techniques: Iyer and Abramovici – IEEE-VLSI Systems, 1996 Agrawal et al. -- ATS, 1996 Gaur et al. -- DELTA, 2002 Mehta et al. -- VLSI Design, 2003

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Implication Graph An implication graph (IG) Digital circuit in the

form of a set of binary and higher-order relations.

ab

cBoolean equation AND: c = ab

Boolean false function* AND: ab c = 0

ac + bc + abc = 0

Λ3

a b c

cba

Λ1

Λ2

* Chakradhar et al. -- IEEE-D&T, 1990

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Observability Implications

bOa

Oc

Λ3

b

b

Λ1

Λ2

Oc Oa

OcOa

b

as

Os

OsOsa

Osa Osb

Osb

Observability nodes – Agrawal, Lin and Bushnell -- ATS, 1996

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Redundancy Identification Obtain an implication graph from the circuit

topology and compute transitive closure.

There are 8 different conditions on the basis of which a fault is said to be redundant.*

Examples: If node c implies c then s-a-0 fault on line c is redundant. If node Oc implies Oc then c is unobservable and both s-a-

0 and s-a-1 faults on line c are redundant.

* Agrawal et al. -- ATS, 1996 & Gaur et al. -- DELTA, 2002

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Motivation – Problem Statement Implication graph (IG) Digital circuit represented

as a set of binary and higher-order relations. Binary relations full implication edges. Higher-order relations partial implications using

anding nodes. Incomplete representation, can be improved.

An improvement--use contrapositive rule to derive new partial implication nodes, oring nodes, to incorporate more complete logic information in the implication graph.

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Oring Nodes

Expansion of Boolean false function AND : ac + bc + abc = 0

a c c aContrapositive

b c c bContrapositive

(a Λ b) c

c (b V c)Contrapositive

c (b V c)De-Morgan

(a Λ c) b

b (a V c)Contrapositive

b (a V c)De-Morgan

(b Λ c) a

a (b V c)Contrapositive

a (b V c)De-Morgan

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Use of Oring Nodes

V1

a b c

cba

Λ1Λ2

ab

c

d

d

d

V2

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Extended Use of Oring Node

ab c

de

s-a-0

Λ1

b

dOc

Oac

Λ2

ab

aV1

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Motivation - A Problem Statement Addition of a new edge can change the transitive

closure (TC). Re-computation of TC is required. Algorithms are needed to update TC rather than re-

computing it.

Develop new algorithms that dynamically update the transitive closure graph while extracting implications from a logic network.

Apply new implication graph and new dynamic update algorithms to redundancy identification to obtain better performances.

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Update routine

(1) Update(G, vs, vn){(2) for each parent Pi of source vs {(3) for each child Cj of destination vn{(4) if (edge Pi Cj does not exist)(5) addTcEdge(Pi, Cj);(6) } } }//Update

b

cd

a

NodesParents Nodes

Child Nodes

a a a, b, d

b b, a b

c c c, d

d d, a, c d

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Update_Partial_A Converts partial implications in to possible full

implications using anding nodes. New edge, vs vd, added???

Check if vd is a parent of an anding node Λx. Find a common grandparent Gp of the node Λx.

Add TC edge from Gp to successor(Λx).

e

c

d

a Λ1

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Update_Partial_AO Converts partial implications in to possible full

implications using oring nodes. New edge, vs vd, added???

Check if vs is a child of an oring node Vx. Find a common grandchild Gc of the node Vx.

Add TC edge from predecessor(Vx) to Gc.

e

c

d

a V1

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Update_Partial_AO (contd…) Also obtains backward partial implications using

oring nodes that were previously obtained by extra anding nodes.

c

de

Λ1

b

dOc

Oac

Λ2

ab

aV1

ab

s-a-0

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An Example

w x m

p

n

b

a

c

z

n m

V1 Λ1

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Number of Partial Nodes

0

5000

10000

15000

20000

25000

30000

ISCAS Benchmark Circuits

No

. of

Pa

rtia

l no

de

s

Series1

Series2

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Results on ISCAS Circuits

CircuitTotal faults

Redundant faults identified and run time

TRAN FIRE TCM Our Algorithm

Red. faults

CPU

Sec.Red.

FaultsCPU

Sec.Red.

FaultsCPU

Sec.Red.

FaultsCPU

Sec.

c1908 1879 7 13.0 6 1.8 2 3.2 5 5.7

c2670 2747 115 95.2 29 1.5 59 4.0 69 6.0

c7552 7550 131 308.0 30 4.7 51 11.5 65 17.7

c1238 1355 69 17.4 6 1.9 20 2.6 51 5.4

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ISCAS ’85 -- C1908

979887

74

s-a-1952

953

949

926 s-a-1

Redundant faults

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ISCAS ’85 -- C5315

1

0/1

0/1

1

1

1

1

1

0/1

PI

PI

PO

0 0

0 0

0/1

0

1

1

1

Redundant fault

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ISCAS ’85 -- C5315

1

0/1

0/1

1

0

0

0

1

0/1

PI

PI

PO

1 1

1 0/1

0

1

0

Redundant fault

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Conclusion – Future Work Contributions of thesis

New partial implication structure called oring node enhances implication graph of logic circuits; more complete and more compact the the graph with just anding nodes.

New algorithms dynamically update the transitive closure every time a new implication edge is added; greater efficiency over complete recomputation.

New and improved fault-independent redundancy identification.

New techniques can be further explored in following areas:

Fanout stem unobservability – proposed solution Equivalence checking Test generation

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Thank You